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x86: drop bogus IgnoreSize from SSE2 insns
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1ee3e487
JB		 12018-09-13 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
4 * i386-tbl.h: Re-generate.
5
a5f580e5
JB		 62018-09-13 Jan Beulich <jbeulich@suse.com>
7
8 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
9 * i386-tbl.h: Re-generate.
10
49d5d12d
JB		 112018-09-13 Jan Beulich <jbeulich@suse.com>
12
13 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
14 (vpbroadcastw, rdpid): Drop NoRex64.
15 * i386-tbl.h: Re-generate.
16
f5eb1d70
JB		 172018-09-13 Jan Beulich <jbeulich@suse.com>
18
19 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
20 store templates, adding D.
21 * i386-tbl.h: Re-generate.
22
dbbc8b7e
JB		 232018-09-13 Jan Beulich <jbeulich@suse.com>
24
25 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
26 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
27 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
28 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
29 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
30 Fold load and store templates where possible, adding D. Drop
31 IgnoreSize where it was pointlessly present. Drop redundant
32 *word.
33 * i386-tbl.h: Re-generate.
34
d276ec69
JB		 352018-09-13 Jan Beulich <jbeulich@suse.com>
36
37 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
38 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
39 (intel_operand_size): Handle v_bndmk_mode.
40 (OP_E_memory): Likewise. Produce (bad) when also riprel.
41
9da4dfd6
JD		 422018-09-08 John Darrington <john@darrington.wattle.id.au>
43
44 * disassemble.c (ARCH_s12z): Define if ARCH_all.
45
be192bc2
JW		 462018-08-31 Kito Cheng <kito@andestech.com>
47
48 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
49 compressed floating point instructions.
50
43135d3b
JW		 512018-08-30 Kito Cheng <kito@andestech.com>
52
53 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
54 riscv_opcode.xlen_requirement.
55 * riscv-opc.c (riscv_opcodes): Update for struct change.
56
df28970f
MA		 572018-08-29 Martin Aberg <maberg@gaisler.com>
58
59 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
60 psr (PWRPSR) instruction.
61
9108bc33
CX		 622018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
63
64 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
65
bd782c07
CX		 662018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
67
68 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
69
ac8cb70f
CX		 702018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
71
72 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
73 loongson3a as an alias of gs464 for compatibility.
74 * mips-opc.c (mips_opcodes): Change Comments.
75
a693765e
CX		 762018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
77
78 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
79 option.
80 (print_mips_disassembler_options): Document -M loongson-ext.
81 * mips-opc.c (LEXT2): New macro.
82 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
83
bdc6c06e
CX		 842018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
85
86 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
87 descriptors.
88 (parse_mips_ase_option): Handle -M loongson-ext option.
89 (print_mips_disassembler_options): Document -M loongson-ext.
90 * mips-opc.c (IL3A): Delete.
91 * mips-opc.c (LEXT): New macro.
92 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
93 instructions.
94
716c08de
CX		 952018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
96
97 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
98 descriptors.
99 (parse_mips_ase_option): Handle -M loongson-cam option.
100 (print_mips_disassembler_options): Document -M loongson-cam.
101 * mips-opc.c (LCAM): New macro.
102 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
103 instructions.
104
9cf7e568
AM		 1052018-08-21 Alan Modra <amodra@gmail.com>
106
107 * ppc-dis.c (operand_value_powerpc): Init "invalid".
108 (skip_optional_operands): Count optional operands, and update
109 ppc_optional_operand_value call.
110 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
111 (extract_vlensi): Likewise.
112 (extract_fxm): Return default value for missing optional operand.
113 (extract_ls, extract_raq, extract_tbr): Likewise.
114 (insert_sxl, extract_sxl): New functions.
115 (insert_esync, extract_esync): Remove Power9 handling and simplify.
116 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
117 flag and extra entry.
118 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
119 extract_sxl.
120
d203b41a 1212018-08-20 Alan Modra <amodra@gmail.com>
f4107842 122
d203b41a 123 * sh-opc.h (MASK): Simplify.
f4107842 124
08a8fe2f 1252018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 126
d203b41a
AM		 127 * s12z-dis.c (bm_decode): Deal with cases where the mode is
128 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 129 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 130
08a8fe2f 1312018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 132
133 * s12z.h: Delete.
7ba3ba91 134
1bc60e56
L		 1352018-08-14 H.J. Lu <hongjiu.lu@intel.com>
136
137 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
138 address with the addr32 prefix and without base nor index
139 registers.
140
d871f3f4
L		 1412018-08-11 H.J. Lu <hongjiu.lu@intel.com>
142
143 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
144 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
145 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
146 (cpu_flags): Add CpuCMOV and CpuFXSR.
147 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
148 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
149 * i386-init.h: Regenerated.
150 * i386-tbl.h: Likewise.
151
b6523c37 1522018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
153
154 * arc-regs.h: Update auxiliary registers.
155
e968fc9b
JB		 1562018-08-06 Jan Beulich <jbeulich@suse.com>
157
158 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
159 (RegIP, RegIZ): Define.
160 * i386-reg.tbl: Adjust comments.
161 (rip): Use Qword instead of BaseIndex. Use RegIP.
162 (eip): Use Dword instead of BaseIndex. Use RegIP.
163 (riz): Add Qword. Use RegIZ.
164 (eiz): Add Dword. Use RegIZ.
165 * i386-tbl.h: Re-generate.
166
dbf8be89
JB		 1672018-08-03 Jan Beulich <jbeulich@suse.com>
168
169 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
170 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
171 vpmovzxdq, vpmovzxwd): Remove NoRex64.
172 * i386-tbl.h: Re-generate.
173
c48dadc9
JB		 1742018-08-03 Jan Beulich <jbeulich@suse.com>
175
176 * i386-gen.c (operand_types): Remove Mem field.
177 * i386-opc.h (union i386_operand_type): Remove mem field.
178 * i386-init.h, i386-tbl.h: Re-generate.
179
cb86a42a
AM		 1802018-08-01 Alan Modra <amodra@gmail.com>
181
182 * po/POTFILES.in: Regenerate.
183
07cc0450
NC		 1842018-07-31 Nick Clifton <nickc@redhat.com>
185
186 * po/sv.po: Updated Swedish translation.
187
1424ad86
JB		 1882018-07-31 Jan Beulich <jbeulich@suse.com>
189
190 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
191 * i386-init.h, i386-tbl.h: Re-generate.
192
ae2387fe
JB		 1932018-07-31 Jan Beulich <jbeulich@suse.com>
194
195 * i386-opc.h (ZEROING_MASKING) Rename to ...
196 (DYNAMIC_MASKING): ... this. Adjust comment.
197 * i386-opc.tbl (MaskingMorZ): Define.
198 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
199 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
200 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
201 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
202 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
203 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
204 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
205 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
206 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
207
6ff00b5e
JB		 2082018-07-31 Jan Beulich <jbeulich@suse.com>
209
210 * i386-opc.tbl: Use element rather than vector size for AVX512*
211 scatter/gather insns.
212 * i386-tbl.h: Re-generate.
213
e951d5ca
JB		 2142018-07-31 Jan Beulich <jbeulich@suse.com>
215
216 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
217 (cpu_flags): Drop CpuVREX.
218 * i386-opc.h (CpuVREX): Delete.
219 (union i386_cpu_flags): Remove cpuvrex.
220 * i386-init.h, i386-tbl.h: Re-generate.
221
eb41b248
JW		 2222018-07-30 Jim Wilson <jimw@sifive.com>
223
224 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
225 fields.
226 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
227
b8891f8d
AJ		 2282018-07-30 Andrew Jenner <andrew@codesourcery.com>
229
230 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
231 * Makefile.in: Regenerated.
232 * configure.ac: Add C-SKY.
233 * configure: Regenerated.
234 * csky-dis.c: New file.
235 * csky-opc.h: New file.
236 * disassemble.c (ARCH_csky): Define.
237 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
238 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
239
16065af1
AM		 2402018-07-27 Alan Modra <amodra@gmail.com>
241
242 * ppc-opc.c (insert_sprbat): Correct function parameter and
243 return type.
244 (extract_sprbat): Likewise, variable too.
245
fa758a70
AC		 2462018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
247 Alan Modra <amodra@gmail.com>
248
249 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
250 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
251 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
252 support disjointed BAT.
253 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
254 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
255 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
256
4a1b91ea
L		 2572018-07-25 H.J. Lu <hongjiu.lu@intel.com>
258 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
259
260 * i386-gen.c (adjust_broadcast_modifier): New function.
261 (process_i386_opcode_modifier): Add an argument for operands.
262 Adjust the Broadcast value based on operands.
263 (output_i386_opcode): Pass operand_types to
264 process_i386_opcode_modifier.
265 (process_i386_opcodes): Pass NULL as operands to
266 process_i386_opcode_modifier.
267 * i386-opc.h (BYTE_BROADCAST): New.
268 (WORD_BROADCAST): Likewise.
269 (DWORD_BROADCAST): Likewise.
270 (QWORD_BROADCAST): Likewise.
271 (i386_opcode_modifier): Expand broadcast to 3 bits.
272 * i386-tbl.h: Regenerated.
273
67ce483b
AM		 2742018-07-24 Alan Modra <amodra@gmail.com>
275
276 PR 23430
277 * or1k-desc.h: Regenerate.
278
4174bfff
JB		 2792018-07-24 Jan Beulich <jbeulich@suse.com>
280
281 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
282 vcvtusi2ss, and vcvtusi2sd.
283 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
284 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
285 * i386-tbl.h: Re-generate.
286
04e65276
CZ		 2872018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
288
289 * arc-opc.c (extract_w6): Fix extending the sign.
290
47e6f81c
CZ		 2912018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
292
293 * arc-tbl.h (vewt): Allow it for ARC EM family.
294
bb71536f
AM		 2952018-07-23 Alan Modra <amodra@gmail.com>
296
297 PR 23419
298 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
299 opcode variants for mtspr/mfspr encodings.
300
8095d2f7
CX		 3012018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
302 Maciej W. Rozycki <macro@mips.com>
303
304 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
305 loongson3a descriptors.
306 (parse_mips_ase_option): Handle -M loongson-mmi option.
307 (print_mips_disassembler_options): Document -M loongson-mmi.
308 * mips-opc.c (LMMI): New macro.
309 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
310 instructions.
311
5f32791e
JB		 3122018-07-19 Jan Beulich <jbeulich@suse.com>
313
314 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
315 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
316 IgnoreSize and [XYZ]MMword where applicable.
317 * i386-tbl.h: Re-generate.
318
625cbd7a
JB		 3192018-07-19 Jan Beulich <jbeulich@suse.com>
320
321 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
322 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
323 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
324 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
325 * i386-tbl.h: Re-generate.
326
86b15c32
JB		 3272018-07-19 Jan Beulich <jbeulich@suse.com>
328
329 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
330 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
331 VPCLMULQDQ templates into their respective AVX512VL counterparts
332 where possible, using Disp8ShiftVL and CheckRegSize instead of
333 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
334 * i386-tbl.h: Re-generate.
335
cf769ed5
JB		 3362018-07-19 Jan Beulich <jbeulich@suse.com>
337
338 * i386-opc.tbl: Fold AVX512DQ templates into their respective
339 AVX512VL counterparts where possible, using Disp8ShiftVL and
340 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
341 IgnoreSize) as appropriate.
342 * i386-tbl.h: Re-generate.
343
8282b7ad
JB		 3442018-07-19 Jan Beulich <jbeulich@suse.com>
345
346 * i386-opc.tbl: Fold AVX512BW templates into their respective
347 AVX512VL counterparts where possible, using Disp8ShiftVL and
348 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
349 IgnoreSize) as appropriate.
350 * i386-tbl.h: Re-generate.
351
755908cc
JB		 3522018-07-19 Jan Beulich <jbeulich@suse.com>
353
354 * i386-opc.tbl: Fold AVX512CD templates into their respective
355 AVX512VL counterparts where possible, using Disp8ShiftVL and
356 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
357 IgnoreSize) as appropriate.
358 * i386-tbl.h: Re-generate.
359
7091c612
JB		 3602018-07-19 Jan Beulich <jbeulich@suse.com>
361
362 * i386-opc.h (DISP8_SHIFT_VL): New.
363 * i386-opc.tbl (Disp8ShiftVL): Define.
364 (various): Fold AVX512VL templates into their respective
365 AVX512F counterparts where possible, using Disp8ShiftVL and
366 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
367 IgnoreSize) as appropriate.
368 * i386-tbl.h: Re-generate.
369
c30be56e
JB		 3702018-07-19 Jan Beulich <jbeulich@suse.com>
371
372 * Makefile.am: Change dependencies and rule for
373 $(srcdir)/i386-init.h.
374 * Makefile.in: Re-generate.
375 * i386-gen.c (process_i386_opcodes): New local variable
376 "marker". Drop opening of input file. Recognize marker and line
377 number directives.
378 * i386-opc.tbl (OPCODE_I386_H): Define.
379 (i386-opc.h): Include it.
380 (None): Undefine.
381
11a322db
L		 3822018-07-18 H.J. Lu <hongjiu.lu@intel.com>
383
384 PR gas/23418
385 * i386-opc.h (Byte): Update comments.
386 (Word): Likewise.
387 (Dword): Likewise.
388 (Fword): Likewise.
389 (Qword): Likewise.
390 (Tbyte): Likewise.
391 (Xmmword): Likewise.
392 (Ymmword): Likewise.
393 (Zmmword): Likewise.
394 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
395 vcvttps2uqq.
396 * i386-tbl.h: Regenerated.
397
cde3679e
NC		 3982018-07-12 Sudakshina Das <sudi.das@arm.com>
399
400 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
401 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
402 * aarch64-asm-2.c: Regenerate.
403 * aarch64-dis-2.c: Regenerate.
404 * aarch64-opc-2.c: Regenerate.
405
45a28947
TC		 4062018-07-12 Tamar Christina <tamar.christina@arm.com>
407
408 PR binutils/23192
409 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
410 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
411 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
412 sqdmulh, sqrdmulh): Use Em16.
413
c597cc3d
SD		 4142018-07-11 Sudakshina Das <sudi.das@arm.com>
415
416 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
417 csdb together with them.
418 (thumb32_opcodes): Likewise.
419
a79eaed6
JB		 4202018-07-11 Jan Beulich <jbeulich@suse.com>
421
422 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
423 requiring 32-bit registers as operands 2 and 3. Improve
424 comments.
425 (mwait, mwaitx): Fold templates. Improve comments.
426 OPERAND_TYPE_INOUTPORTREG.
427 * i386-tbl.h: Re-generate.
428
2fb5be8d
JB		 4292018-07-11 Jan Beulich <jbeulich@suse.com>
430
431 * i386-gen.c (operand_type_init): Remove
432 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
433 OPERAND_TYPE_INOUTPORTREG.
434 * i386-init.h: Re-generate.
435
7f5cad30
JB		 4362018-07-11 Jan Beulich <jbeulich@suse.com>
437
438 * i386-opc.tbl (wrssd, wrussd): Add Dword.
439 (wrssq, wrussq): Add Qword.
440 * i386-tbl.h: Re-generate.
441
f0a85b07
JB		 4422018-07-11 Jan Beulich <jbeulich@suse.com>
443
444 * i386-opc.h: Rename OTMax to OTNum.
445 (OTNumOfUints): Adjust calculation.
446 (OTUnused): Directly alias to OTNum.
447
9dcb0ba4
MR		 4482018-07-09 Maciej W. Rozycki <macro@mips.com>
449
450 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
451 `reg_xys'.
452 (lea_reg_xys): Likewise.
453 (print_insn_loop_primitive): Rename `reg' local variable to
454 `reg_dxy'.
455
f311ba7e
TC		 4562018-07-06 Tamar Christina <tamar.christina@arm.com>
457
458 PR binutils/23242
459 * aarch64-tbl.h (ldarh): Fix disassembly mask.
460
cba05feb
TC		 4612018-07-06 Tamar Christina <tamar.christina@arm.com>
462
463 PR binutils/23369
464 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
465 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
466
471b9d15
MR		 4672018-07-02 Maciej W. Rozycki <macro@mips.com>
468
469 PR tdep/8282
470 * mips-dis.c (mips_option_arg_t): New enumeration.
471 (mips_options): New variable.
472 (disassembler_options_mips): New function.
473 (print_mips_disassembler_options): Reimplement in terms of
474 `disassembler_options_mips'.
475 * arm-dis.c (disassembler_options_arm): Adapt to using the
476 `disasm_options_and_args_t' structure.
477 * ppc-dis.c (disassembler_options_powerpc): Likewise.
478 * s390-dis.c (disassembler_options_s390): Likewise.
479
c0c468d5
TP		 4802018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
481
482 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
483 expected result.
484 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
485 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
486 * testsuite/ld-arm/tls-longplt.d: Likewise.
487
369c9167
TC		 4882018-06-29 Tamar Christina <tamar.christina@arm.com>
489
490 PR binutils/23192
491 * aarch64-asm-2.c: Regenerate.
492 * aarch64-dis-2.c: Likewise.
493 * aarch64-opc-2.c: Likewise.
494 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
495 * aarch64-opc.c (operand_general_constraint_met_p,
496 aarch64_print_operand): Likewise.
497 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
498 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
499 fmlal2, fmlsl2.
500 (AARCH64_OPERANDS): Add Em2.
501
30aa1306
NC		 5022018-06-26 Nick Clifton <nickc@redhat.com>
503
504 * po/uk.po: Updated Ukranian translation.
505 * po/de.po: Updated German translation.
506 * po/pt_BR.po: Updated Brazilian Portuguese translation.
507
eca4b721
NC		 5082018-06-26 Nick Clifton <nickc@redhat.com>
509
510 * nfp-dis.c: Fix spelling mistake.
511
71300e2c
NC		 5122018-06-24 Nick Clifton <nickc@redhat.com>
513
514 * configure: Regenerate.
515 * po/opcodes.pot: Regenerate.
516
719d8288
NC		 5172018-06-24 Nick Clifton <nickc@redhat.com>
518
519 2.31 branch created.
520
514cd3a0
TC		 5212018-06-19 Tamar Christina <tamar.christina@arm.com>
522
523 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
524 * aarch64-asm-2.c: Regenerate.
525 * aarch64-dis-2.c: Likewise.
526
385e4d0f
MR		 5272018-06-21 Maciej W. Rozycki <macro@mips.com>
528
529 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
530 `-M ginv' option description.
531
160d1b3d
SH		 5322018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
533
534 PR gas/23305
535 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
536 la and lla.
537
d0ac1c44
SM		 5382018-06-19 Simon Marchi <simon.marchi@ericsson.com>
539
540 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
541 * configure.ac: Remove AC_PREREQ.
542 * Makefile.in: Re-generate.
543 * aclocal.m4: Re-generate.
544 * configure: Re-generate.
545
6f20c942
FS		 5462018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
547
548 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
549 mips64r6 descriptors.
550 (parse_mips_ase_option): Handle -Mginv option.
551 (print_mips_disassembler_options): Document -Mginv.
552 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
553 (GINV): New macro.
554 (mips_opcodes): Define ginvi and ginvt.
555
730c3174
SE		 5562018-06-13 Scott Egerton <scott.egerton@imgtec.com>
557 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
558
559 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
560 * mips-opc.c (CRC, CRC64): New macros.
561 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
562 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
563 crc32cd for CRC64.
564
cb366992
EB		 5652018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
566
567 PR 20319
568 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
569 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
570
ce72cd46
AM		 5712018-06-06 Alan Modra <amodra@gmail.com>
572
573 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
574 setjmp. Move init for some other vars later too.
575
4b8e28c7
MF		 5762018-06-04 Max Filippov <jcmvbkbc@gmail.com>
577
578 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
579 (dis_private): Add new fields for property section tracking.
580 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
581 (xtensa_instruction_fits): New functions.
582 (fetch_data): Bump minimal fetch size to 4.
583 (print_insn_xtensa): Make struct dis_private static.
584 Load and prepare property table on section change.
585 Don't disassemble literals. Don't disassemble instructions that
586 cross property table boundaries.
587
55e99962
L		 5882018-06-01 H.J. Lu <hongjiu.lu@intel.com>
589
590 * configure: Regenerated.
591
733bd0ab
JB		 5922018-06-01 Jan Beulich <jbeulich@suse.com>
593
594 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
595 * i386-tbl.h: Re-generate.
596
dfd27d41
JB		 5972018-06-01 Jan Beulich <jbeulich@suse.com>
598
599 * i386-opc.tbl (sldt, str): Add NoRex64.
600 * i386-tbl.h: Re-generate.
601
64795710
JB		 6022018-06-01 Jan Beulich <jbeulich@suse.com>
603
604 * i386-opc.tbl (invpcid): Add Oword.
605 * i386-tbl.h: Re-generate.
606
030157d8
AM		 6072018-06-01 Alan Modra <amodra@gmail.com>
608
609 * sysdep.h (_bfd_error_handler): Don't declare.
610 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
611 * rl78-decode.opc: Likewise.
612 * msp430-decode.c: Regenerate.
613 * rl78-decode.c: Regenerate.
614
a9660a6f
AP		 6152018-05-30 Amit Pawar <Amit.Pawar@amd.com>
616
617 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
618 * i386-init.h : Regenerated.
619
277eb7f6
AM		 6202018-05-25 Alan Modra <amodra@gmail.com>
621
622 * Makefile.in: Regenerate.
623 * po/POTFILES.in: Regenerate.
624
98553ad3
PB		 6252018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
626
627 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
628 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
629 (insert_bab, extract_bab, insert_btab, extract_btab,
630 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
631 (BAT, BBA VBA RBS XB6S): Delete macros.
632 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
633 (BB, BD, RBX, XC6): Update for new macros.
634 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
635 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
636 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
637 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
638
7b4ae824
JD		 6392018-05-18 John Darrington <john@darrington.wattle.id.au>
640
641 * Makefile.am: Add support for s12z architecture.
642 * configure.ac: Likewise.
643 * disassemble.c: Likewise.
644 * disassemble.h: Likewise.
645 * Makefile.in: Regenerate.
646 * configure: Regenerate.
647 * s12z-dis.c: New file.
648 * s12z.h: New file.
649
29e0f0a1
AM		 6502018-05-18 Alan Modra <amodra@gmail.com>
651
652 * nfp-dis.c: Don't #include libbfd.h.
653 (init_nfp3200_priv): Use bfd_get_section_contents.
654 (nit_nfp6000_mecsr_sec): Likewise.
655
809276d2
NC		 6562018-05-17 Nick Clifton <nickc@redhat.com>
657
658 * po/zh_CN.po: Updated simplified Chinese translation.
659
ff329288
TC		 6602018-05-16 Tamar Christina <tamar.christina@arm.com>
661
662 PR binutils/23109
663 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
664 * aarch64-dis-2.c: Regenerate.
665
f9830ec1
TC		 6662018-05-15 Tamar Christina <tamar.christina@arm.com>
667
668 PR binutils/21446
669 * aarch64-asm.c (opintl.h): Include.
670 (aarch64_ins_sysreg): Enforce read/write constraints.
671 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
672 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
673 (F_REG_READ, F_REG_WRITE): New.
674 * aarch64-opc.c (aarch64_print_operand): Generate notes for
675 AARCH64_OPND_SYSREG.
676 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
677 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
678 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
679 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
680 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
681 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
682 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
683 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
684 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
685 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
686 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
687 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
688 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
689 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
690 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
691 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
692 msr (F_SYS_WRITE), mrs (F_SYS_READ).
693
7d02540a
TC		 6942018-05-15 Tamar Christina <tamar.christina@arm.com>
695
696 PR binutils/21446
697 * aarch64-dis.c (no_notes: New.
698 (parse_aarch64_dis_option): Support notes.
699 (aarch64_decode_insn, print_operands): Likewise.
700 (print_aarch64_disassembler_options): Document notes.
701 * aarch64-opc.c (aarch64_print_operand): Support notes.
702
561a72d4
TC		 7032018-05-15 Tamar Christina <tamar.christina@arm.com>
704
705 PR binutils/21446
706 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
707 and take error struct.
708 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
709 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
710 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
711 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
712 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
713 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
714 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
715 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
716 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
717 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
718 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
719 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
720 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
721 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
722 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
723 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
724 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
725 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
726 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
727 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
728 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
729 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
730 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
731 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
732 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
733 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
734 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
735 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
736 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
737 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
738 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
739 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
740 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
741 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
742 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
743 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
744 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
745 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
746 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
747 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
748 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
749 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
750 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
751 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
752 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
753 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
754 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
755 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
756 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
757 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
758 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
759 (determine_disassembling_preference, aarch64_decode_insn,
760 print_insn_aarch64_word, print_insn_data): Take errors struct.
761 (print_insn_aarch64): Use errors.
762 * aarch64-asm-2.c: Regenerate.
763 * aarch64-dis-2.c: Regenerate.
764 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
765 boolean in aarch64_insert_operan.
766 (print_operand_extractor): Likewise.
767 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
768
1678bd35
FT		 7692018-05-15 Francois H. Theron <francois.theron@netronome.com>
770
771 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
772
06cfb1c8
L		 7732018-05-09 H.J. Lu <hongjiu.lu@intel.com>
774
775 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
776
84f9f8c3
AM		 7772018-05-09 Sebastian Rasmussen <sebras@gmail.com>
778
779 * cr16-opc.c (cr16_instruction): Comment typo fix.
780 * hppa-dis.c (print_insn_hppa): Likewise.
781
e6f372ba
JW		 7822018-05-08 Jim Wilson <jimw@sifive.com>
783
784 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
785 (match_c_slli64, match_srxi_as_c_srxi): New.
786 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
787 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
788 <c.slli, c.srli, c.srai>: Use match_s_slli.
789 <c.slli64, c.srli64, c.srai64>: New.
790
f413a913
AM		 7912018-05-08 Alan Modra <amodra@gmail.com>
792
793 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
794 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
795 partition opcode space for index lookup.
796
a87a6478
PB		 7972018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
798
799 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
800 <insn_length>: ...with this. Update usage.
801 Remove duplicate call to *info->memory_error_func.
802
c0a30a9f
L		 8032018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
804 H.J. Lu <hongjiu.lu@intel.com>
805
806 * i386-dis.c (Gva): New.
807 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
808 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
809 (prefix_table): New instructions (see prefix above).
810 (mod_table): New instructions (see prefix above).
811 (OP_G): Handle va_mode.
812 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
813 CPU_MOVDIR64B_FLAGS.
814 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
815 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
816 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
817 * i386-opc.tbl: Add movidir{i,64b}.
818 * i386-init.h: Regenerated.
819 * i386-tbl.h: Likewise.
820
75c0a438
L		 8212018-05-07 H.J. Lu <hongjiu.lu@intel.com>
822
823 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
824 AddrPrefixOpReg.
825 * i386-opc.h (AddrPrefixOp0): Renamed to ...
826 (AddrPrefixOpReg): This.
827 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
828 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
829
2ceb7719
PB		 8302018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
831
832 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
833 (vle_num_opcodes): Likewise.
834 (spe2_num_opcodes): Likewise.
835 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
836 initialization loop.
837 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
838 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
839 only once.
840
b3ac5c6c
TC		 8412018-05-01 Tamar Christina <tamar.christina@arm.com>
842
843 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
844
fe944acf
FT		 8452018-04-30 Francois H. Theron <francois.theron@netronome.com>
846
847 Makefile.am: Added nfp-dis.c.
848 configure.ac: Added bfd_nfp_arch.
849 disassemble.h: Added print_insn_nfp prototype.
850 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
851 nfp-dis.c: New, for NFP support.
852 po/POTFILES.in: Added nfp-dis.c to the list.
853 Makefile.in: Regenerate.
854 configure: Regenerate.
855
e2195274
JB		 8562018-04-26 Jan Beulich <jbeulich@suse.com>
857
858 * i386-opc.tbl: Fold various non-memory operand AVX512VL
859 templates into their base ones.
860 * i386-tlb.h: Re-generate.
861
59ef5df4
JB		 8622018-04-26 Jan Beulich <jbeulich@suse.com>
863
864 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
865 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
866 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
867 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
868 * i386-init.h: Re-generate.
869
6e041cf4
JB		 8702018-04-26 Jan Beulich <jbeulich@suse.com>
871
872 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
873 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
874 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
875 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
876 comment.
877 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
878 and CpuRegMask.
879 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
880 CpuRegMask: Delete.
881 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
882 cpuregzmm, and cpuregmask.
883 * i386-init.h: Re-generate.
884 * i386-tbl.h: Re-generate.
885
0e0eea78
JB		 8862018-04-26 Jan Beulich <jbeulich@suse.com>
887
888 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
889 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
890 * i386-init.h: Re-generate.
891
2f1bada2
JB		 8922018-04-26 Jan Beulich <jbeulich@suse.com>
893
894 * i386-gen.c (VexImmExt): Delete.
895 * i386-opc.h (VexImmExt, veximmext): Delete.
896 * i386-opc.tbl: Drop all VexImmExt uses.
897 * i386-tlb.h: Re-generate.
898
bacd1457
JB		 8992018-04-25 Jan Beulich <jbeulich@suse.com>
900
901 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
902 register-only forms.
903 * i386-tlb.h: Re-generate.
904
10bba94b
TC		 9052018-04-25 Tamar Christina <tamar.christina@arm.com>
906
907 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
908
c48935d7
IT		 9092018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
910
911 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
912 PREFIX_0F1C.
913 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
914 (cpu_flags): Add CpuCLDEMOTE.
915 * i386-init.h: Regenerate.
916 * i386-opc.h (enum): Add CpuCLDEMOTE,
917 (i386_cpu_flags): Add cpucldemote.
918 * i386-opc.tbl: Add cldemote.
919 * i386-tbl.h: Regenerate.
920
211dc24b
AM		 9212018-04-16 Alan Modra <amodra@gmail.com>
922
923 * Makefile.am: Remove sh5 and sh64 support.
924 * configure.ac: Likewise.
925 * disassemble.c: Likewise.
926 * disassemble.h: Likewise.
927 * sh-dis.c: Likewise.
928 * sh64-dis.c: Delete.
929 * sh64-opc.c: Delete.
930 * sh64-opc.h: Delete.
931 * Makefile.in: Regenerate.
932 * configure: Regenerate.
933 * po/POTFILES.in: Regenerate.
934
a9a4b302
AM		 9352018-04-16 Alan Modra <amodra@gmail.com>
936
937 * Makefile.am: Remove w65 support.
938 * configure.ac: Likewise.
939 * disassemble.c: Likewise.
940 * disassemble.h: Likewise.
941 * w65-dis.c: Delete.
942 * w65-opc.h: Delete.
943 * Makefile.in: Regenerate.
944 * configure: Regenerate.
945 * po/POTFILES.in: Regenerate.
946
04cb01fd
AM		 9472018-04-16 Alan Modra <amodra@gmail.com>
948
949 * configure.ac: Remove we32k support.
950 * configure: Regenerate.
951
c2bf1eec
AM		 9522018-04-16 Alan Modra <amodra@gmail.com>
953
954 * Makefile.am: Remove m88k support.
955 * configure.ac: Likewise.
956 * disassemble.c: Likewise.
957 * disassemble.h: Likewise.
958 * m88k-dis.c: Delete.
959 * Makefile.in: Regenerate.
960 * configure: Regenerate.
961 * po/POTFILES.in: Regenerate.
962
6793974d
AM		 9632018-04-16 Alan Modra <amodra@gmail.com>
964
965 * Makefile.am: Remove i370 support.
966 * configure.ac: Likewise.
967 * disassemble.c: Likewise.
968 * disassemble.h: Likewise.
969 * i370-dis.c: Delete.
970 * i370-opc.c: Delete.
971 * Makefile.in: Regenerate.
972 * configure: Regenerate.
973 * po/POTFILES.in: Regenerate.
974
e82aa794
AM		 9752018-04-16 Alan Modra <amodra@gmail.com>
976
977 * Makefile.am: Remove h8500 support.
978 * configure.ac: Likewise.
979 * disassemble.c: Likewise.
980 * disassemble.h: Likewise.
981 * h8500-dis.c: Delete.
982 * h8500-opc.h: Delete.
983 * Makefile.in: Regenerate.
984 * configure: Regenerate.
985 * po/POTFILES.in: Regenerate.
986
fceadf09
AM		 9872018-04-16 Alan Modra <amodra@gmail.com>
988
989 * configure.ac: Remove tahoe support.
990 * configure: Regenerate.
991
ae1d3843
L		 9922018-04-15 H.J. Lu <hongjiu.lu@intel.com>
993
994 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
995 umwait.
996 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
997 64-bit mode.
998 * i386-tbl.h: Regenerated.
999
de89d0a3
IT		 10002018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1001
1002 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1003 PREFIX_MOD_1_0FAE_REG_6.
1004 (va_mode): New.
1005 (OP_E_register): Use va_mode.
1006 * i386-dis-evex.h (prefix_table):
1007 New instructions (see prefixes above).
1008 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1009 (cpu_flags): Likewise.
1010 * i386-opc.h (enum): Likewise.
1011 (i386_cpu_flags): Likewise.
1012 * i386-opc.tbl: Add umonitor, umwait, tpause.
1013 * i386-init.h: Regenerate.
1014 * i386-tbl.h: Likewise.
1015
a8eb42a8
AM		 10162018-04-11 Alan Modra <amodra@gmail.com>
1017
1018 * opcodes/i860-dis.c: Delete.
1019 * opcodes/i960-dis.c: Delete.
1020 * Makefile.am: Remove i860 and i960 support.
1021 * configure.ac: Likewise.
1022 * disassemble.c: Likewise.
1023 * disassemble.h: Likewise.
1024 * Makefile.in: Regenerate.
1025 * configure: Regenerate.
1026 * po/POTFILES.in: Regenerate.
1027
caf0678c
L		 10282018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1029
1030 PR binutils/23025
1031 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1032 to 0.
1033 (print_insn): Clear vex instead of vex.evex.
1034
4fb0d2b9
NC		 10352018-04-04 Nick Clifton <nickc@redhat.com>
1036
1037 * po/es.po: Updated Spanish translation.
1038
c39e5b26
JB		 10392018-03-28 Jan Beulich <jbeulich@suse.com>
1040
1041 * i386-gen.c (opcode_modifiers): Delete VecESize.
1042 * i386-opc.h (VecESize): Delete.
1043 (struct i386_opcode_modifier): Delete vecesize.
1044 * i386-opc.tbl: Drop VecESize.
1045 * i386-tlb.h: Re-generate.
1046
8e6e0792
JB		 10472018-03-28 Jan Beulich <jbeulich@suse.com>
1048
1049 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1050 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1051 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1052 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1053 * i386-tlb.h: Re-generate.
1054
9f123b91
JB		 10552018-03-28 Jan Beulich <jbeulich@suse.com>
1056
1057 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1058 Fold AVX512 forms
1059 * i386-tlb.h: Re-generate.
1060
9646c87b
JB		 10612018-03-28 Jan Beulich <jbeulich@suse.com>
1062
1063 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1064 (vex_len_table): Drop Y for vcvt*2si.
1065 (putop): Replace plain 'Y' handling by abort().
1066
c8d59609
NC		 10672018-03-28 Nick Clifton <nickc@redhat.com>
1068
1069 PR 22988
1070 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1071 instructions with only a base address register.
1072 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1073 handle AARHC64_OPND_SVE_ADDR_R.
1074 (aarch64_print_operand): Likewise.
1075 * aarch64-asm-2.c: Regenerate.
1076 * aarch64_dis-2.c: Regenerate.
1077 * aarch64-opc-2.c: Regenerate.
1078
b8c169f3
JB		 10792018-03-22 Jan Beulich <jbeulich@suse.com>
1080
1081 * i386-opc.tbl: Drop VecESize from register only insn forms and
1082 memory forms not allowing broadcast.
1083 * i386-tlb.h: Re-generate.
1084
96bc132a
JB		 10852018-03-22 Jan Beulich <jbeulich@suse.com>
1086
1087 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1088 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1089 sha256*): Drop Disp<N>.
1090
9f79e886
JB		 10912018-03-22 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-dis.c (EbndS, bnd_swap_mode): New.
1094 (prefix_table): Use EbndS.
1095 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1096 * i386-opc.tbl (bndmov): Move misplaced Load.
1097 * i386-tlb.h: Re-generate.
1098
d6793fa1
JB		 10992018-03-22 Jan Beulich <jbeulich@suse.com>
1100
1101 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1102 templates allowing memory operands and folded ones for register
1103 only flavors.
1104 * i386-tlb.h: Re-generate.
1105
f7768225
JB		 11062018-03-22 Jan Beulich <jbeulich@suse.com>
1107
1108 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1109 256-bit templates. Drop redundant leftover Disp<N>.
1110 * i386-tlb.h: Re-generate.
1111
0e35537d
JW		 11122018-03-14 Kito Cheng <kito.cheng@gmail.com>
1113
1114 * riscv-opc.c (riscv_insn_types): New.
1115
b4a3689a
NC		 11162018-03-13 Nick Clifton <nickc@redhat.com>
1117
1118 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1119
d3d50934
L		 11202018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1121
1122 * i386-opc.tbl: Add Optimize to clr.
1123 * i386-tbl.h: Regenerated.
1124
bd5dea88
L		 11252018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1126
1127 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1128 * i386-opc.h (OldGcc): Removed.
1129 (i386_opcode_modifier): Remove oldgcc.
1130 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1131 instructions for old (<= 2.8.1) versions of gcc.
1132 * i386-tbl.h: Regenerated.
1133
e771e7c9
JB		 11342018-03-08 Jan Beulich <jbeulich@suse.com>
1135
1136 * i386-opc.h (EVEXDYN): New.
1137 * i386-opc.tbl: Fold various AVX512VL templates.
1138 * i386-tlb.h: Re-generate.
1139
ed438a93
JB		 11402018-03-08 Jan Beulich <jbeulich@suse.com>
1141
1142 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1143 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1144 vpexpandd, vpexpandq): Fold AFX512VF templates.
1145 * i386-tlb.h: Re-generate.
1146
454172a9
JB		 11472018-03-08 Jan Beulich <jbeulich@suse.com>
1148
1149 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1150 Fold 128- and 256-bit VEX-encoded templates.
1151 * i386-tlb.h: Re-generate.
1152
36824150
JB		 11532018-03-08 Jan Beulich <jbeulich@suse.com>
1154
1155 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1156 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1157 vpexpandd, vpexpandq): Fold AVX512F templates.
1158 * i386-tlb.h: Re-generate.
1159
e7f5c0a9
JB		 11602018-03-08 Jan Beulich <jbeulich@suse.com>
1161
1162 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1163 64-bit templates. Drop Disp<N>.
1164 * i386-tlb.h: Re-generate.
1165
25a4277f
JB		 11662018-03-08 Jan Beulich <jbeulich@suse.com>
1167
1168 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1169 and 256-bit templates.
1170 * i386-tlb.h: Re-generate.
1171
d2224064
JB		 11722018-03-08 Jan Beulich <jbeulich@suse.com>
1173
1174 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1175 * i386-tlb.h: Re-generate.
1176
1b193f0b
JB		 11772018-03-08 Jan Beulich <jbeulich@suse.com>
1178
1179 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1180 Drop NoAVX.
1181 * i386-tlb.h: Re-generate.
1182
f2f6a710
JB		 11832018-03-08 Jan Beulich <jbeulich@suse.com>
1184
1185 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1186 * i386-tlb.h: Re-generate.
1187
38e314eb
JB		 11882018-03-08 Jan Beulich <jbeulich@suse.com>
1189
1190 * i386-gen.c (opcode_modifiers): Delete FloatD.
1191 * i386-opc.h (FloatD): Delete.
1192 (struct i386_opcode_modifier): Delete floatd.
1193 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1194 FloatD by D.
1195 * i386-tlb.h: Re-generate.
1196
d53e6b98
JB		 11972018-03-08 Jan Beulich <jbeulich@suse.com>
1198
1199 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1200
2907c2f5
JB		 12012018-03-08 Jan Beulich <jbeulich@suse.com>
1202
1203 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1204 * i386-tlb.h: Re-generate.
1205
73053c1f
JB		 12062018-03-08 Jan Beulich <jbeulich@suse.com>
1207
1208 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1209 forms.
1210 * i386-tlb.h: Re-generate.
1211
52fe4420
AM		 12122018-03-07 Alan Modra <amodra@gmail.com>
1213
1214 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1215 bfd_arch_rs6000.
1216 * disassemble.h (print_insn_rs6000): Delete.
1217 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1218 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1219 (print_insn_rs6000): Delete.
1220
a6743a54
AM		 12212018-03-03 Alan Modra <amodra@gmail.com>
1222
1223 * sysdep.h (opcodes_error_handler): Define.
1224 (_bfd_error_handler): Declare.
1225 * Makefile.am: Remove stray #.
1226 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1227 EDIT" comment.
1228 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1229 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1230 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1231 opcodes_error_handler to print errors. Standardize error messages.
1232 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1233 and include opintl.h.
1234 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1235 * i386-gen.c: Standardize error messages.
1236 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1237 * Makefile.in: Regenerate.
1238 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1239 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1240 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1241 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1242 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1243 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1244 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1245 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1246 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1247 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1248 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1249 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1250 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1251
8305403a
L		 12522018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1253
1254 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1255 vpsub[bwdq] instructions.
1256 * i386-tbl.h: Regenerated.
1257
e184813f
AM		 12582018-03-01 Alan Modra <amodra@gmail.com>
1259
1260 * configure.ac (ALL_LINGUAS): Sort.
1261 * configure: Regenerate.
1262
5b616bef
TP		 12632018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1264
1265 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1266 macro by assignements.
1267
b6f8c7c4
L		 12682018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1269
1270 PR gas/22871
1271 * i386-gen.c (opcode_modifiers): Add Optimize.
1272 * i386-opc.h (Optimize): New enum.
1273 (i386_opcode_modifier): Add optimize.
1274 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1275 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1276 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1277 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1278 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1279 vpxord and vpxorq.
1280 * i386-tbl.h: Regenerated.
1281
e95b887f
AM		 12822018-02-26 Alan Modra <amodra@gmail.com>
1283
1284 * crx-dis.c (getregliststring): Allocate a large enough buffer
1285 to silence false positive gcc8 warning.
1286
0bccfb29
JW		 12872018-02-22 Shea Levy <shea@shealevy.com>
1288
1289 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1290
6b6b6807
L		 12912018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1292
1293 * i386-opc.tbl: Add {rex},
1294 * i386-tbl.h: Regenerated.
1295
75f31665
MR		 12962018-02-20 Maciej W. Rozycki <macro@mips.com>
1297
1298 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1299 (mips16_opcodes): Replace `M' with `m' for "restore".
1300
e207bc53
TP		 13012018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1302
1303 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1304
87993319
MR		 13052018-02-13 Maciej W. Rozycki <macro@mips.com>
1306
1307 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1308 variable to `function_index'.
1309
68d20676
NC		 13102018-02-13 Nick Clifton <nickc@redhat.com>
1311
1312 PR 22823
1313 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1314 about truncation of printing.
1315
d2159fdc
HW		 13162018-02-12 Henry Wong <henry@stuffedcow.net>
1317
1318 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1319
f174ef9f
NC		 13202018-02-05 Nick Clifton <nickc@redhat.com>
1321
1322 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1323
be3a8dca
IT		 13242018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1325
1326 * i386-dis.c (enum): Add pconfig.
1327 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1328 (cpu_flags): Add CpuPCONFIG.
1329 * i386-opc.h (enum): Add CpuPCONFIG.
1330 (i386_cpu_flags): Add cpupconfig.
1331 * i386-opc.tbl: Add PCONFIG instruction.
1332 * i386-init.h: Regenerate.
1333 * i386-tbl.h: Likewise.
1334
3233d7d0
IT		 13352018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1336
1337 * i386-dis.c (enum): Add PREFIX_0F09.
1338 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1339 (cpu_flags): Add CpuWBNOINVD.
1340 * i386-opc.h (enum): Add CpuWBNOINVD.
1341 (i386_cpu_flags): Add cpuwbnoinvd.
1342 * i386-opc.tbl: Add WBNOINVD instruction.
1343 * i386-init.h: Regenerate.
1344 * i386-tbl.h: Likewise.
1345
e925c834
JW		 13462018-01-17 Jim Wilson <jimw@sifive.com>
1347
1348 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1349
d777820b
IT		 13502018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1351
1352 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1353 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1354 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1355 (cpu_flags): Add CpuIBT, CpuSHSTK.
1356 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1357 (i386_cpu_flags): Add cpuibt, cpushstk.
1358 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1359 * i386-init.h: Regenerate.
1360 * i386-tbl.h: Likewise.
1361
f6efed01
NC		 13622018-01-16 Nick Clifton <nickc@redhat.com>
1363
1364 * po/pt_BR.po: Updated Brazilian Portugese translation.
1365 * po/de.po: Updated German translation.
1366
2721d702
JW		 13672018-01-15 Jim Wilson <jimw@sifive.com>
1368
1369 * riscv-opc.c (match_c_nop): New.
1370 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1371
616dcb87
NC		 13722018-01-15 Nick Clifton <nickc@redhat.com>
1373
1374 * po/uk.po: Updated Ukranian translation.
1375
3957a496
NC		 13762018-01-13 Nick Clifton <nickc@redhat.com>
1377
1378 * po/opcodes.pot: Regenerated.
1379
769c7ea5
NC		 13802018-01-13 Nick Clifton <nickc@redhat.com>
1381
1382 * configure: Regenerate.
1383
faf766e3
NC		 13842018-01-13 Nick Clifton <nickc@redhat.com>
1385
1386 2.30 branch created.
1387
888a89da
IT		 13882018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1389
1390 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1391 * i386-tbl.h: Regenerate.
1392
cbda583a
JB		 13932018-01-10 Jan Beulich <jbeulich@suse.com>
1394
1395 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1396 * i386-tbl.h: Re-generate.
1397
c9e92278
JB		 13982018-01-10 Jan Beulich <jbeulich@suse.com>
1399
1400 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1401 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1402 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1403 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1404 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1405 Disp8MemShift of AVX512VL forms.
1406 * i386-tbl.h: Re-generate.
1407
35fd2b2b
JW		 14082018-01-09 Jim Wilson <jimw@sifive.com>
1409
1410 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1411 then the hi_addr value is zero.
1412
91d8b670
JG		 14132018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1414
1415 * arm-dis.c (arm_opcodes): Add csdb.
1416 (thumb32_opcodes): Add csdb.
1417
be2e7d95
JG		 14182018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1419
1420 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1421 * aarch64-asm-2.c: Regenerate.
1422 * aarch64-dis-2.c: Regenerate.
1423 * aarch64-opc-2.c: Regenerate.
1424
704a705d
L		 14252018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1426
1427 PR gas/22681
1428 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1429 Remove AVX512 vmovd with 64-bit operands.
1430 * i386-tbl.h: Regenerated.
1431
35eeb78f
JW		 14322018-01-05 Jim Wilson <jimw@sifive.com>
1433
1434 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1435 jalr.
1436
219d1afa
AM		 14372018-01-03 Alan Modra <amodra@gmail.com>
1438
1439 Update year range in copyright notice of all files.
1440
1508bbf5
JB		 14412018-01-02 Jan Beulich <jbeulich@suse.com>
1442
1443 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1444 and OPERAND_TYPE_REGZMM entries.
1445
1e563868 1446For older changes see ChangeLog-2017
3499769a 1447\f
1e563868 1448Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1449
1450Copying and distribution of this file, with or without modification,
1451are permitted in any medium without royalty provided the copyright
1452notice and this notice are preserved.
1453
1454Local Variables:
1455mode: change-log
1456left-margin: 8
1457fill-column: 74
1458version-control: never
1459End:
GDB Binutils - Deliverables
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