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ubsan: s12z: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
205c426a
AM		 12019-12-11 Alan Modra <amodra@gmail.com>
2
3 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
4
fb4cb4e2
AM		 52019-12-11 Alan Modra <amodra@gmail.com>
6
7 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
8 (bit_extract_simple, sign_extend): Likewise.
9
96f1f604
AM		 102019-12-11 Alan Modra <amodra@gmail.com>
11
12 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
13
8c9b4171
AM		 142019-12-11 Alan Modra <amodra@gmail.com>
15
16 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
17
334175b6
AM		 182019-12-11 Alan Modra <amodra@gmail.com>
19
20 * m68k-dis.c (COERCE32): Cast value first.
21 (NEXTLONG, NEXTULONG): Avoid signed overflow.
22
f8a87c78
AM		 232019-12-11 Alan Modra <amodra@gmail.com>
24
25 * h8300-dis.c (extract_immediate): Avoid signed overflow.
26 (bfd_h8_disassemble): Likewise.
27
159653d8
AM		 282019-12-11 Alan Modra <amodra@gmail.com>
29
30 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
31 past end of operands array.
32
d93bba9e
AM		 332019-12-11 Alan Modra <amodra@gmail.com>
34
35 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
36 overflow when collecting bytes of a number.
37
c202f69e
AM		 382019-12-11 Alan Modra <amodra@gmail.com>
39
40 * cris-dis.c (print_with_operands): Avoid signed integer
41 overflow when collecting bytes of a 32-bit integer.
42
0ef562a4
AM		 432019-12-11 Alan Modra <amodra@gmail.com>
44
45 * cr16-dis.c (EXTRACT, SBM): Rewrite.
46 (cr16_match_opcode): Delete duplicate bcond test.
47
2fd2b153
AM		 482019-12-11 Alan Modra <amodra@gmail.com>
49
50 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
51 (SIGNBIT): New.
52 (MASKBITS, SIGNEXTEND): Rewrite.
53 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
54 unsigned arithmetic, instead assign result of SIGNEXTEND back
55 to x.
56 (fmtconst_val): Use 1u in shift expression.
57
a11db3e9
AM		 582019-12-11 Alan Modra <amodra@gmail.com>
59
60 * arc-dis.c (find_format_from_table): Use ull constant when
61 shifting by up to 32.
62
9d48687b
AM		 632019-12-11 Alan Modra <amodra@gmail.com>
64
65 PR 25270
66 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
67 false when field is zero for sve_size_tsz_bhs.
68
b8e61daa
AM		 692019-12-11 Alan Modra <amodra@gmail.com>
70
71 * epiphany-ibld.c: Regenerate.
72
20135676
AM		 732019-12-10 Alan Modra <amodra@gmail.com>
74
75 PR 24960
76 * disassemble.c (disassemble_free_target): New function.
77
103ebbc3
AM		 782019-12-10 Alan Modra <amodra@gmail.com>
79
80 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
81 * disassemble.c (disassemble_init_for_target): Likewise.
82 * bpf-dis.c: Regenerate.
83 * epiphany-dis.c: Regenerate.
84 * fr30-dis.c: Regenerate.
85 * frv-dis.c: Regenerate.
86 * ip2k-dis.c: Regenerate.
87 * iq2000-dis.c: Regenerate.
88 * lm32-dis.c: Regenerate.
89 * m32c-dis.c: Regenerate.
90 * m32r-dis.c: Regenerate.
91 * mep-dis.c: Regenerate.
92 * mt-dis.c: Regenerate.
93 * or1k-dis.c: Regenerate.
94 * xc16x-dis.c: Regenerate.
95 * xstormy16-dis.c: Regenerate.
96
6f0e0752
AM		 972019-12-10 Alan Modra <amodra@gmail.com>
98
99 * ppc-dis.c (private): Delete variable.
100 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
101 (powerpc_init_dialect): Don't use global private.
102
e7c22a69
AM		 1032019-12-10 Alan Modra <amodra@gmail.com>
104
105 * s12z-opc.c: Formatting.
106
0a6aef6b
AM		 1072019-12-08 Alan Modra <amodra@gmail.com>
108
109 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
110 registers.
111
2dc4b12f
JB		 1122019-12-05 Jan Beulich <jbeulich@suse.com>
113
114 * aarch64-tbl.h (aarch64_feature_crypto,
115 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
116 CRYPTO_V8_2_INSN): Delete.
117
378fd436
AM		 1182019-12-05 Alan Modra <amodra@gmail.com>
119
120 PR 25249
121 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
122 (struct string_buf): New.
123 (strbuf): New function.
124 (get_field): Use strbuf rather than strdup of local temp.
125 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
126 (get_field_rfsl, get_field_imm15): Likewise.
127 (get_field_rd, get_field_r1, get_field_r2): Update macros.
128 (get_field_special): Likewise. Don't strcpy spr. Formatting.
129 (print_insn_microblaze): Formatting. Init and pass string_buf to
130 get_field functions.
131
0ba59a29
JB		 1322019-12-04 Jan Beulich <jbeulich@suse.com>
133
134 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
135 * i386-tbl.h: Re-generate.
136
77ad8092
JB		 1372019-12-04 Jan Beulich <jbeulich@suse.com>
138
139 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
140
3036c899
JB		 1412019-12-04 Jan Beulich <jbeulich@suse.com>
142
143 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
144 forms.
145 (xbegin): Drop DefaultSize.
146 * i386-tbl.h: Re-generate.
147
8b301fbb
MI		 1482019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
149
150 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
151 Change the coproc CRC conditions to use the extension
152 feature set, second word, base on ARM_EXT2_CRC.
153
6aa385b9
JB		 1542019-11-14 Jan Beulich <jbeulich@suse.com>
155
156 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
157 * i386-tbl.h: Re-generate.
158
0cfa3eb3
JB		 1592019-11-14 Jan Beulich <jbeulich@suse.com>
160
161 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
162 JumpInterSegment, and JumpAbsolute entries.
163 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
164 JUMP_ABSOLUTE): Define.
165 (struct i386_opcode_modifier): Extend jump field to 3 bits.
166 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
167 fields.
168 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
169 JumpInterSegment): Define.
170 * i386-tbl.h: Re-generate.
171
6f2f06be
JB		 1722019-11-14 Jan Beulich <jbeulich@suse.com>
173
174 * i386-gen.c (operand_type_init): Remove
175 OPERAND_TYPE_JUMPABSOLUTE entry.
176 (opcode_modifiers): Add JumpAbsolute entry.
177 (operand_types): Remove JumpAbsolute entry.
178 * i386-opc.h (JumpAbsolute): Move between enums.
179 (struct i386_opcode_modifier): Add jumpabsolute field.
180 (union i386_operand_type): Remove jumpabsolute field.
181 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
182 * i386-init.h, i386-tbl.h: Re-generate.
183
601e8564
JB		 1842019-11-14 Jan Beulich <jbeulich@suse.com>
185
186 * i386-gen.c (opcode_modifiers): Add AnySize entry.
187 (operand_types): Remove AnySize entry.
188 * i386-opc.h (AnySize): Move between enums.
189 (struct i386_opcode_modifier): Add anysize field.
190 (OTUnused): Un-comment.
191 (union i386_operand_type): Remove anysize field.
192 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
193 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
194 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
195 AnySize.
196 * i386-tbl.h: Re-generate.
197
7722d40a
JW		 1982019-11-12 Nelson Chu <nelson.chu@sifive.com>
199
200 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
201 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
202 use the floating point register (FPR).
203
ce760a76
MI		 2042019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
205
206 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
207 cmode 1101.
208 (is_mve_encoding_conflict): Update cmode conflict checks for
209 MVE_VMVN_IMM.
210
51c8edf6
JB		 2112019-11-12 Jan Beulich <jbeulich@suse.com>
212
213 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
214 entry.
215 (operand_types): Remove EsSeg entry.
216 (main): Replace stale use of OTMax.
217 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
218 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
219 (EsSeg): Delete.
220 (OTUnused): Comment out.
221 (union i386_operand_type): Remove esseg field.
222 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
223 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
224 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
225 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
226 * i386-init.h, i386-tbl.h: Re-generate.
227
474da251
JB		 2282019-11-12 Jan Beulich <jbeulich@suse.com>
229
230 * i386-gen.c (operand_instances): Add RegB entry.
231 * i386-opc.h (enum operand_instance): Add RegB.
232 * i386-opc.tbl (RegC, RegD, RegB): Define.
233 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
234 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
235 monitorx, mwaitx): Drop ImmExt and convert encodings
236 accordingly.
237 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
238 (edx, rdx): Add Instance=RegD.
239 (ebx, rbx): Add Instance=RegB.
240 * i386-tbl.h: Re-generate.
241
75e5731b
JB		 2422019-11-12 Jan Beulich <jbeulich@suse.com>
243
244 * i386-gen.c (operand_type_init): Adjust
245 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
246 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
247 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
248 (operand_instances): New.
249 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
250 (output_operand_type): New parameter "instance". Process it.
251 (process_i386_operand_type): New local variable "instance".
252 (main): Adjust static assertions.
253 * i386-opc.h (INSTANCE_WIDTH): Define.
254 (enum operand_instance): New.
255 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
256 (union i386_operand_type): Replace acc, inoutportreg, and
257 shiftcount by instance.
258 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
259 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
260 Add Instance=.
261 * i386-init.h, i386-tbl.h: Re-generate.
262
91802f3c
JB		 2632019-11-11 Jan Beulich <jbeulich@suse.com>
264
265 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
266 smaxp/sminp entries' "tied_operand" field to 2.
267
4f5fc85d
JB		 2682019-11-11 Jan Beulich <jbeulich@suse.com>
269
270 * aarch64-opc.c (operand_general_constraint_met_p): Replace
271 "index" local variable by that of the already existing "num".
272
dc2be329
L		 2732019-11-08 H.J. Lu <hongjiu.lu@intel.com>
274
275 PR gas/25167
276 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
277 * i386-tbl.h: Regenerated.
278
f74a6307
JB		 2792019-11-08 Jan Beulich <jbeulich@suse.com>
280
281 * i386-gen.c (operand_type_init): Add Class= to
282 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
283 OPERAND_TYPE_REGBND entry.
284 (operand_classes): Add RegMask and RegBND entries.
285 (operand_types): Drop RegMask and RegBND entry.
286 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
287 (RegMask, RegBND): Delete.
288 (union i386_operand_type): Remove regmask and regbnd fields.
289 * i386-opc.tbl (RegMask, RegBND): Define.
290 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
291 Class=RegBND.
292 * i386-init.h, i386-tbl.h: Re-generate.
293
3528c362
JB		 2942019-11-08 Jan Beulich <jbeulich@suse.com>
295
296 * i386-gen.c (operand_type_init): Add Class= to
297 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
298 OPERAND_TYPE_REGZMM entries.
299 (operand_classes): Add RegMMX and RegSIMD entries.
300 (operand_types): Drop RegMMX and RegSIMD entries.
301 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
302 (RegMMX, RegSIMD): Delete.
303 (union i386_operand_type): Remove regmmx and regsimd fields.
304 * i386-opc.tbl (RegMMX): Define.
305 (RegXMM, RegYMM, RegZMM): Add Class=.
306 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
307 Class=RegSIMD.
308 * i386-init.h, i386-tbl.h: Re-generate.
309
4a5c67ed
JB		 3102019-11-08 Jan Beulich <jbeulich@suse.com>
311
312 * i386-gen.c (operand_type_init): Add Class= to
313 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
314 entries.
315 (operand_classes): Add RegCR, RegDR, and RegTR entries.
316 (operand_types): Drop Control, Debug, and Test entries.
317 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
318 (Control, Debug, Test): Delete.
319 (union i386_operand_type): Remove control, debug, and test
320 fields.
321 * i386-opc.tbl (Control, Debug, Test): Define.
322 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
323 Class=RegDR, and Test by Class=RegTR.
324 * i386-init.h, i386-tbl.h: Re-generate.
325
00cee14f
JB		 3262019-11-08 Jan Beulich <jbeulich@suse.com>
327
328 * i386-gen.c (operand_type_init): Add Class= to
329 OPERAND_TYPE_SREG entry.
330 (operand_classes): Add SReg entry.
331 (operand_types): Drop SReg entry.
332 * i386-opc.h (enum operand_class): Add SReg.
333 (SReg): Delete.
334 (union i386_operand_type): Remove sreg field.
335 * i386-opc.tbl (SReg): Define.
336 * i386-reg.tbl: Replace SReg by Class=SReg.
337 * i386-init.h, i386-tbl.h: Re-generate.
338
bab6aec1
JB		 3392019-11-08 Jan Beulich <jbeulich@suse.com>
340
341 * i386-gen.c (operand_type_init): Add Class=. New
342 OPERAND_TYPE_ANYIMM entry.
343 (operand_classes): New.
344 (operand_types): Drop Reg entry.
345 (output_operand_type): New parameter "class". Process it.
346 (process_i386_operand_type): New local variable "class".
347 (main): Adjust static assertions.
348 * i386-opc.h (CLASS_WIDTH): Define.
349 (enum operand_class): New.
350 (Reg): Replace by Class. Adjust comment.
351 (union i386_operand_type): Replace reg by class.
352 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
353 Class=.
354 * i386-reg.tbl: Replace Reg by Class=Reg.
355 * i386-init.h: Re-generate.
356
1f4cd317
MM		 3572019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
358
359 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
360 (aarch64_opcode_table): Add data gathering hint mnemonic.
361 * opcodes/aarch64-dis-2.c: Account for new instruction.
362
616ce08e
MM		 3632019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
364
365 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
366
367
8382113f
MM		 3682019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
369
370 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
371 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
372 aarch64_feature_f64mm): New feature sets.
373 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
374 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
375 instructions.
376 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
377 macros.
378 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
379 (OP_SVE_QQQ): New qualifier.
380 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
381 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
382 the movprfx constraint.
383 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
384 (aarch64_opcode_table): Define new instructions smmla,
385 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
386 uzip{1/2}, trn{1/2}.
387 * aarch64-opc.c (operand_general_constraint_met_p): Handle
388 AARCH64_OPND_SVE_ADDR_RI_S4x32.
389 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
390 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
391 Account for new instructions.
392 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
393 S4x32 operand.
394 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
395
aab2c27d
MM		 3962019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3972019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
398
399 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
400 Armv8.6-A.
401 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
402 (neon_opcodes): Add bfloat SIMD instructions.
403 (print_insn_coprocessor): Add new control character %b to print
404 condition code without checking cp_num.
405 (print_insn_neon): Account for BFloat16 instructions that have no
406 special top-byte handling.
407
33593eaf
MM		 4082019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4092019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
410
411 * arm-dis.c (print_insn_coprocessor,
412 print_insn_generic_coprocessor): Create wrapper functions around
413 the implementation of the print_insn_coprocessor control codes.
414 (print_insn_coprocessor_1): Original print_insn_coprocessor
415 function that now takes which array to look at as an argument.
416 (print_insn_arm): Use both print_insn_coprocessor and
417 print_insn_generic_coprocessor.
418 (print_insn_thumb32): As above.
419
df678013
MM		 4202019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4212019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
422
423 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
424 in reglane special case.
425 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
426 aarch64_find_next_opcode): Account for new instructions.
427 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
428 in reglane special case.
429 * aarch64-opc.c (struct operand_qualifier_data): Add data for
430 new AARCH64_OPND_QLF_S_2H qualifier.
431 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
432 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
433 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
434 sets.
435 (BFLOAT_SVE, BFLOAT): New feature set macros.
436 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
437 instructions.
438 (aarch64_opcode_table): Define new instructions bfdot,
439 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
440 bfcvtn2, bfcvt.
441
8ae2d3d9
MM		 4422019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4432019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
444
445 * aarch64-tbl.h (ARMV8_6): New macro.
446
142861df
JB		 4472019-11-07 Jan Beulich <jbeulich@suse.com>
448
449 * i386-dis.c (prefix_table): Add mcommit.
450 (rm_table): Add rdpru.
451 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
452 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
453 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
454 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
455 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
456 * i386-opc.tbl (mcommit, rdpru): New.
457 * i386-init.h, i386-tbl.h: Re-generate.
458
081e283f
JB		 4592019-11-07 Jan Beulich <jbeulich@suse.com>
460
461 * i386-dis.c (OP_Mwait): Drop local variable "names", use
462 "names32" instead.
463 (OP_Monitor): Drop local variable "op1_names", re-purpose
464 "names" for it instead, and replace former "names" uses by
465 "names32" ones.
466
c050c89a
JB		 4672019-11-07 Jan Beulich <jbeulich@suse.com>
468
469 PR/gas 25167
470 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
471 operand-less forms.
472 * opcodes/i386-tbl.h: Re-generate.
473
7abb8d81
JB		 4742019-11-05 Jan Beulich <jbeulich@suse.com>
475
476 * i386-dis.c (OP_Mwaitx): Delete.
477 (prefix_table): Use OP_Mwait for mwaitx entry.
478 (OP_Mwait): Also handle mwaitx.
479
267b8516
JB		 4802019-11-05 Jan Beulich <jbeulich@suse.com>
481
482 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
483 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
484 (prefix_table): Add respective entries.
485 (rm_table): Link to those entries.
486
f8687e93
JB		 4872019-11-05 Jan Beulich <jbeulich@suse.com>
488
489 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
490 (REG_0F1C_P_0_MOD_0): ... this.
491 (REG_0F1E_MOD_3): Rename to ...
492 (REG_0F1E_P_1_MOD_3): ... this.
493 (RM_0F01_REG_5): Rename to ...
494 (RM_0F01_REG_5_MOD_3): ... this.
495 (RM_0F01_REG_7): Rename to ...
496 (RM_0F01_REG_7_MOD_3): ... this.
497 (RM_0F1E_MOD_3_REG_7): Rename to ...
498 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
499 (RM_0FAE_REG_6): Rename to ...
500 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
501 (RM_0FAE_REG_7): Rename to ...
502 (RM_0FAE_REG_7_MOD_3): ... this.
503 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
504 (PREFIX_0F01_REG_5_MOD_0): ... this.
505 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
506 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
507 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
508 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
509 (PREFIX_0FAE_REG_0): Rename to ...
510 (PREFIX_0FAE_REG_0_MOD_3): ... this.
511 (PREFIX_0FAE_REG_1): Rename to ...
512 (PREFIX_0FAE_REG_1_MOD_3): ... this.
513 (PREFIX_0FAE_REG_2): Rename to ...
514 (PREFIX_0FAE_REG_2_MOD_3): ... this.
515 (PREFIX_0FAE_REG_3): Rename to ...
516 (PREFIX_0FAE_REG_3_MOD_3): ... this.
517 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
518 (PREFIX_0FAE_REG_4_MOD_0): ... this.
519 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
520 (PREFIX_0FAE_REG_4_MOD_3): ... this.
521 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
522 (PREFIX_0FAE_REG_5_MOD_0): ... this.
523 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
524 (PREFIX_0FAE_REG_5_MOD_3): ... this.
525 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
526 (PREFIX_0FAE_REG_6_MOD_0): ... this.
527 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
528 (PREFIX_0FAE_REG_6_MOD_3): ... this.
529 (PREFIX_0FAE_REG_7): Rename to ...
530 (PREFIX_0FAE_REG_7_MOD_0): ... this.
531 (PREFIX_MOD_0_0FC3): Rename to ...
532 (PREFIX_0FC3_MOD_0): ... this.
533 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
534 (PREFIX_0FC7_REG_6_MOD_0): ... this.
535 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
536 (PREFIX_0FC7_REG_6_MOD_3): ... this.
537 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
538 (PREFIX_0FC7_REG_7_MOD_3): ... this.
539 (reg_table, prefix_table, mod_table, rm_table): Adjust
540 accordingly.
541
5103274f
NC		 5422019-11-04 Nick Clifton <nickc@redhat.com>
543
544 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
545 of a v850 system register. Move the v850_sreg_names array into
546 this function.
547 (get_v850_reg_name): Likewise for ordinary register names.
548 (get_v850_vreg_name): Likewise for vector register names.
549 (get_v850_cc_name): Likewise for condition codes.
550 * get_v850_float_cc_name): Likewise for floating point condition
551 codes.
552 (get_v850_cacheop_name): Likewise for cache-ops.
553 (get_v850_prefop_name): Likewise for pref-ops.
554 (disassemble): Use the new accessor functions.
555
1820262b
DB		 5562019-10-30 Delia Burduv <delia.burduv@arm.com>
557
558 * aarch64-opc.c (print_immediate_offset_address): Don't print the
559 immediate for the writeback form of ldraa/ldrab if it is 0.
560 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
561 * aarch64-opc-2.c: Regenerated.
562
3cc17af5
JB		 5632019-10-30 Jan Beulich <jbeulich@suse.com>
564
565 * i386-gen.c (operand_type_shorthands): Delete.
566 (operand_type_init): Expand previous shorthands.
567 (set_bitfield_from_shorthand): Rename back to ...
568 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
569 of operand_type_init[].
570 (set_bitfield): Adjust call to the above function.
571 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
572 RegXMM, RegYMM, RegZMM): Define.
573 * i386-reg.tbl: Expand prior shorthands.
574
a2cebd03
JB		 5752019-10-30 Jan Beulich <jbeulich@suse.com>
576
577 * i386-gen.c (output_i386_opcode): Change order of fields
578 emitted to output.
579 * i386-opc.h (struct insn_template): Move operands field.
580 Convert extension_opcode field to unsigned short.
581 * i386-tbl.h: Re-generate.
582
507916b8
JB		 5832019-10-30 Jan Beulich <jbeulich@suse.com>
584
585 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
586 of W.
587 * i386-opc.h (W): Extend comment.
588 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
589 general purpose variants not allowing for byte operands.
590 * i386-tbl.h: Re-generate.
591
efea62b4
NC		 5922019-10-29 Nick Clifton <nickc@redhat.com>
593
594 * tic30-dis.c (print_branch): Correct size of operand array.
595
9adb2591
NC		 5962019-10-29 Nick Clifton <nickc@redhat.com>
597
598 * d30v-dis.c (print_insn): Check that operand index is valid
599 before attempting to access the operands array.
600
993a00a9
NC		 6012019-10-29 Nick Clifton <nickc@redhat.com>
602
603 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
604 locating the bit to be tested.
605
66a66a17
NC		 6062019-10-29 Nick Clifton <nickc@redhat.com>
607
608 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
609 values.
610 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
611 (print_insn_s12z): Check for illegal size values.
612
1ee3542c
NC		 6132019-10-28 Nick Clifton <nickc@redhat.com>
614
615 * csky-dis.c (csky_chars_to_number): Check for a negative
616 count. Use an unsigned integer to construct the return value.
617
bbf9a0b5
NC		 6182019-10-28 Nick Clifton <nickc@redhat.com>
619
620 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
621 operand buffer. Set value to 15 not 13.
622 (get_register_operand): Use OPERAND_BUFFER_LEN.
623 (get_indirect_operand): Likewise.
624 (print_two_operand): Likewise.
625 (print_three_operand): Likewise.
626 (print_oar_insn): Likewise.
627
d1e304bc
NC		 6282019-10-28 Nick Clifton <nickc@redhat.com>
629
630 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
631 (bit_extract_simple): Likewise.
632 (bit_copy): Likewise.
633 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
634 index_offset array are not accessed.
635
dee33451
NC		 6362019-10-28 Nick Clifton <nickc@redhat.com>
637
638 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
639 operand.
640
27cee81d
NC		 6412019-10-25 Nick Clifton <nickc@redhat.com>
642
643 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
644 access to opcodes.op array element.
645
de6d8dc2
NC		 6462019-10-23 Nick Clifton <nickc@redhat.com>
647
648 * rx-dis.c (get_register_name): Fix spelling typo in error
649 message.
650 (get_condition_name, get_flag_name, get_double_register_name)
651 (get_double_register_high_name, get_double_register_low_name)
652 (get_double_control_register_name, get_double_condition_name)
653 (get_opsize_name, get_size_name): Likewise.
654
6207ed28
NC		 6552019-10-22 Nick Clifton <nickc@redhat.com>
656
657 * rx-dis.c (get_size_name): New function. Provides safe
658 access to name array.
659 (get_opsize_name): Likewise.
660 (print_insn_rx): Use the accessor functions.
661
12234dfd
NC		 6622019-10-16 Nick Clifton <nickc@redhat.com>
663
664 * rx-dis.c (get_register_name): New function. Provides safe
665 access to name array.
666 (get_condition_name, get_flag_name, get_double_register_name)
667 (get_double_register_high_name, get_double_register_low_name)
668 (get_double_control_register_name, get_double_condition_name):
669 Likewise.
670 (print_insn_rx): Use the accessor functions.
671
1d378749
NC		 6722019-10-09 Nick Clifton <nickc@redhat.com>
673
674 PR 25041
675 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
676 instructions.
677
d241b910
JB		 6782019-10-07 Jan Beulich <jbeulich@suse.com>
679
680 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
681 (cmpsd): Likewise. Move EsSeg to other operand.
682 * opcodes/i386-tbl.h: Re-generate.
683
f5c5b7c1
AM		 6842019-09-23 Alan Modra <amodra@gmail.com>
685
686 * m68k-dis.c: Include cpu-m68k.h
687
7beeaeb8
AM		 6882019-09-23 Alan Modra <amodra@gmail.com>
689
690 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
691 "elf/mips.h" earlier.
692
3f9aad11
JB		 6932018-09-20 Jan Beulich <jbeulich@suse.com>
694
695 PR gas/25012
696 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
697 with SReg operand.
698 * i386-tbl.h: Re-generate.
699
fd361982
AM		 7002019-09-18 Alan Modra <amodra@gmail.com>
701
702 * arc-ext.c: Update throughout for bfd section macro changes.
703
e0b2a78c
SM		 7042019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
705
706 * Makefile.in: Re-generate.
707 * configure: Re-generate.
708
7e9ad3a3
JW		 7092019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
710
711 * riscv-opc.c (riscv_opcodes): Change subset field
712 to insn_class field for all instructions.
713 (riscv_insn_types): Likewise.
714
bb695960
PB		 7152019-09-16 Phil Blundell <pb@pbcl.net>
716
717 * configure: Regenerated.
718
8063ab7e
MV		 7192019-09-10 Miod Vallat <miod@online.fr>
720
721 PR 24982
722 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
723
60391a25
PB		 7242019-09-09 Phil Blundell <pb@pbcl.net>
725
726 binutils 2.33 branch created.
727
f44b758d
NC		 7282019-09-03 Nick Clifton <nickc@redhat.com>
729
730 PR 24961
731 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
732 greater than zero before indexing via (bufcnt -1).
733
1e4b5e7d
NC		 7342019-09-03 Nick Clifton <nickc@redhat.com>
735
736 PR 24958
737 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
738 (MAX_SPEC_REG_NAME_LEN): Define.
739 (struct mmix_dis_info): Use defined constants for array lengths.
740 (get_reg_name): New function.
741 (get_sprec_reg_name): New function.
742 (print_insn_mmix): Use new functions.
743
c4a23bf8
SP		 7442019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
745
746 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
747 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
748 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
749
a051e2f3
KT		 7502019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
751
752 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
753 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
754 (aarch64_sys_reg_supported_p): Update checks for the above.
755
08132bdd
SP		 7562019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
757
758 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
759 cases MVE_SQRSHRL and MVE_UQRSHLL.
760 (print_insn_mve): Add case for specifier 'k' to check
761 specific bit of the instruction.
762
d88bdcb4
PA		 7632019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
764
765 PR 24854
766 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
767 encountering an unknown machine type.
768 (print_insn_arc): Handle arc_insn_length returning 0. In error
769 cases return -1 rather than calling abort.
770
bc750500
JB		 7712019-08-07 Jan Beulich <jbeulich@suse.com>
772
773 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
774 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
775 IgnoreSize.
776 * i386-tbl.h: Re-generate.
777
23d188c7
BW		 7782019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
779
780 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
781 instructions.
782
c0d6f62f
JW		 7832019-07-30 Mel Chen <mel.chen@sifive.com>
784
785 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
786 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
787
788 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
789 fscsr.
790
0f3f7167
CZ		 7912019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
792
793 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
794 and MPY class instructions.
795 (parse_option): Add nps400 option.
796 (print_arc_disassembler_options): Add nps400 info.
797
7e126ba3
CZ		 7982019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
799
800 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
801 (bspop): Likewise.
802 (modapp): Likewise.
803 * arc-opc.c (RAD_CHK): Add.
804 * arc-tbl.h: Regenerate.
805
a028026d
KT		 8062019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
807
808 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
809 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
810
ac79ff9e
NC		 8112019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
812
813 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
814 instructions as UNPREDICTABLE.
815
231097b0
JM		 8162019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
817
818 * bpf-desc.c: Regenerated.
819
1d942ae9
JB		 8202019-07-17 Jan Beulich <jbeulich@suse.com>
821
822 * i386-gen.c (static_assert): Define.
823 (main): Use it.
824 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
825 (Opcode_Modifier_Num): ... this.
826 (Mem): Delete.
827
dfd69174
JB		 8282019-07-16 Jan Beulich <jbeulich@suse.com>
829
830 * i386-gen.c (operand_types): Move RegMem ...
831 (opcode_modifiers): ... here.
832 * i386-opc.h (RegMem): Move to opcode modifer enum.
833 (union i386_operand_type): Move regmem field ...
834 (struct i386_opcode_modifier): ... here.
835 * i386-opc.tbl (RegMem): Define.
836 (mov, movq): Move RegMem on segment, control, debug, and test
837 register flavors.
838 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
839 to non-SSE2AVX flavor.
840 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
841 Move RegMem on register only flavors. Drop IgnoreSize from
842 legacy encoding flavors.
843 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
844 flavors.
845 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
846 register only flavors.
847 (vmovd): Move RegMem and drop IgnoreSize on register only
848 flavor. Change opcode and operand order to store form.
849 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
850
21df382b
JB		 8512019-07-16 Jan Beulich <jbeulich@suse.com>
852
853 * i386-gen.c (operand_type_init, operand_types): Replace SReg
854 entries.
855 * i386-opc.h (SReg2, SReg3): Replace by ...
856 (SReg): ... this.
857 (union i386_operand_type): Replace sreg fields.
858 * i386-opc.tbl (mov, ): Use SReg.
859 (push, pop): Likewies. Drop i386 and x86-64 specific segment
860 register flavors.
861 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
862 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
863
3719fd55
JM		 8642019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
865
866 * bpf-desc.c: Regenerate.
867 * bpf-opc.c: Likewise.
868 * bpf-opc.h: Likewise.
869
92434a14
JM		 8702019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
871
872 * bpf-desc.c: Regenerate.
873 * bpf-opc.c: Likewise.
874
43dd7626
HPN		 8752019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
876
877 * arm-dis.c (print_insn_coprocessor): Rename index to
878 index_operand.
879
98602811
JW		 8802019-07-05 Kito Cheng <kito.cheng@sifive.com>
881
882 * riscv-opc.c (riscv_insn_types): Add r4 type.
883
884 * riscv-opc.c (riscv_insn_types): Add b and j type.
885
886 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
887 format for sb type and correct s type.
888
01c1ee4a
RS		 8892019-07-02 Richard Sandiford <richard.sandiford@arm.com>
890
891 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
892 SVE FMOV alias of FCPY.
893
83adff69
RS		 8942019-07-02 Richard Sandiford <richard.sandiford@arm.com>
895
896 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
897 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
898
89418844
RS		 8992019-07-02 Richard Sandiford <richard.sandiford@arm.com>
900
901 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
902 registers in an instruction prefixed by MOVPRFX.
903
41be57ca
MM		 9042019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
905
906 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
907 sve_size_13 icode to account for variant behaviour of
908 pmull{t,b}.
909 * aarch64-dis-2.c: Regenerate.
910 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
911 sve_size_13 icode to account for variant behaviour of
912 pmull{t,b}.
913 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
914 (OP_SVE_VVV_Q_D): Add new qualifier.
915 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
916 (struct aarch64_opcode): Split pmull{t,b} into those requiring
917 AES and those not.
918
9d3bf266
JB		 9192019-07-01 Jan Beulich <jbeulich@suse.com>
920
921 * opcodes/i386-gen.c (operand_type_init): Remove
922 OPERAND_TYPE_VEC_IMM4 entry.
923 (operand_types): Remove Vec_Imm4.
924 * opcodes/i386-opc.h (Vec_Imm4): Delete.
925 (union i386_operand_type): Remove vec_imm4.
926 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
927 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
928
c3949f43
JB		 9292019-07-01 Jan Beulich <jbeulich@suse.com>
930
931 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
932 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
933 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
934 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
935 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
936 monitorx, mwaitx): Drop ImmExt from operand-less forms.
937 * i386-tbl.h: Re-generate.
938
5641ec01
JB		 9392019-07-01 Jan Beulich <jbeulich@suse.com>
940
941 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
942 register operands.
943 * i386-tbl.h: Re-generate.
944
79dec6b7
JB		 9452019-07-01 Jan Beulich <jbeulich@suse.com>
946
947 * i386-opc.tbl (C): New.
948 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
949 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
950 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
951 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
952 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
953 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
954 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
955 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
956 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
957 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
958 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
959 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
960 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
961 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
962 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
963 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
964 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
965 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
966 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
967 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
968 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
969 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
970 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
971 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
972 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
973 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
974 flavors.
975 * i386-tbl.h: Re-generate.
976
a0a1771e
JB		 9772019-07-01 Jan Beulich <jbeulich@suse.com>
978
979 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
980 register operands.
981 * i386-tbl.h: Re-generate.
982
cd546e7b
JB		 9832019-07-01 Jan Beulich <jbeulich@suse.com>
984
985 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
986 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
987 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
988 * i386-tbl.h: Re-generate.
989
e3bba3fc
JB		 9902019-07-01 Jan Beulich <jbeulich@suse.com>
991
992 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
993 Disp8MemShift from register only templates.
994 * i386-tbl.h: Re-generate.
995
36cc073e
JB		 9962019-07-01 Jan Beulich <jbeulich@suse.com>
997
998 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
999 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1000 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1001 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1002 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1003 EVEX_W_0F11_P_3_M_1): Delete.
1004 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1005 EVEX_W_0F11_P_3): New.
1006 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1007 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1008 MOD_EVEX_0F11_PREFIX_3 table entries.
1009 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1010 PREFIX_EVEX_0F11 table entries.
1011 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1012 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1013 EVEX_W_0F11_P_3_M_{0,1} table entries.
1014
219920a7
JB		 10152019-07-01 Jan Beulich <jbeulich@suse.com>
1016
1017 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1018 Delete.
1019
e395f487
L		 10202019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1021
1022 PR binutils/24719
1023 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1024 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1025 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1026 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1027 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1028 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1029 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1030 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1031 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1032 PREFIX_EVEX_0F38C6_REG_6 entries.
1033 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1034 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1035 EVEX_W_0F38C7_R_6_P_2 entries.
1036 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1037 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1038 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1039 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1040 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1041 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1042 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1043
2b7bcc87
JB		 10442019-06-27 Jan Beulich <jbeulich@suse.com>
1045
1046 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1047 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1048 VEX_LEN_0F2D_P_3): Delete.
1049 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1050 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1051 (prefix_table): ... here.
1052
c1dc7af5
JB		 10532019-06-27 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-dis.c (Iq): Delete.
1056 (Id): New.
1057 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1058 TBM insns.
1059 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1060 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1061 (OP_E_memory): Also honor needindex when deciding whether an
1062 address size prefix needs printing.
1063 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1064
d7560e2d
JW		 10652019-06-26 Jim Wilson <jimw@sifive.com>
1066
1067 PR binutils/24739
1068 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1069 Set info->display_endian to info->endian_code.
1070
2c703856
JB		 10712019-06-25 Jan Beulich <jbeulich@suse.com>
1072
1073 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1074 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1075 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1076 OPERAND_TYPE_ACC64 entries.
1077 * i386-init.h: Re-generate.
1078
54fbadc0
JB		 10792019-06-25 Jan Beulich <jbeulich@suse.com>
1080
1081 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1082 Delete.
1083 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1084 of dqa_mode.
1085 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1086 entries here.
1087 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1088 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1089
a280ab8e
JB		 10902019-06-25 Jan Beulich <jbeulich@suse.com>
1091
1092 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1093 variables.
1094
e1a1babd
JB		 10952019-06-25 Jan Beulich <jbeulich@suse.com>
1096
1097 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1098 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1099 movnti.
d7560e2d 1100 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1101 * i386-tbl.h: Re-generate.
1102
b8364fa7
JB		 11032019-06-25 Jan Beulich <jbeulich@suse.com>
1104
1105 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1106 * i386-tbl.h: Re-generate.
1107
ad692897
L		 11082019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1109
1110 * i386-dis-evex.h: Break into ...
1111 * i386-dis-evex-len.h: New file.
1112 * i386-dis-evex-mod.h: Likewise.
1113 * i386-dis-evex-prefix.h: Likewise.
1114 * i386-dis-evex-reg.h: Likewise.
1115 * i386-dis-evex-w.h: Likewise.
1116 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1117 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1118 i386-dis-evex-mod.h.
1119
f0a6222e
L		 11202019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1121
1122 PR binutils/24700
1123 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1124 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1125 EVEX_W_0F385B_P_2.
1126 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1127 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1128 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1129 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1130 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1131 EVEX_LEN_0F385B_P_2_W_1.
1132 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1133 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1134 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1135 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1136 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1137 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1138 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1139 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1140 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1141 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1142
6e1c90b7
L		 11432019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1144
1145 PR binutils/24691
1146 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1147 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1148 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1149 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1150 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1151 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1152 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1153 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1154 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1155 EVEX_LEN_0F3A43_P_2_W_1.
1156 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1157 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1158 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1159 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1160 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1161 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1162 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1163 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1164 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1165 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1166 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1167 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1168
bcc5a6eb
NC		 11692019-06-14 Nick Clifton <nickc@redhat.com>
1170
1171 * po/fr.po; Updated French translation.
1172
e4c4ac46
SH		 11732019-06-13 Stafford Horne <shorne@gmail.com>
1174
1175 * or1k-asm.c: Regenerated.
1176 * or1k-desc.c: Regenerated.
1177 * or1k-desc.h: Regenerated.
1178 * or1k-dis.c: Regenerated.
1179 * or1k-ibld.c: Regenerated.
1180 * or1k-opc.c: Regenerated.
1181 * or1k-opc.h: Regenerated.
1182 * or1k-opinst.c: Regenerated.
1183
a0e44ef5
PB		 11842019-06-12 Peter Bergner <bergner@linux.ibm.com>
1185
1186 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1187
12efd68d
L		 11882019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1189
1190 PR binutils/24633
1191 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1192 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1193 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1194 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1195 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1196 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1197 EVEX_LEN_0F3A1B_P_2_W_1.
1198 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1199 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1200 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1201 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1202 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1203 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1204 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1205 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1206
63c6fc6c
L		 12072019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1208
1209 PR binutils/24626
1210 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1211 EVEX.vvvv when disassembling VEX and EVEX instructions.
1212 (OP_VEX): Set vex.register_specifier to 0 after readding
1213 vex.register_specifier.
1214 (OP_Vex_2src_1): Likewise.
1215 (OP_Vex_2src_2): Likewise.
1216 (OP_LWP_E): Likewise.
1217 (OP_EX_Vex): Don't check vex.register_specifier.
1218 (OP_XMM_Vex): Likewise.
1219
9186c494
L		 12202019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1221 Lili Cui <lili.cui@intel.com>
1222
1223 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1224 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1225 instructions.
1226 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1227 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1228 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1229 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1230 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1231 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1232 * i386-init.h: Regenerated.
1233 * i386-tbl.h: Likewise.
1234
5d79adc4
L		 12352019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1236 Lili Cui <lili.cui@intel.com>
1237
1238 * doc/c-i386.texi: Document enqcmd.
1239 * testsuite/gas/i386/enqcmd-intel.d: New file.
1240 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1241 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1242 * testsuite/gas/i386/enqcmd.d: Likewise.
1243 * testsuite/gas/i386/enqcmd.s: Likewise.
1244 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1245 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1246 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1247 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1248 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1249 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1250 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1251 and x86-64-enqcmd.
1252
a9d96ab9
AH		 12532019-06-04 Alan Hayward <alan.hayward@arm.com>
1254
1255 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1256
4f6d070a
AM		 12572019-06-03 Alan Modra <amodra@gmail.com>
1258
1259 * ppc-dis.c (prefix_opcd_indices): Correct size.
1260
a2f4b66c
L		 12612019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1262
1263 PR gas/24625
1264 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1265 Disp8ShiftVL.
1266 * i386-tbl.h: Regenerated.
1267
405b5bd8
AM		 12682019-05-24 Alan Modra <amodra@gmail.com>
1269
1270 * po/POTFILES.in: Regenerate.
1271
8acf1435
PB		 12722019-05-24 Peter Bergner <bergner@linux.ibm.com>
1273 Alan Modra <amodra@gmail.com>
1274
1275 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1276 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1277 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1278 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1279 XTOP>): Define and add entries.
1280 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1281 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1282 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1283 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1284
dd7efa79
PB		 12852019-05-24 Peter Bergner <bergner@linux.ibm.com>
1286 Alan Modra <amodra@gmail.com>
1287
1288 * ppc-dis.c (ppc_opts): Add "future" entry.
1289 (PREFIX_OPCD_SEGS): Define.
1290 (prefix_opcd_indices): New array.
1291 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1292 (lookup_prefix): New function.
1293 (print_insn_powerpc): Handle 64-bit prefix instructions.
1294 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1295 (PMRR, POWERXX): Define.
1296 (prefix_opcodes): New instruction table.
1297 (prefix_num_opcodes): New constant.
1298
79472b45
JM		 12992019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1300
1301 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1302 * configure: Regenerated.
1303 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1304 and cpu/bpf.opc.
1305 (HFILES): Add bpf-desc.h and bpf-opc.h.
1306 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1307 bpf-ibld.c and bpf-opc.c.
1308 (BPF_DEPS): Define.
1309 * Makefile.in: Regenerated.
1310 * disassemble.c (ARCH_bpf): Define.
1311 (disassembler): Add case for bfd_arch_bpf.
1312 (disassemble_init_for_target): Likewise.
1313 (enum epbf_isa_attr): Define.
1314 * disassemble.h: extern print_insn_bpf.
1315 * bpf-asm.c: Generated.
1316 * bpf-opc.h: Likewise.
1317 * bpf-opc.c: Likewise.
1318 * bpf-ibld.c: Likewise.
1319 * bpf-dis.c: Likewise.
1320 * bpf-desc.h: Likewise.
1321 * bpf-desc.c: Likewise.
1322
ba6cd17f
SD		 13232019-05-21 Sudakshina Das <sudi.das@arm.com>
1324
1325 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1326 and VMSR with the new operands.
1327
e39c1607
SD		 13282019-05-21 Sudakshina Das <sudi.das@arm.com>
1329
1330 * arm-dis.c (enum mve_instructions): New enum
1331 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1332 and cneg.
1333 (mve_opcodes): New instructions as above.
1334 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1335 csneg and csel.
1336 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1337
23d00a41
SD		 13382019-05-21 Sudakshina Das <sudi.das@arm.com>
1339
1340 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1341 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1342 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1343 uqshl, urshrl and urshr.
1344 (is_mve_okay_in_it): Add new instructions to TRUE list.
1345 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1346 (print_insn_mve): Updated to accept new %j,
1347 %<bitfield>m and %<bitfield>n patterns.
1348
cd4797ee
FS		 13492019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1350
1351 * mips-opc.c (mips_builtin_opcodes): Change source register
1352 constraint for DAUI.
1353
999b073b
NC		 13542019-05-20 Nick Clifton <nickc@redhat.com>
1355
1356 * po/fr.po: Updated French translation.
1357
14b456f2
AV		 13582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1359 Michael Collison <michael.collison@arm.com>
1360
1361 * arm-dis.c (thumb32_opcodes): Add new instructions.
1362 (enum mve_instructions): Likewise.
1363 (enum mve_undefined): Add new reasons.
1364 (is_mve_encoding_conflict): Handle new instructions.
1365 (is_mve_undefined): Likewise.
1366 (is_mve_unpredictable): Likewise.
1367 (print_mve_undefined): Likewise.
1368 (print_mve_size): Likewise.
1369
f49bb598
AV		 13702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1371 Michael Collison <michael.collison@arm.com>
1372
1373 * arm-dis.c (thumb32_opcodes): Add new instructions.
1374 (enum mve_instructions): Likewise.
1375 (is_mve_encoding_conflict): Handle new instructions.
1376 (is_mve_undefined): Likewise.
1377 (is_mve_unpredictable): Likewise.
1378 (print_mve_size): Likewise.
1379
56858bea
AV		 13802019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1381 Michael Collison <michael.collison@arm.com>
1382
1383 * arm-dis.c (thumb32_opcodes): Add new instructions.
1384 (enum mve_instructions): Likewise.
1385 (is_mve_encoding_conflict): Likewise.
1386 (is_mve_unpredictable): Likewise.
1387 (print_mve_size): Likewise.
1388
e523f101
AV		 13892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1390 Michael Collison <michael.collison@arm.com>
1391
1392 * arm-dis.c (thumb32_opcodes): Add new instructions.
1393 (enum mve_instructions): Likewise.
1394 (is_mve_encoding_conflict): Handle new instructions.
1395 (is_mve_undefined): Likewise.
1396 (is_mve_unpredictable): Likewise.
1397 (print_mve_size): Likewise.
1398
66dcaa5d
AV		 13992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1400 Michael Collison <michael.collison@arm.com>
1401
1402 * arm-dis.c (thumb32_opcodes): Add new instructions.
1403 (enum mve_instructions): Likewise.
1404 (is_mve_encoding_conflict): Handle new instructions.
1405 (is_mve_undefined): Likewise.
1406 (is_mve_unpredictable): Likewise.
1407 (print_mve_size): Likewise.
1408 (print_insn_mve): Likewise.
1409
d052b9b7
AV		 14102019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1411 Michael Collison <michael.collison@arm.com>
1412
1413 * arm-dis.c (thumb32_opcodes): Add new instructions.
1414 (print_insn_thumb32): Handle new instructions.
1415
ed63aa17
AV		 14162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1417 Michael Collison <michael.collison@arm.com>
1418
1419 * arm-dis.c (enum mve_instructions): Add new instructions.
1420 (enum mve_undefined): Add new reasons.
1421 (is_mve_encoding_conflict): Handle new instructions.
1422 (is_mve_undefined): Likewise.
1423 (is_mve_unpredictable): Likewise.
1424 (print_mve_undefined): Likewise.
1425 (print_mve_size): Likewise.
1426 (print_mve_shift_n): Likewise.
1427 (print_insn_mve): Likewise.
1428
897b9bbc
AV		 14292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1430 Michael Collison <michael.collison@arm.com>
1431
1432 * arm-dis.c (enum mve_instructions): Add new instructions.
1433 (is_mve_encoding_conflict): Handle new instructions.
1434 (is_mve_unpredictable): Likewise.
1435 (print_mve_rotate): Likewise.
1436 (print_mve_size): Likewise.
1437 (print_insn_mve): Likewise.
1438
1c8f2df8
AV		 14392019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1440 Michael Collison <michael.collison@arm.com>
1441
1442 * arm-dis.c (enum mve_instructions): Add new instructions.
1443 (is_mve_encoding_conflict): Handle new instructions.
1444 (is_mve_unpredictable): Likewise.
1445 (print_mve_size): Likewise.
1446 (print_insn_mve): Likewise.
1447
d3b63143
AV		 14482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1449 Michael Collison <michael.collison@arm.com>
1450
1451 * arm-dis.c (enum mve_instructions): Add new instructions.
1452 (enum mve_undefined): Add new reasons.
1453 (is_mve_encoding_conflict): Handle new instructions.
1454 (is_mve_undefined): Likewise.
1455 (is_mve_unpredictable): Likewise.
1456 (print_mve_undefined): Likewise.
1457 (print_mve_size): Likewise.
1458 (print_insn_mve): Likewise.
1459
14925797
AV		 14602019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1461 Michael Collison <michael.collison@arm.com>
1462
1463 * arm-dis.c (enum mve_instructions): Add new instructions.
1464 (is_mve_encoding_conflict): Handle new instructions.
1465 (is_mve_undefined): Likewise.
1466 (is_mve_unpredictable): Likewise.
1467 (print_mve_size): Likewise.
1468 (print_insn_mve): Likewise.
1469
c507f10b
AV		 14702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1471 Michael Collison <michael.collison@arm.com>
1472
1473 * arm-dis.c (enum mve_instructions): Add new instructions.
1474 (enum mve_unpredictable): Add new reasons.
1475 (enum mve_undefined): Likewise.
1476 (is_mve_okay_in_it): Handle new isntructions.
1477 (is_mve_encoding_conflict): Likewise.
1478 (is_mve_undefined): Likewise.
1479 (is_mve_unpredictable): Likewise.
1480 (print_mve_vmov_index): Likewise.
1481 (print_simd_imm8): Likewise.
1482 (print_mve_undefined): Likewise.
1483 (print_mve_unpredictable): Likewise.
1484 (print_mve_size): Likewise.
1485 (print_insn_mve): Likewise.
1486
bf0b396d
AV		 14872019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1488 Michael Collison <michael.collison@arm.com>
1489
1490 * arm-dis.c (enum mve_instructions): Add new instructions.
1491 (enum mve_unpredictable): Add new reasons.
1492 (enum mve_undefined): Likewise.
1493 (is_mve_encoding_conflict): Handle new instructions.
1494 (is_mve_undefined): Likewise.
1495 (is_mve_unpredictable): Likewise.
1496 (print_mve_undefined): Likewise.
1497 (print_mve_unpredictable): Likewise.
1498 (print_mve_rounding_mode): Likewise.
1499 (print_mve_vcvt_size): Likewise.
1500 (print_mve_size): Likewise.
1501 (print_insn_mve): Likewise.
1502
ef1576a1
AV		 15032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1504 Michael Collison <michael.collison@arm.com>
1505
1506 * arm-dis.c (enum mve_instructions): Add new instructions.
1507 (enum mve_unpredictable): Add new reasons.
1508 (enum mve_undefined): Likewise.
1509 (is_mve_undefined): Handle new instructions.
1510 (is_mve_unpredictable): Likewise.
1511 (print_mve_undefined): Likewise.
1512 (print_mve_unpredictable): Likewise.
1513 (print_mve_size): Likewise.
1514 (print_insn_mve): Likewise.
1515
aef6d006
AV		 15162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1517 Michael Collison <michael.collison@arm.com>
1518
1519 * arm-dis.c (enum mve_instructions): Add new instructions.
1520 (enum mve_undefined): Add new reasons.
1521 (insns): Add new instructions.
1522 (is_mve_encoding_conflict):
1523 (print_mve_vld_str_addr): New print function.
1524 (is_mve_undefined): Handle new instructions.
1525 (is_mve_unpredictable): Likewise.
1526 (print_mve_undefined): Likewise.
1527 (print_mve_size): Likewise.
1528 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1529 (print_insn_mve): Handle new operands.
1530
04d54ace
AV		 15312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1532 Michael Collison <michael.collison@arm.com>
1533
1534 * arm-dis.c (enum mve_instructions): Add new instructions.
1535 (enum mve_unpredictable): Add new reasons.
1536 (is_mve_encoding_conflict): Handle new instructions.
1537 (is_mve_unpredictable): Likewise.
1538 (mve_opcodes): Add new instructions.
1539 (print_mve_unpredictable): Handle new reasons.
1540 (print_mve_register_blocks): New print function.
1541 (print_mve_size): Handle new instructions.
1542 (print_insn_mve): Likewise.
1543
9743db03
AV		 15442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1545 Michael Collison <michael.collison@arm.com>
1546
1547 * arm-dis.c (enum mve_instructions): Add new instructions.
1548 (enum mve_unpredictable): Add new reasons.
1549 (enum mve_undefined): Likewise.
1550 (is_mve_encoding_conflict): Handle new instructions.
1551 (is_mve_undefined): Likewise.
1552 (is_mve_unpredictable): Likewise.
1553 (coprocessor_opcodes): Move NEON VDUP from here...
1554 (neon_opcodes): ... to here.
1555 (mve_opcodes): Add new instructions.
1556 (print_mve_undefined): Handle new reasons.
1557 (print_mve_unpredictable): Likewise.
1558 (print_mve_size): Handle new instructions.
1559 (print_insn_neon): Handle vdup.
1560 (print_insn_mve): Handle new operands.
1561
143275ea
AV		 15622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1563 Michael Collison <michael.collison@arm.com>
1564
1565 * arm-dis.c (enum mve_instructions): Add new instructions.
1566 (enum mve_unpredictable): Add new values.
1567 (mve_opcodes): Add new instructions.
1568 (vec_condnames): New array with vector conditions.
1569 (mve_predicatenames): New array with predicate suffixes.
1570 (mve_vec_sizename): New array with vector sizes.
1571 (enum vpt_pred_state): New enum with vector predication states.
1572 (struct vpt_block): New struct type for vpt blocks.
1573 (vpt_block_state): Global struct to keep track of state.
1574 (mve_extract_pred_mask): New helper function.
1575 (num_instructions_vpt_block): Likewise.
1576 (mark_outside_vpt_block): Likewise.
1577 (mark_inside_vpt_block): Likewise.
1578 (invert_next_predicate_state): Likewise.
1579 (update_next_predicate_state): Likewise.
1580 (update_vpt_block_state): Likewise.
1581 (is_vpt_instruction): Likewise.
1582 (is_mve_encoding_conflict): Add entries for new instructions.
1583 (is_mve_unpredictable): Likewise.
1584 (print_mve_unpredictable): Handle new cases.
1585 (print_instruction_predicate): Likewise.
1586 (print_mve_size): New function.
1587 (print_vec_condition): New function.
1588 (print_insn_mve): Handle vpt blocks and new print operands.
1589
f08d8ce3
AV		 15902019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1591
1592 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1593 8, 14 and 15 for Armv8.1-M Mainline.
1594
73cd51e5
AV		 15952019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1596 Michael Collison <michael.collison@arm.com>
1597
1598 * arm-dis.c (enum mve_instructions): New enum.
1599 (enum mve_unpredictable): Likewise.
1600 (enum mve_undefined): Likewise.
1601 (struct mopcode32): New struct.
1602 (is_mve_okay_in_it): New function.
1603 (is_mve_architecture): Likewise.
1604 (arm_decode_field): Likewise.
1605 (arm_decode_field_multiple): Likewise.
1606 (is_mve_encoding_conflict): Likewise.
1607 (is_mve_undefined): Likewise.
1608 (is_mve_unpredictable): Likewise.
1609 (print_mve_undefined): Likewise.
1610 (print_mve_unpredictable): Likewise.
1611 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1612 (print_insn_mve): New function.
1613 (print_insn_thumb32): Handle MVE architecture.
1614 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1615
3076e594
NC		 16162019-05-10 Nick Clifton <nickc@redhat.com>
1617
1618 PR 24538
1619 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1620 end of the table prematurely.
1621
387e7624
FS		 16222019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1623
1624 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1625 macros for R6.
1626
0067be51
AM		 16272019-05-11 Alan Modra <amodra@gmail.com>
1628
1629 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1630 when -Mraw is in effect.
1631
42e6288f
MM		 16322019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1633
1634 * aarch64-dis-2.c: Regenerate.
1635 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1636 (OP_SVE_BBB): New variant set.
1637 (OP_SVE_DDDD): New variant set.
1638 (OP_SVE_HHH): New variant set.
1639 (OP_SVE_HHHU): New variant set.
1640 (OP_SVE_SSS): New variant set.
1641 (OP_SVE_SSSU): New variant set.
1642 (OP_SVE_SHH): New variant set.
1643 (OP_SVE_SBBU): New variant set.
1644 (OP_SVE_DSS): New variant set.
1645 (OP_SVE_DHHU): New variant set.
1646 (OP_SVE_VMV_HSD_BHS): New variant set.
1647 (OP_SVE_VVU_HSD_BHS): New variant set.
1648 (OP_SVE_VVVU_SD_BH): New variant set.
1649 (OP_SVE_VVVU_BHSD): New variant set.
1650 (OP_SVE_VVV_QHD_DBS): New variant set.
1651 (OP_SVE_VVV_HSD_BHS): New variant set.
1652 (OP_SVE_VVV_HSD_BHS2): New variant set.
1653 (OP_SVE_VVV_BHS_HSD): New variant set.
1654 (OP_SVE_VV_BHS_HSD): New variant set.
1655 (OP_SVE_VVV_SD): New variant set.
1656 (OP_SVE_VVU_BHS_HSD): New variant set.
1657 (OP_SVE_VZVV_SD): New variant set.
1658 (OP_SVE_VZVV_BH): New variant set.
1659 (OP_SVE_VZV_SD): New variant set.
1660 (aarch64_opcode_table): Add sve2 instructions.
1661
28ed815a
MM		 16622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1663
1664 * aarch64-asm-2.c: Regenerated.
1665 * aarch64-dis-2.c: Regenerated.
1666 * aarch64-opc-2.c: Regenerated.
1667 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1668 for SVE_SHLIMM_UNPRED_22.
1669 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1670 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1671 operand.
1672
fd1dc4a0
MM		 16732019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1674
1675 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1676 sve_size_tsz_bhs iclass encode.
1677 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1678 sve_size_tsz_bhs iclass decode.
1679
31e36ab3
MM		 16802019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1681
1682 * aarch64-asm-2.c: Regenerated.
1683 * aarch64-dis-2.c: Regenerated.
1684 * aarch64-opc-2.c: Regenerated.
1685 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1686 for SVE_Zm4_11_INDEX.
1687 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1688 (fields): Handle SVE_i2h field.
1689 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1690 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1691
1be5f94f
MM		 16922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1693
1694 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1695 sve_shift_tsz_bhsd iclass encode.
1696 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1697 sve_shift_tsz_bhsd iclass decode.
1698
3c17238b
MM		 16992019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1700
1701 * aarch64-asm-2.c: Regenerated.
1702 * aarch64-dis-2.c: Regenerated.
1703 * aarch64-opc-2.c: Regenerated.
1704 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1705 (aarch64_encode_variant_using_iclass): Handle
1706 sve_shift_tsz_hsd iclass encode.
1707 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1708 sve_shift_tsz_hsd iclass decode.
1709 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1710 for SVE_SHRIMM_UNPRED_22.
1711 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1712 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1713 operand.
1714
cd50a87a
MM		 17152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1716
1717 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1718 sve_size_013 iclass encode.
1719 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1720 sve_size_013 iclass decode.
1721
3c705960
MM		 17222019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1723
1724 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1725 sve_size_bh iclass encode.
1726 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1727 sve_size_bh iclass decode.
1728
0a57e14f
MM		 17292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1730
1731 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1732 sve_size_sd2 iclass encode.
1733 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1734 sve_size_sd2 iclass decode.
1735 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1736 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1737
c469c864
MM		 17382019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1739
1740 * aarch64-asm-2.c: Regenerated.
1741 * aarch64-dis-2.c: Regenerated.
1742 * aarch64-opc-2.c: Regenerated.
1743 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1744 for SVE_ADDR_ZX.
1745 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1746 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1747
116adc27
MM		 17482019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1749
1750 * aarch64-asm-2.c: Regenerated.
1751 * aarch64-dis-2.c: Regenerated.
1752 * aarch64-opc-2.c: Regenerated.
1753 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1754 for SVE_Zm3_11_INDEX.
1755 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1756 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1757 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1758 fields.
1759 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1760
3bd82c86
MM		 17612019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1762
1763 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1764 sve_size_hsd2 iclass encode.
1765 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1766 sve_size_hsd2 iclass decode.
1767 * aarch64-opc.c (fields): Handle SVE_size field.
1768 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1769
adccc507
MM		 17702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1771
1772 * aarch64-asm-2.c: Regenerated.
1773 * aarch64-dis-2.c: Regenerated.
1774 * aarch64-opc-2.c: Regenerated.
1775 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1776 for SVE_IMM_ROT3.
1777 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1778 (fields): Handle SVE_rot3 field.
1779 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1780 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1781
5cd99750
MM		 17822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1783
1784 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1785 instructions.
1786
7ce2460a
MM		 17872019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1788
1789 * aarch64-tbl.h
1790 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1791 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1792 aarch64_feature_sve2bitperm): New feature sets.
1793 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1794 for feature set addresses.
1795 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1796 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1797
41cee089
FS		 17982019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1799 Faraz Shahbazker <fshahbazker@wavecomp.com>
1800
1801 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1802 argument and set ASE_EVA_R6 appropriately.
1803 (set_default_mips_dis_options): Pass ISA to above.
1804 (parse_mips_dis_option): Likewise.
1805 * mips-opc.c (EVAR6): New macro.
1806 (mips_builtin_opcodes): Add llwpe, scwpe.
1807
b83b4b13
SD		 18082019-05-01 Sudakshina Das <sudi.das@arm.com>
1809
1810 * aarch64-asm-2.c: Regenerated.
1811 * aarch64-dis-2.c: Regenerated.
1812 * aarch64-opc-2.c: Regenerated.
1813 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1814 AARCH64_OPND_TME_UIMM16.
1815 (aarch64_print_operand): Likewise.
1816 * aarch64-tbl.h (QL_IMM_NIL): New.
1817 (TME): New.
1818 (_TME_INSN): New.
1819 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1820
4a90ce95
JD		 18212019-04-29 John Darrington <john@darrington.wattle.id.au>
1822
1823 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1824
a45328b9
AB		 18252019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1826 Faraz Shahbazker <fshahbazker@wavecomp.com>
1827
1828 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1829
d10be0cb
JD		 18302019-04-24 John Darrington <john@darrington.wattle.id.au>
1831
1832 * s12z-opc.h: Add extern "C" bracketing to help
1833 users who wish to use this interface in c++ code.
1834
a679f24e
JD		 18352019-04-24 John Darrington <john@darrington.wattle.id.au>
1836
1837 * s12z-opc.c (bm_decode): Handle bit map operations with the
1838 "reserved0" mode.
1839
32c36c3c
AV		 18402019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1841
1842 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1843 specifier. Add entries for VLDR and VSTR of system registers.
1844 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1845 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1846 of %J and %K format specifier.
1847
efd6b359
AV		 18482019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1849
1850 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1851 Add new entries for VSCCLRM instruction.
1852 (print_insn_coprocessor): Handle new %C format control code.
1853
6b0dd094
AV		 18542019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1855
1856 * arm-dis.c (enum isa): New enum.
1857 (struct sopcode32): New structure.
1858 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1859 set isa field of all current entries to ANY.
1860 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1861 Only match an entry if its isa field allows the current mode.
1862
4b5a202f
AV		 18632019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1864
1865 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1866 CLRM.
1867 (print_insn_thumb32): Add logic to print %n CLRM register list.
1868
60f993ce
AV		 18692019-04-15 Sudakshina Das <sudi.das@arm.com>
1870
1871 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1872 and %Q patterns.
1873
f6b2b12d
AV		 18742019-04-15 Sudakshina Das <sudi.das@arm.com>
1875
1876 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1877 (print_insn_thumb32): Edit the switch case for %Z.
1878
1889da70
AV		 18792019-04-15 Sudakshina Das <sudi.das@arm.com>
1880
1881 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1882
65d1bc05
AV		 18832019-04-15 Sudakshina Das <sudi.das@arm.com>
1884
1885 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1886
1caf72a5
AV		 18872019-04-15 Sudakshina Das <sudi.das@arm.com>
1888
1889 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1890
f1c7f421
AV		 18912019-04-15 Sudakshina Das <sudi.das@arm.com>
1892
1893 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1894 Arm register with r13 and r15 unpredictable.
1895 (thumb32_opcodes): New instructions for bfx and bflx.
1896
4389b29a
AV		 18972019-04-15 Sudakshina Das <sudi.das@arm.com>
1898
1899 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1900
e5d6e09e
AV		 19012019-04-15 Sudakshina Das <sudi.das@arm.com>
1902
1903 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1904
e12437dc
AV		 19052019-04-15 Sudakshina Das <sudi.das@arm.com>
1906
1907 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1908
031254f2
AV		 19092019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1910
1911 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1912
e5a557ac
JD		 19132019-04-12 John Darrington <john@darrington.wattle.id.au>
1914
1915 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1916 "optr". ("operator" is a reserved word in c++).
1917
bd7ceb8d
SD		 19182019-04-11 Sudakshina Das <sudi.das@arm.com>
1919
1920 * aarch64-opc.c (aarch64_print_operand): Add case for
1921 AARCH64_OPND_Rt_SP.
1922 (verify_constraints): Likewise.
1923 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1924 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1925 to accept Rt|SP as first operand.
1926 (AARCH64_OPERANDS): Add new Rt_SP.
1927 * aarch64-asm-2.c: Regenerated.
1928 * aarch64-dis-2.c: Regenerated.
1929 * aarch64-opc-2.c: Regenerated.
1930
e54010f1
SD		 19312019-04-11 Sudakshina Das <sudi.das@arm.com>
1932
1933 * aarch64-asm-2.c: Regenerated.
1934 * aarch64-dis-2.c: Likewise.
1935 * aarch64-opc-2.c: Likewise.
1936 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1937
7e96e219
RS		 19382019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1939
1940 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1941
6f2791d5
L		 19422019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1943
1944 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1945 * i386-init.h: Regenerated.
1946
e392bad3
AM		 19472019-04-07 Alan Modra <amodra@gmail.com>
1948
1949 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1950 op_separator to control printing of spaces, comma and parens
1951 rather than need_comma, need_paren and spaces vars.
1952
dffaa15c
AM		 19532019-04-07 Alan Modra <amodra@gmail.com>
1954
1955 PR 24421
1956 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1957 (print_insn_neon, print_insn_arm): Likewise.
1958
d6aab7a1
XG		 19592019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1960
1961 * i386-dis-evex.h (evex_table): Updated to support BF16
1962 instructions.
1963 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1964 and EVEX_W_0F3872_P_3.
1965 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1966 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1967 * i386-opc.h (enum): Add CpuAVX512_BF16.
1968 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1969 * i386-opc.tbl: Add AVX512 BF16 instructions.
1970 * i386-init.h: Regenerated.
1971 * i386-tbl.h: Likewise.
1972
66e85460
AM		 19732019-04-05 Alan Modra <amodra@gmail.com>
1974
1975 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1976 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1977 to favour printing of "-" branch hint when using the "y" bit.
1978 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1979
c2b1c275
AM		 19802019-04-05 Alan Modra <amodra@gmail.com>
1981
1982 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1983 opcode until first operand is output.
1984
aae9718e
PB		 19852019-04-04 Peter Bergner <bergner@linux.ibm.com>
1986
1987 PR gas/24349
1988 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1989 (valid_bo_post_v2): Add support for 'at' branch hints.
1990 (insert_bo): Only error on branch on ctr.
1991 (get_bo_hint_mask): New function.
1992 (insert_boe): Add new 'branch_taken' formal argument. Add support
1993 for inserting 'at' branch hints.
1994 (extract_boe): Add new 'branch_taken' formal argument. Add support
1995 for extracting 'at' branch hints.
1996 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1997 (BOE): Delete operand.
1998 (BOM, BOP): New operands.
1999 (RM): Update value.
2000 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2001 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2002 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2003 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2004 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2005 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2006 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2007 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2008 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2009 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2010 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2011 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2012 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2013 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2014 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2015 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2016 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2017 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2018 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2019 bttarl+>: New extended mnemonics.
2020
96a86c01
AM		 20212019-03-28 Alan Modra <amodra@gmail.com>
2022
2023 PR 24390
2024 * ppc-opc.c (BTF): Define.
2025 (powerpc_opcodes): Use for mtfsb*.
2026 * ppc-dis.c (print_insn_powerpc): Print fields with both
2027 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2028
796d6298
TC		 20292019-03-25 Tamar Christina <tamar.christina@arm.com>
2030
2031 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2032 (mapping_symbol_for_insn): Implement new algorithm.
2033 (print_insn): Remove duplicate code.
2034
60df3720
TC		 20352019-03-25 Tamar Christina <tamar.christina@arm.com>
2036
2037 * aarch64-dis.c (print_insn_aarch64):
2038 Implement override.
2039
51457761
TC		 20402019-03-25 Tamar Christina <tamar.christina@arm.com>
2041
2042 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2043 order.
2044
53b2f36b
TC		 20452019-03-25 Tamar Christina <tamar.christina@arm.com>
2046
2047 * aarch64-dis.c (last_stop_offset): New.
2048 (print_insn_aarch64): Use stop_offset.
2049
89199bb5
L		 20502019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2051
2052 PR gas/24359
2053 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2054 CPU_ANY_AVX2_FLAGS.
2055 * i386-init.h: Regenerated.
2056
97ed31ae
L		 20572019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2058
2059 PR gas/24348
2060 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2061 vmovdqu16, vmovdqu32 and vmovdqu64.
2062 * i386-tbl.h: Regenerated.
2063
0919bfe9
AK		 20642019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2065
2066 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2067 from vstrszb, vstrszh, and vstrszf.
2068
20692019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2070
2071 * s390-opc.txt: Add instruction descriptions.
2072
21820ebe
JW		 20732019-02-08 Jim Wilson <jimw@sifive.com>
2074
2075 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2076 <bne>: Likewise.
2077
f7dd2fb2
TC		 20782019-02-07 Tamar Christina <tamar.christina@arm.com>
2079
2080 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2081
6456d318
TC		 20822019-02-07 Tamar Christina <tamar.christina@arm.com>
2083
2084 PR binutils/23212
2085 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2086 * aarch64-opc.c (verify_elem_sd): New.
2087 (fields): Add FLD_sz entr.
2088 * aarch64-tbl.h (_SIMD_INSN): New.
2089 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2090 fmulx scalar and vector by element isns.
2091
4a83b610
NC		 20922019-02-07 Nick Clifton <nickc@redhat.com>
2093
2094 * po/sv.po: Updated Swedish translation.
2095
fc60b8c8
AK		 20962019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2097
2098 * s390-mkopc.c (main): Accept arch13 as cpu string.
2099 * s390-opc.c: Add new instruction formats and instruction opcode
2100 masks.
2101 * s390-opc.txt: Add new arch13 instructions.
2102
e10620d3
TC		 21032019-01-25 Sudakshina Das <sudi.das@arm.com>
2104
2105 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2106 (aarch64_opcode): Change encoding for stg, stzg
2107 st2g and st2zg.
2108 * aarch64-asm-2.c: Regenerated.
2109 * aarch64-dis-2.c: Regenerated.
2110 * aarch64-opc-2.c: Regenerated.
2111
20a4ca55
SD		 21122019-01-25 Sudakshina Das <sudi.das@arm.com>
2113
2114 * aarch64-asm-2.c: Regenerated.
2115 * aarch64-dis-2.c: Likewise.
2116 * aarch64-opc-2.c: Likewise.
2117 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2118
550fd7bf
SD		 21192019-01-25 Sudakshina Das <sudi.das@arm.com>
2120 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2121
2122 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2123 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2124 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2125 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2126 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2127 case for ldstgv_indexed.
2128 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2129 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2130 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2131 * aarch64-asm-2.c: Regenerated.
2132 * aarch64-dis-2.c: Regenerated.
2133 * aarch64-opc-2.c: Regenerated.
2134
d9938630
NC		 21352019-01-23 Nick Clifton <nickc@redhat.com>
2136
2137 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2138
375cd423
NC		 21392019-01-21 Nick Clifton <nickc@redhat.com>
2140
2141 * po/de.po: Updated German translation.
2142 * po/uk.po: Updated Ukranian translation.
2143
57299f48
CX		 21442019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2145 * mips-dis.c (mips_arch_choices): Fix typo in
2146 gs464, gs464e and gs264e descriptors.
2147
f48dfe41
NC		 21482019-01-19 Nick Clifton <nickc@redhat.com>
2149
2150 * configure: Regenerate.
2151 * po/opcodes.pot: Regenerate.
2152
f974f26c
NC		 21532018-06-24 Nick Clifton <nickc@redhat.com>
2154
2155 2.32 branch created.
2156
39f286cd
JD		 21572019-01-09 John Darrington <john@darrington.wattle.id.au>
2158
448b8ca8
JD		 2159 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2160 if it is null.
2161 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2162 zero.
2163
3107326d
AP		 21642019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2165
2166 * configure: Regenerate.
2167
7e9ca91e
AM		 21682019-01-07 Alan Modra <amodra@gmail.com>
2169
2170 * configure: Regenerate.
2171 * po/POTFILES.in: Regenerate.
2172
ef1ad42b
JD		 21732019-01-03 John Darrington <john@darrington.wattle.id.au>
2174
2175 * s12z-opc.c: New file.
2176 * s12z-opc.h: New file.
2177 * s12z-dis.c: Removed all code not directly related to display
2178 of instructions. Used the interface provided by the new files
2179 instead.
2180 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2181 * Makefile.in: Regenerate.
ef1ad42b 2182 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2183 * configure: Regenerate.
ef1ad42b 2184
82704155
AM		 21852019-01-01 Alan Modra <amodra@gmail.com>
2186
2187 Update year range in copyright notice of all files.
2188
d5c04e1b 2189For older changes see ChangeLog-2018
3499769a 2190\f
d5c04e1b 2191Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2192
2193Copying and distribution of this file, with or without modification,
2194are permitted in any medium without royalty provided the copyright
2195notice and this notice are preserved.
2196
2197Local Variables:
2198mode: change-log
2199left-margin: 8
2200fill-column: 74
2201version-control: never
2202End:
GDB Binutils - Deliverables
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