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x86: use %LW / %XW instead of going through vex_w_table[]
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
21a3faeb
JB		 12020-07-06 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (EVEX_W_0F3838_P_1,
4 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
5 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
6 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
7 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
8 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
9 (putop): Centralize management of last[]. Delete SAVE_LAST.
10 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
11 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
12 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
13 * i386-dis-evex-prefix.h: here.
14
bc152a17
JB		 152020-07-06 Jan Beulich <jbeulich@suse.com>
16
17 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
18 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
19 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
20 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
21 enumerators.
22 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
23 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
24 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
25 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
26 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
27 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
28 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
29 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
30 these, respectively.
31 * i386-dis-evex-len.h: Adjust comments.
32 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
33 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
34 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
35 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
36 MOD_EVEX_0F385B_P_2_W_1 table entries.
37 * i386-dis-evex-w.h: Reference mod_table[] for
38 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
39 EVEX_W_0F385B_P_2.
40
c82a99a0
JB		 412020-07-06 Jan Beulich <jbeulich@suse.com>
42
43 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
44 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
45 EXymm.
46 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
47 Likewise. Mark 256-bit entries invalid.
48
fedfb81e
JB		 492020-07-06 Jan Beulich <jbeulich@suse.com>
50
51 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
52 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
53 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
54 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
55 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
56 PREFIX_EVEX_0F382B): Delete.
57 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
58 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
59 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
60 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
61 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
62 to ...
63 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
64 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
65 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
66 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
67 respectively.
68 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
69 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
70 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
71 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
72 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
73 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
74 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
75 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
76 PREFIX_EVEX_0F382B): Remove table entries.
77 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
78 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
79 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
80
3a57774c
JB		 812020-07-06 Jan Beulich <jbeulich@suse.com>
82
83 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
84 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
85 enumerators.
86 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
87 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
88 EVEX_LEN_0F3A01_P_2_W_1 table entries.
89 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
90 entries.
91
e74d9fa9
JB		 922020-07-06 Jan Beulich <jbeulich@suse.com>
93
94 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
95 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
96 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
97 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
98 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
99 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
100 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
101 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
102 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
103 entries.
104
6431c801
JB		 1052020-07-06 Jan Beulich <jbeulich@suse.com>
106
107 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
108 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
109 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
110 respectively.
111 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
112 entries.
113 * i386-dis-evex.h (evex_table): Reference VEX table entry for
114 opcode 0F3A1D.
115 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
116 entry.
117 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
118
6df22cf6
JB		 1192020-07-06 Jan Beulich <jbeulich@suse.com>
120
121 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
122 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
123 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
124 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
125 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
126 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
127 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
128 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
129 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
130 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
131 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
132 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
133 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
134 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
135 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
136 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
137 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
138 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
139 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
140 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
141 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
142 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
143 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
144 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
145 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
146 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
147 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
148 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
149 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
150 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
151 (prefix_table): Add EXxEVexR to FMA table entries.
152 (OP_Rounding): Move abort() invocation.
153 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
154 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
155 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
156 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
157 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
158 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
159 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
160 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
161 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
162 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
163 0F3ACE, 0F3ACF.
164 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
165 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
166 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
167 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
168 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
169 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
170 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
171 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
172 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
173 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
174 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
175 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
176 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
177 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
178 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
179 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
180 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
181 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
182 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
183 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
184 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
185 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
186 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
187 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
188 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
189 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
190 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
191 Delete table entries.
192 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
193 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
194 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
195 Likewise.
196
39e0f456
JB		 1972020-07-06 Jan Beulich <jbeulich@suse.com>
198
199 * i386-dis.c (EXqScalarS): Delete.
200 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
201 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
202
5b872f7d
JB		 2032020-07-06 Jan Beulich <jbeulich@suse.com>
204
205 * i386-dis.c (safe-ctype.h): Include.
206 (EXdScalar, EXqScalar): Delete.
207 (d_scalar_mode, q_scalar_mode): Delete.
208 (prefix_table, vex_len_table): Use EXxmm_md in place of
209 EXdScalar and EXxmm_mq in place of EXqScalar.
210 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
211 d_scalar_mode and q_scalar_mode.
212 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
213 (vmovsd): Use EXxmm_mq.
214
ddc73fa9
NC		 2152020-07-06 Yuri Chornoivan <yurchor@ukr.net>
216
217 PR 26204
218 * arc-dis.c: Fix spelling mistake.
219 * po/opcodes.pot: Regenerate.
220
17550be7
NC		 2212020-07-06 Nick Clifton <nickc@redhat.com>
222
223 * po/pt_BR.po: Updated Brazilian Portugugese translation.
224 * po/uk.po: Updated Ukranian translation.
225
b19d852d
NC		 2262020-07-04 Nick Clifton <nickc@redhat.com>
227
228 * configure: Regenerate.
229 * po/opcodes.pot: Regenerate.
230
b115b9fd
NC		 2312020-07-04 Nick Clifton <nickc@redhat.com>
232
233 Binutils 2.35 branch created.
234
c2ecccb3
L		 2352020-07-02 H.J. Lu <hongjiu.lu@intel.com>
236
237 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
238 * i386-opc.h (VexSwapSources): New.
239 (i386_opcode_modifier): Add vexswapsources.
240 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
241 with two source operands swapped.
242 * i386-tbl.h: Regenerated.
243
08ccfccf
NC		 2442020-06-30 Nelson Chu <nelson.chu@sifive.com>
245
246 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
247 unprivileged CSR can also be initialized.
248
279edac5
AM		 2492020-06-29 Alan Modra <amodra@gmail.com>
250
251 * arm-dis.c: Use C style comments.
252 * cr16-opc.c: Likewise.
253 * ft32-dis.c: Likewise.
254 * moxie-opc.c: Likewise.
255 * tic54x-dis.c: Likewise.
256 * s12z-opc.c: Remove useless comment.
257 * xgate-dis.c: Likewise.
258
e978ad62
L		 2592020-06-26 H.J. Lu <hongjiu.lu@intel.com>
260
261 * i386-opc.tbl: Add a blank line.
262
63112cd6
L		 2632020-06-26 H.J. Lu <hongjiu.lu@intel.com>
264
265 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
266 (VecSIB128): Renamed to ...
267 (VECSIB128): This.
268 (VecSIB256): Renamed to ...
269 (VECSIB256): This.
270 (VecSIB512): Renamed to ...
271 (VECSIB512): This.
272 (VecSIB): Renamed to ...
273 (SIB): This.
274 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 275 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 276 (VecSIB256): Likewise.
277 (VecSIB512): Likewise.
79b32e73 278 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 279 and VecSIB512, respectively.
280
d1c36125
JB		 2812020-06-26 Jan Beulich <jbeulich@suse.com>
282
283 * i386-dis.c: Adjust description of I macro.
284 (x86_64_table): Drop use of I.
285 (float_mem): Replace use of I.
286 (putop): Remove handling of I. Adjust setting/clearing of "alt".
287
2a1bb84c
JB		 2882020-06-26 Jan Beulich <jbeulich@suse.com>
289
290 * i386-dis.c: (print_insn): Avoid straight assignment to
291 priv.orig_sizeflag when processing -M sub-options.
292
8f570d62
JB		 2932020-06-25 Jan Beulich <jbeulich@suse.com>
294
295 * i386-dis.c: Adjust description of J macro.
296 (dis386, x86_64_table, mod_table): Replace J.
297 (putop): Remove handling of J.
298
464dc4af
JB		 2992020-06-25 Jan Beulich <jbeulich@suse.com>
300
301 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
302
589958d6
JB		 3032020-06-25 Jan Beulich <jbeulich@suse.com>
304
305 * i386-dis.c: Adjust description of "LQ" macro.
306 (dis386_twobyte): Use LQ for sysret.
307 (putop): Adjust handling of LQ.
308
39ff0b81
NC		 3092020-06-22 Nelson Chu <nelson.chu@sifive.com>
310
311 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
312 * riscv-dis.c: Include elfxx-riscv.h.
313
d27c357a
JB		 3142020-06-18 H.J. Lu <hongjiu.lu@intel.com>
315
316 * i386-dis.c (prefix_table): Revert the last vmgexit change.
317
6fde587f
CL		 3182020-06-17 Lili Cui <lili.cui@intel.com>
319
320 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
321
efe30057
L		 3222020-06-14 H.J. Lu <hongjiu.lu@intel.com>
323
324 PR gas/26115
325 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
326 * i386-opc.tbl: Likewise.
327 * i386-tbl.h: Regenerated.
328
d8af286f
NC		 3292020-06-12 Nelson Chu <nelson.chu@sifive.com>
330
331 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
332
14962256
AC		 3332020-06-11 Alex Coplan <alex.coplan@arm.com>
334
335 * aarch64-opc.c (SYSREG): New macro for describing system registers.
336 (SR_CORE): Likewise.
337 (SR_FEAT): Likewise.
338 (SR_RNG): Likewise.
339 (SR_V8_1): Likewise.
340 (SR_V8_2): Likewise.
341 (SR_V8_3): Likewise.
342 (SR_V8_4): Likewise.
343 (SR_PAN): Likewise.
344 (SR_RAS): Likewise.
345 (SR_SSBS): Likewise.
346 (SR_SVE): Likewise.
347 (SR_ID_PFR2): Likewise.
348 (SR_PROFILE): Likewise.
349 (SR_MEMTAG): Likewise.
350 (SR_SCXTNUM): Likewise.
351 (aarch64_sys_regs): Refactor to store feature information in the table.
352 (aarch64_sys_reg_supported_p): Collapse logic for system registers
353 that now describe their own features.
354 (aarch64_pstatefield_supported_p): Likewise.
355
f9630fa6
L		 3562020-06-09 H.J. Lu <hongjiu.lu@intel.com>
357
358 * i386-dis.c (prefix_table): Fix a typo in comments.
359
73239888
JB		 3602020-06-09 Jan Beulich <jbeulich@suse.com>
361
362 * i386-dis.c (rex_ignored): Delete.
363 (ckprefix): Drop rex_ignored initialization.
364 (get_valid_dis386): Drop setting of rex_ignored.
365 (print_insn): Drop checking of rex_ignored. Don't record data
366 size prefix as used with VEX-and-alike encodings.
367
18897deb
JB		 3682020-06-09 Jan Beulich <jbeulich@suse.com>
369
370 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
371 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
372 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
373 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
374 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
375 VEX_0F12, and VEX_0F16.
376 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
377 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
378 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
379 from movlps and movhlps. New MOD_0F12_PREFIX_2,
380 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
381 MOD_VEX_0F16_PREFIX_2 entries.
382
97e6786a
JB		 3832020-06-09 Jan Beulich <jbeulich@suse.com>
384
385 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
386 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
387 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
388 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
389 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
390 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
391 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
392 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
393 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
394 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
395 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
396 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
397 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
398 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
399 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
400 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
401 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
402 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
403 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
404 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
405 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
406 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
407 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
408 EVEX_W_0FC6_P_2): Delete.
409 (print_insn): Add EVEX.W vs embedded prefix consistency check
410 to prefix validation.
411 * i386-dis-evex.h (evex_table): Don't further descend for
412 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
413 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
414 and 0F2B.
415 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
416 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
417 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
418 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
419 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
420 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
421 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
422 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
423 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
424 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
425 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
426 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
427 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
428 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
429 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
430 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
431 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
432 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
433 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
434 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
435 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
436 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
437 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
438 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
439 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
440 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
441 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
442
bf926894
JB		 4432020-06-09 Jan Beulich <jbeulich@suse.com>
444
445 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
446 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
447 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
448 vmovmskpX.
449 (print_insn): Drop pointless check against bad_opcode. Split
450 prefix validation into legacy and VEX-and-alike parts.
451 (putop): Re-work 'X' macro handling.
452
a5aaedb9
JB		 4532020-06-09 Jan Beulich <jbeulich@suse.com>
454
455 * i386-dis.c (MOD_0F51): Rename to ...
456 (MOD_0F50): ... this.
457
26417f19
AC		 4582020-06-08 Alex Coplan <alex.coplan@arm.com>
459
460 * arm-dis.c (arm_opcodes): Add dfb.
461 (thumb32_opcodes): Add dfb.
462
8a6fb3f9
JB		 4632020-06-08 Jan Beulich <jbeulich@suse.com>
464
465 * i386-opc.h (reg_entry): Const-qualify reg_name field.
466
1424c35d
AM		 4672020-06-06 Alan Modra <amodra@gmail.com>
468
469 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
470
d3d1cc7b
AM		 4712020-06-05 Alan Modra <amodra@gmail.com>
472
473 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
474 size is large enough.
475
d8740be1
JM		 4762020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
477
478 * disassemble.c (disassemble_init_for_target): Set endian_code for
479 bpf targets.
480 * bpf-desc.c: Regenerate.
481 * bpf-opc.c: Likewise.
482 * bpf-dis.c: Likewise.
483
e9bffec9
JM		 4842020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
485
486 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
487 (cgen_put_insn_value): Likewise.
488 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
489 * cgen-dis.in (print_insn): Likewise.
490 * cgen-ibld.in (insert_1): Likewise.
491 (insert_1): Likewise.
492 (insert_insn_normal): Likewise.
493 (extract_1): Likewise.
494 * bpf-dis.c: Regenerate.
495 * bpf-ibld.c: Likewise.
496 * bpf-ibld.c: Likewise.
497 * cgen-dis.in: Likewise.
498 * cgen-ibld.in: Likewise.
499 * cgen-opc.c: Likewise.
500 * epiphany-dis.c: Likewise.
501 * epiphany-ibld.c: Likewise.
502 * fr30-dis.c: Likewise.
503 * fr30-ibld.c: Likewise.
504 * frv-dis.c: Likewise.
505 * frv-ibld.c: Likewise.
506 * ip2k-dis.c: Likewise.
507 * ip2k-ibld.c: Likewise.
508 * iq2000-dis.c: Likewise.
509 * iq2000-ibld.c: Likewise.
510 * lm32-dis.c: Likewise.
511 * lm32-ibld.c: Likewise.
512 * m32c-dis.c: Likewise.
513 * m32c-ibld.c: Likewise.
514 * m32r-dis.c: Likewise.
515 * m32r-ibld.c: Likewise.
516 * mep-dis.c: Likewise.
517 * mep-ibld.c: Likewise.
518 * mt-dis.c: Likewise.
519 * mt-ibld.c: Likewise.
520 * or1k-dis.c: Likewise.
521 * or1k-ibld.c: Likewise.
522 * xc16x-dis.c: Likewise.
523 * xc16x-ibld.c: Likewise.
524 * xstormy16-dis.c: Likewise.
525 * xstormy16-ibld.c: Likewise.
526
b3db6d07
JM		 5272020-06-04 Jose E. Marchesi <jemarch@gnu.org>
528
529 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
530 (print_insn_): Handle instruction endian.
531 * bpf-dis.c: Regenerate.
532 * bpf-desc.c: Regenerate.
533 * epiphany-dis.c: Likewise.
534 * epiphany-desc.c: Likewise.
535 * fr30-dis.c: Likewise.
536 * fr30-desc.c: Likewise.
537 * frv-dis.c: Likewise.
538 * frv-desc.c: Likewise.
539 * ip2k-dis.c: Likewise.
540 * ip2k-desc.c: Likewise.
541 * iq2000-dis.c: Likewise.
542 * iq2000-desc.c: Likewise.
543 * lm32-dis.c: Likewise.
544 * lm32-desc.c: Likewise.
545 * m32c-dis.c: Likewise.
546 * m32c-desc.c: Likewise.
547 * m32r-dis.c: Likewise.
548 * m32r-desc.c: Likewise.
549 * mep-dis.c: Likewise.
550 * mep-desc.c: Likewise.
551 * mt-dis.c: Likewise.
552 * mt-desc.c: Likewise.
553 * or1k-dis.c: Likewise.
554 * or1k-desc.c: Likewise.
555 * xc16x-dis.c: Likewise.
556 * xc16x-desc.c: Likewise.
557 * xstormy16-dis.c: Likewise.
558 * xstormy16-desc.c: Likewise.
559
4ee4189f
NC		 5602020-06-03 Nick Clifton <nickc@redhat.com>
561
562 * po/sr.po: Updated Serbian translation.
563
44730156
NC		 5642020-06-03 Nelson Chu <nelson.chu@sifive.com>
565
566 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
567 (riscv_get_priv_spec_class): Likewise.
568
3c3d0376
AM		 5692020-06-01 Alan Modra <amodra@gmail.com>
570
571 * bpf-desc.c: Regenerate.
572
78c1c354
JM		 5732020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
574 David Faust <david.faust@oracle.com>
575
576 * bpf-desc.c: Regenerate.
577 * bpf-opc.h: Likewise.
578 * bpf-opc.c: Likewise.
579 * bpf-dis.c: Likewise.
580
efcf5fb5
AM		 5812020-05-28 Alan Modra <amodra@gmail.com>
582
583 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
584 values.
585
ab382d64
AM		 5862020-05-28 Alan Modra <amodra@gmail.com>
587
588 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
589 immediates.
590 (print_insn_ns32k): Revert last change.
591
151f5de4
NC		 5922020-05-28 Nick Clifton <nickc@redhat.com>
593
594 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
595 static.
596
25e1eca8
SL		 5972020-05-26 Sandra Loosemore <sandra@codesourcery.com>
598
599 Fix extraction of signed constants in nios2 disassembler (again).
600
601 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
602 extractions of signed fields.
603
57b17940
SSF		 6042020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
605
606 * s390-opc.txt: Relocate vector load/store instructions with
607 additional alignment parameter and change architecture level
608 constraint from z14 to z13.
609
d96bf37b
AM		 6102020-05-21 Alan Modra <amodra@gmail.com>
611
612 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
613 * sparc-dis.c: Likewise.
614 * tic4x-dis.c: Likewise.
615 * xtensa-dis.c: Likewise.
616 * bpf-desc.c: Regenerate.
617 * epiphany-desc.c: Regenerate.
618 * fr30-desc.c: Regenerate.
619 * frv-desc.c: Regenerate.
620 * ip2k-desc.c: Regenerate.
621 * iq2000-desc.c: Regenerate.
622 * lm32-desc.c: Regenerate.
623 * m32c-desc.c: Regenerate.
624 * m32r-desc.c: Regenerate.
625 * mep-asm.c: Regenerate.
626 * mep-desc.c: Regenerate.
627 * mt-desc.c: Regenerate.
628 * or1k-desc.c: Regenerate.
629 * xc16x-desc.c: Regenerate.
630 * xstormy16-desc.c: Regenerate.
631
8f595e9b
NC		 6322020-05-20 Nelson Chu <nelson.chu@sifive.com>
633
634 * riscv-opc.c (riscv_ext_version_table): The table used to store
635 all information about the supported spec and the corresponding ISA
636 versions. Currently, only Zicsr is supported to verify the
637 correctness of Z sub extension settings. Others will be supported
638 in the future patches.
639 (struct isa_spec_t, isa_specs): List for all supported ISA spec
640 classes and the corresponding strings.
641 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
642 spec class by giving a ISA spec string.
643 * riscv-opc.c (struct priv_spec_t): New structure.
644 (struct priv_spec_t priv_specs): List for all supported privilege spec
645 classes and the corresponding strings.
646 (riscv_get_priv_spec_class): New function. Get the corresponding
647 privilege spec class by giving a spec string.
648 (riscv_get_priv_spec_name): New function. Get the corresponding
649 privilege spec string by giving a CSR version class.
650 * riscv-dis.c: Updated since DECLARE_CSR is changed.
651 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
652 according to the chosen version. Build a hash table riscv_csr_hash to
653 store the valid CSR for the chosen pirv verison. Dump the direct
654 CSR address rather than it's name if it is invalid.
655 (parse_riscv_dis_option_without_args): New function. Parse the options
656 without arguments.
657 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
658 parse the options without arguments first, and then handle the options
659 with arguments. Add the new option -Mpriv-spec, which has argument.
660 * riscv-dis.c (print_riscv_disassembler_options): Add description
661 about the new OBJDUMP option.
662
3d205eb4
PB		 6632020-05-19 Peter Bergner <bergner@linux.ibm.com>
664
665 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
666 WC values on POWER10 sync, dcbf and wait instructions.
667 (insert_pl, extract_pl): New functions.
668 (L2OPT, LS, WC): Use insert_ls and extract_ls.
669 (LS3): New , 3-bit L for sync.
670 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
671 (SC2, PL): New, 2-bit SC and PL for sync and wait.
672 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
673 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
674 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
675 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
676 <wait>: Enable PL operand on POWER10.
677 <dcbf>: Enable L3OPT operand on POWER10.
678 <sync>: Enable SC2 operand on POWER10.
679
a501eb44
SH		 6802020-05-19 Stafford Horne <shorne@gmail.com>
681
682 PR 25184
683 * or1k-asm.c: Regenerate.
684 * or1k-desc.c: Regenerate.
685 * or1k-desc.h: Regenerate.
686 * or1k-dis.c: Regenerate.
687 * or1k-ibld.c: Regenerate.
688 * or1k-opc.c: Regenerate.
689 * or1k-opc.h: Regenerate.
690 * or1k-opinst.c: Regenerate.
691
3b646889
AM		 6922020-05-11 Alan Modra <amodra@gmail.com>
693
694 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
695 xsmaxcqp, xsmincqp.
696
9cc4ce88
AM		 6972020-05-11 Alan Modra <amodra@gmail.com>
698
699 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
700 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
701
5d57bc3f
AM		 7022020-05-11 Alan Modra <amodra@gmail.com>
703
704 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
705
66ef5847
AM		 7062020-05-11 Alan Modra <amodra@gmail.com>
707
708 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
709 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
710
4f3e9537
PB		 7112020-05-11 Peter Bergner <bergner@linux.ibm.com>
712
713 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
714 mnemonics.
715
ec40e91c
AM		 7162020-05-11 Alan Modra <amodra@gmail.com>
717
718 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
719 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
720 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
721 (prefix_opcodes): Add xxeval.
722
d7e97a76
AM		 7232020-05-11 Alan Modra <amodra@gmail.com>
724
725 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
726 xxgenpcvwm, xxgenpcvdm.
727
fdefed7c
AM		 7282020-05-11 Alan Modra <amodra@gmail.com>
729
730 * ppc-opc.c (MP, VXVAM_MASK): Define.
731 (VXVAPS_MASK): Use VXVA_MASK.
732 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
733 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
734 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
735 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
736
aa3c112f
AM		 7372020-05-11 Alan Modra <amodra@gmail.com>
738 Peter Bergner <bergner@linux.ibm.com>
739
740 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
741 New functions.
742 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
743 YMSK2, XA6a, XA6ap, XB6a entries.
744 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
745 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
746 (PPCVSX4): Define.
747 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
748 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
749 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
750 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
751 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
752 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
753 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
754 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
755 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
756 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
757 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
758 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
759 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
760 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
761
6edbfd3b
AM		 7622020-05-11 Alan Modra <amodra@gmail.com>
763
764 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
765 (insert_xts, extract_xts): New functions.
766 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
767 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
768 (VXRC_MASK, VXSH_MASK): Define.
769 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
770 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
771 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
772 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
773 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
774 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
775 xxblendvh, xxblendvw, xxblendvd, xxpermx.
776
c7d7aea2
AM		 7772020-05-11 Alan Modra <amodra@gmail.com>
778
779 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
780 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
781 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
782 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
783 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
784
94ba9882
AM		 7852020-05-11 Alan Modra <amodra@gmail.com>
786
787 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
788 (XTP, DQXP, DQXP_MASK): Define.
789 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
790 (prefix_opcodes): Add plxvp and pstxvp.
791
f4791f1a
AM		 7922020-05-11 Alan Modra <amodra@gmail.com>
793
794 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
795 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
796 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
797
3ff0a5ba
PB		 7982020-05-11 Peter Bergner <bergner@linux.ibm.com>
799
800 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
801
afef4fe9
PB		 8022020-05-11 Peter Bergner <bergner@linux.ibm.com>
803
804 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
805 (L1OPT): Define.
806 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
807
1224c05d
PB		 8082020-05-11 Peter Bergner <bergner@linux.ibm.com>
809
810 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
811
6bbb0c05
AM		 8122020-05-11 Alan Modra <amodra@gmail.com>
813
814 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
815
7c1f4227
AM		 8162020-05-11 Alan Modra <amodra@gmail.com>
817
818 * ppc-dis.c (ppc_opts): Add "power10" entry.
819 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
820 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
821
73199c2b
NC		 8222020-05-11 Nick Clifton <nickc@redhat.com>
823
824 * po/fr.po: Updated French translation.
825
09c1e68a
AC		 8262020-04-30 Alex Coplan <alex.coplan@arm.com>
827
828 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
829 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
830 (operand_general_constraint_met_p): validate
831 AARCH64_OPND_UNDEFINED.
832 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
833 for FLD_imm16_2.
834 * aarch64-asm-2.c: Regenerated.
835 * aarch64-dis-2.c: Regenerated.
836 * aarch64-opc-2.c: Regenerated.
837
9654d51a
NC		 8382020-04-29 Nick Clifton <nickc@redhat.com>
839
840 PR 22699
841 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
842 and SETRC insns.
843
c2e71e57
NC		 8442020-04-29 Nick Clifton <nickc@redhat.com>
845
846 * po/sv.po: Updated Swedish translation.
847
5c936ef5
NC		 8482020-04-29 Nick Clifton <nickc@redhat.com>
849
850 PR 22699
851 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
852 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
853 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
854 IMM0_8U case.
855
bb2a1453
AS		 8562020-04-21 Andreas Schwab <schwab@linux-m68k.org>
857
858 PR 25848
859 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
860 cmpi only on m68020up and cpu32.
861
c2e5c986
SD		 8622020-04-20 Sudakshina Das <sudi.das@arm.com>
863
864 * aarch64-asm.c (aarch64_ins_none): New.
865 * aarch64-asm.h (ins_none): New declaration.
866 * aarch64-dis.c (aarch64_ext_none): New.
867 * aarch64-dis.h (ext_none): New declaration.
868 * aarch64-opc.c (aarch64_print_operand): Update case for
869 AARCH64_OPND_BARRIER_PSB.
870 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
871 (AARCH64_OPERANDS): Update inserter/extracter for
872 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
873 * aarch64-asm-2.c: Regenerated.
874 * aarch64-dis-2.c: Regenerated.
875 * aarch64-opc-2.c: Regenerated.
876
8a6e1d1d
SD		 8772020-04-20 Sudakshina Das <sudi.das@arm.com>
878
879 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
880 (aarch64_feature_ras, RAS): Likewise.
881 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
882 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
883 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
884 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
885 * aarch64-asm-2.c: Regenerated.
886 * aarch64-dis-2.c: Regenerated.
887 * aarch64-opc-2.c: Regenerated.
888
e409955d
FS		 8892020-04-17 Fredrik Strupe <fredrik@strupe.net>
890
891 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
892 (print_insn_neon): Support disassembly of conditional
893 instructions.
894
c54a9b56
DF		 8952020-02-16 David Faust <david.faust@oracle.com>
896
897 * bpf-desc.c: Regenerate.
898 * bpf-desc.h: Likewise.
899 * bpf-opc.c: Regenerate.
900 * bpf-opc.h: Likewise.
901
bb651e8b
CL		 9022020-04-07 Lili Cui <lili.cui@intel.com>
903
904 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
905 (prefix_table): New instructions (see prefixes above).
906 (rm_table): Likewise
907 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
908 CPU_ANY_TSXLDTRK_FLAGS.
909 (cpu_flags): Add CpuTSXLDTRK.
910 * i386-opc.h (enum): Add CpuTSXLDTRK.
911 (i386_cpu_flags): Add cputsxldtrk.
912 * i386-opc.tbl: Add XSUSPLDTRK insns.
913 * i386-init.h: Regenerate.
914 * i386-tbl.h: Likewise.
915
4b27d27c
L		 9162020-04-02 Lili Cui <lili.cui@intel.com>
917
918 * i386-dis.c (prefix_table): New instructions serialize.
919 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
920 CPU_ANY_SERIALIZE_FLAGS.
921 (cpu_flags): Add CpuSERIALIZE.
922 * i386-opc.h (enum): Add CpuSERIALIZE.
923 (i386_cpu_flags): Add cpuserialize.
924 * i386-opc.tbl: Add SERIALIZE insns.
925 * i386-init.h: Regenerate.
926 * i386-tbl.h: Likewise.
927
832a5807
AM		 9282020-03-26 Alan Modra <amodra@gmail.com>
929
930 * disassemble.h (opcodes_assert): Declare.
931 (OPCODES_ASSERT): Define.
932 * disassemble.c: Don't include assert.h. Include opintl.h.
933 (opcodes_assert): New function.
934 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
935 (bfd_h8_disassemble): Reduce size of data array. Correctly
936 calculate maxlen. Omit insn decoding when insn length exceeds
937 maxlen. Exit from nibble loop when looking for E, before
938 accessing next data byte. Move processing of E outside loop.
939 Replace tests of maxlen in loop with assertions.
940
4c4addbe
AM		 9412020-03-26 Alan Modra <amodra@gmail.com>
942
943 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
944
a18cd0ca
AM		 9452020-03-25 Alan Modra <amodra@gmail.com>
946
947 * z80-dis.c (suffix): Init mybuf.
948
57cb32b3
AM		 9492020-03-22 Alan Modra <amodra@gmail.com>
950
951 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
952 successflly read from section.
953
beea5cc1
AM		 9542020-03-22 Alan Modra <amodra@gmail.com>
955
956 * arc-dis.c (find_format): Use ISO C string concatenation rather
957 than line continuation within a string. Don't access needs_limm
958 before testing opcode != NULL.
959
03704c77
AM		 9602020-03-22 Alan Modra <amodra@gmail.com>
961
962 * ns32k-dis.c (print_insn_arg): Update comment.
963 (print_insn_ns32k): Reduce size of index_offset array, and
964 initialize, passing -1 to print_insn_arg for args that are not
965 an index. Don't exit arg loop early. Abort on bad arg number.
966
d1023b5d
AM		 9672020-03-22 Alan Modra <amodra@gmail.com>
968
969 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
970 * s12z-opc.c: Formatting.
971 (operands_f): Return an int.
972 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
973 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
974 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
975 (exg_sex_discrim): Likewise.
976 (create_immediate_operand, create_bitfield_operand),
977 (create_register_operand_with_size, create_register_all_operand),
978 (create_register_all16_operand, create_simple_memory_operand),
979 (create_memory_operand, create_memory_auto_operand): Don't
980 segfault on malloc failure.
981 (z_ext24_decode): Return an int status, negative on fail, zero
982 on success.
983 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
984 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
985 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
986 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
987 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
988 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
989 (loop_primitive_decode, shift_decode, psh_pul_decode),
990 (bit_field_decode): Similarly.
991 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
992 to return value, update callers.
993 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
994 Don't segfault on NULL operand.
995 (decode_operation): Return OP_INVALID on first fail.
996 (decode_s12z): Check all reads, returning -1 on fail.
997
340f3ac8
AM		 9982020-03-20 Alan Modra <amodra@gmail.com>
999
1000 * metag-dis.c (print_insn_metag): Don't ignore status from
1001 read_memory_func.
1002
fe90ae8a
AM		 10032020-03-20 Alan Modra <amodra@gmail.com>
1004
1005 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1006 Initialize parts of buffer not written when handling a possible
1007 2-byte insn at end of section. Don't attempt decoding of such
1008 an insn by the 4-byte machinery.
1009
833d919c
AM		 10102020-03-20 Alan Modra <amodra@gmail.com>
1011
1012 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1013 partially filled buffer. Prevent lookup of 4-byte insns when
1014 only VLE 2-byte insns are possible due to section size. Print
1015 ".word" rather than ".long" for 2-byte leftovers.
1016
327ef784
NC		 10172020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1018
1019 PR 25641
1020 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1021
1673df32
JB		 10222020-03-13 Jan Beulich <jbeulich@suse.com>
1023
1024 * i386-dis.c (X86_64_0D): Rename to ...
1025 (X86_64_0E): ... this.
1026
384f3689
L		 10272020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1028
1029 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1030 * Makefile.in: Regenerated.
1031
865e2027
JB		 10322020-03-09 Jan Beulich <jbeulich@suse.com>
1033
1034 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1035 3-operand pseudos.
1036 * i386-tbl.h: Re-generate.
1037
2f13234b
JB		 10382020-03-09 Jan Beulich <jbeulich@suse.com>
1039
1040 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1041 vprot*, vpsha*, and vpshl*.
1042 * i386-tbl.h: Re-generate.
1043
3fabc179
JB		 10442020-03-09 Jan Beulich <jbeulich@suse.com>
1045
1046 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1047 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1048 * i386-tbl.h: Re-generate.
1049
3677e4c1
JB		 10502020-03-09 Jan Beulich <jbeulich@suse.com>
1051
1052 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1053 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1054 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1055 * i386-tbl.h: Re-generate.
1056
4c4898e8
JB		 10572020-03-09 Jan Beulich <jbeulich@suse.com>
1058
1059 * i386-gen.c (struct template_arg, struct template_instance,
1060 struct template_param, struct template, templates,
1061 parse_template, expand_templates): New.
1062 (process_i386_opcodes): Various local variables moved to
1063 expand_templates. Call parse_template and expand_templates.
1064 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1065 * i386-tbl.h: Re-generate.
1066
bc49bfd8
JB		 10672020-03-06 Jan Beulich <jbeulich@suse.com>
1068
1069 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1070 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1071 register and memory source templates. Replace VexW= by VexW*
1072 where applicable.
1073 * i386-tbl.h: Re-generate.
1074
4873e243
JB		 10752020-03-06 Jan Beulich <jbeulich@suse.com>
1076
1077 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1078 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1079 * i386-tbl.h: Re-generate.
1080
672a349b
JB		 10812020-03-06 Jan Beulich <jbeulich@suse.com>
1082
1083 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1084 * i386-tbl.h: Re-generate.
1085
4ed21b58
JB		 10862020-03-06 Jan Beulich <jbeulich@suse.com>
1087
1088 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1089 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1090 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1091 VexW0 on SSE2AVX variants.
1092 (vmovq): Drop NoRex64 from XMM/XMM variants.
1093 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1094 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1095 applicable use VexW0.
1096 * i386-tbl.h: Re-generate.
1097
643bb870
JB		 10982020-03-06 Jan Beulich <jbeulich@suse.com>
1099
1100 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1101 * i386-opc.h (Rex64): Delete.
1102 (struct i386_opcode_modifier): Remove rex64 field.
1103 * i386-opc.tbl (crc32): Drop Rex64.
1104 Replace Rex64 with Size64 everywhere else.
1105 * i386-tbl.h: Re-generate.
1106
a23b33b3
JB		 11072020-03-06 Jan Beulich <jbeulich@suse.com>
1108
1109 * i386-dis.c (OP_E_memory): Exclude recording of used address
1110 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1111 addressed memory operands for MPX insns.
1112
a0497384
JB		 11132020-03-06 Jan Beulich <jbeulich@suse.com>
1114
1115 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1116 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1117 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1118 (ptwrite): Split into non-64-bit and 64-bit forms.
1119 * i386-tbl.h: Re-generate.
1120
b630c145
JB		 11212020-03-06 Jan Beulich <jbeulich@suse.com>
1122
1123 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1124 template.
1125 * i386-tbl.h: Re-generate.
1126
a847e322
JB		 11272020-03-04 Jan Beulich <jbeulich@suse.com>
1128
1129 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1130 (prefix_table): Move vmmcall here. Add vmgexit.
1131 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1132 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1133 (cpu_flags): Add CpuSEV_ES entry.
1134 * i386-opc.h (CpuSEV_ES): New.
1135 (union i386_cpu_flags): Add cpusev_es field.
1136 * i386-opc.tbl (vmgexit): New.
1137 * i386-init.h, i386-tbl.h: Re-generate.
1138
3cd7f3e3
L		 11392020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1140
1141 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1142 with MnemonicSize.
1143 * i386-opc.h (IGNORESIZE): New.
1144 (DEFAULTSIZE): Likewise.
1145 (IgnoreSize): Removed.
1146 (DefaultSize): Likewise.
1147 (MnemonicSize): New.
1148 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1149 mnemonicsize.
1150 * i386-opc.tbl (IgnoreSize): New.
1151 (DefaultSize): Likewise.
1152 * i386-tbl.h: Regenerated.
1153
b8ba1385
SB		 11542020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1155
1156 PR 25627
1157 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1158 instructions.
1159
10d97a0f
L		 11602020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1161
1162 PR gas/25622
1163 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1164 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1165 * i386-tbl.h: Regenerated.
1166
dc1e8a47
AM		 11672020-02-26 Alan Modra <amodra@gmail.com>
1168
1169 * aarch64-asm.c: Indent labels correctly.
1170 * aarch64-dis.c: Likewise.
1171 * aarch64-gen.c: Likewise.
1172 * aarch64-opc.c: Likewise.
1173 * alpha-dis.c: Likewise.
1174 * i386-dis.c: Likewise.
1175 * nds32-asm.c: Likewise.
1176 * nfp-dis.c: Likewise.
1177 * visium-dis.c: Likewise.
1178
265b4673
CZ		 11792020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1180
1181 * arc-regs.h (int_vector_base): Make it available for all ARC
1182 CPUs.
1183
bd0cf5a6
NC		 11842020-02-20 Nelson Chu <nelson.chu@sifive.com>
1185
1186 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1187 changed.
1188
fa164239
JW		 11892020-02-19 Nelson Chu <nelson.chu@sifive.com>
1190
1191 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1192 c.mv/c.li if rs1 is zero.
1193
272a84b1
L		 11942020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1195
1196 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1197 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1198 CPU_POPCNT_FLAGS.
1199 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1200 * i386-opc.h (CpuABM): Removed.
1201 (CpuPOPCNT): New.
1202 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1203 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1204 popcnt. Remove CpuABM from lzcnt.
1205 * i386-init.h: Regenerated.
1206 * i386-tbl.h: Likewise.
1207
1f730c46
JB		 12082020-02-17 Jan Beulich <jbeulich@suse.com>
1209
1210 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1211 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1212 VexW1 instead of open-coding them.
1213 * i386-tbl.h: Re-generate.
1214
c8f8eebc
JB		 12152020-02-17 Jan Beulich <jbeulich@suse.com>
1216
1217 * i386-opc.tbl (AddrPrefixOpReg): Define.
1218 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1219 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1220 templates. Drop NoRex64.
1221 * i386-tbl.h: Re-generate.
1222
b9915cbc
JB		 12232020-02-17 Jan Beulich <jbeulich@suse.com>
1224
1225 PR gas/6518
1226 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1227 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1228 into Intel syntax instance (with Unpsecified) and AT&T one
1229 (without).
1230 (vcvtneps2bf16): Likewise, along with folding the two so far
1231 separate ones.
1232 * i386-tbl.h: Re-generate.
1233
ce504911
L		 12342020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1235
1236 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1237 CPU_ANY_SSE4A_FLAGS.
1238
dabec65d
AM		 12392020-02-17 Alan Modra <amodra@gmail.com>
1240
1241 * i386-gen.c (cpu_flag_init): Correct last change.
1242
af5c13b0
L		 12432020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1244
1245 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1246 CPU_ANY_SSE4_FLAGS.
1247
6867aac0
L		 12482020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1249
1250 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1251 (movzx): Likewise.
1252
65fca059
JB		 12532020-02-14 Jan Beulich <jbeulich@suse.com>
1254
1255 PR gas/25438
1256 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1257 destination for Cpu64-only variant.
1258 (movzx): Fold patterns.
1259 * i386-tbl.h: Re-generate.
1260
7deea9aa
JB		 12612020-02-13 Jan Beulich <jbeulich@suse.com>
1262
1263 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1264 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1265 CPU_ANY_SSE4_FLAGS entry.
1266 * i386-init.h: Re-generate.
1267
6c0946d0
JB		 12682020-02-12 Jan Beulich <jbeulich@suse.com>
1269
1270 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1271 with Unspecified, making the present one AT&T syntax only.
1272 * i386-tbl.h: Re-generate.
1273
ddb56fe6
JB		 12742020-02-12 Jan Beulich <jbeulich@suse.com>
1275
1276 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1277 * i386-tbl.h: Re-generate.
1278
5990e377
JB		 12792020-02-12 Jan Beulich <jbeulich@suse.com>
1280
1281 PR gas/24546
1282 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1283 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1284 Amd64 and Intel64 templates.
1285 (call, jmp): Likewise for far indirect variants. Dro
1286 Unspecified.
1287 * i386-tbl.h: Re-generate.
1288
50128d0c
JB		 12892020-02-11 Jan Beulich <jbeulich@suse.com>
1290
1291 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1292 * i386-opc.h (ShortForm): Delete.
1293 (struct i386_opcode_modifier): Remove shortform field.
1294 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1295 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1296 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1297 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1298 Drop ShortForm.
1299 * i386-tbl.h: Re-generate.
1300
1e05b5c4
JB		 13012020-02-11 Jan Beulich <jbeulich@suse.com>
1302
1303 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1304 fucompi): Drop ShortForm from operand-less templates.
1305 * i386-tbl.h: Re-generate.
1306
2f5dd314
AM		 13072020-02-11 Alan Modra <amodra@gmail.com>
1308
1309 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1310 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1311 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1312 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1313 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1314
5aae9ae9
MM		 13152020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1316
1317 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1318 (cde_opcodes): Add VCX* instructions.
1319
4934a27c
MM		 13202020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1321 Matthew Malcomson <matthew.malcomson@arm.com>
1322
1323 * arm-dis.c (struct cdeopcode32): New.
1324 (CDE_OPCODE): New macro.
1325 (cde_opcodes): New disassembly table.
1326 (regnames): New option to table.
1327 (cde_coprocs): New global variable.
1328 (print_insn_cde): New
1329 (print_insn_thumb32): Use print_insn_cde.
1330 (parse_arm_disassembler_options): Parse coprocN args.
1331
4b5aaf5f
L		 13322020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1333
1334 PR gas/25516
1335 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1336 with ISA64.
1337 * i386-opc.h (AMD64): Removed.
1338 (Intel64): Likewose.
1339 (AMD64): New.
1340 (INTEL64): Likewise.
1341 (INTEL64ONLY): Likewise.
1342 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1343 * i386-opc.tbl (Amd64): New.
1344 (Intel64): Likewise.
1345 (Intel64Only): Likewise.
1346 Replace AMD64 with Amd64. Update sysenter/sysenter with
1347 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1348 * i386-tbl.h: Regenerated.
1349
9fc0b501
SB		 13502020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1351
1352 PR 25469
1353 * z80-dis.c: Add support for GBZ80 opcodes.
1354
c5d7be0c
AM		 13552020-02-04 Alan Modra <amodra@gmail.com>
1356
1357 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1358
44e4546f
AM		 13592020-02-03 Alan Modra <amodra@gmail.com>
1360
1361 * m32c-ibld.c: Regenerate.
1362
b2b1453a
AM		 13632020-02-01 Alan Modra <amodra@gmail.com>
1364
1365 * frv-ibld.c: Regenerate.
1366
4102be5c
JB		 13672020-01-31 Jan Beulich <jbeulich@suse.com>
1368
1369 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1370 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1371 (OP_E_memory): Replace xmm_mdq_mode case label by
1372 vex_scalar_w_dq_mode one.
1373 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1374
825bd36c
JB		 13752020-01-31 Jan Beulich <jbeulich@suse.com>
1376
1377 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1378 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1379 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1380 (intel_operand_size): Drop vex_w_dq_mode case label.
1381
c3036ed0
RS		 13822020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1383
1384 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1385 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1386
0c115f84
AM		 13872020-01-30 Alan Modra <amodra@gmail.com>
1388
1389 * m32c-ibld.c: Regenerate.
1390
bd434cc4
JM		 13912020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1392
1393 * bpf-opc.c: Regenerate.
1394
aeab2b26
JB		 13952020-01-30 Jan Beulich <jbeulich@suse.com>
1396
1397 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1398 (dis386): Use them to replace C2/C3 table entries.
1399 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1400 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1401 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1402 * i386-tbl.h: Re-generate.
1403
62b3f548
JB		 14042020-01-30 Jan Beulich <jbeulich@suse.com>
1405
1406 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1407 forms.
1408 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1409 DefaultSize.
1410 * i386-tbl.h: Re-generate.
1411
1bd8ae10
AM		 14122020-01-30 Alan Modra <amodra@gmail.com>
1413
1414 * tic4x-dis.c (tic4x_dp): Make unsigned.
1415
bc31405e
L		 14162020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1417 Jan Beulich <jbeulich@suse.com>
1418
1419 PR binutils/25445
1420 * i386-dis.c (MOVSXD_Fixup): New function.
1421 (movsxd_mode): New enum.
1422 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1423 (intel_operand_size): Handle movsxd_mode.
1424 (OP_E_register): Likewise.
1425 (OP_G): Likewise.
1426 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1427 register on movsxd. Add movsxd with 16-bit destination register
1428 for AMD64 and Intel64 ISAs.
1429 * i386-tbl.h: Regenerated.
1430
7568c93b
TC		 14312020-01-27 Tamar Christina <tamar.christina@arm.com>
1432
1433 PR 25403
1434 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1435 * aarch64-asm-2.c: Regenerate
1436 * aarch64-dis-2.c: Likewise.
1437 * aarch64-opc-2.c: Likewise.
1438
c006a730
JB		 14392020-01-21 Jan Beulich <jbeulich@suse.com>
1440
1441 * i386-opc.tbl (sysret): Drop DefaultSize.
1442 * i386-tbl.h: Re-generate.
1443
c906a69a
JB		 14442020-01-21 Jan Beulich <jbeulich@suse.com>
1445
1446 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1447 Dword.
1448 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1449 * i386-tbl.h: Re-generate.
1450
26916852
NC		 14512020-01-20 Nick Clifton <nickc@redhat.com>
1452
1453 * po/de.po: Updated German translation.
1454 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1455 * po/uk.po: Updated Ukranian translation.
1456
4d6cbb64
AM		 14572020-01-20 Alan Modra <amodra@gmail.com>
1458
1459 * hppa-dis.c (fput_const): Remove useless cast.
1460
2bddb71a
AM		 14612020-01-20 Alan Modra <amodra@gmail.com>
1462
1463 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1464
1b1bb2c6
NC		 14652020-01-18 Nick Clifton <nickc@redhat.com>
1466
1467 * configure: Regenerate.
1468 * po/opcodes.pot: Regenerate.
1469
ae774686
NC		 14702020-01-18 Nick Clifton <nickc@redhat.com>
1471
1472 Binutils 2.34 branch created.
1473
07f1f3aa
CB		 14742020-01-17 Christian Biesinger <cbiesinger@google.com>
1475
1476 * opintl.h: Fix spelling error (seperate).
1477
42e04b36
L		 14782020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1479
1480 * i386-opc.tbl: Add {vex} pseudo prefix.
1481 * i386-tbl.h: Regenerated.
1482
2da2eaf4
AV		 14832020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1484
1485 PR 25376
1486 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1487 (neon_opcodes): Likewise.
1488 (select_arm_features): Make sure we enable MVE bits when selecting
1489 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1490 any architecture.
1491
d0849eed
JB		 14922020-01-16 Jan Beulich <jbeulich@suse.com>
1493
1494 * i386-opc.tbl: Drop stale comment from XOP section.
1495
9cf70a44
JB		 14962020-01-16 Jan Beulich <jbeulich@suse.com>
1497
1498 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1499 (extractps): Add VexWIG to SSE2AVX forms.
1500 * i386-tbl.h: Re-generate.
1501
4814632e
JB		 15022020-01-16 Jan Beulich <jbeulich@suse.com>
1503
1504 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1505 Size64 from and use VexW1 on SSE2AVX forms.
1506 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1507 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1508 * i386-tbl.h: Re-generate.
1509
aad09917
AM		 15102020-01-15 Alan Modra <amodra@gmail.com>
1511
1512 * tic4x-dis.c (tic4x_version): Make unsigned long.
1513 (optab, optab_special, registernames): New file scope vars.
1514 (tic4x_print_register): Set up registernames rather than
1515 malloc'd registertable.
1516 (tic4x_disassemble): Delete optable and optable_special. Use
1517 optab and optab_special instead. Throw away old optab,
1518 optab_special and registernames when info->mach changes.
1519
7a6bf3be
SB		 15202020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1521
1522 PR 25377
1523 * z80-dis.c (suffix): Use .db instruction to generate double
1524 prefix.
1525
ca1eaac0
AM		 15262020-01-14 Alan Modra <amodra@gmail.com>
1527
1528 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1529 values to unsigned before shifting.
1530
1d67fe3b
TT		 15312020-01-13 Thomas Troeger <tstroege@gmx.de>
1532
1533 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1534 flow instructions.
1535 (print_insn_thumb16, print_insn_thumb32): Likewise.
1536 (print_insn): Initialize the insn info.
1537 * i386-dis.c (print_insn): Initialize the insn info fields, and
1538 detect jumps.
1539
5e4f7e05
CZ		 15402012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1541
1542 * arc-opc.c (C_NE): Make it required.
1543
b9fe6b8a
CZ		 15442012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1545
1546 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1547 reserved register name.
1548
90dee485
AM		 15492020-01-13 Alan Modra <amodra@gmail.com>
1550
1551 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1552 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1553
febda64f
AM		 15542020-01-13 Alan Modra <amodra@gmail.com>
1555
1556 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1557 result of wasm_read_leb128 in a uint64_t and check that bits
1558 are not lost when copying to other locals. Use uint32_t for
1559 most locals. Use PRId64 when printing int64_t.
1560
df08b588
AM		 15612020-01-13 Alan Modra <amodra@gmail.com>
1562
1563 * score-dis.c: Formatting.
1564 * score7-dis.c: Formatting.
1565
b2c759ce
AM		 15662020-01-13 Alan Modra <amodra@gmail.com>
1567
1568 * score-dis.c (print_insn_score48): Use unsigned variables for
1569 unsigned values. Don't left shift negative values.
1570 (print_insn_score32): Likewise.
1571 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1572
5496abe1
AM		 15732020-01-13 Alan Modra <amodra@gmail.com>
1574
1575 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1576
202e762b
AM		 15772020-01-13 Alan Modra <amodra@gmail.com>
1578
1579 * fr30-ibld.c: Regenerate.
1580
7ef412cf
AM		 15812020-01-13 Alan Modra <amodra@gmail.com>
1582
1583 * xgate-dis.c (print_insn): Don't left shift signed value.
1584 (ripBits): Formatting, use 1u.
1585
7f578b95
AM		 15862020-01-10 Alan Modra <amodra@gmail.com>
1587
1588 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1589 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1590
441af85b
AM		 15912020-01-10 Alan Modra <amodra@gmail.com>
1592
1593 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1594 and XRREG value earlier to avoid a shift with negative exponent.
1595 * m10200-dis.c (disassemble): Similarly.
1596
bce58db4
NC		 15972020-01-09 Nick Clifton <nickc@redhat.com>
1598
1599 PR 25224
1600 * z80-dis.c (ld_ii_ii): Use correct cast.
1601
40c75bc8
SB		 16022020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1603
1604 PR 25224
1605 * z80-dis.c (ld_ii_ii): Use character constant when checking
1606 opcode byte value.
1607
d835a58b
JB		 16082020-01-09 Jan Beulich <jbeulich@suse.com>
1609
1610 * i386-dis.c (SEP_Fixup): New.
1611 (SEP): Define.
1612 (dis386_twobyte): Use it for sysenter/sysexit.
1613 (enum x86_64_isa): Change amd64 enumerator to value 1.
1614 (OP_J): Compare isa64 against intel64 instead of amd64.
1615 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1616 forms.
1617 * i386-tbl.h: Re-generate.
1618
030a2e78
AM		 16192020-01-08 Alan Modra <amodra@gmail.com>
1620
1621 * z8k-dis.c: Include libiberty.h
1622 (instr_data_s): Make max_fetched unsigned.
1623 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1624 Don't exceed byte_info bounds.
1625 (output_instr): Make num_bytes unsigned.
1626 (unpack_instr): Likewise for nibl_count and loop.
1627 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1628 idx unsigned.
1629 * z8k-opc.h: Regenerate.
1630
bb82aefe
SV		 16312020-01-07 Shahab Vahedi <shahab@synopsys.com>
1632
1633 * arc-tbl.h (llock): Use 'LLOCK' as class.
1634 (llockd): Likewise.
1635 (scond): Use 'SCOND' as class.
1636 (scondd): Likewise.
1637 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1638 (scondd): Likewise.
1639
cc6aa1a6
AM		 16402020-01-06 Alan Modra <amodra@gmail.com>
1641
1642 * m32c-ibld.c: Regenerate.
1643
660e62b1
AM		 16442020-01-06 Alan Modra <amodra@gmail.com>
1645
1646 PR 25344
1647 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1648 Peek at next byte to prevent recursion on repeated prefix bytes.
1649 Ensure uninitialised "mybuf" is not accessed.
1650 (print_insn_z80): Don't zero n_fetch and n_used here,..
1651 (print_insn_z80_buf): ..do it here instead.
1652
c9ae58fe
AM		 16532020-01-04 Alan Modra <amodra@gmail.com>
1654
1655 * m32r-ibld.c: Regenerate.
1656
5f57d4ec
AM		 16572020-01-04 Alan Modra <amodra@gmail.com>
1658
1659 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1660
2c5c1196
AM		 16612020-01-04 Alan Modra <amodra@gmail.com>
1662
1663 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1664
2e98c6c5
AM		 16652020-01-04 Alan Modra <amodra@gmail.com>
1666
1667 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1668
567dfba2
JB		 16692020-01-03 Jan Beulich <jbeulich@suse.com>
1670
5437a02a
JB		 1671 * aarch64-tbl.h (aarch64_opcode_table): Use
1672 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1673
16742020-01-03 Jan Beulich <jbeulich@suse.com>
1675
1676 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1677 forms of SUDOT and USDOT.
1678
8c45011a
JB		 16792020-01-03 Jan Beulich <jbeulich@suse.com>
1680
5437a02a 1681 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1682 uzip{1,2}.
1683 * opcodes/aarch64-dis-2.c: Re-generate.
1684
f4950f76
JB		 16852020-01-03 Jan Beulich <jbeulich@suse.com>
1686
5437a02a 1687 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1688 FMMLA encoding.
1689 * opcodes/aarch64-dis-2.c: Re-generate.
1690
6655dba2
SB		 16912020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1692
1693 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1694
b14ce8bf
AM		 16952020-01-01 Alan Modra <amodra@gmail.com>
1696
1697 Update year range in copyright notice of all files.
1698
0b114740 1699For older changes see ChangeLog-2019
3499769a 1700\f
0b114740 1701Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1702
1703Copying and distribution of this file, with or without modification,
1704are permitted in any medium without royalty provided the copyright
1705notice and this notice are preserved.
1706
1707Local Variables:
1708mode: change-log
1709left-margin: 8
1710fill-column: 74
1711version-control: never
1712End:
GDB Binutils - Deliverables
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