[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.

2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>

	* lm32-desc.c: Regenerate.

2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl (riz): Add RegRex64.
	* i386-tbl.h: Regenerated.

2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

2013-02-27  Alan Modra  <amodra@gmail.com>

	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	* rl78-decode.c: Regenerate.

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
21fde85c SL	1	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	2
	3	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
	4
dd5181d5 KT	5	2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	6
	7	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	8	(thumb32_opcodes): Likewise.
	9	(print_insn_thumb32): Handle 'S' control char.
	10
87a8d6cb NC	11	2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
	12
	13	* lm32-desc.c: Regenerate.
	14
99dce992 L	15	2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
	16
	17	* i386-reg.tbl (riz): Add RegRex64.
	18	* i386-tbl.h: Regenerated.
	19
e60bb1dd YZ	20	2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
	21
	22	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	23	(aarch64_feature_crc): New static.
	24	(CRC): New macro.
	25	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	26	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	27	* aarch64-asm-2.c: Re-generate.
	28	* aarch64-dis-2.c: Ditto.
	29	* aarch64-opc-2.c: Ditto.
	30
c7570fcd AM	31	2013-02-27 Alan Modra <amodra@gmail.com>
	32
	33	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	34	* rl78-decode.c: Regenerate.
	35
151fa98f NC	36	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	37
	38	* rl78-decode.opc: Fix encoding of DIVWU insn.
	39	* rl78-decode.c: Regenerate.
	40
5c111e37 L	41	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	42
	43	PR gas/15159
	44	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	45
	46	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	47	(cpu_flags): Add CpuSMAP.
	48
	49	* i386-opc.h (CpuSMAP): New.
	50	(i386_cpu_flags): Add cpusmap.
	51
	52	* i386-opc.tbl: Add clac and stac.
	53
	54	* i386-init.h: Regenerated.
	55	* i386-tbl.h: Likewise.
	56
9d1df426 NC	57	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	58
	59	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	60	which also makes the disassembler output be in little
	61	endian like it should be.
	62
a1ccaec9 YZ	63	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	64
	65	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	66	fields to NULL.
	67	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	68
ef068ef4	69	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	70
	71	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	72	section disassembled.
	73
6fe6ded9 RE	74	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	75
	76	* arm-dis.c: Update strht pattern.
	77
0aa27725 RS	78	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	79
	80	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	81	single-float. Disable ll, lld, sc and scd for EE. Disable the
	82	trunc.w.s macro for EE.
	83
36591ba1 SL	84	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	85	Andrew Jenner <andrew@codesourcery.com>
	86
	87	Based on patches from Altera Corporation.
	88
	89	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	90	nios2-opc.c.
	91	* Makefile.in: Regenerated.
	92	* configure.in: Add case for bfd_nios2_arch.
	93	* configure: Regenerated.
	94	* disassemble.c (ARCH_nios2): Define.
	95	(disassembler): Add case for bfd_arch_nios2.
	96	* nios2-dis.c: New file.
	97	* nios2-opc.c: New file.
	98
545093a4 AM	99	2013-02-04 Alan Modra <amodra@gmail.com>
	100
	101	* po/POTFILES.in: Regenerate.
	102	* rl78-decode.c: Regenerate.
	103	* rx-decode.c: Regenerate.
	104
e30181a5 YZ	105	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	106
	107	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	108	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	109	* aarch64-asm.c (convert_xtl_to_shll): New function.
	110	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	111	calling convert_xtl_to_shll.
	112	* aarch64-dis.c (convert_shll_to_xtl): New function.
	113	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	114	calling convert_shll_to_xtl.
	115	* aarch64-gen.c: Update copyright year.
	116	* aarch64-asm-2.c: Re-generate.
	117	* aarch64-dis-2.c: Re-generate.
	118	* aarch64-opc-2.c: Re-generate.
	119
78c8d46c NC	120	2013-01-24 Nick Clifton <nickc@redhat.com>
	121
	122	* v850-dis.c: Add support for e3v5 architecture.
	123	* v850-opc.c: Likewise.
	124
f5555712 YZ	125	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	126
	127	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	128	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	129	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	130	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	131	alignment check; change to call set_sft_amount_out_of_range_error
	132	instead of set_imm_out_of_range_error.
	133	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	134	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	135	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	136	SIMD_IMM_SFT.
	137
2f81ff92 L	138	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	139
	140	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	141
	142	* i386-init.h: Regenerated.
	143	* i386-tbl.h: Likewise.
	144
dd42f060 NC	145	2013-01-15 Nick Clifton <nickc@redhat.com>
	146
	147	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	148	values.
	149	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	150
a4533ed8 NC	151	2013-01-14 Will Newton <will.newton@imgtec.com>
	152
	153	* metag-dis.c (REG_WIDTH): Increase to 64.
	154
5817ffd1 PB	155	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	156
	157	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	158	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	159	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	160	(SH6): Update.
	161	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	162	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	163	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	164	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	165
a3c62988 NC	166	2013-01-10 Will Newton <will.newton@imgtec.com>
	167
	168	* Makefile.am: Add Meta.
	169	* configure.in: Add Meta.
	170	* disassemble.c: Add Meta support.
	171	* metag-dis.c: New file.
	172	* Makefile.in: Regenerate.
	173	* configure: Regenerate.
	174
73335eae NC	175	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	176
	177	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	178	(match_opcode): Rename to cr16_match_opcode.
	179
e407c74b NC	180	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	181
	182	* mips-dis.c: Add names for CP0 registers of r5900.
	183	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	184	instructions sq and lq.
	185	Add support for MIPS r5900 CPU.
	186	Add support for 128 bit MMI (Multimedia Instructions).
	187	Add support for EE instructions (Emotion Engine).
	188	Disable unsupported floating point instructions (64 bit and
	189	undefined compare operations).
	190	Enable instructions of MIPS ISA IV which are supported by r5900.
	191	Disable 64 bit co processor instructions.
	192	Disable 64 bit multiplication and division instructions.
	193	Disable instructions for co-processor 2 and 3, because these are
	194	not supported (preparation for later VU0 support (Vector Unit)).
	195	Disable cvt.w.s because this behaves like trunc.w.s and the
	196	correct execution can't be ensured on r5900.
	197	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	198	will confuse less developers and compilers.
	199
a32c3ff8 NC	200	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	201
fb098a1e YZ	202	* aarch64-opc.c (aarch64_print_operand): Change to print
	203	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	204	in comment.
	205	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	206	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	207	OP_MOV_IMM_WIDE.
	208
	209	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	210
	211	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	212	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	213
62658407 L	214	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	215
	216	* i386-gen.c (process_copyright): Update copyright year to 2013.
	217
bab4becb	218	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	219
bab4becb NC	220	* cr16-dis.c (match_opcode,make_instruction): Remove static
	221	declaration.
	222	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	223	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	224
bab4becb	225	For older changes see ChangeLog-2012
252b5132	226	\f
bab4becb	227	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	228
	229	Copying and distribution of this file, with or without modification,
	230	are permitted in any medium without royalty provided the copyright
	231	notice and this notice are preserved.
	232
252b5132	233	Local Variables:
2f6d2f85 NC	234	mode: change-log
	235	left-margin: 8
	236	fill-column: 74
252b5132 RH	237	version-control: never
252b5132 RH	238	End: