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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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23e69e47
RS		 12013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
4 "+S" for "cins".
5 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
6 Combine cases.
7
27c5c572
RS		 82013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
9
10 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
11 "jalx".
12 * mips16-opc.c (mips16_opcodes): Likewise.
13 * micromips-opc.c (micromips_opcodes): Likewise.
14 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
15 (print_insn_mips16): Handle "+i".
16 (print_insn_micromips): Likewise. Conditionally preserve the
17 ISA bit for "a" but not for "+i".
18
e76ff5ab
RS		 192013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
20
21 * micromips-opc.c (WR_mhi): Rename to..
22 (WR_mh): ...this.
23 (micromips_opcodes): Update "movep" entry accordingly. Replace
24 "mh,mi" with "mh".
25 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
26 (micromips_to_32_reg_h_map1): ...this.
27 (micromips_to_32_reg_i_map): Rename to...
28 (micromips_to_32_reg_h_map2): ...this.
29 (print_micromips_insn): Remove "mi" case. Print both registers
30 in the pair for "mh".
31
fa7616a4
RS		 322013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
33
34 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
35 * micromips-opc.c (micromips_opcodes): Likewise.
36 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
37 and "+T" handling. Check for a "0" suffix when deciding whether to
38 use coprocessor 0 names. In that case, also check for ",H" selectors.
39
fb798c50
AK		 402013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
41
42 * s390-opc.c (J12_12, J24_24): New macros.
43 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
44 (MASK_MII_UPI): Rename to MASK_MII_UPP.
45 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
46
58ae08f2
AM		 472013-07-04 Alan Modra <amodra@gmail.com>
48
49 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
50
b5e04c2b
NC		 512013-06-26 Nick Clifton <nickc@redhat.com>
52
53 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
54 field when checking for type 2 nop.
55 * rx-decode.c: Regenerate.
56
833794fc
MR		 572013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
58
59 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
60 and "movep" macros.
61
1bbce132
MR		 622013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
63
64 * mips-dis.c (is_mips16_plt_tail): New function.
65 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
66 word.
67 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
68
34c911a4
NC		 692013-06-21 DJ Delorie <dj@redhat.com>
70
71 * msp430-decode.opc: New.
72 * msp430-decode.c: New/generated.
73 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
74 (MAINTAINER_CLEANFILES): Likewise.
75 Add rule to build msp430-decode.c frommsp430decode.opc
76 using the opc2c program.
77 * Makefile.in: Regenerate.
78 * configure.in: Add msp430-decode.lo to msp430 architecture files.
79 * configure: Regenerate.
80
b9eead84
YZ		 812013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
82
83 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
84 (SYMTAB_AVAILABLE): Removed.
85 (#include "elf/aarch64.h): Ditto.
86
7f3c4072
CM		 872013-06-17 Catherine Moore <clm@codesourcery.com>
88 Maciej W. Rozycki <macro@codesourcery.com>
89 Chao-Ying Fu <fu@mips.com>
90
91 * micromips-opc.c (EVA): Define.
92 (TLBINV): Define.
93 (micromips_opcodes): Add EVA opcodes.
94 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
95 (print_insn_args): Handle EVA offsets.
96 (print_insn_micromips): Likewise.
97 * mips-opc.c (EVA): Define.
98 (TLBINV): Define.
99 (mips_builtin_opcodes): Add EVA opcodes.
100
de40ceb6
AM		 1012013-06-17 Alan Modra <amodra@gmail.com>
102
103 * Makefile.am (mips-opc.lo): Add rules to create automatic
104 dependency files. Pass archdefs.
105 (micromips-opc.lo, mips16-opc.lo): Likewise.
106 * Makefile.in: Regenerate.
107
3531d549
DD		 1082013-06-14 DJ Delorie <dj@redhat.com>
109
110 * rx-decode.opc (rx_decode_opcode): Bit operations on
111 registers are 32-bit operations, not 8-bit operations.
112 * rx-decode.c: Regenerate.
113
ba92f7fb
CF		 1142013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
115
116 * micromips-opc.c (IVIRT): New define.
117 (IVIRT64): New define.
118 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
119 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
120
121 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
122 dmtgc0 to print cp0 names.
123
9daf7bab
SL		 1242013-06-09 Sandra Loosemore <sandra@codesourcery.com>
125
126 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
127 argument.
128
d301a56b
RS		 1292013-06-08 Catherine Moore <clm@codesourcery.com>
130 Richard Sandiford <rdsandiford@googlemail.com>
131
132 * micromips-opc.c (D32, D33, MC): Update definitions.
133 (micromips_opcodes): Initialize ase field.
134 * mips-dis.c (mips_arch_choice): Add ase field.
135 (mips_arch_choices): Initialize ase field.
136 (set_default_mips_dis_options): Declare and setup mips_ase.
137 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
138 MT32, MC): Update definitions.
139 (mips_builtin_opcodes): Initialize ase field.
140
a3dcb6c5
RS		 1412013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
142
143 * s390-opc.txt (flogr): Require a register pair destination.
144
6cf1d90c
AK		 1452013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
146
147 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
148 instruction format.
149
c77c0862
RS		 1502013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
151
152 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
153
c0637f3a
PB		 1542013-05-20 Peter Bergner <bergner@vnet.ibm.com>
155
156 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
157 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
158 XLS_MASK, PPCVSX2): New defines.
159 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
160 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
161 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
162 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
163 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
164 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
165 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
166 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
167 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
168 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
169 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
170 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
171 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
172 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
173 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
174 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
175 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
176 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
177 <lxvx, stxvx>: New extended mnemonics.
178
4934fdaf
AM		 1792013-05-17 Alan Modra <amodra@gmail.com>
180
181 * ia64-raw.tbl: Replace non-ASCII char.
182 * ia64-waw.tbl: Likewise.
183 * ia64-asmtab.c: Regenerate.
184
6091d651
SE		 1852013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
186
187 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
188 * i386-init.h: Regenerated.
189
d2865ed3
YZ		 1902013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
191
192 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
193 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
194 check from [0, 255] to [-128, 255].
195
b015e599
AP		 1962013-05-09 Andrew Pinski <apinski@cavium.com>
197
198 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
199 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
200 (parse_mips_dis_option): Handle the virt option.
201 (print_insn_args): Handle "+J".
202 (print_mips_disassembler_options): Print out message about virt64.
203 * mips-opc.c (IVIRT): New define.
204 (IVIRT64): New define.
205 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
206 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
207 Move rfe to the bottom as it conflicts with tlbgp.
208
9f0682fe
AM		 2092013-05-09 Alan Modra <amodra@gmail.com>
210
211 * ppc-opc.c (extract_vlesi): Properly sign extend.
212 (extract_vlensi): Likewise. Comment reason for setting invalid.
213
13761a11
NC		 2142013-05-02 Nick Clifton <nickc@redhat.com>
215
216 * msp430-dis.c: Add support for MSP430X instructions.
217
e3031850
SL		 2182013-04-24 Sandra Loosemore <sandra@codesourcery.com>
219
220 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
221 to "eccinj".
222
17310e56
NC		 2232013-04-17 Wei-chen Wang <cole945@gmail.com>
224
225 PR binutils/15369
226 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
227 of CGEN_CPU_ENDIAN.
228 (hash_insns_list): Likewise.
229
731df338
JK		 2302013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
231
232 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
233 warning workaround.
234
5f77db52
JB		 2352013-04-08 Jan Beulich <jbeulich@suse.com>
236
237 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
238 * i386-tbl.h: Re-generate.
239
0afd1215
DM		 2402013-04-06 David S. Miller <davem@davemloft.net>
241
242 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
243 of an opcode, prefer the one with F_PREFERRED set.
244 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
245 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
246 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
247 mark existing mnenomics as aliases. Add "cc" suffix to edge
248 instructions generating condition codes, mark existing mnenomics
249 as aliases. Add "fp" prefix to VIS compare instructions, mark
250 existing mnenomics as aliases.
251
41702d50
NC		 2522013-04-03 Nick Clifton <nickc@redhat.com>
253
254 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
255 destination address by subtracting the operand from the current
256 address.
257 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
258 a positive value in the insn.
259 (extract_u16_loop): Do not negate the returned value.
260 (D16_LOOP): Add V850_INVERSE_PCREL flag.
261
262 (ceilf.sw): Remove duplicate entry.
263 (cvtf.hs): New entry.
264 (cvtf.sh): Likewise.
265 (fmaf.s): Likewise.
266 (fmsf.s): Likewise.
267 (fnmaf.s): Likewise.
268 (fnmsf.s): Likewise.
269 (maddf.s): Restrict to E3V5 architectures.
270 (msubf.s): Likewise.
271 (nmaddf.s): Likewise.
272 (nmsubf.s): Likewise.
273
55cf16e1
L		 2742013-03-27 H.J. Lu <hongjiu.lu@intel.com>
275
276 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
277 check address mode.
278 (print_insn): Pass sizeflag to get_sib.
279
51dcdd4d
NC		 2802013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
281
282 PR binutils/15068
283 * tic6x-dis.c: Add support for displaying 16-bit insns.
284
795b8e6b
NC		 2852013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
286
287 PR gas/15095
288 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
289 individual msb and lsb halves in src1 & src2 fields. Discard the
290 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
291 follow what Ti SDK does in that case as any value in the src1
292 field yields the same output with SDK disassembler.
293
314d60dd
ME		 2942013-03-12 Michael Eager <eager@eagercon.com>
295
795b8e6b 296 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 297
dad60f8e
SL		 2982013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
299
300 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
301
f5cb796a
SL		 3022013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
303
304 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
305
21fde85c
SL		 3062013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
307
308 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
309
dd5181d5
KT		 3102013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
311
312 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
313 (thumb32_opcodes): Likewise.
314 (print_insn_thumb32): Handle 'S' control char.
315
87a8d6cb
NC		 3162013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
317
318 * lm32-desc.c: Regenerate.
319
99dce992
L		 3202013-03-01 H.J. Lu <hongjiu.lu@intel.com>
321
322 * i386-reg.tbl (riz): Add RegRex64.
323 * i386-tbl.h: Regenerated.
324
e60bb1dd
YZ		 3252013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
326
327 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
328 (aarch64_feature_crc): New static.
329 (CRC): New macro.
330 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
331 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
332 * aarch64-asm-2.c: Re-generate.
333 * aarch64-dis-2.c: Ditto.
334 * aarch64-opc-2.c: Ditto.
335
c7570fcd
AM		 3362013-02-27 Alan Modra <amodra@gmail.com>
337
338 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
339 * rl78-decode.c: Regenerate.
340
151fa98f
NC		 3412013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
342
343 * rl78-decode.opc: Fix encoding of DIVWU insn.
344 * rl78-decode.c: Regenerate.
345
5c111e37
L		 3462013-02-19 H.J. Lu <hongjiu.lu@intel.com>
347
348 PR gas/15159
349 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
350
351 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
352 (cpu_flags): Add CpuSMAP.
353
354 * i386-opc.h (CpuSMAP): New.
355 (i386_cpu_flags): Add cpusmap.
356
357 * i386-opc.tbl: Add clac and stac.
358
359 * i386-init.h: Regenerated.
360 * i386-tbl.h: Likewise.
361
9d1df426
NC		 3622013-02-15 Markos Chandras <markos.chandras@imgtec.com>
363
364 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
365 which also makes the disassembler output be in little
366 endian like it should be.
367
a1ccaec9
YZ		 3682013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
369
370 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
371 fields to NULL.
372 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
373
ef068ef4 3742013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 375
376 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
377 section disassembled.
378
6fe6ded9
RE		 3792013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
380
381 * arm-dis.c: Update strht pattern.
382
0aa27725
RS		 3832013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
384
385 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
386 single-float. Disable ll, lld, sc and scd for EE. Disable the
387 trunc.w.s macro for EE.
388
36591ba1
SL		 3892013-02-06 Sandra Loosemore <sandra@codesourcery.com>
390 Andrew Jenner <andrew@codesourcery.com>
391
392 Based on patches from Altera Corporation.
393
394 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
395 nios2-opc.c.
396 * Makefile.in: Regenerated.
397 * configure.in: Add case for bfd_nios2_arch.
398 * configure: Regenerated.
399 * disassemble.c (ARCH_nios2): Define.
400 (disassembler): Add case for bfd_arch_nios2.
401 * nios2-dis.c: New file.
402 * nios2-opc.c: New file.
403
545093a4
AM		 4042013-02-04 Alan Modra <amodra@gmail.com>
405
406 * po/POTFILES.in: Regenerate.
407 * rl78-decode.c: Regenerate.
408 * rx-decode.c: Regenerate.
409
e30181a5
YZ		 4102013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
411
412 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
413 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
414 * aarch64-asm.c (convert_xtl_to_shll): New function.
415 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
416 calling convert_xtl_to_shll.
417 * aarch64-dis.c (convert_shll_to_xtl): New function.
418 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
419 calling convert_shll_to_xtl.
420 * aarch64-gen.c: Update copyright year.
421 * aarch64-asm-2.c: Re-generate.
422 * aarch64-dis-2.c: Re-generate.
423 * aarch64-opc-2.c: Re-generate.
424
78c8d46c
NC		 4252013-01-24 Nick Clifton <nickc@redhat.com>
426
427 * v850-dis.c: Add support for e3v5 architecture.
428 * v850-opc.c: Likewise.
429
f5555712
YZ		 4302013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
431
432 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
433 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
434 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 435 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 436 alignment check; change to call set_sft_amount_out_of_range_error
437 instead of set_imm_out_of_range_error.
438 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
439 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
440 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
441 SIMD_IMM_SFT.
442
2f81ff92
L		 4432013-01-16 H.J. Lu <hongjiu.lu@intel.com>
444
445 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
446
447 * i386-init.h: Regenerated.
448 * i386-tbl.h: Likewise.
449
dd42f060
NC		 4502013-01-15 Nick Clifton <nickc@redhat.com>
451
452 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
453 values.
454 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
455
a4533ed8
NC		 4562013-01-14 Will Newton <will.newton@imgtec.com>
457
458 * metag-dis.c (REG_WIDTH): Increase to 64.
459
5817ffd1
PB		 4602013-01-10 Peter Bergner <bergner@vnet.ibm.com>
461
462 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
463 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
464 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
465 (SH6): Update.
466 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
467 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
468 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
469 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
470
a3c62988
NC		 4712013-01-10 Will Newton <will.newton@imgtec.com>
472
473 * Makefile.am: Add Meta.
474 * configure.in: Add Meta.
475 * disassemble.c: Add Meta support.
476 * metag-dis.c: New file.
477 * Makefile.in: Regenerate.
478 * configure: Regenerate.
479
73335eae
NC		 4802013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
481
482 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
483 (match_opcode): Rename to cr16_match_opcode.
484
e407c74b
NC		 4852013-01-04 Juergen Urban <JuergenUrban@gmx.de>
486
487 * mips-dis.c: Add names for CP0 registers of r5900.
488 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
489 instructions sq and lq.
490 Add support for MIPS r5900 CPU.
491 Add support for 128 bit MMI (Multimedia Instructions).
492 Add support for EE instructions (Emotion Engine).
493 Disable unsupported floating point instructions (64 bit and
494 undefined compare operations).
495 Enable instructions of MIPS ISA IV which are supported by r5900.
496 Disable 64 bit co processor instructions.
497 Disable 64 bit multiplication and division instructions.
498 Disable instructions for co-processor 2 and 3, because these are
499 not supported (preparation for later VU0 support (Vector Unit)).
500 Disable cvt.w.s because this behaves like trunc.w.s and the
501 correct execution can't be ensured on r5900.
502 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
503 will confuse less developers and compilers.
504
a32c3ff8
NC		 5052013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
506
fb098a1e
YZ		 507 * aarch64-opc.c (aarch64_print_operand): Change to print
508 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
509 in comment.
510 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
511 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
512 OP_MOV_IMM_WIDE.
513
5142013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
515
516 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
517 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 518
62658407
L		 5192013-01-02 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-gen.c (process_copyright): Update copyright year to 2013.
522
bab4becb 5232013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 524
bab4becb
NC		 525 * cr16-dis.c (match_opcode,make_instruction): Remove static
526 declaration.
527 (dwordU,wordU): Moved typedefs to opcode/cr16.h
528 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 529
bab4becb 530For older changes see ChangeLog-2012
252b5132 531\f
bab4becb 532Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 533
534Copying and distribution of this file, with or without modification,
535are permitted in any medium without royalty provided the copyright
536notice and this notice are preserved.
537
252b5132 538Local Variables:
2f6d2f85
NC		 539mode: change-log
540left-margin: 8
541fill-column: 74
252b5132
RH		 542version-control: never
543End:
GDB Binutils - Deliverables
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