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More signed overflow fixes
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
2480b6fa
AM		 12019-12-18 Alan Modra <amodra@gmail.com>
2
3 * alpha-opc.c (OP): Avoid signed overflow.
4 * arm-dis.c (print_insn): Likewise.
5 * mcore-dis.c (print_insn_mcore): Likewise.
6 * pj-dis.c (get_int): Likewise.
7 * ppc-opc.c (EBD15, EBD15BI): Likewise.
8 * score7-dis.c (s7_print_insn): Likewise.
9 * tic30-dis.c (print_insn_tic30): Likewise.
10 * v850-opc.c (insert_SELID): Likewise.
11 * vax-dis.c (print_insn_vax): Likewise.
12 * arc-ext.c (create_map): Likewise.
13 (struct ExtAuxRegister): Make "address" field unsigned int.
14 (arcExtMap_auxRegName): Pass unsigned address.
15 (dump_ARC_extmap): Adjust.
16 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
17
eb7b5046
AM		 182019-12-17 Alan Modra <amodra@gmail.com>
19
20 * visium-dis.c (print_insn_visium): Avoid signed overflow.
21
29298bf6
AM		 222019-12-17 Alan Modra <amodra@gmail.com>
23
24 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
25 (value_fit_unsigned_field_p): Likewise.
26 (aarch64_wide_constant_p): Likewise.
27 (operand_general_constraint_met_p): Likewise.
28 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
29
e46d79a7
AM		 302019-12-17 Alan Modra <amodra@gmail.com>
31
32 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
33 (print_insn_nds32): Use uint64_t for "given" and "given1".
34
5b660084
AM		 352019-12-17 Alan Modra <amodra@gmail.com>
36
37 * tic80-dis.c: Delete file.
38 * tic80-opc.c: Delete file.
39 * disassemble.c: Remove tic80 support.
40 * disassemble.h: Likewise.
41 * Makefile.am: Likewise.
42 * configure.ac: Likewise.
43 * Makefile.in: Regenerate.
44 * configure: Regenerate.
45 * po/POTFILES.in: Regenerate.
46
62e65990
AM		 472019-12-17 Alan Modra <amodra@gmail.com>
48
49 * bpf-ibld.c: Regenerate.
50
f81e7e2d
AM		 512019-12-16 Alan Modra <amodra@gmail.com>
52
53 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
54 conditional.
55 (aarch64_ext_imm): Avoid signed overflow.
56
488d02fe
AM		 572019-12-16 Alan Modra <amodra@gmail.com>
58
59 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
60
8a92faab
AM		 612019-12-16 Alan Modra <amodra@gmail.com>
62
63 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
64
e6ced26a
AM		 652019-12-16 Alan Modra <amodra@gmail.com>
66
67 * xstormy16-ibld.c: Regenerate.
68
84e098cd
AM		 692019-12-16 Alan Modra <amodra@gmail.com>
70
71 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
72 value adjustment so that it doesn't affect reg field too.
73
36bd8ea7
AM		 742019-12-16 Alan Modra <amodra@gmail.com>
75
76 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
77 (get_number_of_operands, getargtype, getbits, getregname),
78 (getcopregname, getprocregname, gettrapstring, getcinvstring),
79 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
80 (powerof2, match_opcode, make_instruction, print_arguments),
81 (print_arg): Delete forward declarations, moving static to..
82 (getregname, getcopregname, getregliststring): ..these definitions.
83 (build_mask): Return unsigned int mask.
84 (match_opcode): Use unsigned int vars.
85
cedfc774
AM		 862019-12-16 Alan Modra <amodra@gmail.com>
87
88 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
89
4bdb25fe
AM		 902019-12-16 Alan Modra <amodra@gmail.com>
91
92 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
93 (struct objdump_disasm_info): Delete.
94 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
95 N32_IMMS to unsigned before shifting left.
96
cf950fd4
AM		 972019-12-16 Alan Modra <amodra@gmail.com>
98
99 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
100 (print_insn_moxie): Remove unnecessary cast.
101
967354c3
AM		 1022019-12-12 Alan Modra <amodra@gmail.com>
103
104 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
105 mask.
106
1d61b032
AM		 1072019-12-11 Alan Modra <amodra@gmail.com>
108
109 * arc-dis.c (BITS): Don't truncate high bits with shifts.
110 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
111 * tic54x-dis.c (print_instruction): Likewise.
112 * tilegx-opc.c (parse_insn_tilegx): Likewise.
113 * tilepro-opc.c (parse_insn_tilepro): Likewise.
114 * visium-dis.c (disassem_class0): Likewise.
115 * pdp11-dis.c (sign_extend): Likewise.
116 (SIGN_BITS): Delete.
117 * epiphany-ibld.c: Regenerate.
118 * lm32-ibld.c: Regenerate.
119 * m32c-ibld.c: Regenerate.
120
5afa80e9
AM		 1212019-12-11 Alan Modra <amodra@gmail.com>
122
123 * ns32k-dis.c (sign_extend): Correct last patch.
124
5c05618a
AM		 1252019-12-11 Alan Modra <amodra@gmail.com>
126
127 * vax-dis.c (NEXTLONG): Avoid signed overflow.
128
2a81ccbb
AM		 1292019-12-11 Alan Modra <amodra@gmail.com>
130
131 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
132 sign extend using shifts.
133
b84f6152
AM		 1342019-12-11 Alan Modra <amodra@gmail.com>
135
136 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
137
66152f16
AM		 1382019-12-11 Alan Modra <amodra@gmail.com>
139
140 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
141 on NULL registertable entry.
142 (tic4x_hash_opcode): Use unsigned arithmetic.
143
205c426a
AM		 1442019-12-11 Alan Modra <amodra@gmail.com>
145
146 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
147
fb4cb4e2
AM		 1482019-12-11 Alan Modra <amodra@gmail.com>
149
150 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
151 (bit_extract_simple, sign_extend): Likewise.
152
96f1f604
AM		 1532019-12-11 Alan Modra <amodra@gmail.com>
154
155 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
156
8c9b4171
AM		 1572019-12-11 Alan Modra <amodra@gmail.com>
158
159 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
160
334175b6
AM		 1612019-12-11 Alan Modra <amodra@gmail.com>
162
163 * m68k-dis.c (COERCE32): Cast value first.
164 (NEXTLONG, NEXTULONG): Avoid signed overflow.
165
f8a87c78
AM		 1662019-12-11 Alan Modra <amodra@gmail.com>
167
168 * h8300-dis.c (extract_immediate): Avoid signed overflow.
169 (bfd_h8_disassemble): Likewise.
170
159653d8
AM		 1712019-12-11 Alan Modra <amodra@gmail.com>
172
173 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
174 past end of operands array.
175
d93bba9e
AM		 1762019-12-11 Alan Modra <amodra@gmail.com>
177
178 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
179 overflow when collecting bytes of a number.
180
c202f69e
AM		 1812019-12-11 Alan Modra <amodra@gmail.com>
182
183 * cris-dis.c (print_with_operands): Avoid signed integer
184 overflow when collecting bytes of a 32-bit integer.
185
0ef562a4
AM		 1862019-12-11 Alan Modra <amodra@gmail.com>
187
188 * cr16-dis.c (EXTRACT, SBM): Rewrite.
189 (cr16_match_opcode): Delete duplicate bcond test.
190
2fd2b153
AM		 1912019-12-11 Alan Modra <amodra@gmail.com>
192
193 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
194 (SIGNBIT): New.
195 (MASKBITS, SIGNEXTEND): Rewrite.
196 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
197 unsigned arithmetic, instead assign result of SIGNEXTEND back
198 to x.
199 (fmtconst_val): Use 1u in shift expression.
200
a11db3e9
AM		 2012019-12-11 Alan Modra <amodra@gmail.com>
202
203 * arc-dis.c (find_format_from_table): Use ull constant when
204 shifting by up to 32.
205
9d48687b
AM		 2062019-12-11 Alan Modra <amodra@gmail.com>
207
208 PR 25270
209 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
210 false when field is zero for sve_size_tsz_bhs.
211
b8e61daa
AM		 2122019-12-11 Alan Modra <amodra@gmail.com>
213
214 * epiphany-ibld.c: Regenerate.
215
20135676
AM		 2162019-12-10 Alan Modra <amodra@gmail.com>
217
218 PR 24960
219 * disassemble.c (disassemble_free_target): New function.
220
103ebbc3
AM		 2212019-12-10 Alan Modra <amodra@gmail.com>
222
223 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
224 * disassemble.c (disassemble_init_for_target): Likewise.
225 * bpf-dis.c: Regenerate.
226 * epiphany-dis.c: Regenerate.
227 * fr30-dis.c: Regenerate.
228 * frv-dis.c: Regenerate.
229 * ip2k-dis.c: Regenerate.
230 * iq2000-dis.c: Regenerate.
231 * lm32-dis.c: Regenerate.
232 * m32c-dis.c: Regenerate.
233 * m32r-dis.c: Regenerate.
234 * mep-dis.c: Regenerate.
235 * mt-dis.c: Regenerate.
236 * or1k-dis.c: Regenerate.
237 * xc16x-dis.c: Regenerate.
238 * xstormy16-dis.c: Regenerate.
239
6f0e0752
AM		 2402019-12-10 Alan Modra <amodra@gmail.com>
241
242 * ppc-dis.c (private): Delete variable.
243 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
244 (powerpc_init_dialect): Don't use global private.
245
e7c22a69
AM		 2462019-12-10 Alan Modra <amodra@gmail.com>
247
248 * s12z-opc.c: Formatting.
249
0a6aef6b
AM		 2502019-12-08 Alan Modra <amodra@gmail.com>
251
252 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
253 registers.
254
2dc4b12f
JB		 2552019-12-05 Jan Beulich <jbeulich@suse.com>
256
257 * aarch64-tbl.h (aarch64_feature_crypto,
258 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
259 CRYPTO_V8_2_INSN): Delete.
260
378fd436
AM		 2612019-12-05 Alan Modra <amodra@gmail.com>
262
263 PR 25249
264 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
265 (struct string_buf): New.
266 (strbuf): New function.
267 (get_field): Use strbuf rather than strdup of local temp.
268 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
269 (get_field_rfsl, get_field_imm15): Likewise.
270 (get_field_rd, get_field_r1, get_field_r2): Update macros.
271 (get_field_special): Likewise. Don't strcpy spr. Formatting.
272 (print_insn_microblaze): Formatting. Init and pass string_buf to
273 get_field functions.
274
0ba59a29
JB		 2752019-12-04 Jan Beulich <jbeulich@suse.com>
276
277 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
278 * i386-tbl.h: Re-generate.
279
77ad8092
JB		 2802019-12-04 Jan Beulich <jbeulich@suse.com>
281
282 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
283
3036c899
JB		 2842019-12-04 Jan Beulich <jbeulich@suse.com>
285
286 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
287 forms.
288 (xbegin): Drop DefaultSize.
289 * i386-tbl.h: Re-generate.
290
8b301fbb
MI		 2912019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
292
293 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
294 Change the coproc CRC conditions to use the extension
295 feature set, second word, base on ARM_EXT2_CRC.
296
6aa385b9
JB		 2972019-11-14 Jan Beulich <jbeulich@suse.com>
298
299 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
300 * i386-tbl.h: Re-generate.
301
0cfa3eb3
JB		 3022019-11-14 Jan Beulich <jbeulich@suse.com>
303
304 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
305 JumpInterSegment, and JumpAbsolute entries.
306 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
307 JUMP_ABSOLUTE): Define.
308 (struct i386_opcode_modifier): Extend jump field to 3 bits.
309 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
310 fields.
311 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
312 JumpInterSegment): Define.
313 * i386-tbl.h: Re-generate.
314
6f2f06be
JB		 3152019-11-14 Jan Beulich <jbeulich@suse.com>
316
317 * i386-gen.c (operand_type_init): Remove
318 OPERAND_TYPE_JUMPABSOLUTE entry.
319 (opcode_modifiers): Add JumpAbsolute entry.
320 (operand_types): Remove JumpAbsolute entry.
321 * i386-opc.h (JumpAbsolute): Move between enums.
322 (struct i386_opcode_modifier): Add jumpabsolute field.
323 (union i386_operand_type): Remove jumpabsolute field.
324 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
325 * i386-init.h, i386-tbl.h: Re-generate.
326
601e8564
JB		 3272019-11-14 Jan Beulich <jbeulich@suse.com>
328
329 * i386-gen.c (opcode_modifiers): Add AnySize entry.
330 (operand_types): Remove AnySize entry.
331 * i386-opc.h (AnySize): Move between enums.
332 (struct i386_opcode_modifier): Add anysize field.
333 (OTUnused): Un-comment.
334 (union i386_operand_type): Remove anysize field.
335 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
336 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
337 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
338 AnySize.
339 * i386-tbl.h: Re-generate.
340
7722d40a
JW		 3412019-11-12 Nelson Chu <nelson.chu@sifive.com>
342
343 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
344 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
345 use the floating point register (FPR).
346
ce760a76
MI		 3472019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
348
349 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
350 cmode 1101.
351 (is_mve_encoding_conflict): Update cmode conflict checks for
352 MVE_VMVN_IMM.
353
51c8edf6
JB		 3542019-11-12 Jan Beulich <jbeulich@suse.com>
355
356 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
357 entry.
358 (operand_types): Remove EsSeg entry.
359 (main): Replace stale use of OTMax.
360 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
361 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
362 (EsSeg): Delete.
363 (OTUnused): Comment out.
364 (union i386_operand_type): Remove esseg field.
365 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
366 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
367 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
368 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
369 * i386-init.h, i386-tbl.h: Re-generate.
370
474da251
JB		 3712019-11-12 Jan Beulich <jbeulich@suse.com>
372
373 * i386-gen.c (operand_instances): Add RegB entry.
374 * i386-opc.h (enum operand_instance): Add RegB.
375 * i386-opc.tbl (RegC, RegD, RegB): Define.
376 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
377 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
378 monitorx, mwaitx): Drop ImmExt and convert encodings
379 accordingly.
380 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
381 (edx, rdx): Add Instance=RegD.
382 (ebx, rbx): Add Instance=RegB.
383 * i386-tbl.h: Re-generate.
384
75e5731b
JB		 3852019-11-12 Jan Beulich <jbeulich@suse.com>
386
387 * i386-gen.c (operand_type_init): Adjust
388 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
389 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
390 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
391 (operand_instances): New.
392 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
393 (output_operand_type): New parameter "instance". Process it.
394 (process_i386_operand_type): New local variable "instance".
395 (main): Adjust static assertions.
396 * i386-opc.h (INSTANCE_WIDTH): Define.
397 (enum operand_instance): New.
398 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
399 (union i386_operand_type): Replace acc, inoutportreg, and
400 shiftcount by instance.
401 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
402 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
403 Add Instance=.
404 * i386-init.h, i386-tbl.h: Re-generate.
405
91802f3c
JB		 4062019-11-11 Jan Beulich <jbeulich@suse.com>
407
408 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
409 smaxp/sminp entries' "tied_operand" field to 2.
410
4f5fc85d
JB		 4112019-11-11 Jan Beulich <jbeulich@suse.com>
412
413 * aarch64-opc.c (operand_general_constraint_met_p): Replace
414 "index" local variable by that of the already existing "num".
415
dc2be329
L		 4162019-11-08 H.J. Lu <hongjiu.lu@intel.com>
417
418 PR gas/25167
419 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
420 * i386-tbl.h: Regenerated.
421
f74a6307
JB		 4222019-11-08 Jan Beulich <jbeulich@suse.com>
423
424 * i386-gen.c (operand_type_init): Add Class= to
425 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
426 OPERAND_TYPE_REGBND entry.
427 (operand_classes): Add RegMask and RegBND entries.
428 (operand_types): Drop RegMask and RegBND entry.
429 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
430 (RegMask, RegBND): Delete.
431 (union i386_operand_type): Remove regmask and regbnd fields.
432 * i386-opc.tbl (RegMask, RegBND): Define.
433 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
434 Class=RegBND.
435 * i386-init.h, i386-tbl.h: Re-generate.
436
3528c362
JB		 4372019-11-08 Jan Beulich <jbeulich@suse.com>
438
439 * i386-gen.c (operand_type_init): Add Class= to
440 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
441 OPERAND_TYPE_REGZMM entries.
442 (operand_classes): Add RegMMX and RegSIMD entries.
443 (operand_types): Drop RegMMX and RegSIMD entries.
444 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
445 (RegMMX, RegSIMD): Delete.
446 (union i386_operand_type): Remove regmmx and regsimd fields.
447 * i386-opc.tbl (RegMMX): Define.
448 (RegXMM, RegYMM, RegZMM): Add Class=.
449 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
450 Class=RegSIMD.
451 * i386-init.h, i386-tbl.h: Re-generate.
452
4a5c67ed
JB		 4532019-11-08 Jan Beulich <jbeulich@suse.com>
454
455 * i386-gen.c (operand_type_init): Add Class= to
456 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
457 entries.
458 (operand_classes): Add RegCR, RegDR, and RegTR entries.
459 (operand_types): Drop Control, Debug, and Test entries.
460 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
461 (Control, Debug, Test): Delete.
462 (union i386_operand_type): Remove control, debug, and test
463 fields.
464 * i386-opc.tbl (Control, Debug, Test): Define.
465 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
466 Class=RegDR, and Test by Class=RegTR.
467 * i386-init.h, i386-tbl.h: Re-generate.
468
00cee14f
JB		 4692019-11-08 Jan Beulich <jbeulich@suse.com>
470
471 * i386-gen.c (operand_type_init): Add Class= to
472 OPERAND_TYPE_SREG entry.
473 (operand_classes): Add SReg entry.
474 (operand_types): Drop SReg entry.
475 * i386-opc.h (enum operand_class): Add SReg.
476 (SReg): Delete.
477 (union i386_operand_type): Remove sreg field.
478 * i386-opc.tbl (SReg): Define.
479 * i386-reg.tbl: Replace SReg by Class=SReg.
480 * i386-init.h, i386-tbl.h: Re-generate.
481
bab6aec1
JB		 4822019-11-08 Jan Beulich <jbeulich@suse.com>
483
484 * i386-gen.c (operand_type_init): Add Class=. New
485 OPERAND_TYPE_ANYIMM entry.
486 (operand_classes): New.
487 (operand_types): Drop Reg entry.
488 (output_operand_type): New parameter "class". Process it.
489 (process_i386_operand_type): New local variable "class".
490 (main): Adjust static assertions.
491 * i386-opc.h (CLASS_WIDTH): Define.
492 (enum operand_class): New.
493 (Reg): Replace by Class. Adjust comment.
494 (union i386_operand_type): Replace reg by class.
495 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
496 Class=.
497 * i386-reg.tbl: Replace Reg by Class=Reg.
498 * i386-init.h: Re-generate.
499
1f4cd317
MM		 5002019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
501
502 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
503 (aarch64_opcode_table): Add data gathering hint mnemonic.
504 * opcodes/aarch64-dis-2.c: Account for new instruction.
505
616ce08e
MM		 5062019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
507
508 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
509
510
8382113f
MM		 5112019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
512
513 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
514 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
515 aarch64_feature_f64mm): New feature sets.
516 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
517 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
518 instructions.
519 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
520 macros.
521 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
522 (OP_SVE_QQQ): New qualifier.
523 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
524 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
525 the movprfx constraint.
526 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
527 (aarch64_opcode_table): Define new instructions smmla,
528 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
529 uzip{1/2}, trn{1/2}.
530 * aarch64-opc.c (operand_general_constraint_met_p): Handle
531 AARCH64_OPND_SVE_ADDR_RI_S4x32.
532 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
533 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
534 Account for new instructions.
535 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
536 S4x32 operand.
537 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
538
aab2c27d
MM		 5392019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5402019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
541
542 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
543 Armv8.6-A.
544 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
545 (neon_opcodes): Add bfloat SIMD instructions.
546 (print_insn_coprocessor): Add new control character %b to print
547 condition code without checking cp_num.
548 (print_insn_neon): Account for BFloat16 instructions that have no
549 special top-byte handling.
550
33593eaf
MM		 5512019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5522019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
553
554 * arm-dis.c (print_insn_coprocessor,
555 print_insn_generic_coprocessor): Create wrapper functions around
556 the implementation of the print_insn_coprocessor control codes.
557 (print_insn_coprocessor_1): Original print_insn_coprocessor
558 function that now takes which array to look at as an argument.
559 (print_insn_arm): Use both print_insn_coprocessor and
560 print_insn_generic_coprocessor.
561 (print_insn_thumb32): As above.
562
df678013
MM		 5632019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5642019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
565
566 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
567 in reglane special case.
568 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
569 aarch64_find_next_opcode): Account for new instructions.
570 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
571 in reglane special case.
572 * aarch64-opc.c (struct operand_qualifier_data): Add data for
573 new AARCH64_OPND_QLF_S_2H qualifier.
574 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
575 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
576 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
577 sets.
578 (BFLOAT_SVE, BFLOAT): New feature set macros.
579 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
580 instructions.
581 (aarch64_opcode_table): Define new instructions bfdot,
582 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
583 bfcvtn2, bfcvt.
584
8ae2d3d9
MM		 5852019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5862019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
587
588 * aarch64-tbl.h (ARMV8_6): New macro.
589
142861df
JB		 5902019-11-07 Jan Beulich <jbeulich@suse.com>
591
592 * i386-dis.c (prefix_table): Add mcommit.
593 (rm_table): Add rdpru.
594 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
595 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
596 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
597 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
598 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
599 * i386-opc.tbl (mcommit, rdpru): New.
600 * i386-init.h, i386-tbl.h: Re-generate.
601
081e283f
JB		 6022019-11-07 Jan Beulich <jbeulich@suse.com>
603
604 * i386-dis.c (OP_Mwait): Drop local variable "names", use
605 "names32" instead.
606 (OP_Monitor): Drop local variable "op1_names", re-purpose
607 "names" for it instead, and replace former "names" uses by
608 "names32" ones.
609
c050c89a
JB		 6102019-11-07 Jan Beulich <jbeulich@suse.com>
611
612 PR/gas 25167
613 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
614 operand-less forms.
615 * opcodes/i386-tbl.h: Re-generate.
616
7abb8d81
JB		 6172019-11-05 Jan Beulich <jbeulich@suse.com>
618
619 * i386-dis.c (OP_Mwaitx): Delete.
620 (prefix_table): Use OP_Mwait for mwaitx entry.
621 (OP_Mwait): Also handle mwaitx.
622
267b8516
JB		 6232019-11-05 Jan Beulich <jbeulich@suse.com>
624
625 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
626 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
627 (prefix_table): Add respective entries.
628 (rm_table): Link to those entries.
629
f8687e93
JB		 6302019-11-05 Jan Beulich <jbeulich@suse.com>
631
632 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
633 (REG_0F1C_P_0_MOD_0): ... this.
634 (REG_0F1E_MOD_3): Rename to ...
635 (REG_0F1E_P_1_MOD_3): ... this.
636 (RM_0F01_REG_5): Rename to ...
637 (RM_0F01_REG_5_MOD_3): ... this.
638 (RM_0F01_REG_7): Rename to ...
639 (RM_0F01_REG_7_MOD_3): ... this.
640 (RM_0F1E_MOD_3_REG_7): Rename to ...
641 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
642 (RM_0FAE_REG_6): Rename to ...
643 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
644 (RM_0FAE_REG_7): Rename to ...
645 (RM_0FAE_REG_7_MOD_3): ... this.
646 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
647 (PREFIX_0F01_REG_5_MOD_0): ... this.
648 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
649 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
650 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
651 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
652 (PREFIX_0FAE_REG_0): Rename to ...
653 (PREFIX_0FAE_REG_0_MOD_3): ... this.
654 (PREFIX_0FAE_REG_1): Rename to ...
655 (PREFIX_0FAE_REG_1_MOD_3): ... this.
656 (PREFIX_0FAE_REG_2): Rename to ...
657 (PREFIX_0FAE_REG_2_MOD_3): ... this.
658 (PREFIX_0FAE_REG_3): Rename to ...
659 (PREFIX_0FAE_REG_3_MOD_3): ... this.
660 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
661 (PREFIX_0FAE_REG_4_MOD_0): ... this.
662 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
663 (PREFIX_0FAE_REG_4_MOD_3): ... this.
664 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
665 (PREFIX_0FAE_REG_5_MOD_0): ... this.
666 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
667 (PREFIX_0FAE_REG_5_MOD_3): ... this.
668 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
669 (PREFIX_0FAE_REG_6_MOD_0): ... this.
670 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
671 (PREFIX_0FAE_REG_6_MOD_3): ... this.
672 (PREFIX_0FAE_REG_7): Rename to ...
673 (PREFIX_0FAE_REG_7_MOD_0): ... this.
674 (PREFIX_MOD_0_0FC3): Rename to ...
675 (PREFIX_0FC3_MOD_0): ... this.
676 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
677 (PREFIX_0FC7_REG_6_MOD_0): ... this.
678 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
679 (PREFIX_0FC7_REG_6_MOD_3): ... this.
680 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
681 (PREFIX_0FC7_REG_7_MOD_3): ... this.
682 (reg_table, prefix_table, mod_table, rm_table): Adjust
683 accordingly.
684
5103274f
NC		 6852019-11-04 Nick Clifton <nickc@redhat.com>
686
687 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
688 of a v850 system register. Move the v850_sreg_names array into
689 this function.
690 (get_v850_reg_name): Likewise for ordinary register names.
691 (get_v850_vreg_name): Likewise for vector register names.
692 (get_v850_cc_name): Likewise for condition codes.
693 * get_v850_float_cc_name): Likewise for floating point condition
694 codes.
695 (get_v850_cacheop_name): Likewise for cache-ops.
696 (get_v850_prefop_name): Likewise for pref-ops.
697 (disassemble): Use the new accessor functions.
698
1820262b
DB		 6992019-10-30 Delia Burduv <delia.burduv@arm.com>
700
701 * aarch64-opc.c (print_immediate_offset_address): Don't print the
702 immediate for the writeback form of ldraa/ldrab if it is 0.
703 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
704 * aarch64-opc-2.c: Regenerated.
705
3cc17af5
JB		 7062019-10-30 Jan Beulich <jbeulich@suse.com>
707
708 * i386-gen.c (operand_type_shorthands): Delete.
709 (operand_type_init): Expand previous shorthands.
710 (set_bitfield_from_shorthand): Rename back to ...
711 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
712 of operand_type_init[].
713 (set_bitfield): Adjust call to the above function.
714 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
715 RegXMM, RegYMM, RegZMM): Define.
716 * i386-reg.tbl: Expand prior shorthands.
717
a2cebd03
JB		 7182019-10-30 Jan Beulich <jbeulich@suse.com>
719
720 * i386-gen.c (output_i386_opcode): Change order of fields
721 emitted to output.
722 * i386-opc.h (struct insn_template): Move operands field.
723 Convert extension_opcode field to unsigned short.
724 * i386-tbl.h: Re-generate.
725
507916b8
JB		 7262019-10-30 Jan Beulich <jbeulich@suse.com>
727
728 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
729 of W.
730 * i386-opc.h (W): Extend comment.
731 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
732 general purpose variants not allowing for byte operands.
733 * i386-tbl.h: Re-generate.
734
efea62b4
NC		 7352019-10-29 Nick Clifton <nickc@redhat.com>
736
737 * tic30-dis.c (print_branch): Correct size of operand array.
738
9adb2591
NC		 7392019-10-29 Nick Clifton <nickc@redhat.com>
740
741 * d30v-dis.c (print_insn): Check that operand index is valid
742 before attempting to access the operands array.
743
993a00a9
NC		 7442019-10-29 Nick Clifton <nickc@redhat.com>
745
746 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
747 locating the bit to be tested.
748
66a66a17
NC		 7492019-10-29 Nick Clifton <nickc@redhat.com>
750
751 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
752 values.
753 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
754 (print_insn_s12z): Check for illegal size values.
755
1ee3542c
NC		 7562019-10-28 Nick Clifton <nickc@redhat.com>
757
758 * csky-dis.c (csky_chars_to_number): Check for a negative
759 count. Use an unsigned integer to construct the return value.
760
bbf9a0b5
NC		 7612019-10-28 Nick Clifton <nickc@redhat.com>
762
763 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
764 operand buffer. Set value to 15 not 13.
765 (get_register_operand): Use OPERAND_BUFFER_LEN.
766 (get_indirect_operand): Likewise.
767 (print_two_operand): Likewise.
768 (print_three_operand): Likewise.
769 (print_oar_insn): Likewise.
770
d1e304bc
NC		 7712019-10-28 Nick Clifton <nickc@redhat.com>
772
773 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
774 (bit_extract_simple): Likewise.
775 (bit_copy): Likewise.
776 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
777 index_offset array are not accessed.
778
dee33451
NC		 7792019-10-28 Nick Clifton <nickc@redhat.com>
780
781 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
782 operand.
783
27cee81d
NC		 7842019-10-25 Nick Clifton <nickc@redhat.com>
785
786 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
787 access to opcodes.op array element.
788
de6d8dc2
NC		 7892019-10-23 Nick Clifton <nickc@redhat.com>
790
791 * rx-dis.c (get_register_name): Fix spelling typo in error
792 message.
793 (get_condition_name, get_flag_name, get_double_register_name)
794 (get_double_register_high_name, get_double_register_low_name)
795 (get_double_control_register_name, get_double_condition_name)
796 (get_opsize_name, get_size_name): Likewise.
797
6207ed28
NC		 7982019-10-22 Nick Clifton <nickc@redhat.com>
799
800 * rx-dis.c (get_size_name): New function. Provides safe
801 access to name array.
802 (get_opsize_name): Likewise.
803 (print_insn_rx): Use the accessor functions.
804
12234dfd
NC		 8052019-10-16 Nick Clifton <nickc@redhat.com>
806
807 * rx-dis.c (get_register_name): New function. Provides safe
808 access to name array.
809 (get_condition_name, get_flag_name, get_double_register_name)
810 (get_double_register_high_name, get_double_register_low_name)
811 (get_double_control_register_name, get_double_condition_name):
812 Likewise.
813 (print_insn_rx): Use the accessor functions.
814
1d378749
NC		 8152019-10-09 Nick Clifton <nickc@redhat.com>
816
817 PR 25041
818 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
819 instructions.
820
d241b910
JB		 8212019-10-07 Jan Beulich <jbeulich@suse.com>
822
823 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
824 (cmpsd): Likewise. Move EsSeg to other operand.
825 * opcodes/i386-tbl.h: Re-generate.
826
f5c5b7c1
AM		 8272019-09-23 Alan Modra <amodra@gmail.com>
828
829 * m68k-dis.c: Include cpu-m68k.h
830
7beeaeb8
AM		 8312019-09-23 Alan Modra <amodra@gmail.com>
832
833 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
834 "elf/mips.h" earlier.
835
3f9aad11
JB		 8362018-09-20 Jan Beulich <jbeulich@suse.com>
837
838 PR gas/25012
839 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
840 with SReg operand.
841 * i386-tbl.h: Re-generate.
842
fd361982
AM		 8432019-09-18 Alan Modra <amodra@gmail.com>
844
845 * arc-ext.c: Update throughout for bfd section macro changes.
846
e0b2a78c
SM		 8472019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
848
849 * Makefile.in: Re-generate.
850 * configure: Re-generate.
851
7e9ad3a3
JW		 8522019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
853
854 * riscv-opc.c (riscv_opcodes): Change subset field
855 to insn_class field for all instructions.
856 (riscv_insn_types): Likewise.
857
bb695960
PB		 8582019-09-16 Phil Blundell <pb@pbcl.net>
859
860 * configure: Regenerated.
861
8063ab7e
MV		 8622019-09-10 Miod Vallat <miod@online.fr>
863
864 PR 24982
865 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
866
60391a25
PB		 8672019-09-09 Phil Blundell <pb@pbcl.net>
868
869 binutils 2.33 branch created.
870
f44b758d
NC		 8712019-09-03 Nick Clifton <nickc@redhat.com>
872
873 PR 24961
874 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
875 greater than zero before indexing via (bufcnt -1).
876
1e4b5e7d
NC		 8772019-09-03 Nick Clifton <nickc@redhat.com>
878
879 PR 24958
880 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
881 (MAX_SPEC_REG_NAME_LEN): Define.
882 (struct mmix_dis_info): Use defined constants for array lengths.
883 (get_reg_name): New function.
884 (get_sprec_reg_name): New function.
885 (print_insn_mmix): Use new functions.
886
c4a23bf8
SP		 8872019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
888
889 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
890 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
891 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
892
a051e2f3
KT		 8932019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
894
895 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
896 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
897 (aarch64_sys_reg_supported_p): Update checks for the above.
898
08132bdd
SP		 8992019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
900
901 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
902 cases MVE_SQRSHRL and MVE_UQRSHLL.
903 (print_insn_mve): Add case for specifier 'k' to check
904 specific bit of the instruction.
905
d88bdcb4
PA		 9062019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
907
908 PR 24854
909 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
910 encountering an unknown machine type.
911 (print_insn_arc): Handle arc_insn_length returning 0. In error
912 cases return -1 rather than calling abort.
913
bc750500
JB		 9142019-08-07 Jan Beulich <jbeulich@suse.com>
915
916 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
917 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
918 IgnoreSize.
919 * i386-tbl.h: Re-generate.
920
23d188c7
BW		 9212019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
922
923 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
924 instructions.
925
c0d6f62f
JW		 9262019-07-30 Mel Chen <mel.chen@sifive.com>
927
928 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
929 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
930
931 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
932 fscsr.
933
0f3f7167
CZ		 9342019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
935
936 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
937 and MPY class instructions.
938 (parse_option): Add nps400 option.
939 (print_arc_disassembler_options): Add nps400 info.
940
7e126ba3
CZ		 9412019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
942
943 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
944 (bspop): Likewise.
945 (modapp): Likewise.
946 * arc-opc.c (RAD_CHK): Add.
947 * arc-tbl.h: Regenerate.
948
a028026d
KT		 9492019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
950
951 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
952 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
953
ac79ff9e
NC		 9542019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
955
956 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
957 instructions as UNPREDICTABLE.
958
231097b0
JM		 9592019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
960
961 * bpf-desc.c: Regenerated.
962
1d942ae9
JB		 9632019-07-17 Jan Beulich <jbeulich@suse.com>
964
965 * i386-gen.c (static_assert): Define.
966 (main): Use it.
967 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
968 (Opcode_Modifier_Num): ... this.
969 (Mem): Delete.
970
dfd69174
JB		 9712019-07-16 Jan Beulich <jbeulich@suse.com>
972
973 * i386-gen.c (operand_types): Move RegMem ...
974 (opcode_modifiers): ... here.
975 * i386-opc.h (RegMem): Move to opcode modifer enum.
976 (union i386_operand_type): Move regmem field ...
977 (struct i386_opcode_modifier): ... here.
978 * i386-opc.tbl (RegMem): Define.
979 (mov, movq): Move RegMem on segment, control, debug, and test
980 register flavors.
981 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
982 to non-SSE2AVX flavor.
983 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
984 Move RegMem on register only flavors. Drop IgnoreSize from
985 legacy encoding flavors.
986 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
987 flavors.
988 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
989 register only flavors.
990 (vmovd): Move RegMem and drop IgnoreSize on register only
991 flavor. Change opcode and operand order to store form.
992 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
993
21df382b
JB		 9942019-07-16 Jan Beulich <jbeulich@suse.com>
995
996 * i386-gen.c (operand_type_init, operand_types): Replace SReg
997 entries.
998 * i386-opc.h (SReg2, SReg3): Replace by ...
999 (SReg): ... this.
1000 (union i386_operand_type): Replace sreg fields.
1001 * i386-opc.tbl (mov, ): Use SReg.
1002 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1003 register flavors.
1004 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1005 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1006
3719fd55
JM		 10072019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1008
1009 * bpf-desc.c: Regenerate.
1010 * bpf-opc.c: Likewise.
1011 * bpf-opc.h: Likewise.
1012
92434a14
JM		 10132019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1014
1015 * bpf-desc.c: Regenerate.
1016 * bpf-opc.c: Likewise.
1017
43dd7626
HPN		 10182019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1019
1020 * arm-dis.c (print_insn_coprocessor): Rename index to
1021 index_operand.
1022
98602811
JW		 10232019-07-05 Kito Cheng <kito.cheng@sifive.com>
1024
1025 * riscv-opc.c (riscv_insn_types): Add r4 type.
1026
1027 * riscv-opc.c (riscv_insn_types): Add b and j type.
1028
1029 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1030 format for sb type and correct s type.
1031
01c1ee4a
RS		 10322019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1033
1034 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1035 SVE FMOV alias of FCPY.
1036
83adff69
RS		 10372019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1038
1039 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1040 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1041
89418844
RS		 10422019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1043
1044 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1045 registers in an instruction prefixed by MOVPRFX.
1046
41be57ca
MM		 10472019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1048
1049 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1050 sve_size_13 icode to account for variant behaviour of
1051 pmull{t,b}.
1052 * aarch64-dis-2.c: Regenerate.
1053 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1054 sve_size_13 icode to account for variant behaviour of
1055 pmull{t,b}.
1056 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1057 (OP_SVE_VVV_Q_D): Add new qualifier.
1058 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1059 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1060 AES and those not.
1061
9d3bf266
JB		 10622019-07-01 Jan Beulich <jbeulich@suse.com>
1063
1064 * opcodes/i386-gen.c (operand_type_init): Remove
1065 OPERAND_TYPE_VEC_IMM4 entry.
1066 (operand_types): Remove Vec_Imm4.
1067 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1068 (union i386_operand_type): Remove vec_imm4.
1069 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1070 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1071
c3949f43
JB		 10722019-07-01 Jan Beulich <jbeulich@suse.com>
1073
1074 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1075 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1076 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1077 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1078 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1079 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1080 * i386-tbl.h: Re-generate.
1081
5641ec01
JB		 10822019-07-01 Jan Beulich <jbeulich@suse.com>
1083
1084 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1085 register operands.
1086 * i386-tbl.h: Re-generate.
1087
79dec6b7
JB		 10882019-07-01 Jan Beulich <jbeulich@suse.com>
1089
1090 * i386-opc.tbl (C): New.
1091 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1092 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1093 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1094 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1095 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1096 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1097 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1098 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1099 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1100 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1101 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1102 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1103 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1104 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1105 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1106 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1107 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1108 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1109 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1110 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1111 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1112 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1113 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1114 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1115 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1116 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1117 flavors.
1118 * i386-tbl.h: Re-generate.
1119
a0a1771e
JB		 11202019-07-01 Jan Beulich <jbeulich@suse.com>
1121
1122 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1123 register operands.
1124 * i386-tbl.h: Re-generate.
1125
cd546e7b
JB		 11262019-07-01 Jan Beulich <jbeulich@suse.com>
1127
1128 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1129 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1130 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1131 * i386-tbl.h: Re-generate.
1132
e3bba3fc
JB		 11332019-07-01 Jan Beulich <jbeulich@suse.com>
1134
1135 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1136 Disp8MemShift from register only templates.
1137 * i386-tbl.h: Re-generate.
1138
36cc073e
JB		 11392019-07-01 Jan Beulich <jbeulich@suse.com>
1140
1141 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1142 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1143 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1144 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1145 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1146 EVEX_W_0F11_P_3_M_1): Delete.
1147 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1148 EVEX_W_0F11_P_3): New.
1149 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1150 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1151 MOD_EVEX_0F11_PREFIX_3 table entries.
1152 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1153 PREFIX_EVEX_0F11 table entries.
1154 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1155 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1156 EVEX_W_0F11_P_3_M_{0,1} table entries.
1157
219920a7
JB		 11582019-07-01 Jan Beulich <jbeulich@suse.com>
1159
1160 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1161 Delete.
1162
e395f487
L		 11632019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1164
1165 PR binutils/24719
1166 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1167 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1168 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1169 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1170 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1171 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1172 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1173 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1174 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1175 PREFIX_EVEX_0F38C6_REG_6 entries.
1176 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1177 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1178 EVEX_W_0F38C7_R_6_P_2 entries.
1179 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1180 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1181 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1182 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1183 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1184 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1185 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1186
2b7bcc87
JB		 11872019-06-27 Jan Beulich <jbeulich@suse.com>
1188
1189 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1190 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1191 VEX_LEN_0F2D_P_3): Delete.
1192 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1193 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1194 (prefix_table): ... here.
1195
c1dc7af5
JB		 11962019-06-27 Jan Beulich <jbeulich@suse.com>
1197
1198 * i386-dis.c (Iq): Delete.
1199 (Id): New.
1200 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1201 TBM insns.
1202 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1203 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1204 (OP_E_memory): Also honor needindex when deciding whether an
1205 address size prefix needs printing.
1206 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1207
d7560e2d
JW		 12082019-06-26 Jim Wilson <jimw@sifive.com>
1209
1210 PR binutils/24739
1211 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1212 Set info->display_endian to info->endian_code.
1213
2c703856
JB		 12142019-06-25 Jan Beulich <jbeulich@suse.com>
1215
1216 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1217 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1218 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1219 OPERAND_TYPE_ACC64 entries.
1220 * i386-init.h: Re-generate.
1221
54fbadc0
JB		 12222019-06-25 Jan Beulich <jbeulich@suse.com>
1223
1224 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1225 Delete.
1226 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1227 of dqa_mode.
1228 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1229 entries here.
1230 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1231 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1232
a280ab8e
JB		 12332019-06-25 Jan Beulich <jbeulich@suse.com>
1234
1235 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1236 variables.
1237
e1a1babd
JB		 12382019-06-25 Jan Beulich <jbeulich@suse.com>
1239
1240 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1241 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1242 movnti.
d7560e2d 1243 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1244 * i386-tbl.h: Re-generate.
1245
b8364fa7
JB		 12462019-06-25 Jan Beulich <jbeulich@suse.com>
1247
1248 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1249 * i386-tbl.h: Re-generate.
1250
ad692897
L		 12512019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1252
1253 * i386-dis-evex.h: Break into ...
1254 * i386-dis-evex-len.h: New file.
1255 * i386-dis-evex-mod.h: Likewise.
1256 * i386-dis-evex-prefix.h: Likewise.
1257 * i386-dis-evex-reg.h: Likewise.
1258 * i386-dis-evex-w.h: Likewise.
1259 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1260 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1261 i386-dis-evex-mod.h.
1262
f0a6222e
L		 12632019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1264
1265 PR binutils/24700
1266 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1267 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1268 EVEX_W_0F385B_P_2.
1269 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1270 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1271 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1272 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1273 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1274 EVEX_LEN_0F385B_P_2_W_1.
1275 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1276 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1277 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1278 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1279 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1280 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1281 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1282 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1283 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1284 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1285
6e1c90b7
L		 12862019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1287
1288 PR binutils/24691
1289 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1290 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1291 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1292 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1293 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1294 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1295 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1296 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1297 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1298 EVEX_LEN_0F3A43_P_2_W_1.
1299 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1300 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1301 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1302 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1303 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1304 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1305 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1306 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1307 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1308 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1309 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1310 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1311
bcc5a6eb
NC		 13122019-06-14 Nick Clifton <nickc@redhat.com>
1313
1314 * po/fr.po; Updated French translation.
1315
e4c4ac46
SH		 13162019-06-13 Stafford Horne <shorne@gmail.com>
1317
1318 * or1k-asm.c: Regenerated.
1319 * or1k-desc.c: Regenerated.
1320 * or1k-desc.h: Regenerated.
1321 * or1k-dis.c: Regenerated.
1322 * or1k-ibld.c: Regenerated.
1323 * or1k-opc.c: Regenerated.
1324 * or1k-opc.h: Regenerated.
1325 * or1k-opinst.c: Regenerated.
1326
a0e44ef5
PB		 13272019-06-12 Peter Bergner <bergner@linux.ibm.com>
1328
1329 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1330
12efd68d
L		 13312019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1332
1333 PR binutils/24633
1334 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1335 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1336 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1337 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1338 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1339 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1340 EVEX_LEN_0F3A1B_P_2_W_1.
1341 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1342 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1343 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1344 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1345 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1346 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1347 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1348 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1349
63c6fc6c
L		 13502019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1351
1352 PR binutils/24626
1353 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1354 EVEX.vvvv when disassembling VEX and EVEX instructions.
1355 (OP_VEX): Set vex.register_specifier to 0 after readding
1356 vex.register_specifier.
1357 (OP_Vex_2src_1): Likewise.
1358 (OP_Vex_2src_2): Likewise.
1359 (OP_LWP_E): Likewise.
1360 (OP_EX_Vex): Don't check vex.register_specifier.
1361 (OP_XMM_Vex): Likewise.
1362
9186c494
L		 13632019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1364 Lili Cui <lili.cui@intel.com>
1365
1366 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1367 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1368 instructions.
1369 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1370 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1371 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1372 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1373 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1374 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1375 * i386-init.h: Regenerated.
1376 * i386-tbl.h: Likewise.
1377
5d79adc4
L		 13782019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1379 Lili Cui <lili.cui@intel.com>
1380
1381 * doc/c-i386.texi: Document enqcmd.
1382 * testsuite/gas/i386/enqcmd-intel.d: New file.
1383 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1384 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1385 * testsuite/gas/i386/enqcmd.d: Likewise.
1386 * testsuite/gas/i386/enqcmd.s: Likewise.
1387 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1388 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1389 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1390 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1391 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1392 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1393 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1394 and x86-64-enqcmd.
1395
a9d96ab9
AH		 13962019-06-04 Alan Hayward <alan.hayward@arm.com>
1397
1398 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1399
4f6d070a
AM		 14002019-06-03 Alan Modra <amodra@gmail.com>
1401
1402 * ppc-dis.c (prefix_opcd_indices): Correct size.
1403
a2f4b66c
L		 14042019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1405
1406 PR gas/24625
1407 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1408 Disp8ShiftVL.
1409 * i386-tbl.h: Regenerated.
1410
405b5bd8
AM		 14112019-05-24 Alan Modra <amodra@gmail.com>
1412
1413 * po/POTFILES.in: Regenerate.
1414
8acf1435
PB		 14152019-05-24 Peter Bergner <bergner@linux.ibm.com>
1416 Alan Modra <amodra@gmail.com>
1417
1418 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1419 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1420 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1421 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1422 XTOP>): Define and add entries.
1423 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1424 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1425 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1426 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1427
dd7efa79
PB		 14282019-05-24 Peter Bergner <bergner@linux.ibm.com>
1429 Alan Modra <amodra@gmail.com>
1430
1431 * ppc-dis.c (ppc_opts): Add "future" entry.
1432 (PREFIX_OPCD_SEGS): Define.
1433 (prefix_opcd_indices): New array.
1434 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1435 (lookup_prefix): New function.
1436 (print_insn_powerpc): Handle 64-bit prefix instructions.
1437 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1438 (PMRR, POWERXX): Define.
1439 (prefix_opcodes): New instruction table.
1440 (prefix_num_opcodes): New constant.
1441
79472b45
JM		 14422019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1443
1444 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1445 * configure: Regenerated.
1446 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1447 and cpu/bpf.opc.
1448 (HFILES): Add bpf-desc.h and bpf-opc.h.
1449 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1450 bpf-ibld.c and bpf-opc.c.
1451 (BPF_DEPS): Define.
1452 * Makefile.in: Regenerated.
1453 * disassemble.c (ARCH_bpf): Define.
1454 (disassembler): Add case for bfd_arch_bpf.
1455 (disassemble_init_for_target): Likewise.
1456 (enum epbf_isa_attr): Define.
1457 * disassemble.h: extern print_insn_bpf.
1458 * bpf-asm.c: Generated.
1459 * bpf-opc.h: Likewise.
1460 * bpf-opc.c: Likewise.
1461 * bpf-ibld.c: Likewise.
1462 * bpf-dis.c: Likewise.
1463 * bpf-desc.h: Likewise.
1464 * bpf-desc.c: Likewise.
1465
ba6cd17f
SD		 14662019-05-21 Sudakshina Das <sudi.das@arm.com>
1467
1468 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1469 and VMSR with the new operands.
1470
e39c1607
SD		 14712019-05-21 Sudakshina Das <sudi.das@arm.com>
1472
1473 * arm-dis.c (enum mve_instructions): New enum
1474 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1475 and cneg.
1476 (mve_opcodes): New instructions as above.
1477 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1478 csneg and csel.
1479 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1480
23d00a41
SD		 14812019-05-21 Sudakshina Das <sudi.das@arm.com>
1482
1483 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1484 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1485 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1486 uqshl, urshrl and urshr.
1487 (is_mve_okay_in_it): Add new instructions to TRUE list.
1488 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1489 (print_insn_mve): Updated to accept new %j,
1490 %<bitfield>m and %<bitfield>n patterns.
1491
cd4797ee
FS		 14922019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1493
1494 * mips-opc.c (mips_builtin_opcodes): Change source register
1495 constraint for DAUI.
1496
999b073b
NC		 14972019-05-20 Nick Clifton <nickc@redhat.com>
1498
1499 * po/fr.po: Updated French translation.
1500
14b456f2
AV		 15012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1502 Michael Collison <michael.collison@arm.com>
1503
1504 * arm-dis.c (thumb32_opcodes): Add new instructions.
1505 (enum mve_instructions): Likewise.
1506 (enum mve_undefined): Add new reasons.
1507 (is_mve_encoding_conflict): Handle new instructions.
1508 (is_mve_undefined): Likewise.
1509 (is_mve_unpredictable): Likewise.
1510 (print_mve_undefined): Likewise.
1511 (print_mve_size): Likewise.
1512
f49bb598
AV		 15132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1514 Michael Collison <michael.collison@arm.com>
1515
1516 * arm-dis.c (thumb32_opcodes): Add new instructions.
1517 (enum mve_instructions): Likewise.
1518 (is_mve_encoding_conflict): Handle new instructions.
1519 (is_mve_undefined): Likewise.
1520 (is_mve_unpredictable): Likewise.
1521 (print_mve_size): Likewise.
1522
56858bea
AV		 15232019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1524 Michael Collison <michael.collison@arm.com>
1525
1526 * arm-dis.c (thumb32_opcodes): Add new instructions.
1527 (enum mve_instructions): Likewise.
1528 (is_mve_encoding_conflict): Likewise.
1529 (is_mve_unpredictable): Likewise.
1530 (print_mve_size): Likewise.
1531
e523f101
AV		 15322019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1533 Michael Collison <michael.collison@arm.com>
1534
1535 * arm-dis.c (thumb32_opcodes): Add new instructions.
1536 (enum mve_instructions): Likewise.
1537 (is_mve_encoding_conflict): Handle new instructions.
1538 (is_mve_undefined): Likewise.
1539 (is_mve_unpredictable): Likewise.
1540 (print_mve_size): Likewise.
1541
66dcaa5d
AV		 15422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1543 Michael Collison <michael.collison@arm.com>
1544
1545 * arm-dis.c (thumb32_opcodes): Add new instructions.
1546 (enum mve_instructions): Likewise.
1547 (is_mve_encoding_conflict): Handle new instructions.
1548 (is_mve_undefined): Likewise.
1549 (is_mve_unpredictable): Likewise.
1550 (print_mve_size): Likewise.
1551 (print_insn_mve): Likewise.
1552
d052b9b7
AV		 15532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1554 Michael Collison <michael.collison@arm.com>
1555
1556 * arm-dis.c (thumb32_opcodes): Add new instructions.
1557 (print_insn_thumb32): Handle new instructions.
1558
ed63aa17
AV		 15592019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1560 Michael Collison <michael.collison@arm.com>
1561
1562 * arm-dis.c (enum mve_instructions): Add new instructions.
1563 (enum mve_undefined): Add new reasons.
1564 (is_mve_encoding_conflict): Handle new instructions.
1565 (is_mve_undefined): Likewise.
1566 (is_mve_unpredictable): Likewise.
1567 (print_mve_undefined): Likewise.
1568 (print_mve_size): Likewise.
1569 (print_mve_shift_n): Likewise.
1570 (print_insn_mve): Likewise.
1571
897b9bbc
AV		 15722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1573 Michael Collison <michael.collison@arm.com>
1574
1575 * arm-dis.c (enum mve_instructions): Add new instructions.
1576 (is_mve_encoding_conflict): Handle new instructions.
1577 (is_mve_unpredictable): Likewise.
1578 (print_mve_rotate): Likewise.
1579 (print_mve_size): Likewise.
1580 (print_insn_mve): Likewise.
1581
1c8f2df8
AV		 15822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1583 Michael Collison <michael.collison@arm.com>
1584
1585 * arm-dis.c (enum mve_instructions): Add new instructions.
1586 (is_mve_encoding_conflict): Handle new instructions.
1587 (is_mve_unpredictable): Likewise.
1588 (print_mve_size): Likewise.
1589 (print_insn_mve): Likewise.
1590
d3b63143
AV		 15912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1592 Michael Collison <michael.collison@arm.com>
1593
1594 * arm-dis.c (enum mve_instructions): Add new instructions.
1595 (enum mve_undefined): Add new reasons.
1596 (is_mve_encoding_conflict): Handle new instructions.
1597 (is_mve_undefined): Likewise.
1598 (is_mve_unpredictable): Likewise.
1599 (print_mve_undefined): Likewise.
1600 (print_mve_size): Likewise.
1601 (print_insn_mve): Likewise.
1602
14925797
AV		 16032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1604 Michael Collison <michael.collison@arm.com>
1605
1606 * arm-dis.c (enum mve_instructions): Add new instructions.
1607 (is_mve_encoding_conflict): Handle new instructions.
1608 (is_mve_undefined): Likewise.
1609 (is_mve_unpredictable): Likewise.
1610 (print_mve_size): Likewise.
1611 (print_insn_mve): Likewise.
1612
c507f10b
AV		 16132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1614 Michael Collison <michael.collison@arm.com>
1615
1616 * arm-dis.c (enum mve_instructions): Add new instructions.
1617 (enum mve_unpredictable): Add new reasons.
1618 (enum mve_undefined): Likewise.
1619 (is_mve_okay_in_it): Handle new isntructions.
1620 (is_mve_encoding_conflict): Likewise.
1621 (is_mve_undefined): Likewise.
1622 (is_mve_unpredictable): Likewise.
1623 (print_mve_vmov_index): Likewise.
1624 (print_simd_imm8): Likewise.
1625 (print_mve_undefined): Likewise.
1626 (print_mve_unpredictable): Likewise.
1627 (print_mve_size): Likewise.
1628 (print_insn_mve): Likewise.
1629
bf0b396d
AV		 16302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1631 Michael Collison <michael.collison@arm.com>
1632
1633 * arm-dis.c (enum mve_instructions): Add new instructions.
1634 (enum mve_unpredictable): Add new reasons.
1635 (enum mve_undefined): Likewise.
1636 (is_mve_encoding_conflict): Handle new instructions.
1637 (is_mve_undefined): Likewise.
1638 (is_mve_unpredictable): Likewise.
1639 (print_mve_undefined): Likewise.
1640 (print_mve_unpredictable): Likewise.
1641 (print_mve_rounding_mode): Likewise.
1642 (print_mve_vcvt_size): Likewise.
1643 (print_mve_size): Likewise.
1644 (print_insn_mve): Likewise.
1645
ef1576a1
AV		 16462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1647 Michael Collison <michael.collison@arm.com>
1648
1649 * arm-dis.c (enum mve_instructions): Add new instructions.
1650 (enum mve_unpredictable): Add new reasons.
1651 (enum mve_undefined): Likewise.
1652 (is_mve_undefined): Handle new instructions.
1653 (is_mve_unpredictable): Likewise.
1654 (print_mve_undefined): Likewise.
1655 (print_mve_unpredictable): Likewise.
1656 (print_mve_size): Likewise.
1657 (print_insn_mve): Likewise.
1658
aef6d006
AV		 16592019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1660 Michael Collison <michael.collison@arm.com>
1661
1662 * arm-dis.c (enum mve_instructions): Add new instructions.
1663 (enum mve_undefined): Add new reasons.
1664 (insns): Add new instructions.
1665 (is_mve_encoding_conflict):
1666 (print_mve_vld_str_addr): New print function.
1667 (is_mve_undefined): Handle new instructions.
1668 (is_mve_unpredictable): Likewise.
1669 (print_mve_undefined): Likewise.
1670 (print_mve_size): Likewise.
1671 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1672 (print_insn_mve): Handle new operands.
1673
04d54ace
AV		 16742019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1675 Michael Collison <michael.collison@arm.com>
1676
1677 * arm-dis.c (enum mve_instructions): Add new instructions.
1678 (enum mve_unpredictable): Add new reasons.
1679 (is_mve_encoding_conflict): Handle new instructions.
1680 (is_mve_unpredictable): Likewise.
1681 (mve_opcodes): Add new instructions.
1682 (print_mve_unpredictable): Handle new reasons.
1683 (print_mve_register_blocks): New print function.
1684 (print_mve_size): Handle new instructions.
1685 (print_insn_mve): Likewise.
1686
9743db03
AV		 16872019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1688 Michael Collison <michael.collison@arm.com>
1689
1690 * arm-dis.c (enum mve_instructions): Add new instructions.
1691 (enum mve_unpredictable): Add new reasons.
1692 (enum mve_undefined): Likewise.
1693 (is_mve_encoding_conflict): Handle new instructions.
1694 (is_mve_undefined): Likewise.
1695 (is_mve_unpredictable): Likewise.
1696 (coprocessor_opcodes): Move NEON VDUP from here...
1697 (neon_opcodes): ... to here.
1698 (mve_opcodes): Add new instructions.
1699 (print_mve_undefined): Handle new reasons.
1700 (print_mve_unpredictable): Likewise.
1701 (print_mve_size): Handle new instructions.
1702 (print_insn_neon): Handle vdup.
1703 (print_insn_mve): Handle new operands.
1704
143275ea
AV		 17052019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1706 Michael Collison <michael.collison@arm.com>
1707
1708 * arm-dis.c (enum mve_instructions): Add new instructions.
1709 (enum mve_unpredictable): Add new values.
1710 (mve_opcodes): Add new instructions.
1711 (vec_condnames): New array with vector conditions.
1712 (mve_predicatenames): New array with predicate suffixes.
1713 (mve_vec_sizename): New array with vector sizes.
1714 (enum vpt_pred_state): New enum with vector predication states.
1715 (struct vpt_block): New struct type for vpt blocks.
1716 (vpt_block_state): Global struct to keep track of state.
1717 (mve_extract_pred_mask): New helper function.
1718 (num_instructions_vpt_block): Likewise.
1719 (mark_outside_vpt_block): Likewise.
1720 (mark_inside_vpt_block): Likewise.
1721 (invert_next_predicate_state): Likewise.
1722 (update_next_predicate_state): Likewise.
1723 (update_vpt_block_state): Likewise.
1724 (is_vpt_instruction): Likewise.
1725 (is_mve_encoding_conflict): Add entries for new instructions.
1726 (is_mve_unpredictable): Likewise.
1727 (print_mve_unpredictable): Handle new cases.
1728 (print_instruction_predicate): Likewise.
1729 (print_mve_size): New function.
1730 (print_vec_condition): New function.
1731 (print_insn_mve): Handle vpt blocks and new print operands.
1732
f08d8ce3
AV		 17332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1734
1735 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1736 8, 14 and 15 for Armv8.1-M Mainline.
1737
73cd51e5
AV		 17382019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1739 Michael Collison <michael.collison@arm.com>
1740
1741 * arm-dis.c (enum mve_instructions): New enum.
1742 (enum mve_unpredictable): Likewise.
1743 (enum mve_undefined): Likewise.
1744 (struct mopcode32): New struct.
1745 (is_mve_okay_in_it): New function.
1746 (is_mve_architecture): Likewise.
1747 (arm_decode_field): Likewise.
1748 (arm_decode_field_multiple): Likewise.
1749 (is_mve_encoding_conflict): Likewise.
1750 (is_mve_undefined): Likewise.
1751 (is_mve_unpredictable): Likewise.
1752 (print_mve_undefined): Likewise.
1753 (print_mve_unpredictable): Likewise.
1754 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1755 (print_insn_mve): New function.
1756 (print_insn_thumb32): Handle MVE architecture.
1757 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1758
3076e594
NC		 17592019-05-10 Nick Clifton <nickc@redhat.com>
1760
1761 PR 24538
1762 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1763 end of the table prematurely.
1764
387e7624
FS		 17652019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1766
1767 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1768 macros for R6.
1769
0067be51
AM		 17702019-05-11 Alan Modra <amodra@gmail.com>
1771
1772 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1773 when -Mraw is in effect.
1774
42e6288f
MM		 17752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1776
1777 * aarch64-dis-2.c: Regenerate.
1778 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1779 (OP_SVE_BBB): New variant set.
1780 (OP_SVE_DDDD): New variant set.
1781 (OP_SVE_HHH): New variant set.
1782 (OP_SVE_HHHU): New variant set.
1783 (OP_SVE_SSS): New variant set.
1784 (OP_SVE_SSSU): New variant set.
1785 (OP_SVE_SHH): New variant set.
1786 (OP_SVE_SBBU): New variant set.
1787 (OP_SVE_DSS): New variant set.
1788 (OP_SVE_DHHU): New variant set.
1789 (OP_SVE_VMV_HSD_BHS): New variant set.
1790 (OP_SVE_VVU_HSD_BHS): New variant set.
1791 (OP_SVE_VVVU_SD_BH): New variant set.
1792 (OP_SVE_VVVU_BHSD): New variant set.
1793 (OP_SVE_VVV_QHD_DBS): New variant set.
1794 (OP_SVE_VVV_HSD_BHS): New variant set.
1795 (OP_SVE_VVV_HSD_BHS2): New variant set.
1796 (OP_SVE_VVV_BHS_HSD): New variant set.
1797 (OP_SVE_VV_BHS_HSD): New variant set.
1798 (OP_SVE_VVV_SD): New variant set.
1799 (OP_SVE_VVU_BHS_HSD): New variant set.
1800 (OP_SVE_VZVV_SD): New variant set.
1801 (OP_SVE_VZVV_BH): New variant set.
1802 (OP_SVE_VZV_SD): New variant set.
1803 (aarch64_opcode_table): Add sve2 instructions.
1804
28ed815a
MM		 18052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1806
1807 * aarch64-asm-2.c: Regenerated.
1808 * aarch64-dis-2.c: Regenerated.
1809 * aarch64-opc-2.c: Regenerated.
1810 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1811 for SVE_SHLIMM_UNPRED_22.
1812 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1813 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1814 operand.
1815
fd1dc4a0
MM		 18162019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1817
1818 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1819 sve_size_tsz_bhs iclass encode.
1820 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1821 sve_size_tsz_bhs iclass decode.
1822
31e36ab3
MM		 18232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1824
1825 * aarch64-asm-2.c: Regenerated.
1826 * aarch64-dis-2.c: Regenerated.
1827 * aarch64-opc-2.c: Regenerated.
1828 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1829 for SVE_Zm4_11_INDEX.
1830 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1831 (fields): Handle SVE_i2h field.
1832 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1833 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1834
1be5f94f
MM		 18352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1836
1837 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1838 sve_shift_tsz_bhsd iclass encode.
1839 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1840 sve_shift_tsz_bhsd iclass decode.
1841
3c17238b
MM		 18422019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1843
1844 * aarch64-asm-2.c: Regenerated.
1845 * aarch64-dis-2.c: Regenerated.
1846 * aarch64-opc-2.c: Regenerated.
1847 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1848 (aarch64_encode_variant_using_iclass): Handle
1849 sve_shift_tsz_hsd iclass encode.
1850 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1851 sve_shift_tsz_hsd iclass decode.
1852 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1853 for SVE_SHRIMM_UNPRED_22.
1854 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1855 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1856 operand.
1857
cd50a87a
MM		 18582019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1859
1860 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1861 sve_size_013 iclass encode.
1862 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1863 sve_size_013 iclass decode.
1864
3c705960
MM		 18652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1866
1867 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1868 sve_size_bh iclass encode.
1869 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1870 sve_size_bh iclass decode.
1871
0a57e14f
MM		 18722019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1873
1874 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1875 sve_size_sd2 iclass encode.
1876 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1877 sve_size_sd2 iclass decode.
1878 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1879 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1880
c469c864
MM		 18812019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1882
1883 * aarch64-asm-2.c: Regenerated.
1884 * aarch64-dis-2.c: Regenerated.
1885 * aarch64-opc-2.c: Regenerated.
1886 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1887 for SVE_ADDR_ZX.
1888 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1889 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1890
116adc27
MM		 18912019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1892
1893 * aarch64-asm-2.c: Regenerated.
1894 * aarch64-dis-2.c: Regenerated.
1895 * aarch64-opc-2.c: Regenerated.
1896 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1897 for SVE_Zm3_11_INDEX.
1898 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1899 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1900 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1901 fields.
1902 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1903
3bd82c86
MM		 19042019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1905
1906 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1907 sve_size_hsd2 iclass encode.
1908 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1909 sve_size_hsd2 iclass decode.
1910 * aarch64-opc.c (fields): Handle SVE_size field.
1911 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1912
adccc507
MM		 19132019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1914
1915 * aarch64-asm-2.c: Regenerated.
1916 * aarch64-dis-2.c: Regenerated.
1917 * aarch64-opc-2.c: Regenerated.
1918 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1919 for SVE_IMM_ROT3.
1920 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1921 (fields): Handle SVE_rot3 field.
1922 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1923 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1924
5cd99750
MM		 19252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1926
1927 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1928 instructions.
1929
7ce2460a
MM		 19302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1931
1932 * aarch64-tbl.h
1933 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1934 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1935 aarch64_feature_sve2bitperm): New feature sets.
1936 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1937 for feature set addresses.
1938 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1939 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1940
41cee089
FS		 19412019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1942 Faraz Shahbazker <fshahbazker@wavecomp.com>
1943
1944 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1945 argument and set ASE_EVA_R6 appropriately.
1946 (set_default_mips_dis_options): Pass ISA to above.
1947 (parse_mips_dis_option): Likewise.
1948 * mips-opc.c (EVAR6): New macro.
1949 (mips_builtin_opcodes): Add llwpe, scwpe.
1950
b83b4b13
SD		 19512019-05-01 Sudakshina Das <sudi.das@arm.com>
1952
1953 * aarch64-asm-2.c: Regenerated.
1954 * aarch64-dis-2.c: Regenerated.
1955 * aarch64-opc-2.c: Regenerated.
1956 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1957 AARCH64_OPND_TME_UIMM16.
1958 (aarch64_print_operand): Likewise.
1959 * aarch64-tbl.h (QL_IMM_NIL): New.
1960 (TME): New.
1961 (_TME_INSN): New.
1962 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1963
4a90ce95
JD		 19642019-04-29 John Darrington <john@darrington.wattle.id.au>
1965
1966 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1967
a45328b9
AB		 19682019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1969 Faraz Shahbazker <fshahbazker@wavecomp.com>
1970
1971 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1972
d10be0cb
JD		 19732019-04-24 John Darrington <john@darrington.wattle.id.au>
1974
1975 * s12z-opc.h: Add extern "C" bracketing to help
1976 users who wish to use this interface in c++ code.
1977
a679f24e
JD		 19782019-04-24 John Darrington <john@darrington.wattle.id.au>
1979
1980 * s12z-opc.c (bm_decode): Handle bit map operations with the
1981 "reserved0" mode.
1982
32c36c3c
AV		 19832019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1984
1985 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1986 specifier. Add entries for VLDR and VSTR of system registers.
1987 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1988 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1989 of %J and %K format specifier.
1990
efd6b359
AV		 19912019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1992
1993 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1994 Add new entries for VSCCLRM instruction.
1995 (print_insn_coprocessor): Handle new %C format control code.
1996
6b0dd094
AV		 19972019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1998
1999 * arm-dis.c (enum isa): New enum.
2000 (struct sopcode32): New structure.
2001 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2002 set isa field of all current entries to ANY.
2003 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2004 Only match an entry if its isa field allows the current mode.
2005
4b5a202f
AV		 20062019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2007
2008 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2009 CLRM.
2010 (print_insn_thumb32): Add logic to print %n CLRM register list.
2011
60f993ce
AV		 20122019-04-15 Sudakshina Das <sudi.das@arm.com>
2013
2014 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2015 and %Q patterns.
2016
f6b2b12d
AV		 20172019-04-15 Sudakshina Das <sudi.das@arm.com>
2018
2019 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2020 (print_insn_thumb32): Edit the switch case for %Z.
2021
1889da70
AV		 20222019-04-15 Sudakshina Das <sudi.das@arm.com>
2023
2024 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2025
65d1bc05
AV		 20262019-04-15 Sudakshina Das <sudi.das@arm.com>
2027
2028 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2029
1caf72a5
AV		 20302019-04-15 Sudakshina Das <sudi.das@arm.com>
2031
2032 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2033
f1c7f421
AV		 20342019-04-15 Sudakshina Das <sudi.das@arm.com>
2035
2036 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2037 Arm register with r13 and r15 unpredictable.
2038 (thumb32_opcodes): New instructions for bfx and bflx.
2039
4389b29a
AV		 20402019-04-15 Sudakshina Das <sudi.das@arm.com>
2041
2042 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2043
e5d6e09e
AV		 20442019-04-15 Sudakshina Das <sudi.das@arm.com>
2045
2046 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2047
e12437dc
AV		 20482019-04-15 Sudakshina Das <sudi.das@arm.com>
2049
2050 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2051
031254f2
AV		 20522019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2053
2054 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2055
e5a557ac
JD		 20562019-04-12 John Darrington <john@darrington.wattle.id.au>
2057
2058 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2059 "optr". ("operator" is a reserved word in c++).
2060
bd7ceb8d
SD		 20612019-04-11 Sudakshina Das <sudi.das@arm.com>
2062
2063 * aarch64-opc.c (aarch64_print_operand): Add case for
2064 AARCH64_OPND_Rt_SP.
2065 (verify_constraints): Likewise.
2066 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2067 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2068 to accept Rt|SP as first operand.
2069 (AARCH64_OPERANDS): Add new Rt_SP.
2070 * aarch64-asm-2.c: Regenerated.
2071 * aarch64-dis-2.c: Regenerated.
2072 * aarch64-opc-2.c: Regenerated.
2073
e54010f1
SD		 20742019-04-11 Sudakshina Das <sudi.das@arm.com>
2075
2076 * aarch64-asm-2.c: Regenerated.
2077 * aarch64-dis-2.c: Likewise.
2078 * aarch64-opc-2.c: Likewise.
2079 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2080
7e96e219
RS		 20812019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2082
2083 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2084
6f2791d5
L		 20852019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2086
2087 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2088 * i386-init.h: Regenerated.
2089
e392bad3
AM		 20902019-04-07 Alan Modra <amodra@gmail.com>
2091
2092 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2093 op_separator to control printing of spaces, comma and parens
2094 rather than need_comma, need_paren and spaces vars.
2095
dffaa15c
AM		 20962019-04-07 Alan Modra <amodra@gmail.com>
2097
2098 PR 24421
2099 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2100 (print_insn_neon, print_insn_arm): Likewise.
2101
d6aab7a1
XG		 21022019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2103
2104 * i386-dis-evex.h (evex_table): Updated to support BF16
2105 instructions.
2106 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2107 and EVEX_W_0F3872_P_3.
2108 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2109 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2110 * i386-opc.h (enum): Add CpuAVX512_BF16.
2111 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2112 * i386-opc.tbl: Add AVX512 BF16 instructions.
2113 * i386-init.h: Regenerated.
2114 * i386-tbl.h: Likewise.
2115
66e85460
AM		 21162019-04-05 Alan Modra <amodra@gmail.com>
2117
2118 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2119 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2120 to favour printing of "-" branch hint when using the "y" bit.
2121 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2122
c2b1c275
AM		 21232019-04-05 Alan Modra <amodra@gmail.com>
2124
2125 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2126 opcode until first operand is output.
2127
aae9718e
PB		 21282019-04-04 Peter Bergner <bergner@linux.ibm.com>
2129
2130 PR gas/24349
2131 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2132 (valid_bo_post_v2): Add support for 'at' branch hints.
2133 (insert_bo): Only error on branch on ctr.
2134 (get_bo_hint_mask): New function.
2135 (insert_boe): Add new 'branch_taken' formal argument. Add support
2136 for inserting 'at' branch hints.
2137 (extract_boe): Add new 'branch_taken' formal argument. Add support
2138 for extracting 'at' branch hints.
2139 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2140 (BOE): Delete operand.
2141 (BOM, BOP): New operands.
2142 (RM): Update value.
2143 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2144 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2145 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2146 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2147 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2148 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2149 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2150 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2151 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2152 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2153 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2154 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2155 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2156 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2157 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2158 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2159 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2160 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2161 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2162 bttarl+>: New extended mnemonics.
2163
96a86c01
AM		 21642019-03-28 Alan Modra <amodra@gmail.com>
2165
2166 PR 24390
2167 * ppc-opc.c (BTF): Define.
2168 (powerpc_opcodes): Use for mtfsb*.
2169 * ppc-dis.c (print_insn_powerpc): Print fields with both
2170 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2171
796d6298
TC		 21722019-03-25 Tamar Christina <tamar.christina@arm.com>
2173
2174 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2175 (mapping_symbol_for_insn): Implement new algorithm.
2176 (print_insn): Remove duplicate code.
2177
60df3720
TC		 21782019-03-25 Tamar Christina <tamar.christina@arm.com>
2179
2180 * aarch64-dis.c (print_insn_aarch64):
2181 Implement override.
2182
51457761
TC		 21832019-03-25 Tamar Christina <tamar.christina@arm.com>
2184
2185 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2186 order.
2187
53b2f36b
TC		 21882019-03-25 Tamar Christina <tamar.christina@arm.com>
2189
2190 * aarch64-dis.c (last_stop_offset): New.
2191 (print_insn_aarch64): Use stop_offset.
2192
89199bb5
L		 21932019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2194
2195 PR gas/24359
2196 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2197 CPU_ANY_AVX2_FLAGS.
2198 * i386-init.h: Regenerated.
2199
97ed31ae
L		 22002019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2201
2202 PR gas/24348
2203 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2204 vmovdqu16, vmovdqu32 and vmovdqu64.
2205 * i386-tbl.h: Regenerated.
2206
0919bfe9
AK		 22072019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2208
2209 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2210 from vstrszb, vstrszh, and vstrszf.
2211
22122019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2213
2214 * s390-opc.txt: Add instruction descriptions.
2215
21820ebe
JW		 22162019-02-08 Jim Wilson <jimw@sifive.com>
2217
2218 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2219 <bne>: Likewise.
2220
f7dd2fb2
TC		 22212019-02-07 Tamar Christina <tamar.christina@arm.com>
2222
2223 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2224
6456d318
TC		 22252019-02-07 Tamar Christina <tamar.christina@arm.com>
2226
2227 PR binutils/23212
2228 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2229 * aarch64-opc.c (verify_elem_sd): New.
2230 (fields): Add FLD_sz entr.
2231 * aarch64-tbl.h (_SIMD_INSN): New.
2232 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2233 fmulx scalar and vector by element isns.
2234
4a83b610
NC		 22352019-02-07 Nick Clifton <nickc@redhat.com>
2236
2237 * po/sv.po: Updated Swedish translation.
2238
fc60b8c8
AK		 22392019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2240
2241 * s390-mkopc.c (main): Accept arch13 as cpu string.
2242 * s390-opc.c: Add new instruction formats and instruction opcode
2243 masks.
2244 * s390-opc.txt: Add new arch13 instructions.
2245
e10620d3
TC		 22462019-01-25 Sudakshina Das <sudi.das@arm.com>
2247
2248 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2249 (aarch64_opcode): Change encoding for stg, stzg
2250 st2g and st2zg.
2251 * aarch64-asm-2.c: Regenerated.
2252 * aarch64-dis-2.c: Regenerated.
2253 * aarch64-opc-2.c: Regenerated.
2254
20a4ca55
SD		 22552019-01-25 Sudakshina Das <sudi.das@arm.com>
2256
2257 * aarch64-asm-2.c: Regenerated.
2258 * aarch64-dis-2.c: Likewise.
2259 * aarch64-opc-2.c: Likewise.
2260 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2261
550fd7bf
SD		 22622019-01-25 Sudakshina Das <sudi.das@arm.com>
2263 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2264
2265 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2266 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2267 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2268 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2269 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2270 case for ldstgv_indexed.
2271 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2272 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2273 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2274 * aarch64-asm-2.c: Regenerated.
2275 * aarch64-dis-2.c: Regenerated.
2276 * aarch64-opc-2.c: Regenerated.
2277
d9938630
NC		 22782019-01-23 Nick Clifton <nickc@redhat.com>
2279
2280 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2281
375cd423
NC		 22822019-01-21 Nick Clifton <nickc@redhat.com>
2283
2284 * po/de.po: Updated German translation.
2285 * po/uk.po: Updated Ukranian translation.
2286
57299f48
CX		 22872019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2288 * mips-dis.c (mips_arch_choices): Fix typo in
2289 gs464, gs464e and gs264e descriptors.
2290
f48dfe41
NC		 22912019-01-19 Nick Clifton <nickc@redhat.com>
2292
2293 * configure: Regenerate.
2294 * po/opcodes.pot: Regenerate.
2295
f974f26c
NC		 22962018-06-24 Nick Clifton <nickc@redhat.com>
2297
2298 2.32 branch created.
2299
39f286cd
JD		 23002019-01-09 John Darrington <john@darrington.wattle.id.au>
2301
448b8ca8
JD		 2302 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2303 if it is null.
2304 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2305 zero.
2306
3107326d
AP		 23072019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2308
2309 * configure: Regenerate.
2310
7e9ca91e
AM		 23112019-01-07 Alan Modra <amodra@gmail.com>
2312
2313 * configure: Regenerate.
2314 * po/POTFILES.in: Regenerate.
2315
ef1ad42b
JD		 23162019-01-03 John Darrington <john@darrington.wattle.id.au>
2317
2318 * s12z-opc.c: New file.
2319 * s12z-opc.h: New file.
2320 * s12z-dis.c: Removed all code not directly related to display
2321 of instructions. Used the interface provided by the new files
2322 instead.
2323 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2324 * Makefile.in: Regenerate.
ef1ad42b 2325 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2326 * configure: Regenerate.
ef1ad42b 2327
82704155
AM		 23282019-01-01 Alan Modra <amodra@gmail.com>
2329
2330 Update year range in copyright notice of all files.
2331
d5c04e1b 2332For older changes see ChangeLog-2018
3499769a 2333\f
d5c04e1b 2334Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2335
2336Copying and distribution of this file, with or without modification,
2337are permitted in any medium without royalty provided the copyright
2338notice and this notice are preserved.
2339
2340Local Variables:
2341mode: change-log
2342left-margin: 8
2343fill-column: 74
2344version-control: never
2345End:
GDB Binutils - Deliverables
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