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x86: drop bogus IgnoreSize from AVX512_4* insns
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
2589a7e5
JB		 12018-09-13 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
4 AVX512_4VNNIW insns.
5 * i386-tbl.h: Re-generate.
6
a760eb41
JB		 72018-09-13 Jan Beulich <jbeulich@suse.com>
8
9 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
10 meaningless.
11 * i386-tbl.h: Re-generate.
12
e9042658
JB		 132018-09-13 Jan Beulich <jbeulich@suse.com>
14
15 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
16 meaningless.
17 * i386-tbl.h: Re-generate.
18
9caa306f
JB		 192018-09-13 Jan Beulich <jbeulich@suse.com>
20
21 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
22 meaningless.
23 * i386-tbl.h: Re-generate.
24
fb6ce599
JB		 252018-09-13 Jan Beulich <jbeulich@suse.com>
26
27 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
28 meaningless.
29 * i386-tbl.h: Re-generate.
30
6a8da886
JB		 312018-09-13 Jan Beulich <jbeulich@suse.com>
32
33 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
34 meaningless.
35 * i386-tbl.h: Re-generate.
36
c7f27919
JB		 372018-09-13 Jan Beulich <jbeulich@suse.com>
38
39 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
40 * i386-tbl.h: Re-generate.
41
0f407ee9
JB		 422018-09-13 Jan Beulich <jbeulich@suse.com>
43
44 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
45 * i386-tbl.h: Re-generate.
46
2fbbbee5
JB		 472018-09-13 Jan Beulich <jbeulich@suse.com>
48
49 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
50 meaningless.
51 * i386-tbl.h: Re-generate.
52
2b02b9a2
JB		 532018-09-13 Jan Beulich <jbeulich@suse.com>
54
55 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
56 meaningless.
57 * i386-tbl.h: Re-generate.
58
963c68aa
JB		 592018-09-13 Jan Beulich <jbeulich@suse.com>
60
61 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
62 * i386-tbl.h: Re-generate.
63
64e025c3
JB		 642018-09-13 Jan Beulich <jbeulich@suse.com>
65
66 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
67 * i386-tbl.h: Re-generate.
68
47603f88
JB		 692018-09-13 Jan Beulich <jbeulich@suse.com>
70
71 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
72 * i386-tbl.h: Re-generate.
73
0001cfd0
JB		 742018-09-13 Jan Beulich <jbeulich@suse.com>
75
76 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
77 meaningless.
78 * i386-tbl.h: Re-generate.
79
be4b452e
JB		 802018-09-13 Jan Beulich <jbeulich@suse.com>
81
82 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
83 meaningless.
84 * i386-tbl.h: Re-generate.
85
d09a1394
JB		 862018-09-13 Jan Beulich <jbeulich@suse.com>
87
88 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
89 meaningless.
90 * i386-tbl.h: Re-generate.
91
07599e13
JB		 922018-09-13 Jan Beulich <jbeulich@suse.com>
93
94 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
95 * i386-tbl.h: Re-generate.
96
1ee3e487
JB		 972018-09-13 Jan Beulich <jbeulich@suse.com>
98
99 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
100 * i386-tbl.h: Re-generate.
101
a5f580e5
JB		 1022018-09-13 Jan Beulich <jbeulich@suse.com>
103
104 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
105 * i386-tbl.h: Re-generate.
106
49d5d12d
JB		 1072018-09-13 Jan Beulich <jbeulich@suse.com>
108
109 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
110 (vpbroadcastw, rdpid): Drop NoRex64.
111 * i386-tbl.h: Re-generate.
112
f5eb1d70
JB		 1132018-09-13 Jan Beulich <jbeulich@suse.com>
114
115 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
116 store templates, adding D.
117 * i386-tbl.h: Re-generate.
118
dbbc8b7e
JB		 1192018-09-13 Jan Beulich <jbeulich@suse.com>
120
121 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
122 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
123 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
124 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
125 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
126 Fold load and store templates where possible, adding D. Drop
127 IgnoreSize where it was pointlessly present. Drop redundant
128 *word.
129 * i386-tbl.h: Re-generate.
130
d276ec69
JB		 1312018-09-13 Jan Beulich <jbeulich@suse.com>
132
133 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
134 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
135 (intel_operand_size): Handle v_bndmk_mode.
136 (OP_E_memory): Likewise. Produce (bad) when also riprel.
137
9da4dfd6
JD		 1382018-09-08 John Darrington <john@darrington.wattle.id.au>
139
140 * disassemble.c (ARCH_s12z): Define if ARCH_all.
141
be192bc2
JW		 1422018-08-31 Kito Cheng <kito@andestech.com>
143
144 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
145 compressed floating point instructions.
146
43135d3b
JW		 1472018-08-30 Kito Cheng <kito@andestech.com>
148
149 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
150 riscv_opcode.xlen_requirement.
151 * riscv-opc.c (riscv_opcodes): Update for struct change.
152
df28970f
MA		 1532018-08-29 Martin Aberg <maberg@gaisler.com>
154
155 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
156 psr (PWRPSR) instruction.
157
9108bc33
CX		 1582018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
159
160 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
161
bd782c07
CX		 1622018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
163
164 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
165
ac8cb70f
CX		 1662018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
167
168 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
169 loongson3a as an alias of gs464 for compatibility.
170 * mips-opc.c (mips_opcodes): Change Comments.
171
a693765e
CX		 1722018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
173
174 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
175 option.
176 (print_mips_disassembler_options): Document -M loongson-ext.
177 * mips-opc.c (LEXT2): New macro.
178 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
179
bdc6c06e
CX		 1802018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
181
182 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
183 descriptors.
184 (parse_mips_ase_option): Handle -M loongson-ext option.
185 (print_mips_disassembler_options): Document -M loongson-ext.
186 * mips-opc.c (IL3A): Delete.
187 * mips-opc.c (LEXT): New macro.
188 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
189 instructions.
190
716c08de
CX		 1912018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
192
193 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
194 descriptors.
195 (parse_mips_ase_option): Handle -M loongson-cam option.
196 (print_mips_disassembler_options): Document -M loongson-cam.
197 * mips-opc.c (LCAM): New macro.
198 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
199 instructions.
200
9cf7e568
AM		 2012018-08-21 Alan Modra <amodra@gmail.com>
202
203 * ppc-dis.c (operand_value_powerpc): Init "invalid".
204 (skip_optional_operands): Count optional operands, and update
205 ppc_optional_operand_value call.
206 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
207 (extract_vlensi): Likewise.
208 (extract_fxm): Return default value for missing optional operand.
209 (extract_ls, extract_raq, extract_tbr): Likewise.
210 (insert_sxl, extract_sxl): New functions.
211 (insert_esync, extract_esync): Remove Power9 handling and simplify.
212 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
213 flag and extra entry.
214 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
215 extract_sxl.
216
d203b41a 2172018-08-20 Alan Modra <amodra@gmail.com>
f4107842 218
d203b41a 219 * sh-opc.h (MASK): Simplify.
f4107842 220
08a8fe2f 2212018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 222
d203b41a
AM		 223 * s12z-dis.c (bm_decode): Deal with cases where the mode is
224 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 225 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 226
08a8fe2f 2272018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 228
229 * s12z.h: Delete.
7ba3ba91 230
1bc60e56
L		 2312018-08-14 H.J. Lu <hongjiu.lu@intel.com>
232
233 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
234 address with the addr32 prefix and without base nor index
235 registers.
236
d871f3f4
L		 2372018-08-11 H.J. Lu <hongjiu.lu@intel.com>
238
239 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
240 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
241 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
242 (cpu_flags): Add CpuCMOV and CpuFXSR.
243 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
244 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
245 * i386-init.h: Regenerated.
246 * i386-tbl.h: Likewise.
247
b6523c37 2482018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
249
250 * arc-regs.h: Update auxiliary registers.
251
e968fc9b
JB		 2522018-08-06 Jan Beulich <jbeulich@suse.com>
253
254 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
255 (RegIP, RegIZ): Define.
256 * i386-reg.tbl: Adjust comments.
257 (rip): Use Qword instead of BaseIndex. Use RegIP.
258 (eip): Use Dword instead of BaseIndex. Use RegIP.
259 (riz): Add Qword. Use RegIZ.
260 (eiz): Add Dword. Use RegIZ.
261 * i386-tbl.h: Re-generate.
262
dbf8be89
JB		 2632018-08-03 Jan Beulich <jbeulich@suse.com>
264
265 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
266 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
267 vpmovzxdq, vpmovzxwd): Remove NoRex64.
268 * i386-tbl.h: Re-generate.
269
c48dadc9
JB		 2702018-08-03 Jan Beulich <jbeulich@suse.com>
271
272 * i386-gen.c (operand_types): Remove Mem field.
273 * i386-opc.h (union i386_operand_type): Remove mem field.
274 * i386-init.h, i386-tbl.h: Re-generate.
275
cb86a42a
AM		 2762018-08-01 Alan Modra <amodra@gmail.com>
277
278 * po/POTFILES.in: Regenerate.
279
07cc0450
NC		 2802018-07-31 Nick Clifton <nickc@redhat.com>
281
282 * po/sv.po: Updated Swedish translation.
283
1424ad86
JB		 2842018-07-31 Jan Beulich <jbeulich@suse.com>
285
286 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
287 * i386-init.h, i386-tbl.h: Re-generate.
288
ae2387fe
JB		 2892018-07-31 Jan Beulich <jbeulich@suse.com>
290
291 * i386-opc.h (ZEROING_MASKING) Rename to ...
292 (DYNAMIC_MASKING): ... this. Adjust comment.
293 * i386-opc.tbl (MaskingMorZ): Define.
294 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
295 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
296 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
297 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
298 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
299 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
300 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
301 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
302 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
303
6ff00b5e
JB		 3042018-07-31 Jan Beulich <jbeulich@suse.com>
305
306 * i386-opc.tbl: Use element rather than vector size for AVX512*
307 scatter/gather insns.
308 * i386-tbl.h: Re-generate.
309
e951d5ca
JB		 3102018-07-31 Jan Beulich <jbeulich@suse.com>
311
312 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
313 (cpu_flags): Drop CpuVREX.
314 * i386-opc.h (CpuVREX): Delete.
315 (union i386_cpu_flags): Remove cpuvrex.
316 * i386-init.h, i386-tbl.h: Re-generate.
317
eb41b248
JW		 3182018-07-30 Jim Wilson <jimw@sifive.com>
319
320 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
321 fields.
322 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
323
b8891f8d
AJ		 3242018-07-30 Andrew Jenner <andrew@codesourcery.com>
325
326 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
327 * Makefile.in: Regenerated.
328 * configure.ac: Add C-SKY.
329 * configure: Regenerated.
330 * csky-dis.c: New file.
331 * csky-opc.h: New file.
332 * disassemble.c (ARCH_csky): Define.
333 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
334 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
335
16065af1
AM		 3362018-07-27 Alan Modra <amodra@gmail.com>
337
338 * ppc-opc.c (insert_sprbat): Correct function parameter and
339 return type.
340 (extract_sprbat): Likewise, variable too.
341
fa758a70
AC		 3422018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
343 Alan Modra <amodra@gmail.com>
344
345 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
346 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
347 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
348 support disjointed BAT.
349 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
350 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
351 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
352
4a1b91ea
L		 3532018-07-25 H.J. Lu <hongjiu.lu@intel.com>
354 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
355
356 * i386-gen.c (adjust_broadcast_modifier): New function.
357 (process_i386_opcode_modifier): Add an argument for operands.
358 Adjust the Broadcast value based on operands.
359 (output_i386_opcode): Pass operand_types to
360 process_i386_opcode_modifier.
361 (process_i386_opcodes): Pass NULL as operands to
362 process_i386_opcode_modifier.
363 * i386-opc.h (BYTE_BROADCAST): New.
364 (WORD_BROADCAST): Likewise.
365 (DWORD_BROADCAST): Likewise.
366 (QWORD_BROADCAST): Likewise.
367 (i386_opcode_modifier): Expand broadcast to 3 bits.
368 * i386-tbl.h: Regenerated.
369
67ce483b
AM		 3702018-07-24 Alan Modra <amodra@gmail.com>
371
372 PR 23430
373 * or1k-desc.h: Regenerate.
374
4174bfff
JB		 3752018-07-24 Jan Beulich <jbeulich@suse.com>
376
377 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
378 vcvtusi2ss, and vcvtusi2sd.
379 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
380 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
381 * i386-tbl.h: Re-generate.
382
04e65276
CZ		 3832018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
384
385 * arc-opc.c (extract_w6): Fix extending the sign.
386
47e6f81c
CZ		 3872018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
388
389 * arc-tbl.h (vewt): Allow it for ARC EM family.
390
bb71536f
AM		 3912018-07-23 Alan Modra <amodra@gmail.com>
392
393 PR 23419
394 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
395 opcode variants for mtspr/mfspr encodings.
396
8095d2f7
CX		 3972018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
398 Maciej W. Rozycki <macro@mips.com>
399
400 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
401 loongson3a descriptors.
402 (parse_mips_ase_option): Handle -M loongson-mmi option.
403 (print_mips_disassembler_options): Document -M loongson-mmi.
404 * mips-opc.c (LMMI): New macro.
405 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
406 instructions.
407
5f32791e
JB		 4082018-07-19 Jan Beulich <jbeulich@suse.com>
409
410 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
411 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
412 IgnoreSize and [XYZ]MMword where applicable.
413 * i386-tbl.h: Re-generate.
414
625cbd7a
JB		 4152018-07-19 Jan Beulich <jbeulich@suse.com>
416
417 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
418 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
419 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
420 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
421 * i386-tbl.h: Re-generate.
422
86b15c32
JB		 4232018-07-19 Jan Beulich <jbeulich@suse.com>
424
425 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
426 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
427 VPCLMULQDQ templates into their respective AVX512VL counterparts
428 where possible, using Disp8ShiftVL and CheckRegSize instead of
429 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
430 * i386-tbl.h: Re-generate.
431
cf769ed5
JB		 4322018-07-19 Jan Beulich <jbeulich@suse.com>
433
434 * i386-opc.tbl: Fold AVX512DQ templates into their respective
435 AVX512VL counterparts where possible, using Disp8ShiftVL and
436 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
437 IgnoreSize) as appropriate.
438 * i386-tbl.h: Re-generate.
439
8282b7ad
JB		 4402018-07-19 Jan Beulich <jbeulich@suse.com>
441
442 * i386-opc.tbl: Fold AVX512BW templates into their respective
443 AVX512VL counterparts where possible, using Disp8ShiftVL and
444 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
445 IgnoreSize) as appropriate.
446 * i386-tbl.h: Re-generate.
447
755908cc
JB		 4482018-07-19 Jan Beulich <jbeulich@suse.com>
449
450 * i386-opc.tbl: Fold AVX512CD templates into their respective
451 AVX512VL counterparts where possible, using Disp8ShiftVL and
452 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
453 IgnoreSize) as appropriate.
454 * i386-tbl.h: Re-generate.
455
7091c612
JB		 4562018-07-19 Jan Beulich <jbeulich@suse.com>
457
458 * i386-opc.h (DISP8_SHIFT_VL): New.
459 * i386-opc.tbl (Disp8ShiftVL): Define.
460 (various): Fold AVX512VL templates into their respective
461 AVX512F counterparts where possible, using Disp8ShiftVL and
462 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
463 IgnoreSize) as appropriate.
464 * i386-tbl.h: Re-generate.
465
c30be56e
JB		 4662018-07-19 Jan Beulich <jbeulich@suse.com>
467
468 * Makefile.am: Change dependencies and rule for
469 $(srcdir)/i386-init.h.
470 * Makefile.in: Re-generate.
471 * i386-gen.c (process_i386_opcodes): New local variable
472 "marker". Drop opening of input file. Recognize marker and line
473 number directives.
474 * i386-opc.tbl (OPCODE_I386_H): Define.
475 (i386-opc.h): Include it.
476 (None): Undefine.
477
11a322db
L		 4782018-07-18 H.J. Lu <hongjiu.lu@intel.com>
479
480 PR gas/23418
481 * i386-opc.h (Byte): Update comments.
482 (Word): Likewise.
483 (Dword): Likewise.
484 (Fword): Likewise.
485 (Qword): Likewise.
486 (Tbyte): Likewise.
487 (Xmmword): Likewise.
488 (Ymmword): Likewise.
489 (Zmmword): Likewise.
490 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
491 vcvttps2uqq.
492 * i386-tbl.h: Regenerated.
493
cde3679e
NC		 4942018-07-12 Sudakshina Das <sudi.das@arm.com>
495
496 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
497 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
498 * aarch64-asm-2.c: Regenerate.
499 * aarch64-dis-2.c: Regenerate.
500 * aarch64-opc-2.c: Regenerate.
501
45a28947
TC		 5022018-07-12 Tamar Christina <tamar.christina@arm.com>
503
504 PR binutils/23192
505 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
506 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
507 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
508 sqdmulh, sqrdmulh): Use Em16.
509
c597cc3d
SD		 5102018-07-11 Sudakshina Das <sudi.das@arm.com>
511
512 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
513 csdb together with them.
514 (thumb32_opcodes): Likewise.
515
a79eaed6
JB		 5162018-07-11 Jan Beulich <jbeulich@suse.com>
517
518 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
519 requiring 32-bit registers as operands 2 and 3. Improve
520 comments.
521 (mwait, mwaitx): Fold templates. Improve comments.
522 OPERAND_TYPE_INOUTPORTREG.
523 * i386-tbl.h: Re-generate.
524
2fb5be8d
JB		 5252018-07-11 Jan Beulich <jbeulich@suse.com>
526
527 * i386-gen.c (operand_type_init): Remove
528 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
529 OPERAND_TYPE_INOUTPORTREG.
530 * i386-init.h: Re-generate.
531
7f5cad30
JB		 5322018-07-11 Jan Beulich <jbeulich@suse.com>
533
534 * i386-opc.tbl (wrssd, wrussd): Add Dword.
535 (wrssq, wrussq): Add Qword.
536 * i386-tbl.h: Re-generate.
537
f0a85b07
JB		 5382018-07-11 Jan Beulich <jbeulich@suse.com>
539
540 * i386-opc.h: Rename OTMax to OTNum.
541 (OTNumOfUints): Adjust calculation.
542 (OTUnused): Directly alias to OTNum.
543
9dcb0ba4
MR		 5442018-07-09 Maciej W. Rozycki <macro@mips.com>
545
546 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
547 `reg_xys'.
548 (lea_reg_xys): Likewise.
549 (print_insn_loop_primitive): Rename `reg' local variable to
550 `reg_dxy'.
551
f311ba7e
TC		 5522018-07-06 Tamar Christina <tamar.christina@arm.com>
553
554 PR binutils/23242
555 * aarch64-tbl.h (ldarh): Fix disassembly mask.
556
cba05feb
TC		 5572018-07-06 Tamar Christina <tamar.christina@arm.com>
558
559 PR binutils/23369
560 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
561 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
562
471b9d15
MR		 5632018-07-02 Maciej W. Rozycki <macro@mips.com>
564
565 PR tdep/8282
566 * mips-dis.c (mips_option_arg_t): New enumeration.
567 (mips_options): New variable.
568 (disassembler_options_mips): New function.
569 (print_mips_disassembler_options): Reimplement in terms of
570 `disassembler_options_mips'.
571 * arm-dis.c (disassembler_options_arm): Adapt to using the
572 `disasm_options_and_args_t' structure.
573 * ppc-dis.c (disassembler_options_powerpc): Likewise.
574 * s390-dis.c (disassembler_options_s390): Likewise.
575
c0c468d5
TP		 5762018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
577
578 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
579 expected result.
580 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
581 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
582 * testsuite/ld-arm/tls-longplt.d: Likewise.
583
369c9167
TC		 5842018-06-29 Tamar Christina <tamar.christina@arm.com>
585
586 PR binutils/23192
587 * aarch64-asm-2.c: Regenerate.
588 * aarch64-dis-2.c: Likewise.
589 * aarch64-opc-2.c: Likewise.
590 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
591 * aarch64-opc.c (operand_general_constraint_met_p,
592 aarch64_print_operand): Likewise.
593 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
594 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
595 fmlal2, fmlsl2.
596 (AARCH64_OPERANDS): Add Em2.
597
30aa1306
NC		 5982018-06-26 Nick Clifton <nickc@redhat.com>
599
600 * po/uk.po: Updated Ukranian translation.
601 * po/de.po: Updated German translation.
602 * po/pt_BR.po: Updated Brazilian Portuguese translation.
603
eca4b721
NC		 6042018-06-26 Nick Clifton <nickc@redhat.com>
605
606 * nfp-dis.c: Fix spelling mistake.
607
71300e2c
NC		 6082018-06-24 Nick Clifton <nickc@redhat.com>
609
610 * configure: Regenerate.
611 * po/opcodes.pot: Regenerate.
612
719d8288
NC		 6132018-06-24 Nick Clifton <nickc@redhat.com>
614
615 2.31 branch created.
616
514cd3a0
TC		 6172018-06-19 Tamar Christina <tamar.christina@arm.com>
618
619 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
620 * aarch64-asm-2.c: Regenerate.
621 * aarch64-dis-2.c: Likewise.
622
385e4d0f
MR		 6232018-06-21 Maciej W. Rozycki <macro@mips.com>
624
625 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
626 `-M ginv' option description.
627
160d1b3d
SH		 6282018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
629
630 PR gas/23305
631 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
632 la and lla.
633
d0ac1c44
SM		 6342018-06-19 Simon Marchi <simon.marchi@ericsson.com>
635
636 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
637 * configure.ac: Remove AC_PREREQ.
638 * Makefile.in: Re-generate.
639 * aclocal.m4: Re-generate.
640 * configure: Re-generate.
641
6f20c942
FS		 6422018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
643
644 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
645 mips64r6 descriptors.
646 (parse_mips_ase_option): Handle -Mginv option.
647 (print_mips_disassembler_options): Document -Mginv.
648 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
649 (GINV): New macro.
650 (mips_opcodes): Define ginvi and ginvt.
651
730c3174
SE		 6522018-06-13 Scott Egerton <scott.egerton@imgtec.com>
653 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
654
655 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
656 * mips-opc.c (CRC, CRC64): New macros.
657 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
658 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
659 crc32cd for CRC64.
660
cb366992
EB		 6612018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
662
663 PR 20319
664 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
665 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
666
ce72cd46
AM		 6672018-06-06 Alan Modra <amodra@gmail.com>
668
669 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
670 setjmp. Move init for some other vars later too.
671
4b8e28c7
MF		 6722018-06-04 Max Filippov <jcmvbkbc@gmail.com>
673
674 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
675 (dis_private): Add new fields for property section tracking.
676 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
677 (xtensa_instruction_fits): New functions.
678 (fetch_data): Bump minimal fetch size to 4.
679 (print_insn_xtensa): Make struct dis_private static.
680 Load and prepare property table on section change.
681 Don't disassemble literals. Don't disassemble instructions that
682 cross property table boundaries.
683
55e99962
L		 6842018-06-01 H.J. Lu <hongjiu.lu@intel.com>
685
686 * configure: Regenerated.
687
733bd0ab
JB		 6882018-06-01 Jan Beulich <jbeulich@suse.com>
689
690 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
691 * i386-tbl.h: Re-generate.
692
dfd27d41
JB		 6932018-06-01 Jan Beulich <jbeulich@suse.com>
694
695 * i386-opc.tbl (sldt, str): Add NoRex64.
696 * i386-tbl.h: Re-generate.
697
64795710
JB		 6982018-06-01 Jan Beulich <jbeulich@suse.com>
699
700 * i386-opc.tbl (invpcid): Add Oword.
701 * i386-tbl.h: Re-generate.
702
030157d8
AM		 7032018-06-01 Alan Modra <amodra@gmail.com>
704
705 * sysdep.h (_bfd_error_handler): Don't declare.
706 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
707 * rl78-decode.opc: Likewise.
708 * msp430-decode.c: Regenerate.
709 * rl78-decode.c: Regenerate.
710
a9660a6f
AP		 7112018-05-30 Amit Pawar <Amit.Pawar@amd.com>
712
713 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
714 * i386-init.h : Regenerated.
715
277eb7f6
AM		 7162018-05-25 Alan Modra <amodra@gmail.com>
717
718 * Makefile.in: Regenerate.
719 * po/POTFILES.in: Regenerate.
720
98553ad3
PB		 7212018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
722
723 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
724 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
725 (insert_bab, extract_bab, insert_btab, extract_btab,
726 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
727 (BAT, BBA VBA RBS XB6S): Delete macros.
728 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
729 (BB, BD, RBX, XC6): Update for new macros.
730 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
731 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
732 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
733 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
734
7b4ae824
JD		 7352018-05-18 John Darrington <john@darrington.wattle.id.au>
736
737 * Makefile.am: Add support for s12z architecture.
738 * configure.ac: Likewise.
739 * disassemble.c: Likewise.
740 * disassemble.h: Likewise.
741 * Makefile.in: Regenerate.
742 * configure: Regenerate.
743 * s12z-dis.c: New file.
744 * s12z.h: New file.
745
29e0f0a1
AM		 7462018-05-18 Alan Modra <amodra@gmail.com>
747
748 * nfp-dis.c: Don't #include libbfd.h.
749 (init_nfp3200_priv): Use bfd_get_section_contents.
750 (nit_nfp6000_mecsr_sec): Likewise.
751
809276d2
NC		 7522018-05-17 Nick Clifton <nickc@redhat.com>
753
754 * po/zh_CN.po: Updated simplified Chinese translation.
755
ff329288
TC		 7562018-05-16 Tamar Christina <tamar.christina@arm.com>
757
758 PR binutils/23109
759 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
760 * aarch64-dis-2.c: Regenerate.
761
f9830ec1
TC		 7622018-05-15 Tamar Christina <tamar.christina@arm.com>
763
764 PR binutils/21446
765 * aarch64-asm.c (opintl.h): Include.
766 (aarch64_ins_sysreg): Enforce read/write constraints.
767 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
768 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
769 (F_REG_READ, F_REG_WRITE): New.
770 * aarch64-opc.c (aarch64_print_operand): Generate notes for
771 AARCH64_OPND_SYSREG.
772 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
773 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
774 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
775 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
776 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
777 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
778 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
779 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
780 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
781 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
782 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
783 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
784 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
785 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
786 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
787 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
788 msr (F_SYS_WRITE), mrs (F_SYS_READ).
789
7d02540a
TC		 7902018-05-15 Tamar Christina <tamar.christina@arm.com>
791
792 PR binutils/21446
793 * aarch64-dis.c (no_notes: New.
794 (parse_aarch64_dis_option): Support notes.
795 (aarch64_decode_insn, print_operands): Likewise.
796 (print_aarch64_disassembler_options): Document notes.
797 * aarch64-opc.c (aarch64_print_operand): Support notes.
798
561a72d4
TC		 7992018-05-15 Tamar Christina <tamar.christina@arm.com>
800
801 PR binutils/21446
802 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
803 and take error struct.
804 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
805 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
806 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
807 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
808 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
809 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
810 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
811 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
812 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
813 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
814 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
815 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
816 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
817 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
818 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
819 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
820 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
821 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
822 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
823 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
824 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
825 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
826 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
827 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
828 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
829 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
830 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
831 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
832 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
833 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
834 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
835 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
836 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
837 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
838 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
839 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
840 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
841 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
842 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
843 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
844 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
845 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
846 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
847 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
848 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
849 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
850 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
851 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
852 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
853 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
854 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
855 (determine_disassembling_preference, aarch64_decode_insn,
856 print_insn_aarch64_word, print_insn_data): Take errors struct.
857 (print_insn_aarch64): Use errors.
858 * aarch64-asm-2.c: Regenerate.
859 * aarch64-dis-2.c: Regenerate.
860 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
861 boolean in aarch64_insert_operan.
862 (print_operand_extractor): Likewise.
863 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
864
1678bd35
FT		 8652018-05-15 Francois H. Theron <francois.theron@netronome.com>
866
867 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
868
06cfb1c8
L		 8692018-05-09 H.J. Lu <hongjiu.lu@intel.com>
870
871 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
872
84f9f8c3
AM		 8732018-05-09 Sebastian Rasmussen <sebras@gmail.com>
874
875 * cr16-opc.c (cr16_instruction): Comment typo fix.
876 * hppa-dis.c (print_insn_hppa): Likewise.
877
e6f372ba
JW		 8782018-05-08 Jim Wilson <jimw@sifive.com>
879
880 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
881 (match_c_slli64, match_srxi_as_c_srxi): New.
882 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
883 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
884 <c.slli, c.srli, c.srai>: Use match_s_slli.
885 <c.slli64, c.srli64, c.srai64>: New.
886
f413a913
AM		 8872018-05-08 Alan Modra <amodra@gmail.com>
888
889 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
890 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
891 partition opcode space for index lookup.
892
a87a6478
PB		 8932018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
894
895 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
896 <insn_length>: ...with this. Update usage.
897 Remove duplicate call to *info->memory_error_func.
898
c0a30a9f
L		 8992018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
900 H.J. Lu <hongjiu.lu@intel.com>
901
902 * i386-dis.c (Gva): New.
903 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
904 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
905 (prefix_table): New instructions (see prefix above).
906 (mod_table): New instructions (see prefix above).
907 (OP_G): Handle va_mode.
908 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
909 CPU_MOVDIR64B_FLAGS.
910 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
911 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
912 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
913 * i386-opc.tbl: Add movidir{i,64b}.
914 * i386-init.h: Regenerated.
915 * i386-tbl.h: Likewise.
916
75c0a438
L		 9172018-05-07 H.J. Lu <hongjiu.lu@intel.com>
918
919 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
920 AddrPrefixOpReg.
921 * i386-opc.h (AddrPrefixOp0): Renamed to ...
922 (AddrPrefixOpReg): This.
923 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
924 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
925
2ceb7719
PB		 9262018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
927
928 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
929 (vle_num_opcodes): Likewise.
930 (spe2_num_opcodes): Likewise.
931 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
932 initialization loop.
933 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
934 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
935 only once.
936
b3ac5c6c
TC		 9372018-05-01 Tamar Christina <tamar.christina@arm.com>
938
939 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
940
fe944acf
FT		 9412018-04-30 Francois H. Theron <francois.theron@netronome.com>
942
943 Makefile.am: Added nfp-dis.c.
944 configure.ac: Added bfd_nfp_arch.
945 disassemble.h: Added print_insn_nfp prototype.
946 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
947 nfp-dis.c: New, for NFP support.
948 po/POTFILES.in: Added nfp-dis.c to the list.
949 Makefile.in: Regenerate.
950 configure: Regenerate.
951
e2195274
JB		 9522018-04-26 Jan Beulich <jbeulich@suse.com>
953
954 * i386-opc.tbl: Fold various non-memory operand AVX512VL
955 templates into their base ones.
956 * i386-tlb.h: Re-generate.
957
59ef5df4
JB		 9582018-04-26 Jan Beulich <jbeulich@suse.com>
959
960 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
961 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
962 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
963 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
964 * i386-init.h: Re-generate.
965
6e041cf4
JB		 9662018-04-26 Jan Beulich <jbeulich@suse.com>
967
968 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
969 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
970 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
971 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
972 comment.
973 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
974 and CpuRegMask.
975 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
976 CpuRegMask: Delete.
977 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
978 cpuregzmm, and cpuregmask.
979 * i386-init.h: Re-generate.
980 * i386-tbl.h: Re-generate.
981
0e0eea78
JB		 9822018-04-26 Jan Beulich <jbeulich@suse.com>
983
984 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
985 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
986 * i386-init.h: Re-generate.
987
2f1bada2
JB		 9882018-04-26 Jan Beulich <jbeulich@suse.com>
989
990 * i386-gen.c (VexImmExt): Delete.
991 * i386-opc.h (VexImmExt, veximmext): Delete.
992 * i386-opc.tbl: Drop all VexImmExt uses.
993 * i386-tlb.h: Re-generate.
994
bacd1457
JB		 9952018-04-25 Jan Beulich <jbeulich@suse.com>
996
997 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
998 register-only forms.
999 * i386-tlb.h: Re-generate.
1000
10bba94b
TC		 10012018-04-25 Tamar Christina <tamar.christina@arm.com>
1002
1003 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1004
c48935d7
IT		 10052018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1006
1007 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1008 PREFIX_0F1C.
1009 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1010 (cpu_flags): Add CpuCLDEMOTE.
1011 * i386-init.h: Regenerate.
1012 * i386-opc.h (enum): Add CpuCLDEMOTE,
1013 (i386_cpu_flags): Add cpucldemote.
1014 * i386-opc.tbl: Add cldemote.
1015 * i386-tbl.h: Regenerate.
1016
211dc24b
AM		 10172018-04-16 Alan Modra <amodra@gmail.com>
1018
1019 * Makefile.am: Remove sh5 and sh64 support.
1020 * configure.ac: Likewise.
1021 * disassemble.c: Likewise.
1022 * disassemble.h: Likewise.
1023 * sh-dis.c: Likewise.
1024 * sh64-dis.c: Delete.
1025 * sh64-opc.c: Delete.
1026 * sh64-opc.h: Delete.
1027 * Makefile.in: Regenerate.
1028 * configure: Regenerate.
1029 * po/POTFILES.in: Regenerate.
1030
a9a4b302
AM		 10312018-04-16 Alan Modra <amodra@gmail.com>
1032
1033 * Makefile.am: Remove w65 support.
1034 * configure.ac: Likewise.
1035 * disassemble.c: Likewise.
1036 * disassemble.h: Likewise.
1037 * w65-dis.c: Delete.
1038 * w65-opc.h: Delete.
1039 * Makefile.in: Regenerate.
1040 * configure: Regenerate.
1041 * po/POTFILES.in: Regenerate.
1042
04cb01fd
AM		 10432018-04-16 Alan Modra <amodra@gmail.com>
1044
1045 * configure.ac: Remove we32k support.
1046 * configure: Regenerate.
1047
c2bf1eec
AM		 10482018-04-16 Alan Modra <amodra@gmail.com>
1049
1050 * Makefile.am: Remove m88k support.
1051 * configure.ac: Likewise.
1052 * disassemble.c: Likewise.
1053 * disassemble.h: Likewise.
1054 * m88k-dis.c: Delete.
1055 * Makefile.in: Regenerate.
1056 * configure: Regenerate.
1057 * po/POTFILES.in: Regenerate.
1058
6793974d
AM		 10592018-04-16 Alan Modra <amodra@gmail.com>
1060
1061 * Makefile.am: Remove i370 support.
1062 * configure.ac: Likewise.
1063 * disassemble.c: Likewise.
1064 * disassemble.h: Likewise.
1065 * i370-dis.c: Delete.
1066 * i370-opc.c: Delete.
1067 * Makefile.in: Regenerate.
1068 * configure: Regenerate.
1069 * po/POTFILES.in: Regenerate.
1070
e82aa794
AM		 10712018-04-16 Alan Modra <amodra@gmail.com>
1072
1073 * Makefile.am: Remove h8500 support.
1074 * configure.ac: Likewise.
1075 * disassemble.c: Likewise.
1076 * disassemble.h: Likewise.
1077 * h8500-dis.c: Delete.
1078 * h8500-opc.h: Delete.
1079 * Makefile.in: Regenerate.
1080 * configure: Regenerate.
1081 * po/POTFILES.in: Regenerate.
1082
fceadf09
AM		 10832018-04-16 Alan Modra <amodra@gmail.com>
1084
1085 * configure.ac: Remove tahoe support.
1086 * configure: Regenerate.
1087
ae1d3843
L		 10882018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1089
1090 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1091 umwait.
1092 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1093 64-bit mode.
1094 * i386-tbl.h: Regenerated.
1095
de89d0a3
IT		 10962018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1097
1098 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1099 PREFIX_MOD_1_0FAE_REG_6.
1100 (va_mode): New.
1101 (OP_E_register): Use va_mode.
1102 * i386-dis-evex.h (prefix_table):
1103 New instructions (see prefixes above).
1104 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1105 (cpu_flags): Likewise.
1106 * i386-opc.h (enum): Likewise.
1107 (i386_cpu_flags): Likewise.
1108 * i386-opc.tbl: Add umonitor, umwait, tpause.
1109 * i386-init.h: Regenerate.
1110 * i386-tbl.h: Likewise.
1111
a8eb42a8
AM		 11122018-04-11 Alan Modra <amodra@gmail.com>
1113
1114 * opcodes/i860-dis.c: Delete.
1115 * opcodes/i960-dis.c: Delete.
1116 * Makefile.am: Remove i860 and i960 support.
1117 * configure.ac: Likewise.
1118 * disassemble.c: Likewise.
1119 * disassemble.h: Likewise.
1120 * Makefile.in: Regenerate.
1121 * configure: Regenerate.
1122 * po/POTFILES.in: Regenerate.
1123
caf0678c
L		 11242018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1125
1126 PR binutils/23025
1127 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1128 to 0.
1129 (print_insn): Clear vex instead of vex.evex.
1130
4fb0d2b9
NC		 11312018-04-04 Nick Clifton <nickc@redhat.com>
1132
1133 * po/es.po: Updated Spanish translation.
1134
c39e5b26
JB		 11352018-03-28 Jan Beulich <jbeulich@suse.com>
1136
1137 * i386-gen.c (opcode_modifiers): Delete VecESize.
1138 * i386-opc.h (VecESize): Delete.
1139 (struct i386_opcode_modifier): Delete vecesize.
1140 * i386-opc.tbl: Drop VecESize.
1141 * i386-tlb.h: Re-generate.
1142
8e6e0792
JB		 11432018-03-28 Jan Beulich <jbeulich@suse.com>
1144
1145 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1146 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1147 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1148 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1149 * i386-tlb.h: Re-generate.
1150
9f123b91
JB		 11512018-03-28 Jan Beulich <jbeulich@suse.com>
1152
1153 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1154 Fold AVX512 forms
1155 * i386-tlb.h: Re-generate.
1156
9646c87b
JB		 11572018-03-28 Jan Beulich <jbeulich@suse.com>
1158
1159 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1160 (vex_len_table): Drop Y for vcvt*2si.
1161 (putop): Replace plain 'Y' handling by abort().
1162
c8d59609
NC		 11632018-03-28 Nick Clifton <nickc@redhat.com>
1164
1165 PR 22988
1166 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1167 instructions with only a base address register.
1168 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1169 handle AARHC64_OPND_SVE_ADDR_R.
1170 (aarch64_print_operand): Likewise.
1171 * aarch64-asm-2.c: Regenerate.
1172 * aarch64_dis-2.c: Regenerate.
1173 * aarch64-opc-2.c: Regenerate.
1174
b8c169f3
JB		 11752018-03-22 Jan Beulich <jbeulich@suse.com>
1176
1177 * i386-opc.tbl: Drop VecESize from register only insn forms and
1178 memory forms not allowing broadcast.
1179 * i386-tlb.h: Re-generate.
1180
96bc132a
JB		 11812018-03-22 Jan Beulich <jbeulich@suse.com>
1182
1183 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1184 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1185 sha256*): Drop Disp<N>.
1186
9f79e886
JB		 11872018-03-22 Jan Beulich <jbeulich@suse.com>
1188
1189 * i386-dis.c (EbndS, bnd_swap_mode): New.
1190 (prefix_table): Use EbndS.
1191 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1192 * i386-opc.tbl (bndmov): Move misplaced Load.
1193 * i386-tlb.h: Re-generate.
1194
d6793fa1
JB		 11952018-03-22 Jan Beulich <jbeulich@suse.com>
1196
1197 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1198 templates allowing memory operands and folded ones for register
1199 only flavors.
1200 * i386-tlb.h: Re-generate.
1201
f7768225
JB		 12022018-03-22 Jan Beulich <jbeulich@suse.com>
1203
1204 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1205 256-bit templates. Drop redundant leftover Disp<N>.
1206 * i386-tlb.h: Re-generate.
1207
0e35537d
JW		 12082018-03-14 Kito Cheng <kito.cheng@gmail.com>
1209
1210 * riscv-opc.c (riscv_insn_types): New.
1211
b4a3689a
NC		 12122018-03-13 Nick Clifton <nickc@redhat.com>
1213
1214 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1215
d3d50934
L		 12162018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1217
1218 * i386-opc.tbl: Add Optimize to clr.
1219 * i386-tbl.h: Regenerated.
1220
bd5dea88
L		 12212018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1222
1223 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1224 * i386-opc.h (OldGcc): Removed.
1225 (i386_opcode_modifier): Remove oldgcc.
1226 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1227 instructions for old (<= 2.8.1) versions of gcc.
1228 * i386-tbl.h: Regenerated.
1229
e771e7c9
JB		 12302018-03-08 Jan Beulich <jbeulich@suse.com>
1231
1232 * i386-opc.h (EVEXDYN): New.
1233 * i386-opc.tbl: Fold various AVX512VL templates.
1234 * i386-tlb.h: Re-generate.
1235
ed438a93
JB		 12362018-03-08 Jan Beulich <jbeulich@suse.com>
1237
1238 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1239 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1240 vpexpandd, vpexpandq): Fold AFX512VF templates.
1241 * i386-tlb.h: Re-generate.
1242
454172a9
JB		 12432018-03-08 Jan Beulich <jbeulich@suse.com>
1244
1245 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1246 Fold 128- and 256-bit VEX-encoded templates.
1247 * i386-tlb.h: Re-generate.
1248
36824150
JB		 12492018-03-08 Jan Beulich <jbeulich@suse.com>
1250
1251 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1252 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1253 vpexpandd, vpexpandq): Fold AVX512F templates.
1254 * i386-tlb.h: Re-generate.
1255
e7f5c0a9
JB		 12562018-03-08 Jan Beulich <jbeulich@suse.com>
1257
1258 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1259 64-bit templates. Drop Disp<N>.
1260 * i386-tlb.h: Re-generate.
1261
25a4277f
JB		 12622018-03-08 Jan Beulich <jbeulich@suse.com>
1263
1264 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1265 and 256-bit templates.
1266 * i386-tlb.h: Re-generate.
1267
d2224064
JB		 12682018-03-08 Jan Beulich <jbeulich@suse.com>
1269
1270 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1271 * i386-tlb.h: Re-generate.
1272
1b193f0b
JB		 12732018-03-08 Jan Beulich <jbeulich@suse.com>
1274
1275 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1276 Drop NoAVX.
1277 * i386-tlb.h: Re-generate.
1278
f2f6a710
JB		 12792018-03-08 Jan Beulich <jbeulich@suse.com>
1280
1281 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1282 * i386-tlb.h: Re-generate.
1283
38e314eb
JB		 12842018-03-08 Jan Beulich <jbeulich@suse.com>
1285
1286 * i386-gen.c (opcode_modifiers): Delete FloatD.
1287 * i386-opc.h (FloatD): Delete.
1288 (struct i386_opcode_modifier): Delete floatd.
1289 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1290 FloatD by D.
1291 * i386-tlb.h: Re-generate.
1292
d53e6b98
JB		 12932018-03-08 Jan Beulich <jbeulich@suse.com>
1294
1295 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1296
2907c2f5
JB		 12972018-03-08 Jan Beulich <jbeulich@suse.com>
1298
1299 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1300 * i386-tlb.h: Re-generate.
1301
73053c1f
JB		 13022018-03-08 Jan Beulich <jbeulich@suse.com>
1303
1304 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1305 forms.
1306 * i386-tlb.h: Re-generate.
1307
52fe4420
AM		 13082018-03-07 Alan Modra <amodra@gmail.com>
1309
1310 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1311 bfd_arch_rs6000.
1312 * disassemble.h (print_insn_rs6000): Delete.
1313 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1314 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1315 (print_insn_rs6000): Delete.
1316
a6743a54
AM		 13172018-03-03 Alan Modra <amodra@gmail.com>
1318
1319 * sysdep.h (opcodes_error_handler): Define.
1320 (_bfd_error_handler): Declare.
1321 * Makefile.am: Remove stray #.
1322 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1323 EDIT" comment.
1324 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1325 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1326 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1327 opcodes_error_handler to print errors. Standardize error messages.
1328 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1329 and include opintl.h.
1330 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1331 * i386-gen.c: Standardize error messages.
1332 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1333 * Makefile.in: Regenerate.
1334 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1335 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1336 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1337 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1338 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1339 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1340 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1341 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1342 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1343 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1344 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1345 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1346 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1347
8305403a
L		 13482018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1349
1350 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1351 vpsub[bwdq] instructions.
1352 * i386-tbl.h: Regenerated.
1353
e184813f
AM		 13542018-03-01 Alan Modra <amodra@gmail.com>
1355
1356 * configure.ac (ALL_LINGUAS): Sort.
1357 * configure: Regenerate.
1358
5b616bef
TP		 13592018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1360
1361 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1362 macro by assignements.
1363
b6f8c7c4
L		 13642018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1365
1366 PR gas/22871
1367 * i386-gen.c (opcode_modifiers): Add Optimize.
1368 * i386-opc.h (Optimize): New enum.
1369 (i386_opcode_modifier): Add optimize.
1370 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1371 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1372 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1373 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1374 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1375 vpxord and vpxorq.
1376 * i386-tbl.h: Regenerated.
1377
e95b887f
AM		 13782018-02-26 Alan Modra <amodra@gmail.com>
1379
1380 * crx-dis.c (getregliststring): Allocate a large enough buffer
1381 to silence false positive gcc8 warning.
1382
0bccfb29
JW		 13832018-02-22 Shea Levy <shea@shealevy.com>
1384
1385 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1386
6b6b6807
L		 13872018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1388
1389 * i386-opc.tbl: Add {rex},
1390 * i386-tbl.h: Regenerated.
1391
75f31665
MR		 13922018-02-20 Maciej W. Rozycki <macro@mips.com>
1393
1394 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1395 (mips16_opcodes): Replace `M' with `m' for "restore".
1396
e207bc53
TP		 13972018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1398
1399 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1400
87993319
MR		 14012018-02-13 Maciej W. Rozycki <macro@mips.com>
1402
1403 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1404 variable to `function_index'.
1405
68d20676
NC		 14062018-02-13 Nick Clifton <nickc@redhat.com>
1407
1408 PR 22823
1409 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1410 about truncation of printing.
1411
d2159fdc
HW		 14122018-02-12 Henry Wong <henry@stuffedcow.net>
1413
1414 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1415
f174ef9f
NC		 14162018-02-05 Nick Clifton <nickc@redhat.com>
1417
1418 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1419
be3a8dca
IT		 14202018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1421
1422 * i386-dis.c (enum): Add pconfig.
1423 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1424 (cpu_flags): Add CpuPCONFIG.
1425 * i386-opc.h (enum): Add CpuPCONFIG.
1426 (i386_cpu_flags): Add cpupconfig.
1427 * i386-opc.tbl: Add PCONFIG instruction.
1428 * i386-init.h: Regenerate.
1429 * i386-tbl.h: Likewise.
1430
3233d7d0
IT		 14312018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1432
1433 * i386-dis.c (enum): Add PREFIX_0F09.
1434 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1435 (cpu_flags): Add CpuWBNOINVD.
1436 * i386-opc.h (enum): Add CpuWBNOINVD.
1437 (i386_cpu_flags): Add cpuwbnoinvd.
1438 * i386-opc.tbl: Add WBNOINVD instruction.
1439 * i386-init.h: Regenerate.
1440 * i386-tbl.h: Likewise.
1441
e925c834
JW		 14422018-01-17 Jim Wilson <jimw@sifive.com>
1443
1444 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1445
d777820b
IT		 14462018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1447
1448 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1449 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1450 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1451 (cpu_flags): Add CpuIBT, CpuSHSTK.
1452 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1453 (i386_cpu_flags): Add cpuibt, cpushstk.
1454 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1455 * i386-init.h: Regenerate.
1456 * i386-tbl.h: Likewise.
1457
f6efed01
NC		 14582018-01-16 Nick Clifton <nickc@redhat.com>
1459
1460 * po/pt_BR.po: Updated Brazilian Portugese translation.
1461 * po/de.po: Updated German translation.
1462
2721d702
JW		 14632018-01-15 Jim Wilson <jimw@sifive.com>
1464
1465 * riscv-opc.c (match_c_nop): New.
1466 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1467
616dcb87
NC		 14682018-01-15 Nick Clifton <nickc@redhat.com>
1469
1470 * po/uk.po: Updated Ukranian translation.
1471
3957a496
NC		 14722018-01-13 Nick Clifton <nickc@redhat.com>
1473
1474 * po/opcodes.pot: Regenerated.
1475
769c7ea5
NC		 14762018-01-13 Nick Clifton <nickc@redhat.com>
1477
1478 * configure: Regenerate.
1479
faf766e3
NC		 14802018-01-13 Nick Clifton <nickc@redhat.com>
1481
1482 2.30 branch created.
1483
888a89da
IT		 14842018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1485
1486 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1487 * i386-tbl.h: Regenerate.
1488
cbda583a
JB		 14892018-01-10 Jan Beulich <jbeulich@suse.com>
1490
1491 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1492 * i386-tbl.h: Re-generate.
1493
c9e92278
JB		 14942018-01-10 Jan Beulich <jbeulich@suse.com>
1495
1496 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1497 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1498 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1499 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1500 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1501 Disp8MemShift of AVX512VL forms.
1502 * i386-tbl.h: Re-generate.
1503
35fd2b2b
JW		 15042018-01-09 Jim Wilson <jimw@sifive.com>
1505
1506 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1507 then the hi_addr value is zero.
1508
91d8b670
JG		 15092018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1510
1511 * arm-dis.c (arm_opcodes): Add csdb.
1512 (thumb32_opcodes): Add csdb.
1513
be2e7d95
JG		 15142018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1515
1516 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1517 * aarch64-asm-2.c: Regenerate.
1518 * aarch64-dis-2.c: Regenerate.
1519 * aarch64-opc-2.c: Regenerate.
1520
704a705d
L		 15212018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1522
1523 PR gas/22681
1524 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1525 Remove AVX512 vmovd with 64-bit operands.
1526 * i386-tbl.h: Regenerated.
1527
35eeb78f
JW		 15282018-01-05 Jim Wilson <jimw@sifive.com>
1529
1530 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1531 jalr.
1532
219d1afa
AM		 15332018-01-03 Alan Modra <amodra@gmail.com>
1534
1535 Update year range in copyright notice of all files.
1536
1508bbf5
JB		 15372018-01-02 Jan Beulich <jbeulich@suse.com>
1538
1539 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1540 and OPERAND_TYPE_REGZMM entries.
1541
1e563868 1542For older changes see ChangeLog-2017
3499769a 1543\f
1e563868 1544Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1545
1546Copying and distribution of this file, with or without modification,
1547are permitted in any medium without royalty provided the copyright
1548notice and this notice are preserved.
1549
1550Local Variables:
1551mode: change-log
1552left-margin: 8
1553fill-column: 74
1554version-control: never
1555End:
GDB Binutils - Deliverables
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