[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_lor): New.
	(LOR): New.
	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	"stllrb", "stllrh".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (F_ARCHEXT): New.
	(aarch64_sys_regs): Add "pan".
	(aarch64_sys_reg_supported_p): New.
	(aarch64_pstatefields): Add "pan".
	(aarch64_pstatefield_supported_p): New.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-tbl.h: Regenerate.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.

2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	* i386-init.h: Regenerated.

2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (IH) New define.
	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	<tlbie>: Add RS operand for POWER7.
	<slbia>: Add IH operand for POWER6.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
	direct branch.
	(jmp): Likewise.
	* i386-tbl.h: Regenerated.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.

2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.

2015-04-30  DJ Delorie  <dj@redhat.com>

	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

2015-04-29  Nick Clifton  <nickc@redhat.com>

	* po/fr.po: Updated French translation.

2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	(PREFIX_UD_REPZ): Likewise.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_requirement): Removed.
	(print_insn): Don't set prefix_requirement.  Check
	dp->prefix_requirement instead of prefix_requirement.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	(PREFIX_MANDATORY_REPNZ): Likewise.
	(PREFIX_MANDATORY_DATA): Likewise.
	(PREFIX_MANDATORY_ADDR): Likewise.
	(PREFIX_MANDATORY_LOCK): Likewise.
	(PREFIX_MANDATORY): Likewise.
	(PREFIX_UD_SHIFT): Set to 8
	(PREFIX_UD_REPZ): Updated.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.
	(PREFIX_IGNORED_SHIFT): New.
	(PREFIX_IGNORED_REPZ): Likewise.
	(PREFIX_IGNORED_REPNZ): Likewise.
	(PREFIX_IGNORED_DATA): Likewise.
	(PREFIX_IGNORED_ADDR): Likewise.
	(PREFIX_IGNORED_LOCK): Likewise.
	(PREFIX_OPCODE): Likewise.
	(PREFIX_IGNORED): Likewise.
	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	(three_byte_table): Likewise.
	(mod_table): Likewise.
	(mandatory_prefix): Renamed to ...
	(prefix_requirement): This.
	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	Update PREFIX_90 entry.
	(get_valid_dis386): Check prefix_requirement to see if a prefix
	should be ignored.
	(print_insn): Replace mandatory_prefix with prefix_requirement.

2015-04-15  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	use it for ssat and ssat16.
	(print_insn_thumb32): Add handle case for 'D' control code.

2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	Fill prefix_requirement field.
	(struct dis386): Add prefix_requirement field.
	(dis386): Fill prefix_requirement field.
	(dis386_twobyte): Ditto.
	(twobyte_has_mandatory_prefix_: Remove.
	(reg_table): Fill prefix_requirement field.
	(prefix_table): Ditto.
	(x86_64_table): Ditto.
	(three_byte_table): Ditto.
	(xop_table): Ditto.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(bad_opcode): Ditto.
	(print_insn): Use prefix_requirement.
	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	(float_reg): Ditto.

2015-03-30  Mike Frysinger  <vapier@gentoo.org>

	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.

2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.in: Regenerated.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	powerpc_opcd_indices and vle_opcd_indices once.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c (powerpc_opcodes): Add slbfee.

2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.

2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>

	* i386-dis.c (rm_table): Add clzero.
	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	Add CPU_CLZERO_FLAGS.
	(cpu_flags): Add CpuCLZERO.
	* i386-opc.h: Add CpuCLZERO.
	* i386-opc.tbl: Add clzero.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (decode_mips_operand): Fix constraint issues
	with u and y operands.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add new IBM z13 instructions.
	* s390-opc.txt: Likewise.

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	related alias.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2015-03-03  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>

	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

2015-02-23  Vinay  <Vinay.G@kpit.com>

	* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.

2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".

2015-02-10  Pedro Alves  <palves@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	microblaze_and, microblaze_xor.
	* microblaze-opc.h (opcodes): Adjust.

2015-01-28  James Bowman  <james.bowman@ftdichip.com>

	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* nds32-asm.c (keyword_sr): Add new system registers.

2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.

2015-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2014
\f
Copyright (C) 2015 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
290806fd MW	1	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	2
	3	* aarch64-tbl.h (aarch64_feature_lor): New.
	4	(LOR): New.
	5	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	6	"stllrb", "stllrh".
	7	* aarch64-asm-2.c: Regenerate.
	8	* aarch64-dis-2.c: Regenerate.
	9	* aarch64-opc-2.c: Regenerate.
	10
f21cce2c MW	11	2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
	12
	13	* aarch64-opc.c (F_ARCHEXT): New.
	14	(aarch64_sys_regs): Add "pan".
	15	(aarch64_sys_reg_supported_p): New.
	16	(aarch64_pstatefields): Add "pan".
	17	(aarch64_pstatefield_supported_p): New.
	18
d194d186 JB	19	2015-06-01 Jan Beulich <jbeulich@suse.com>
	20
	21	* i386-tbl.h: Regenerate.
	22
3a8547d2 JB	23	2015-06-01 Jan Beulich <jbeulich@suse.com>
	24
	25	* i386-dis.c (print_insn): Swap rounding mode specifier and
	26	general purpose register in Intel mode.
	27
015c54d5 JB	28	2015-06-01 Jan Beulich <jbeulich@suse.com>
	29
	30	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	31	* i386-tbl.h: Regenerate.
	32
071f0063 L	33	2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
	34
	35	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	36	* i386-init.h: Regenerated.
	37
5db04b09 L	38	2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
	39
	40	PR binutis/18386
	41	* i386-dis.c: Add comments for '@'.
	42	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	43	(enum x86_64_isa): New.
	44	(isa64): Likewise.
	45	(print_i386_disassembler_options): Add amd64 and intel64.
	46	(print_insn): Handle amd64 and intel64.
	47	(putop): Handle '@'.
	48	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	49	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	50	* i386-opc.h (AMD64): New.
	51	(CpuIntel64): Likewise.
	52	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	53	* i386-opc.tbl: Add direct call/jmp with Disp16\|Disp32 for AMD64.
	54	Mark direct call/jmp without Disp16\|Disp32 as Intel64.
	55	* i386-init.h: Regenerated.
	56	* i386-tbl.h: Likewise.
	57
4bc0608a PB	58	2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
	59
	60	* ppc-opc.c (IH) New define.
	61	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	62	<tlbie>: Add RS operand for POWER7.
	63	<slbia>: Add IH operand for POWER6.
	64
70cead07 L	65	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	66
	67	* opcodes/i386-opc.tbl (call): Remove Disp16\|Disp32 from 64-bit
	68	direct branch.
	69	(jmp): Likewise.
	70	* i386-tbl.h: Regenerated.
	71
7b6d09fb L	72	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	73
	74	* configure.ac: Support bfd_iamcu_arch.
	75	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	76	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	77	CPU_IAMCU_COMPAT_FLAGS.
	78	(cpu_flags): Add CpuIAMCU.
	79	* i386-opc.h (CpuIAMCU): New.
	80	(i386_cpu_flags): Add cpuiamcu.
	81	* configure: Regenerated.
	82	* i386-init.h: Likewise.
	83	* i386-tbl.h: Likewise.
	84
31955f99 L	85	2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
	86
	87	PR binutis/18386
	88	* i386-dis.c (X86_64_E8): New.
	89	(X86_64_E9): Likewise.
	90	Update comments on 'T', 'U', 'V'. Add comments for '^'.
	91	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	92	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	93	(mod_table): Replace {T\|} with ^ on Jcall/Jmp.
	94	(putop): Handle '^'.
	95	(OP_J): Ignore the operand size prefix in 64-bit. Don't check
	96	REX_W.
	97
0952813b DD	98	2015-04-30 DJ Delorie <dj@redhat.com>
	99
	100	* disassemble.c (disassembler): Choose suitable disassembler based
	101	on E_ABI.
	102	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
	103	it to decode mul/div insns.
	104	* rl78-decode.c: Regenerate.
	105	* rl78-dis.c (print_insn_rl78): Rename to...
	106	(print_insn_rl78_common): ...this, take ISA parameter.
	107	(print_insn_rl78): New.
	108	(print_insn_rl78_g10): New.
	109	(print_insn_rl78_g13): New.
	110	(print_insn_rl78_g14): New.
	111	(rl78_get_disassembler): New.
	112
f9d3ecaa NC	113	2015-04-29 Nick Clifton <nickc@redhat.com>
	114
	115	* po/fr.po: Updated French translation.
	116
4fff86c5 PB	117	2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
	118
	119	* ppc-opc.c (DCBT_EO): New define.
	120	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	121	<lharx>: Likewise.
	122	<stbcx.>: Likewise.
	123	<sthcx.>: Likewise.
	124	<waitrsv>: Do not enable for POWER7 and later.
	125	<waitimpl>: Likewise.
	126	<dcbt>: Default to the two operand form of the instruction for all
	127	"old" cpus. For "new" cpus, use the operand ordering that matches
	128	whether the cpu is server or embedded.
	129	<dcbtst>: Likewise.
	130
3b78cfe1 AK	131	2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	132
	133	* s390-opc.c: New instruction type VV0UU2.
	134	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	135	and WFC.
	136
04d824a4 JB	137	2015-04-23 Jan Beulich <jbeulich@suse.com>
	138
	139	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	140	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	141	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	142	(vfpclasspd, vfpclassps): Add %XZ.
	143
09708981 L	144	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	145
	146	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	147	(PREFIX_UD_REPZ): Likewise.
	148	(PREFIX_UD_REPNZ): Likewise.
	149	(PREFIX_UD_DATA): Likewise.
	150	(PREFIX_UD_ADDR): Likewise.
	151	(PREFIX_UD_LOCK): Likewise.
	152
3888916d L	153	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	154
	155	* i386-dis.c (prefix_requirement): Removed.
	156	(print_insn): Don't set prefix_requirement. Check
	157	dp->prefix_requirement instead of prefix_requirement.
	158
f24bcbaa L	159	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	160
	161	PR binutils/17898
	162	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	163	(PREFIX_MOD_0_0FC7_REG_6): This.
	164	(PREFIX_MOD_3_0FC7_REG_6): New.
	165	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	166	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	167	PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
	168	PREFIX_MOD_3_0FC7_REG_7.
	169	(mod_table): Replace PREFIX_0FC7_REG_6 with
	170	PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
	171	PREFIX_MOD_3_0FC7_REG_7.
	172
507bd325 L	173	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	174
	175	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	176	(PREFIX_MANDATORY_REPNZ): Likewise.
	177	(PREFIX_MANDATORY_DATA): Likewise.
	178	(PREFIX_MANDATORY_ADDR): Likewise.
	179	(PREFIX_MANDATORY_LOCK): Likewise.
	180	(PREFIX_MANDATORY): Likewise.
	181	(PREFIX_UD_SHIFT): Set to 8
	182	(PREFIX_UD_REPZ): Updated.
	183	(PREFIX_UD_REPNZ): Likewise.
	184	(PREFIX_UD_DATA): Likewise.
	185	(PREFIX_UD_ADDR): Likewise.
	186	(PREFIX_UD_LOCK): Likewise.
	187	(PREFIX_IGNORED_SHIFT): New.
	188	(PREFIX_IGNORED_REPZ): Likewise.
	189	(PREFIX_IGNORED_REPNZ): Likewise.
	190	(PREFIX_IGNORED_DATA): Likewise.
	191	(PREFIX_IGNORED_ADDR): Likewise.
	192	(PREFIX_IGNORED_LOCK): Likewise.
	193	(PREFIX_OPCODE): Likewise.
	194	(PREFIX_IGNORED): Likewise.
	195	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	196	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	197	(three_byte_table): Likewise.
	198	(mod_table): Likewise.
	199	(mandatory_prefix): Renamed to ...
	200	(prefix_requirement): This.
	201	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	202	Update PREFIX_90 entry.
	203	(get_valid_dis386): Check prefix_requirement to see if a prefix
	204	should be ignored.
	205	(print_insn): Replace mandatory_prefix with prefix_requirement.
	206
f0fba320 RL	207	2015-04-15 Renlin Li <renlin.li@arm.com>
	208
	209	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	210	use it for ssat and ssat16.
	211	(print_insn_thumb32): Add handle case for 'D' control code.
	212
bf890a93 IT	213	2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
	214	H.J. Lu <hongjiu.lu@intel.com>
	215
	216	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	217	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	218	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	219	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	220	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	221	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	222	Fill prefix_requirement field.
	223	(struct dis386): Add prefix_requirement field.
	224	(dis386): Fill prefix_requirement field.
	225	(dis386_twobyte): Ditto.
	226	(twobyte_has_mandatory_prefix_: Remove.
	227	(reg_table): Fill prefix_requirement field.
	228	(prefix_table): Ditto.
	229	(x86_64_table): Ditto.
	230	(three_byte_table): Ditto.
	231	(xop_table): Ditto.
	232	(vex_table): Ditto.
	233	(vex_len_table): Ditto.
	234	(vex_w_table): Ditto.
	235	(mod_table): Ditto.
	236	(bad_opcode): Ditto.
	237	(print_insn): Use prefix_requirement.
	238	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	239	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	240	(float_reg): Ditto.
	241
2f783c1f MF	242	2015-03-30 Mike Frysinger <vapier@gentoo.org>
	243
	244	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
	245
b9d94d62 L	246	2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
	247
	248	* Makefile.in: Regenerated.
	249
27c49e9a AB	250	2015-03-25 Anton Blanchard <anton@samba.org>
	251
	252	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	253	powerpc_opcd_indices and vle_opcd_indices once.
	254
c4e676f1 AB	255	2015-03-25 Anton Blanchard <anton@samba.org>
	256
	257	* ppc-opc.c (powerpc_opcodes): Add slbfee.
	258
823d2571 TG	259	2015-03-24 Terry Guo <terry.guo@arm.com>
	260
	261	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	262	(opcode16): Likewise.
	263	(coprocessor_opcodes): Replace bit with feature struct.
	264	(neon_opcodes): Likewise.
	265	(arm_opcodes): Likewise.
	266	(thumb_opcodes): Likewise.
	267	(thumb32_opcodes): Likewise.
	268	(print_insn_coprocessor): Likewise.
	269	(print_insn_arm): Likewise.
	270	(select_arm_features): Follow new feature struct.
	271
029f3522 GG	272	2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
	273
	274	* i386-dis.c (rm_table): Add clzero.
	275	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	276	Add CPU_CLZERO_FLAGS.
	277	(cpu_flags): Add CpuCLZERO.
	278	* i386-opc.h: Add CpuCLZERO.
	279	* i386-opc.tbl: Add clzero.
	280	* i386-init.h: Re-generated.
	281	* i386-tbl.h: Re-generated.
	282
6914869a AB	283	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	284
	285	* mips-opc.c (decode_mips_operand): Fix constraint issues
	286	with u and y operands.
	287
21e20815 AB	288	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	289
	290	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
	291
6b1d7593 AK	292	2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	293
	294	* s390-opc.c: Add new IBM z13 instructions.
	295	* s390-opc.txt: Likewise.
	296
c8f89a34 JW	297	2015-03-10 Renlin Li <renlin.li@arm.com>
	298
	299	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	300	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	301	related alias.
	302	* aarch64-asm-2.c: Regenerate.
	303	* aarch64-dis-2.c: Likewise.
	304	* aarch64-opc-2.c: Likewise.
	305
d8282f0e JW	306	2015-03-03 Jiong Wang <jiong.wang@arm.com>
	307
	308	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
	309
ac994365 OE	310	2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
	311
	312	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	313	arch_sh_up.
	314	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	315	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
	316
fd63f640 V	317	2015-02-23 Vinay <Vinay.G@kpit.com>
	318
	319	* rl78-decode.opc (MOV): Added space between two operands for
	320	'mov' instruction in index addressing mode.
	321	* rl78-decode.c: Regenerate.
	322
f63c1776 PA	323	2015-02-19 Pedro Alves <palves@redhat.com>
	324
	325	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
	326
07774fcc PA	327	2015-02-10 Pedro Alves <palves@redhat.com>
	328	Tom Tromey <tromey@redhat.com>
	329
	330	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	331	microblaze_and, microblaze_xor.
	332	* microblaze-opc.h (opcodes): Adjust.
	333
3f8107ab AM	334	2015-01-28 James Bowman <james.bowman@ftdichip.com>
	335
	336	* Makefile.am: Add FT32 files.
	337	* configure.ac: Handle FT32.
	338	* disassemble.c (disassembler): Call print_insn_ft32.
	339	* ft32-dis.c: New file.
	340	* ft32-opc.c: New file.
	341	* Makefile.in: Regenerate.
	342	* configure: Regenerate.
	343	* po/POTFILES.in: Regenerate.
	344
e5fe4957 KLC	345	2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
	346
	347	* nds32-asm.c (keyword_sr): Add new system registers.
	348
1e2e8c52 AK	349	2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	350
	351	* s390-dis.c (s390_extract_operand): Support vector register
	352	operands.
	353	(s390_print_insn_with_opcode): Support new operands types and add
	354	new handling of optional operands.
	355	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	356	and include opcode/s390.h instead.
	357	(struct op_struct): New field `flags'.
	358	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	359	(dumpTable): Dump flags.
	360	(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
	361	string.
	362	* s390-opc.c: Add new operands types, instruction formats, and
	363	instruction masks.
	364	(s390_opformats): Add new formats for .insn.
	365	* s390-opc.txt: Add new instructions.
	366
b90efa5b	367	2015-01-01 Alan Modra <amodra@gmail.com>
bffb6004	368
b90efa5b	369	Update year range in copyright notice of all files.
bffb6004	370
b90efa5b	371	For older changes see ChangeLog-2014
252b5132	372	\f
b90efa5b	373	Copyright (C) 2015 Free Software Foundation, Inc.
752937aa NC	374
	375	Copying and distribution of this file, with or without modification,
	376	are permitted in any medium without royalty provided the copyright
	377	notice and this notice are preserved.
	378
252b5132	379	Local Variables:
2f6d2f85 NC	380	mode: change-log
	381	left-margin: 8
	382	fill-column: 74
252b5132 RH	383	version-control: never
252b5132 RH	384	End: