Add a new Portuguese translation for the bfd sub-directory.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
06cfb1c8
L
12018-05-09 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
4
84f9f8c3
AM
52018-05-09 Sebastian Rasmussen <sebras@gmail.com>
6
7 * cr16-opc.c (cr16_instruction): Comment typo fix.
8 * hppa-dis.c (print_insn_hppa): Likewise.
9
e6f372ba
JW
102018-05-08 Jim Wilson <jimw@sifive.com>
11
12 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
13 (match_c_slli64, match_srxi_as_c_srxi): New.
14 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
15 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
16 <c.slli, c.srli, c.srai>: Use match_s_slli.
17 <c.slli64, c.srli64, c.srai64>: New.
18
f413a913
AM
192018-05-08 Alan Modra <amodra@gmail.com>
20
21 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
22 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
23 partition opcode space for index lookup.
24
a87a6478
PB
252018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
26
27 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
28 <insn_length>: ...with this. Update usage.
29 Remove duplicate call to *info->memory_error_func.
30
c0a30a9f
L
312018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
32 H.J. Lu <hongjiu.lu@intel.com>
33
34 * i386-dis.c (Gva): New.
35 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
36 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
37 (prefix_table): New instructions (see prefix above).
38 (mod_table): New instructions (see prefix above).
39 (OP_G): Handle va_mode.
40 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
41 CPU_MOVDIR64B_FLAGS.
42 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
43 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
44 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
45 * i386-opc.tbl: Add movidir{i,64b}.
46 * i386-init.h: Regenerated.
47 * i386-tbl.h: Likewise.
48
75c0a438
L
492018-05-07 H.J. Lu <hongjiu.lu@intel.com>
50
51 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
52 AddrPrefixOpReg.
53 * i386-opc.h (AddrPrefixOp0): Renamed to ...
54 (AddrPrefixOpReg): This.
55 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
56 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
57
2ceb7719
PB
582018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
59
60 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
61 (vle_num_opcodes): Likewise.
62 (spe2_num_opcodes): Likewise.
63 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
64 initialization loop.
65 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
66 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
67 only once.
68
b3ac5c6c
TC
692018-05-01 Tamar Christina <tamar.christina@arm.com>
70
71 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
72
fe944acf
FT
732018-04-30 Francois H. Theron <francois.theron@netronome.com>
74
75 Makefile.am: Added nfp-dis.c.
76 configure.ac: Added bfd_nfp_arch.
77 disassemble.h: Added print_insn_nfp prototype.
78 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
79 nfp-dis.c: New, for NFP support.
80 po/POTFILES.in: Added nfp-dis.c to the list.
81 Makefile.in: Regenerate.
82 configure: Regenerate.
83
e2195274
JB
842018-04-26 Jan Beulich <jbeulich@suse.com>
85
86 * i386-opc.tbl: Fold various non-memory operand AVX512VL
87 templates into their base ones.
88 * i386-tlb.h: Re-generate.
89
59ef5df4
JB
902018-04-26 Jan Beulich <jbeulich@suse.com>
91
92 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
93 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
94 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
95 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
96 * i386-init.h: Re-generate.
97
6e041cf4
JB
982018-04-26 Jan Beulich <jbeulich@suse.com>
99
100 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
101 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
102 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
103 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
104 comment.
105 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
106 and CpuRegMask.
107 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
108 CpuRegMask: Delete.
109 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
110 cpuregzmm, and cpuregmask.
111 * i386-init.h: Re-generate.
112 * i386-tbl.h: Re-generate.
113
0e0eea78
JB
1142018-04-26 Jan Beulich <jbeulich@suse.com>
115
116 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
117 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
118 * i386-init.h: Re-generate.
119
2f1bada2
JB
1202018-04-26 Jan Beulich <jbeulich@suse.com>
121
122 * i386-gen.c (VexImmExt): Delete.
123 * i386-opc.h (VexImmExt, veximmext): Delete.
124 * i386-opc.tbl: Drop all VexImmExt uses.
125 * i386-tlb.h: Re-generate.
126
bacd1457
JB
1272018-04-25 Jan Beulich <jbeulich@suse.com>
128
129 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
130 register-only forms.
131 * i386-tlb.h: Re-generate.
132
10bba94b
TC
1332018-04-25 Tamar Christina <tamar.christina@arm.com>
134
135 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
136
c48935d7
IT
1372018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
138
139 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
140 PREFIX_0F1C.
141 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
142 (cpu_flags): Add CpuCLDEMOTE.
143 * i386-init.h: Regenerate.
144 * i386-opc.h (enum): Add CpuCLDEMOTE,
145 (i386_cpu_flags): Add cpucldemote.
146 * i386-opc.tbl: Add cldemote.
147 * i386-tbl.h: Regenerate.
148
211dc24b
AM
1492018-04-16 Alan Modra <amodra@gmail.com>
150
151 * Makefile.am: Remove sh5 and sh64 support.
152 * configure.ac: Likewise.
153 * disassemble.c: Likewise.
154 * disassemble.h: Likewise.
155 * sh-dis.c: Likewise.
156 * sh64-dis.c: Delete.
157 * sh64-opc.c: Delete.
158 * sh64-opc.h: Delete.
159 * Makefile.in: Regenerate.
160 * configure: Regenerate.
161 * po/POTFILES.in: Regenerate.
162
a9a4b302
AM
1632018-04-16 Alan Modra <amodra@gmail.com>
164
165 * Makefile.am: Remove w65 support.
166 * configure.ac: Likewise.
167 * disassemble.c: Likewise.
168 * disassemble.h: Likewise.
169 * w65-dis.c: Delete.
170 * w65-opc.h: Delete.
171 * Makefile.in: Regenerate.
172 * configure: Regenerate.
173 * po/POTFILES.in: Regenerate.
174
04cb01fd
AM
1752018-04-16 Alan Modra <amodra@gmail.com>
176
177 * configure.ac: Remove we32k support.
178 * configure: Regenerate.
179
c2bf1eec
AM
1802018-04-16 Alan Modra <amodra@gmail.com>
181
182 * Makefile.am: Remove m88k support.
183 * configure.ac: Likewise.
184 * disassemble.c: Likewise.
185 * disassemble.h: Likewise.
186 * m88k-dis.c: Delete.
187 * Makefile.in: Regenerate.
188 * configure: Regenerate.
189 * po/POTFILES.in: Regenerate.
190
6793974d
AM
1912018-04-16 Alan Modra <amodra@gmail.com>
192
193 * Makefile.am: Remove i370 support.
194 * configure.ac: Likewise.
195 * disassemble.c: Likewise.
196 * disassemble.h: Likewise.
197 * i370-dis.c: Delete.
198 * i370-opc.c: Delete.
199 * Makefile.in: Regenerate.
200 * configure: Regenerate.
201 * po/POTFILES.in: Regenerate.
202
e82aa794
AM
2032018-04-16 Alan Modra <amodra@gmail.com>
204
205 * Makefile.am: Remove h8500 support.
206 * configure.ac: Likewise.
207 * disassemble.c: Likewise.
208 * disassemble.h: Likewise.
209 * h8500-dis.c: Delete.
210 * h8500-opc.h: Delete.
211 * Makefile.in: Regenerate.
212 * configure: Regenerate.
213 * po/POTFILES.in: Regenerate.
214
fceadf09
AM
2152018-04-16 Alan Modra <amodra@gmail.com>
216
217 * configure.ac: Remove tahoe support.
218 * configure: Regenerate.
219
ae1d3843
L
2202018-04-15 H.J. Lu <hongjiu.lu@intel.com>
221
222 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
223 umwait.
224 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
225 64-bit mode.
226 * i386-tbl.h: Regenerated.
227
de89d0a3
IT
2282018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
229
230 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
231 PREFIX_MOD_1_0FAE_REG_6.
232 (va_mode): New.
233 (OP_E_register): Use va_mode.
234 * i386-dis-evex.h (prefix_table):
235 New instructions (see prefixes above).
236 * i386-gen.c (cpu_flag_init): Add WAITPKG.
237 (cpu_flags): Likewise.
238 * i386-opc.h (enum): Likewise.
239 (i386_cpu_flags): Likewise.
240 * i386-opc.tbl: Add umonitor, umwait, tpause.
241 * i386-init.h: Regenerate.
242 * i386-tbl.h: Likewise.
243
a8eb42a8
AM
2442018-04-11 Alan Modra <amodra@gmail.com>
245
246 * opcodes/i860-dis.c: Delete.
247 * opcodes/i960-dis.c: Delete.
248 * Makefile.am: Remove i860 and i960 support.
249 * configure.ac: Likewise.
250 * disassemble.c: Likewise.
251 * disassemble.h: Likewise.
252 * Makefile.in: Regenerate.
253 * configure: Regenerate.
254 * po/POTFILES.in: Regenerate.
255
caf0678c
L
2562018-04-04 H.J. Lu <hongjiu.lu@intel.com>
257
258 PR binutils/23025
259 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
260 to 0.
261 (print_insn): Clear vex instead of vex.evex.
262
4fb0d2b9
NC
2632018-04-04 Nick Clifton <nickc@redhat.com>
264
265 * po/es.po: Updated Spanish translation.
266
c39e5b26
JB
2672018-03-28 Jan Beulich <jbeulich@suse.com>
268
269 * i386-gen.c (opcode_modifiers): Delete VecESize.
270 * i386-opc.h (VecESize): Delete.
271 (struct i386_opcode_modifier): Delete vecesize.
272 * i386-opc.tbl: Drop VecESize.
273 * i386-tlb.h: Re-generate.
274
8e6e0792
JB
2752018-03-28 Jan Beulich <jbeulich@suse.com>
276
277 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
278 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
279 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
280 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
281 * i386-tlb.h: Re-generate.
282
9f123b91
JB
2832018-03-28 Jan Beulich <jbeulich@suse.com>
284
285 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
286 Fold AVX512 forms
287 * i386-tlb.h: Re-generate.
288
9646c87b
JB
2892018-03-28 Jan Beulich <jbeulich@suse.com>
290
291 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
292 (vex_len_table): Drop Y for vcvt*2si.
293 (putop): Replace plain 'Y' handling by abort().
294
c8d59609
NC
2952018-03-28 Nick Clifton <nickc@redhat.com>
296
297 PR 22988
298 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
299 instructions with only a base address register.
300 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
301 handle AARHC64_OPND_SVE_ADDR_R.
302 (aarch64_print_operand): Likewise.
303 * aarch64-asm-2.c: Regenerate.
304 * aarch64_dis-2.c: Regenerate.
305 * aarch64-opc-2.c: Regenerate.
306
b8c169f3
JB
3072018-03-22 Jan Beulich <jbeulich@suse.com>
308
309 * i386-opc.tbl: Drop VecESize from register only insn forms and
310 memory forms not allowing broadcast.
311 * i386-tlb.h: Re-generate.
312
96bc132a
JB
3132018-03-22 Jan Beulich <jbeulich@suse.com>
314
315 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
316 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
317 sha256*): Drop Disp<N>.
318
9f79e886
JB
3192018-03-22 Jan Beulich <jbeulich@suse.com>
320
321 * i386-dis.c (EbndS, bnd_swap_mode): New.
322 (prefix_table): Use EbndS.
323 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
324 * i386-opc.tbl (bndmov): Move misplaced Load.
325 * i386-tlb.h: Re-generate.
326
d6793fa1
JB
3272018-03-22 Jan Beulich <jbeulich@suse.com>
328
329 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
330 templates allowing memory operands and folded ones for register
331 only flavors.
332 * i386-tlb.h: Re-generate.
333
f7768225
JB
3342018-03-22 Jan Beulich <jbeulich@suse.com>
335
336 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
337 256-bit templates. Drop redundant leftover Disp<N>.
338 * i386-tlb.h: Re-generate.
339
0e35537d
JW
3402018-03-14 Kito Cheng <kito.cheng@gmail.com>
341
342 * riscv-opc.c (riscv_insn_types): New.
343
b4a3689a
NC
3442018-03-13 Nick Clifton <nickc@redhat.com>
345
346 * po/pt_BR.po: Updated Brazilian Portuguese translation.
347
d3d50934
L
3482018-03-08 H.J. Lu <hongjiu.lu@intel.com>
349
350 * i386-opc.tbl: Add Optimize to clr.
351 * i386-tbl.h: Regenerated.
352
bd5dea88
L
3532018-03-08 H.J. Lu <hongjiu.lu@intel.com>
354
355 * i386-gen.c (opcode_modifiers): Remove OldGcc.
356 * i386-opc.h (OldGcc): Removed.
357 (i386_opcode_modifier): Remove oldgcc.
358 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
359 instructions for old (<= 2.8.1) versions of gcc.
360 * i386-tbl.h: Regenerated.
361
e771e7c9
JB
3622018-03-08 Jan Beulich <jbeulich@suse.com>
363
364 * i386-opc.h (EVEXDYN): New.
365 * i386-opc.tbl: Fold various AVX512VL templates.
366 * i386-tlb.h: Re-generate.
367
ed438a93
JB
3682018-03-08 Jan Beulich <jbeulich@suse.com>
369
370 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
371 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
372 vpexpandd, vpexpandq): Fold AFX512VF templates.
373 * i386-tlb.h: Re-generate.
374
454172a9
JB
3752018-03-08 Jan Beulich <jbeulich@suse.com>
376
377 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
378 Fold 128- and 256-bit VEX-encoded templates.
379 * i386-tlb.h: Re-generate.
380
36824150
JB
3812018-03-08 Jan Beulich <jbeulich@suse.com>
382
383 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
384 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
385 vpexpandd, vpexpandq): Fold AVX512F templates.
386 * i386-tlb.h: Re-generate.
387
e7f5c0a9
JB
3882018-03-08 Jan Beulich <jbeulich@suse.com>
389
390 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
391 64-bit templates. Drop Disp<N>.
392 * i386-tlb.h: Re-generate.
393
25a4277f
JB
3942018-03-08 Jan Beulich <jbeulich@suse.com>
395
396 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
397 and 256-bit templates.
398 * i386-tlb.h: Re-generate.
399
d2224064
JB
4002018-03-08 Jan Beulich <jbeulich@suse.com>
401
402 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
403 * i386-tlb.h: Re-generate.
404
1b193f0b
JB
4052018-03-08 Jan Beulich <jbeulich@suse.com>
406
407 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
408 Drop NoAVX.
409 * i386-tlb.h: Re-generate.
410
f2f6a710
JB
4112018-03-08 Jan Beulich <jbeulich@suse.com>
412
413 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
414 * i386-tlb.h: Re-generate.
415
38e314eb
JB
4162018-03-08 Jan Beulich <jbeulich@suse.com>
417
418 * i386-gen.c (opcode_modifiers): Delete FloatD.
419 * i386-opc.h (FloatD): Delete.
420 (struct i386_opcode_modifier): Delete floatd.
421 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
422 FloatD by D.
423 * i386-tlb.h: Re-generate.
424
d53e6b98
JB
4252018-03-08 Jan Beulich <jbeulich@suse.com>
426
427 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
428
2907c2f5
JB
4292018-03-08 Jan Beulich <jbeulich@suse.com>
430
431 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
432 * i386-tlb.h: Re-generate.
433
73053c1f
JB
4342018-03-08 Jan Beulich <jbeulich@suse.com>
435
436 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
437 forms.
438 * i386-tlb.h: Re-generate.
439
52fe4420
AM
4402018-03-07 Alan Modra <amodra@gmail.com>
441
442 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
443 bfd_arch_rs6000.
444 * disassemble.h (print_insn_rs6000): Delete.
445 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
446 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
447 (print_insn_rs6000): Delete.
448
a6743a54
AM
4492018-03-03 Alan Modra <amodra@gmail.com>
450
451 * sysdep.h (opcodes_error_handler): Define.
452 (_bfd_error_handler): Declare.
453 * Makefile.am: Remove stray #.
454 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
455 EDIT" comment.
456 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
457 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
458 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
459 opcodes_error_handler to print errors. Standardize error messages.
460 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
461 and include opintl.h.
462 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
463 * i386-gen.c: Standardize error messages.
464 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
465 * Makefile.in: Regenerate.
466 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
467 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
468 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
469 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
470 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
471 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
472 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
473 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
474 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
475 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
476 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
477 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
478 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
479
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4802018-03-01 H.J. Lu <hongjiu.lu@intel.com>
481
482 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
483 vpsub[bwdq] instructions.
484 * i386-tbl.h: Regenerated.
485
e184813f
AM
4862018-03-01 Alan Modra <amodra@gmail.com>
487
488 * configure.ac (ALL_LINGUAS): Sort.
489 * configure: Regenerate.
490
5b616bef
TP
4912018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
492
493 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
494 macro by assignements.
495
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4962018-02-27 H.J. Lu <hongjiu.lu@intel.com>
497
498 PR gas/22871
499 * i386-gen.c (opcode_modifiers): Add Optimize.
500 * i386-opc.h (Optimize): New enum.
501 (i386_opcode_modifier): Add optimize.
502 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
503 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
504 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
505 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
506 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
507 vpxord and vpxorq.
508 * i386-tbl.h: Regenerated.
509
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5102018-02-26 Alan Modra <amodra@gmail.com>
511
512 * crx-dis.c (getregliststring): Allocate a large enough buffer
513 to silence false positive gcc8 warning.
514
0bccfb29
JW
5152018-02-22 Shea Levy <shea@shealevy.com>
516
517 * disassemble.c (ARCH_riscv): Define if ARCH_all.
518
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5192018-02-22 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-opc.tbl: Add {rex},
522 * i386-tbl.h: Regenerated.
523
75f31665
MR
5242018-02-20 Maciej W. Rozycki <macro@mips.com>
525
526 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
527 (mips16_opcodes): Replace `M' with `m' for "restore".
528
e207bc53
TP
5292018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
530
531 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
532
87993319
MR
5332018-02-13 Maciej W. Rozycki <macro@mips.com>
534
535 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
536 variable to `function_index'.
537
68d20676
NC
5382018-02-13 Nick Clifton <nickc@redhat.com>
539
540 PR 22823
541 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
542 about truncation of printing.
543
d2159fdc
HW
5442018-02-12 Henry Wong <henry@stuffedcow.net>
545
546 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
547
f174ef9f
NC
5482018-02-05 Nick Clifton <nickc@redhat.com>
549
550 * po/pt_BR.po: Updated Brazilian Portuguese translation.
551
be3a8dca
IT
5522018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
553
554 * i386-dis.c (enum): Add pconfig.
555 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
556 (cpu_flags): Add CpuPCONFIG.
557 * i386-opc.h (enum): Add CpuPCONFIG.
558 (i386_cpu_flags): Add cpupconfig.
559 * i386-opc.tbl: Add PCONFIG instruction.
560 * i386-init.h: Regenerate.
561 * i386-tbl.h: Likewise.
562
3233d7d0
IT
5632018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
564
565 * i386-dis.c (enum): Add PREFIX_0F09.
566 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
567 (cpu_flags): Add CpuWBNOINVD.
568 * i386-opc.h (enum): Add CpuWBNOINVD.
569 (i386_cpu_flags): Add cpuwbnoinvd.
570 * i386-opc.tbl: Add WBNOINVD instruction.
571 * i386-init.h: Regenerate.
572 * i386-tbl.h: Likewise.
573
e925c834
JW
5742018-01-17 Jim Wilson <jimw@sifive.com>
575
576 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
577
d777820b
IT
5782018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
579
580 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
581 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
582 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
583 (cpu_flags): Add CpuIBT, CpuSHSTK.
584 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
585 (i386_cpu_flags): Add cpuibt, cpushstk.
586 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
587 * i386-init.h: Regenerate.
588 * i386-tbl.h: Likewise.
589
f6efed01
NC
5902018-01-16 Nick Clifton <nickc@redhat.com>
591
592 * po/pt_BR.po: Updated Brazilian Portugese translation.
593 * po/de.po: Updated German translation.
594
2721d702
JW
5952018-01-15 Jim Wilson <jimw@sifive.com>
596
597 * riscv-opc.c (match_c_nop): New.
598 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
599
616dcb87
NC
6002018-01-15 Nick Clifton <nickc@redhat.com>
601
602 * po/uk.po: Updated Ukranian translation.
603
3957a496
NC
6042018-01-13 Nick Clifton <nickc@redhat.com>
605
606 * po/opcodes.pot: Regenerated.
607
769c7ea5
NC
6082018-01-13 Nick Clifton <nickc@redhat.com>
609
610 * configure: Regenerate.
611
faf766e3
NC
6122018-01-13 Nick Clifton <nickc@redhat.com>
613
614 2.30 branch created.
615
888a89da
IT
6162018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
617
618 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
619 * i386-tbl.h: Regenerate.
620
cbda583a
JB
6212018-01-10 Jan Beulich <jbeulich@suse.com>
622
623 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
624 * i386-tbl.h: Re-generate.
625
c9e92278
JB
6262018-01-10 Jan Beulich <jbeulich@suse.com>
627
628 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
629 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
630 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
631 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
632 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
633 Disp8MemShift of AVX512VL forms.
634 * i386-tbl.h: Re-generate.
635
35fd2b2b
JW
6362018-01-09 Jim Wilson <jimw@sifive.com>
637
638 * riscv-dis.c (maybe_print_address): If base_reg is zero,
639 then the hi_addr value is zero.
640
91d8b670
JG
6412018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
642
643 * arm-dis.c (arm_opcodes): Add csdb.
644 (thumb32_opcodes): Add csdb.
645
be2e7d95
JG
6462018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
647
648 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
649 * aarch64-asm-2.c: Regenerate.
650 * aarch64-dis-2.c: Regenerate.
651 * aarch64-opc-2.c: Regenerate.
652
704a705d
L
6532018-01-08 H.J. Lu <hongjiu.lu@intel.com>
654
655 PR gas/22681
656 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
657 Remove AVX512 vmovd with 64-bit operands.
658 * i386-tbl.h: Regenerated.
659
35eeb78f
JW
6602018-01-05 Jim Wilson <jimw@sifive.com>
661
662 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
663 jalr.
664
219d1afa
AM
6652018-01-03 Alan Modra <amodra@gmail.com>
666
667 Update year range in copyright notice of all files.
668
1508bbf5
JB
6692018-01-02 Jan Beulich <jbeulich@suse.com>
670
671 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
672 and OPERAND_TYPE_REGZMM entries.
673
1e563868 674For older changes see ChangeLog-2017
3499769a 675\f
1e563868 676Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
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677
678Copying and distribution of this file, with or without modification,
679are permitted in any medium without royalty provided the copyright
680notice and this notice are preserved.
681
682Local Variables:
683mode: change-log
684left-margin: 8
685fill-column: 74
686version-control: never
687End:
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