projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gas/
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
cc537e56
RS		 12013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
4 in macros.
5
7a5f87ce
RS		 62013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
7
8 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
9 ADDA.S, MULA.S and SUBA.S.
10
41741fa4
L		 112013-07-08 H.J. Lu <hongjiu.lu@intel.com>
12
13 PR gas/13572
14 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
15 * i386-tbl.h: Regenerated.
16
f2ae14a1
RS		 172013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
18
19 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
20 and SD A(B) macros up.
21 * micromips-opc.c (micromips_opcodes): Likewise.
22
04c9d415
RS		 232013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
24
25 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
26 instructions.
27
5c324c16
RS		 282013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
29
30 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
31 MDMX-like instructions.
32 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
33 printing "Q" operands for INSN_5400 instructions.
34
23e69e47
RS		 352013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
36
37 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
38 "+S" for "cins".
39 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
40 Combine cases.
41
27c5c572
RS		 422013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
43
44 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
45 "jalx".
46 * mips16-opc.c (mips16_opcodes): Likewise.
47 * micromips-opc.c (micromips_opcodes): Likewise.
48 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
49 (print_insn_mips16): Handle "+i".
50 (print_insn_micromips): Likewise. Conditionally preserve the
51 ISA bit for "a" but not for "+i".
52
e76ff5ab
RS		 532013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
54
55 * micromips-opc.c (WR_mhi): Rename to..
56 (WR_mh): ...this.
57 (micromips_opcodes): Update "movep" entry accordingly. Replace
58 "mh,mi" with "mh".
59 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
60 (micromips_to_32_reg_h_map1): ...this.
61 (micromips_to_32_reg_i_map): Rename to...
62 (micromips_to_32_reg_h_map2): ...this.
63 (print_micromips_insn): Remove "mi" case. Print both registers
64 in the pair for "mh".
65
fa7616a4
RS		 662013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
67
68 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
69 * micromips-opc.c (micromips_opcodes): Likewise.
70 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
71 and "+T" handling. Check for a "0" suffix when deciding whether to
72 use coprocessor 0 names. In that case, also check for ",H" selectors.
73
fb798c50
AK		 742013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
75
76 * s390-opc.c (J12_12, J24_24): New macros.
77 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
78 (MASK_MII_UPI): Rename to MASK_MII_UPP.
79 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
80
58ae08f2
AM		 812013-07-04 Alan Modra <amodra@gmail.com>
82
83 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
84
b5e04c2b
NC		 852013-06-26 Nick Clifton <nickc@redhat.com>
86
87 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
88 field when checking for type 2 nop.
89 * rx-decode.c: Regenerate.
90
833794fc
MR		 912013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
92
93 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
94 and "movep" macros.
95
1bbce132
MR		 962013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
97
98 * mips-dis.c (is_mips16_plt_tail): New function.
99 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
100 word.
101 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
102
34c911a4
NC		 1032013-06-21 DJ Delorie <dj@redhat.com>
104
105 * msp430-decode.opc: New.
106 * msp430-decode.c: New/generated.
107 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
108 (MAINTAINER_CLEANFILES): Likewise.
109 Add rule to build msp430-decode.c frommsp430decode.opc
110 using the opc2c program.
111 * Makefile.in: Regenerate.
112 * configure.in: Add msp430-decode.lo to msp430 architecture files.
113 * configure: Regenerate.
114
b9eead84
YZ		 1152013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
116
117 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
118 (SYMTAB_AVAILABLE): Removed.
119 (#include "elf/aarch64.h): Ditto.
120
7f3c4072
CM		 1212013-06-17 Catherine Moore <clm@codesourcery.com>
122 Maciej W. Rozycki <macro@codesourcery.com>
123 Chao-Ying Fu <fu@mips.com>
124
125 * micromips-opc.c (EVA): Define.
126 (TLBINV): Define.
127 (micromips_opcodes): Add EVA opcodes.
128 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
129 (print_insn_args): Handle EVA offsets.
130 (print_insn_micromips): Likewise.
131 * mips-opc.c (EVA): Define.
132 (TLBINV): Define.
133 (mips_builtin_opcodes): Add EVA opcodes.
134
de40ceb6
AM		 1352013-06-17 Alan Modra <amodra@gmail.com>
136
137 * Makefile.am (mips-opc.lo): Add rules to create automatic
138 dependency files. Pass archdefs.
139 (micromips-opc.lo, mips16-opc.lo): Likewise.
140 * Makefile.in: Regenerate.
141
3531d549
DD		 1422013-06-14 DJ Delorie <dj@redhat.com>
143
144 * rx-decode.opc (rx_decode_opcode): Bit operations on
145 registers are 32-bit operations, not 8-bit operations.
146 * rx-decode.c: Regenerate.
147
ba92f7fb
CF		 1482013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
149
150 * micromips-opc.c (IVIRT): New define.
151 (IVIRT64): New define.
152 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
153 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
154
155 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
156 dmtgc0 to print cp0 names.
157
9daf7bab
SL		 1582013-06-09 Sandra Loosemore <sandra@codesourcery.com>
159
160 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
161 argument.
162
d301a56b
RS		 1632013-06-08 Catherine Moore <clm@codesourcery.com>
164 Richard Sandiford <rdsandiford@googlemail.com>
165
166 * micromips-opc.c (D32, D33, MC): Update definitions.
167 (micromips_opcodes): Initialize ase field.
168 * mips-dis.c (mips_arch_choice): Add ase field.
169 (mips_arch_choices): Initialize ase field.
170 (set_default_mips_dis_options): Declare and setup mips_ase.
171 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
172 MT32, MC): Update definitions.
173 (mips_builtin_opcodes): Initialize ase field.
174
a3dcb6c5
RS		 1752013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
176
177 * s390-opc.txt (flogr): Require a register pair destination.
178
6cf1d90c
AK		 1792013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
180
181 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
182 instruction format.
183
c77c0862
RS		 1842013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
185
186 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
187
c0637f3a
PB		 1882013-05-20 Peter Bergner <bergner@vnet.ibm.com>
189
190 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
191 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
192 XLS_MASK, PPCVSX2): New defines.
193 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
194 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
195 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
196 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
197 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
198 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
199 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
200 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
201 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
202 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
203 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
204 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
205 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
206 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
207 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
208 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
209 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
210 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
211 <lxvx, stxvx>: New extended mnemonics.
212
4934fdaf
AM		 2132013-05-17 Alan Modra <amodra@gmail.com>
214
215 * ia64-raw.tbl: Replace non-ASCII char.
216 * ia64-waw.tbl: Likewise.
217 * ia64-asmtab.c: Regenerate.
218
6091d651
SE		 2192013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
220
221 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
222 * i386-init.h: Regenerated.
223
d2865ed3
YZ		 2242013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
225
226 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
227 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
228 check from [0, 255] to [-128, 255].
229
b015e599
AP		 2302013-05-09 Andrew Pinski <apinski@cavium.com>
231
232 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
233 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
234 (parse_mips_dis_option): Handle the virt option.
235 (print_insn_args): Handle "+J".
236 (print_mips_disassembler_options): Print out message about virt64.
237 * mips-opc.c (IVIRT): New define.
238 (IVIRT64): New define.
239 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
240 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
241 Move rfe to the bottom as it conflicts with tlbgp.
242
9f0682fe
AM		 2432013-05-09 Alan Modra <amodra@gmail.com>
244
245 * ppc-opc.c (extract_vlesi): Properly sign extend.
246 (extract_vlensi): Likewise. Comment reason for setting invalid.
247
13761a11
NC		 2482013-05-02 Nick Clifton <nickc@redhat.com>
249
250 * msp430-dis.c: Add support for MSP430X instructions.
251
e3031850
SL		 2522013-04-24 Sandra Loosemore <sandra@codesourcery.com>
253
254 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
255 to "eccinj".
256
17310e56
NC		 2572013-04-17 Wei-chen Wang <cole945@gmail.com>
258
259 PR binutils/15369
260 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
261 of CGEN_CPU_ENDIAN.
262 (hash_insns_list): Likewise.
263
731df338
JK		 2642013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
265
266 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
267 warning workaround.
268
5f77db52
JB		 2692013-04-08 Jan Beulich <jbeulich@suse.com>
270
271 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
272 * i386-tbl.h: Re-generate.
273
0afd1215
DM		 2742013-04-06 David S. Miller <davem@davemloft.net>
275
276 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
277 of an opcode, prefer the one with F_PREFERRED set.
278 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
279 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
280 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
281 mark existing mnenomics as aliases. Add "cc" suffix to edge
282 instructions generating condition codes, mark existing mnenomics
283 as aliases. Add "fp" prefix to VIS compare instructions, mark
284 existing mnenomics as aliases.
285
41702d50
NC		 2862013-04-03 Nick Clifton <nickc@redhat.com>
287
288 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
289 destination address by subtracting the operand from the current
290 address.
291 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
292 a positive value in the insn.
293 (extract_u16_loop): Do not negate the returned value.
294 (D16_LOOP): Add V850_INVERSE_PCREL flag.
295
296 (ceilf.sw): Remove duplicate entry.
297 (cvtf.hs): New entry.
298 (cvtf.sh): Likewise.
299 (fmaf.s): Likewise.
300 (fmsf.s): Likewise.
301 (fnmaf.s): Likewise.
302 (fnmsf.s): Likewise.
303 (maddf.s): Restrict to E3V5 architectures.
304 (msubf.s): Likewise.
305 (nmaddf.s): Likewise.
306 (nmsubf.s): Likewise.
307
55cf16e1
L		 3082013-03-27 H.J. Lu <hongjiu.lu@intel.com>
309
310 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
311 check address mode.
312 (print_insn): Pass sizeflag to get_sib.
313
51dcdd4d
NC		 3142013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
315
316 PR binutils/15068
317 * tic6x-dis.c: Add support for displaying 16-bit insns.
318
795b8e6b
NC		 3192013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
320
321 PR gas/15095
322 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
323 individual msb and lsb halves in src1 & src2 fields. Discard the
324 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
325 follow what Ti SDK does in that case as any value in the src1
326 field yields the same output with SDK disassembler.
327
314d60dd
ME		 3282013-03-12 Michael Eager <eager@eagercon.com>
329
795b8e6b 330 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 331
dad60f8e
SL		 3322013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
333
334 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
335
f5cb796a
SL		 3362013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
337
338 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
339
21fde85c
SL		 3402013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
341
342 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
343
dd5181d5
KT		 3442013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
345
346 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
347 (thumb32_opcodes): Likewise.
348 (print_insn_thumb32): Handle 'S' control char.
349
87a8d6cb
NC		 3502013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
351
352 * lm32-desc.c: Regenerate.
353
99dce992
L		 3542013-03-01 H.J. Lu <hongjiu.lu@intel.com>
355
356 * i386-reg.tbl (riz): Add RegRex64.
357 * i386-tbl.h: Regenerated.
358
e60bb1dd
YZ		 3592013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
360
361 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
362 (aarch64_feature_crc): New static.
363 (CRC): New macro.
364 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
365 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
366 * aarch64-asm-2.c: Re-generate.
367 * aarch64-dis-2.c: Ditto.
368 * aarch64-opc-2.c: Ditto.
369
c7570fcd
AM		 3702013-02-27 Alan Modra <amodra@gmail.com>
371
372 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
373 * rl78-decode.c: Regenerate.
374
151fa98f
NC		 3752013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
376
377 * rl78-decode.opc: Fix encoding of DIVWU insn.
378 * rl78-decode.c: Regenerate.
379
5c111e37
L		 3802013-02-19 H.J. Lu <hongjiu.lu@intel.com>
381
382 PR gas/15159
383 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
384
385 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
386 (cpu_flags): Add CpuSMAP.
387
388 * i386-opc.h (CpuSMAP): New.
389 (i386_cpu_flags): Add cpusmap.
390
391 * i386-opc.tbl: Add clac and stac.
392
393 * i386-init.h: Regenerated.
394 * i386-tbl.h: Likewise.
395
9d1df426
NC		 3962013-02-15 Markos Chandras <markos.chandras@imgtec.com>
397
398 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
399 which also makes the disassembler output be in little
400 endian like it should be.
401
a1ccaec9
YZ		 4022013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
403
404 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
405 fields to NULL.
406 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
407
ef068ef4 4082013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 409
410 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
411 section disassembled.
412
6fe6ded9
RE		 4132013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
414
415 * arm-dis.c: Update strht pattern.
416
0aa27725
RS		 4172013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
418
419 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
420 single-float. Disable ll, lld, sc and scd for EE. Disable the
421 trunc.w.s macro for EE.
422
36591ba1
SL		 4232013-02-06 Sandra Loosemore <sandra@codesourcery.com>
424 Andrew Jenner <andrew@codesourcery.com>
425
426 Based on patches from Altera Corporation.
427
428 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
429 nios2-opc.c.
430 * Makefile.in: Regenerated.
431 * configure.in: Add case for bfd_nios2_arch.
432 * configure: Regenerated.
433 * disassemble.c (ARCH_nios2): Define.
434 (disassembler): Add case for bfd_arch_nios2.
435 * nios2-dis.c: New file.
436 * nios2-opc.c: New file.
437
545093a4
AM		 4382013-02-04 Alan Modra <amodra@gmail.com>
439
440 * po/POTFILES.in: Regenerate.
441 * rl78-decode.c: Regenerate.
442 * rx-decode.c: Regenerate.
443
e30181a5
YZ		 4442013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
445
446 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
447 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
448 * aarch64-asm.c (convert_xtl_to_shll): New function.
449 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
450 calling convert_xtl_to_shll.
451 * aarch64-dis.c (convert_shll_to_xtl): New function.
452 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
453 calling convert_shll_to_xtl.
454 * aarch64-gen.c: Update copyright year.
455 * aarch64-asm-2.c: Re-generate.
456 * aarch64-dis-2.c: Re-generate.
457 * aarch64-opc-2.c: Re-generate.
458
78c8d46c
NC		 4592013-01-24 Nick Clifton <nickc@redhat.com>
460
461 * v850-dis.c: Add support for e3v5 architecture.
462 * v850-opc.c: Likewise.
463
f5555712
YZ		 4642013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
465
466 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
467 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
468 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 469 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 470 alignment check; change to call set_sft_amount_out_of_range_error
471 instead of set_imm_out_of_range_error.
472 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
473 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
474 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
475 SIMD_IMM_SFT.
476
2f81ff92
L		 4772013-01-16 H.J. Lu <hongjiu.lu@intel.com>
478
479 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
480
481 * i386-init.h: Regenerated.
482 * i386-tbl.h: Likewise.
483
dd42f060
NC		 4842013-01-15 Nick Clifton <nickc@redhat.com>
485
486 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
487 values.
488 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
489
a4533ed8
NC		 4902013-01-14 Will Newton <will.newton@imgtec.com>
491
492 * metag-dis.c (REG_WIDTH): Increase to 64.
493
5817ffd1
PB		 4942013-01-10 Peter Bergner <bergner@vnet.ibm.com>
495
496 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
497 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
498 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
499 (SH6): Update.
500 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
501 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
502 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
503 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
504
a3c62988
NC		 5052013-01-10 Will Newton <will.newton@imgtec.com>
506
507 * Makefile.am: Add Meta.
508 * configure.in: Add Meta.
509 * disassemble.c: Add Meta support.
510 * metag-dis.c: New file.
511 * Makefile.in: Regenerate.
512 * configure: Regenerate.
513
73335eae
NC		 5142013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
515
516 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
517 (match_opcode): Rename to cr16_match_opcode.
518
e407c74b
NC		 5192013-01-04 Juergen Urban <JuergenUrban@gmx.de>
520
521 * mips-dis.c: Add names for CP0 registers of r5900.
522 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
523 instructions sq and lq.
524 Add support for MIPS r5900 CPU.
525 Add support for 128 bit MMI (Multimedia Instructions).
526 Add support for EE instructions (Emotion Engine).
527 Disable unsupported floating point instructions (64 bit and
528 undefined compare operations).
529 Enable instructions of MIPS ISA IV which are supported by r5900.
530 Disable 64 bit co processor instructions.
531 Disable 64 bit multiplication and division instructions.
532 Disable instructions for co-processor 2 and 3, because these are
533 not supported (preparation for later VU0 support (Vector Unit)).
534 Disable cvt.w.s because this behaves like trunc.w.s and the
535 correct execution can't be ensured on r5900.
536 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
537 will confuse less developers and compilers.
538
a32c3ff8
NC		 5392013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
540
fb098a1e
YZ		 541 * aarch64-opc.c (aarch64_print_operand): Change to print
542 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
543 in comment.
544 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
545 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
546 OP_MOV_IMM_WIDE.
547
5482013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
549
550 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
551 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 552
62658407
L		 5532013-01-02 H.J. Lu <hongjiu.lu@intel.com>
554
555 * i386-gen.c (process_copyright): Update copyright year to 2013.
556
bab4becb 5572013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 558
bab4becb
NC		 559 * cr16-dis.c (match_opcode,make_instruction): Remove static
560 declaration.
561 (dwordU,wordU): Moved typedefs to opcode/cr16.h
562 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 563
bab4becb 564For older changes see ChangeLog-2012
252b5132 565\f
bab4becb 566Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 567
568Copying and distribution of this file, with or without modification,
569are permitted in any medium without royalty provided the copyright
570notice and this notice are preserved.
571
252b5132 572Local Variables:
2f6d2f85
NC		 573mode: change-log
574left-margin: 8
575fill-column: 74
252b5132
RH		 576version-control: never
577End:
GDB Binutils - Deliverables
This page took 0.65315 seconds and 4 git commands to generate.