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crash printing optimized out variant type
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6d2920c8
L		 12012-09-10 H.J. Lu <hongjiu.lu@intel.com>
2
3 * configure: Regenerated.
4
b3e14eda
L		 52012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
6
7 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
8 * ia64-gen.c: Promote completer index type to longlong.
9 (irf_operand): Add new register recognition.
10 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
11 (lookup_specifier): Add new resource recognition.
12 (insert_bit_table_ent): Relax abort condition according to the
13 changed completer index type.
14 (print_dis_table): Fix printf format for completer index.
15 * ia64-ic.tbl: Add a new instruction class.
16 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
17 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
18 * ia64-opc.h: Define short names for new operand types.
19 * ia64-raw.tbl: Add new RAW resource for DAHR register.
20 * ia64-waw.tbl: Add new WAW resource for DAHR register.
21 * ia64-asmtab.c: Regenerate.
22
382c72e9
PB		 232012-08-29 Peter Bergner <bergner@vnet.ibm.com>
24
25 * ppc-opc.c (VXASHB_MASK): New define.
26 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
27
fb048c26
PB		 282012-08-28 Peter Bergner <bergner@vnet.ibm.com>
29
30 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
31 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
32 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
33 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
34 vupklsh>: Use VXVA_MASK.
35 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
36 <mfvscr>: Use VXVAVB_MASK.
37 <mtvscr>: Use VXVDVA_MASK.
38 <vspltb>: Use VXUIMM4_MASK.
39 <vsplth>: Use VXUIMM3_MASK.
40 <vspltw>: Use VXUIMM2_MASK.
41
3c9017d2
MGD		 422012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
43
44 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
45
48adcd8e
MGD		 462012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
47
48 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
49
4f51b4bd
MGD		 502012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
51
52 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
53
91ff7894
MGD		 542012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
55
56 * arm-dis.c (neon_opcodes): Add support for AES instructions.
57
c70a8987
MGD		 582012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
59
60 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
61 conversions.
62
30bdf752
MGD		 632012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
64
65 * arm-dis.c (coprocessor_opcodes): Add VRINT.
66 (neon_opcodes): Likewise.
67
7e8e6784
MGD		 682012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
69
70 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
71 variants.
72 (neon_opcodes): Likewise.
73
73924fbc
MGD		 742012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
75
76 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
77 (neon_opcodes): Likewise.
78
33399f07
MGD		 792012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
80
81 * arm-dis.c (coprocessor_opcodes): Add VSEL.
82 (print_insn_coprocessor): Add new %<>c bitfield format
83 specifier.
84
9eb6c0f1
MGD		 852012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
86
87 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
88 (thumb32_opcodes): Likewise.
89 (print_arm_insn): Add support for %<>T formatter.
90
8884b720
MGD		 912012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
92
93 * arm-dis.c (arm_opcodes): Add HLT.
94 (thumb_opcodes): Likewise.
95
b79f7053
MGD		 962012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
97
98 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
99
53c4b28b
MGD		 1002012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
101
102 * arm-dis.c (arm_opcodes): Add SEVL.
103 (thumb_opcodes): Likewise.
104 (thumb32_opcodes): Likewise.
105
e797f7e0
MGD		 1062012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
107
108 * arm-dis.c (data_barrier_option): New function.
109 (print_insn_arm): Use data_barrier_option.
110 (print_insn_thumb32): Use data_barrier_option.
111
e2efe87d
MGD		 1122012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
113
114 * arm-dis.c (COND_UNCOND): New constant.
115 (print_insn_coprocessor): Add support for %u format specifier.
116 (print_insn_neon): Likewise.
117
2c63854f
DM		 1182012-08-21 David S. Miller <davem@davemloft.net>
119
120 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
121 F3F4 macro.
122
e67ed0e8
AM		 1232012-08-20 Edmar Wienskoski <edmar@freescale.com>
124
125 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
126 vabsduh, vabsduw, mviwsplt.
127
7b458c12
L		 1282012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
129
130 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
131 CPU_BTVER2_FLAGS.
132
e67ed0e8 133 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 134
135 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
136 * i386-init.h: Regenerated.
137 * i386-tbl.h: Likewise.
138
eb80cb87
NC		 1392012-08-17 Nick Clifton <nickc@redhat.com>
140
141 * po/uk.po: New Ukranian translation.
142 * configure.in (ALL_LINGUAS): Add uk.
143 * configure: Regenerate.
144
8baf7b78
PB		 1452012-08-16 Peter Bergner <bergner@vnet.ibm.com>
146
147 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
148 RBX for the third operand.
149 <"lswi">: Use RAX for second and NBI for the third operand.
150
3d557b4c
DD		 1512012-08-15 DJ Delorie <dj@redhat.com>
152
153 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
154 operands, so that data addresses can be corrected when not
155 ES-overridden.
156 * rl78-decode.c: Regenerate.
157 * rl78-dis.c (print_insn_rl78): Make order of modifiers
158 irrelevent. When the 'e' specifier is used on an operand and no
159 ES prefix is provided, adjust address to make it absolute.
160
588925d0
PB		 1612012-08-15 Peter Bergner <bergner@vnet.ibm.com>
162
163 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
164
9f6a6cc0
PB		 1652012-08-15 Peter Bergner <bergner@vnet.ibm.com>
166
167 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
168
fc8c4fd1
MR		 1692012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
170
171 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
172 macros, use local variables for info struct member accesses,
173 update the type of the variable used to hold the instruction
174 word.
175 (print_insn_mips, print_mips16_insn_arg): Likewise.
176 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
177 local variables for info struct member accesses.
178 (print_insn_micromips): Add GET_OP_S local macro.
179 (_print_insn_mips): Update the type of the variable used to hold
180 the instruction word.
181
a06ea964 1822012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 183 Laurent Desnogues <laurent.desnogues@arm.com>
184 Jim MacArthur <jim.macarthur@arm.com>
185 Marcus Shawcroft <marcus.shawcroft@arm.com>
186 Nigel Stephens <nigel.stephens@arm.com>
187 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
188 Richard Earnshaw <rearnsha@arm.com>
189 Sofiane Naci <sofiane.naci@arm.com>
190 Tejas Belagod <tejas.belagod@arm.com>
191 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 192
193 * Makefile.am: Add AArch64.
194 * Makefile.in: Regenerate.
195 * aarch64-asm.c: New file.
196 * aarch64-asm.h: New file.
197 * aarch64-dis.c: New file.
198 * aarch64-dis.h: New file.
199 * aarch64-gen.c: New file.
200 * aarch64-opc.c: New file.
201 * aarch64-opc.h: New file.
202 * aarch64-tbl.h: New file.
203 * configure.in: Add AArch64.
204 * configure: Regenerate.
205 * disassemble.c: Add AArch64.
206 * aarch64-asm-2.c: New file (automatically generated).
207 * aarch64-dis-2.c: New file (automatically generated).
208 * aarch64-opc-2.c: New file (automatically generated).
209 * po/POTFILES.in: Regenerate.
210
35d0a169
MR		 2112012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
212
213 * micromips-opc.c (micromips_opcodes): Update comment.
214 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
215 instructions for IOCT as appropriate.
216 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
217 opcode_is_member.
218 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
219 the result of a check for the -Wno-missing-field-initializers
220 GCC option.
221 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
222 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
223 compilation.
224 (mips16-opc.lo): Likewise.
225 (micromips-opc.lo): Likewise.
226 * aclocal.m4: Regenerate.
227 * configure: Regenerate.
228 * Makefile.in: Regenerate.
229
5c5acbbd
L		 2302012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
231
232 PR gas/14423
233 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
234 * i386-init.h: Regenerated.
235
3c892704
NC		 2362012-08-09 Nick Clifton <nickc@redhat.com>
237
238 * po/vi.po: Updated Vietnamese translation.
239
d7189fa5
RM		 2402012-08-07 Roland McGrath <mcgrathr@google.com>
241
242 * i386-dis.c (reg_table): Fill out REG_0F0D table with
243 AMD-reserved cases as "prefetch".
244 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
245 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
246 (reg_table): Use those under REG_0F18.
247 (mod_table): Add those cases as "nop/reserved".
248
4c692bc7
JB		 2492012-08-07 Jan Beulich <jbeulich@suse.com>
250
251 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
252
de882298
RM		 2532012-08-06 Roland McGrath <mcgrathr@google.com>
254
255 * i386-dis.c (print_insn): Print spaces between multiple excess
256 prefixes. Return actual number of excess prefixes consumed,
257 not always one.
258
259 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
260
7bb15c6f
RM		 2612012-08-06 Roland McGrath <mcgrathr@google.com>
262 Victor Khimenko <khim@google.com>
263 H.J. Lu <hongjiu.lu@intel.com>
264
265 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
266 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
267 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
268 (OP_E_register): Likewise.
269 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
270
3843081d
JBG		 2712012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
272
273 * configure.in: Formatting.
274 * configure: Regenerate.
275
48891606
AM		 2762012-08-01 Alan Modra <amodra@gmail.com>
277
278 * h8300-dis.c: Fix printf arg warnings.
279 * i960-dis.c: Likewise.
280 * mips-dis.c: Likewise.
281 * pdp11-dis.c: Likewise.
282 * sh-dis.c: Likewise.
283 * v850-dis.c: Likewise.
284 * configure.in: Formatting.
285 * configure: Regenerate.
286 * rl78-decode.c: Regenerate.
287 * po/POTFILES.in: Regenerate.
288
03f66e8a 2892012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 290 Catherine Moore <clm@codesourcery.com>
291 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 292
293 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
294 (DSP_VOLA): Likewise.
295 (D32, D33): Likewise.
296 (micromips_opcodes): Add DSP ASE instructions.
48891606 297 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 298 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
299
94948e64
JB		 3002012-07-31 Jan Beulich <jbeulich@suse.com>
301
302 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
303 instruction group. Mark as requiring AVX2.
304 * i386-tbl.h: Re-generate.
305
a6dc81d2
NC		 3062012-07-30 Nick Clifton <nickc@redhat.com>
307
308 * po/opcodes.pot: Updated template.
309 * po/es.po: Updated Spanish translation.
310 * po/fi.po: Updated Finnish translation.
311
c4dd807e
MF		 3122012-07-27 Mike Frysinger <vapier@gentoo.org>
313
314 * configure.in (BFD_VERSION): Run bfd/configure --version and
315 parse the output of that.
316 * configure: Regenerate.
317
03edbe3b
JL		 3182012-07-25 James Lemke <jwlemke@codesourcery.com>
319
320 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
321
63d08c68
NC		 3222012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
323 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 324
325 PR binutils/13135
326 * arm-dis.c: Add necessary casts for printing integer values.
327 Use %s when printing string values.
328 * hppa-dis.c: Likewise.
329 * m68k-dis.c: Likewise.
330 * microblaze-dis.c: Likewise.
331 * mips-dis.c: Likewise.
332 * sparc-dis.c: Likewise.
333
ff688e1f
L		 3342012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
335
336 PR binutils/14355
337 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
338 (VEX_LEN_0FXOP_08_CD): Likewise.
339 (VEX_LEN_0FXOP_08_CE): Likewise.
340 (VEX_LEN_0FXOP_08_CF): Likewise.
341 (VEX_LEN_0FXOP_08_EC): Likewise.
342 (VEX_LEN_0FXOP_08_ED): Likewise.
343 (VEX_LEN_0FXOP_08_EE): Likewise.
344 (VEX_LEN_0FXOP_08_EF): Likewise.
345 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
346 vpcomub, vpcomuw, vpcomud, vpcomuq.
347 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
348 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
349 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
350 VEX_LEN_0FXOP_08_EF.
351
e2e1fcde
L		 3522012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
353
354 * i386-dis.c (PREFIX_0F38F6): New.
355 (prefix_table): Add adcx, adox instructions.
356 (three_byte_table): Use PREFIX_0F38F6.
357 (mod_table): Add rdseed instruction.
358 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
359 (cpu_flags): Likewise.
360 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
361 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
362 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
363 prefetchw.
364 * i386-tbl.h: Regenerate.
365 * i386-init.h: Likewise.
366
8b99bf0b
TS		 3672012-07-05 Thomas Schwinge <thomas@codesourcery.com>
368
f4263ca2 369 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 370
416cf80a
SK		 3712012-07-05 Sean Keys <skeys@ipdatasys.com>
372
373 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 374 always be false due to overlapping operand masks.
375 * xgate-opc.c: Corrected 'com' opcode entry and
376 fixed spacing.
416cf80a 377
9fa0f14a
RM		 3782012-07-02 Roland McGrath <mcgrathr@google.com>
379
380 * i386-opc.tbl: Add RepPrefixOk to nop.
381 * i386-tbl.h: Regenerate.
382
4c6a93d3
NC		 3832012-06-28 Nick Clifton <nickc@redhat.com>
384
385 * po/vi.po: Updated Vietnamese translation.
386
29c048b6
RM		 3872012-06-22 Roland McGrath <mcgrathr@google.com>
388
fe13e45b
RM		 389 * i386-opc.tbl: Add RepPrefixOk to ret.
390 * i386-tbl.h: Regenerate.
391
29c048b6
RM		 392 * i386-opc.h (RepPrefixOk): New enum constant.
393 (i386_opcode_modifier): New bitfield 'repprefixok'.
394 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
395 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
396 instructions that have IsString.
397 * i386-tbl.h: Regenerate.
398
c7a8dbf9
AS		 3992012-06-11 Andreas Schwab <schwab@linux-m68k.org>
400
401 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
402 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
403 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
404 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
405 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
406 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
407 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
408 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
409 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
410
94caa966
AM		 4112012-05-19 Alan Modra <amodra@gmail.com>
412
413 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
414 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
415
5eb3690e
AM		 4162012-05-18 Alan Modra <amodra@gmail.com>
417
71fe7bab
AM		 418 * ia64-opc.c: Remove #include "ansidecl.h".
419 * z8kgen.c: Include sysdep.h first.
420
5eb3690e
AM		 421 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
422 * bfin-dis.c: Likewise.
423 * i860-dis.c: Likewise.
424 * ia64-dis.c: Likewise.
425 * ia64-gen.c: Likewise.
426 * m68hc11-dis.c: Likewise.
427 * mmix-dis.c: Likewise.
428 * msp430-dis.c: Likewise.
429 * or32-dis.c: Likewise.
430 * rl78-dis.c: Likewise.
431 * rx-dis.c: Likewise.
432 * tic4x-dis.c: Likewise.
433 * tilegx-opc.c: Likewise.
434 * tilepro-opc.c: Likewise.
435 * rx-decode.c: Regenerate.
436
a4ebc835
AM		 4372012-05-17 James Lemke <jwlemke@codesourcery.com>
438
439 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
440
98c76446
AM		 4412012-05-17 James Lemke <jwlemke@codesourcery.com>
442
443 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
444
df7b86aa
NC		 4452012-05-17 Daniel Richard G. <skunk@iskunk.org>
446 Nick Clifton <nickc@redhat.com>
447
448 PR 14072
449 * configure.in: Add check that sysdep.h has been included before
450 any system header files.
451 * configure: Regenerate.
452 * config.in: Regenerate.
453 * sysdep.h: Generate an error if included before config.h.
454 * alpha-opc.c: Include sysdep.h before any other header file.
455 * alpha-dis.c: Likewise.
456 * avr-dis.c: Likewise.
457 * cgen-opc.c: Likewise.
458 * cr16-dis.c: Likewise.
459 * cris-dis.c: Likewise.
460 * crx-dis.c: Likewise.
461 * d10v-dis.c: Likewise.
462 * d10v-opc.c: Likewise.
463 * d30v-dis.c: Likewise.
464 * d30v-opc.c: Likewise.
465 * h8500-dis.c: Likewise.
466 * i370-dis.c: Likewise.
467 * i370-opc.c: Likewise.
468 * m10200-dis.c: Likewise.
469 * m10300-dis.c: Likewise.
470 * micromips-opc.c: Likewise.
471 * mips-opc.c: Likewise.
472 * mips61-opc.c: Likewise.
473 * moxie-dis.c: Likewise.
474 * or32-opc.c: Likewise.
475 * pj-dis.c: Likewise.
476 * ppc-dis.c: Likewise.
477 * ppc-opc.c: Likewise.
478 * s390-dis.c: Likewise.
479 * sh-dis.c: Likewise.
480 * sh64-dis.c: Likewise.
481 * sparc-dis.c: Likewise.
482 * sparc-opc.c: Likewise.
483 * spu-dis.c: Likewise.
484 * tic30-dis.c: Likewise.
485 * tic54x-dis.c: Likewise.
486 * tic80-dis.c: Likewise.
487 * tic80-opc.c: Likewise.
488 * tilegx-dis.c: Likewise.
489 * tilepro-dis.c: Likewise.
490 * v850-dis.c: Likewise.
491 * v850-opc.c: Likewise.
492 * vax-dis.c: Likewise.
493 * w65-dis.c: Likewise.
494 * xgate-dis.c: Likewise.
495 * xtensa-dis.c: Likewise.
496 * rl78-decode.opc: Likewise.
497 * rl78-decode.c: Regenerate.
498 * rx-decode.opc: Likewise.
499 * rx-decode.c: Regenerate.
500
e1dad58d
AM		 5012012-05-17 Alan Modra <amodra@gmail.com>
502
503 * ppc_dis.c: Don't include elf/ppc.h.
504
101af531
NC		 5052012-05-16 Meador Inge <meadori@codesourcery.com>
506
507 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
508 to PUSH/POP {reg}.
509
6927f982
NC		 5102012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
511 Stephane Carrez <stcarrez@nerim.fr>
512
513 * configure.in: Add S12X and XGATE co-processor support to m68hc11
514 target.
515 * disassemble.c: Likewise.
516 * configure: Regenerate.
517 * m68hc11-dis.c: Make objdump output more consistent, use hex
518 instead of decimal and use 0x prefix for hex.
519 * m68hc11-opc.c: Add S12X and XGATE opcodes.
520
b9c361e0
JL		 5212012-05-14 James Lemke <jwlemke@codesourcery.com>
522
523 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
524 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
525 (vle_opcd_indices): New array.
526 (lookup_vle): New function.
527 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
528 (print_insn_powerpc): Likewise.
529 * ppc-opc.c: Likewise.
530
5312012-05-14 Catherine Moore <clm@codesourcery.com>
532 Maciej W. Rozycki <macro@codesourcery.com>
533 Rhonda Wittels <rhonda@codesourcery.com>
534 Nathan Froyd <froydnj@codesourcery.com>
535
536 * ppc-opc.c (insert_arx, extract_arx): New functions.
537 (insert_ary, extract_ary): New functions.
538 (insert_li20, extract_li20): New functions.
539 (insert_rx, extract_rx): New functions.
540 (insert_ry, extract_ry): New functions.
541 (insert_sci8, extract_sci8): New functions.
542 (insert_sci8n, extract_sci8n): New functions.
543 (insert_sd4h, extract_sd4h): New functions.
544 (insert_sd4w, extract_sd4w): New functions.
545 (insert_vlesi, extract_vlesi): New functions.
546 (insert_vlensi, extract_vlensi): New functions.
547 (insert_vleui, extract_vleui): New functions.
548 (insert_vleil, extract_vleil): New functions.
549 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
550 (BI16, BI32, BO32, B8): New.
551 (B15, B24, CRD32, CRS): New.
552 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
553 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
554 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
555 (SH6_MASK): Use PPC_OPSHIFT_INV.
556 (SI8, UI5, OIMM5, UI7, BO16): New.
557 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
558 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
559 (ALLOW8_SPRG): New.
560 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
561 (OPVUP, OPVUP_MASK OPVUP): New
562 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
563 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
564 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
565 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
566 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
567 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
568 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
569 (SE_IM5, SE_IM5_MASK): New.
570 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
571 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
572 (BO32DNZ, BO32DZ): New.
573 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
574 (PPCVLE): New.
575 (powerpc_opcodes): Add new VLE instructions. Update existing
576 instruction to include PPCVLE if supported.
577 * ppc-dis.c (ppc_opts): Add vle entry.
578 (get_powerpc_dialect): New function.
579 (powerpc_init_dialect): VLE support.
580 (print_insn_big_powerpc): Call get_powerpc_dialect.
581 (print_insn_little_powerpc): Likewise.
582 (operand_value_powerpc): Handle negative shift counts.
583 (print_insn_powerpc): Handle 2-byte instruction lengths.
584
208a4923
NC		 5852012-05-11 Daniel Richard G. <skunk@iskunk.org>
586
587 PR binutils/14028
588 * configure.in: Invoke ACX_HEADER_STRING.
589 * configure: Regenerate.
590 * config.in: Regenerate.
591 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
592 string.h and strings.h.
593
6750a3a7
NC		 5942012-05-11 Nick Clifton <nickc@redhat.com>
595
596 PR binutils/14006
597 * arm-dis.c (print_insn): Fix detection of instruction mode in
598 files containing multiple executable sections.
599
f6c1a2d5
NC		 6002012-05-03 Sean Keys <skeys@ipdatasys.com>
601
602 * Makefile.in, configure: regenerate
603 * disassemble.c (disassembler): Recognize ARCH_XGATE.
604 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
605 New functions.
606 * configure.in: Recognize xgate.
607 * xgate-dis.c, xgate-opc.c: New files for support of xgate
608 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
609 and opcode generation for xgate.
610
78e98aab
DD		 6112012-04-30 DJ Delorie <dj@redhat.com>
612
613 * rx-decode.opc (MOV): Do not sign-extend immediates which are
614 already the maximum bit size.
615 * rx-decode.c: Regenerate.
616
ec668d69
DM		 6172012-04-27 David S. Miller <davem@davemloft.net>
618
2e52845b
DM		 619 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
620 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
621
58004e23
DM		 622 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
623 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
624
698544e1
DM		 625 * sparc-opc.c (CBCOND): New define.
626 (CBCOND_XCC): Likewise.
627 (cbcond): New helper macro.
628 (sparc_opcodes): Add compare-and-branch instructions.
629
6cda1326
DM		 630 * sparc-dis.c (print_insn_sparc): Handle ')'.
631 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
632
ec668d69
DM		 633 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
634 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
635
2615994e
DM		 6362012-04-12 David S. Miller <davem@davemloft.net>
637
638 * sparc-dis.c (X_DISP10): Define.
639 (print_insn_sparc): Handle '='.
640
5de10af0
MF		 6412012-04-01 Mike Frysinger <vapier@gentoo.org>
642
643 * bfin-dis.c (fmtconst): Replace decimal handling with a single
644 sprintf call and the '*' field width.
645
55a36193
MK		 6462012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
647
648 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
649
d6688282
AM		 6502012-03-16 Alan Modra <amodra@gmail.com>
651
652 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
653 (powerpc_opcd_indices): Bump array size.
654 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
655 corresponding to unused opcodes to following entry.
656 (lookup_powerpc): New function, extracted and optimised from..
657 (print_insn_powerpc): ..here.
658
b240011a
AM		 6592012-03-15 Alan Modra <amodra@gmail.com>
660 James Lemke <jwlemke@codesourcery.com>
661
662 * disassemble.c (disassemble_init_for_target): Handle ppc init.
663 * ppc-dis.c (private): New var.
664 (powerpc_init_dialect): Don't return calloc failure, instead use
665 private.
666 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
667 (powerpc_opcd_indices): New array.
668 (disassemble_init_powerpc): New function.
669 (print_insn_big_powerpc): Don't init dialect here.
670 (print_insn_little_powerpc): Likewise.
671 (print_insn_powerpc): Start search using powerpc_opcd_indices.
672
aea77599
AM		 6732012-03-10 Edmar Wienskoski <edmar@freescale.com>
674
675 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
676 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
677 (PPCVEC2, PPCTMR, E6500): New short names.
678 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
679 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
680 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
681 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
682 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
683 optional operands on sync instruction for E6500 target.
684
5333187a
AK		 6852012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
686
687 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
688
a597d2d3
AM		 6892012-02-27 Alan Modra <amodra@gmail.com>
690
691 * mt-dis.c: Regenerate.
692
3f26eb3a
AM		 6932012-02-27 Alan Modra <amodra@gmail.com>
694
695 * v850-opc.c (extract_v8): Rearrange to make it obvious this
696 is the inverse of corresponding insert function.
697 (extract_d22, extract_u9, extract_r4): Likewise.
698 (extract_d9): Correct sign extension.
699 (extract_d16_15): Don't assume "long" is 32 bits, and don't
700 rely on implementation defined behaviour for shift right of
701 signed types.
702 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
703 (extract_d23): Likewise, and correct mask.
704
1f42f8b3
AM		 7052012-02-27 Alan Modra <amodra@gmail.com>
706
707 * crx-dis.c (print_arg): Mask constant to 32 bits.
708 * crx-opc.c (cst4_map): Use int array.
709
cdb06235
AM		 7102012-02-27 Alan Modra <amodra@gmail.com>
711
712 * arc-dis.c (BITS): Don't use shifts to mask off bits.
713 (FIELDD): Sign extend with xor,sub.
714
6f7be959
WL		 7152012-02-25 Walter Lee <walt@tilera.com>
716
717 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
718 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
719 TILEPRO_OPC_LW_TLS_SN.
720
82c2def5
L		 7212012-02-21 H.J. Lu <hongjiu.lu@intel.com>
722
723 * i386-opc.h (HLEPrefixNone): New.
724 (HLEPrefixLock): Likewise.
725 (HLEPrefixAny): Likewise.
726 (HLEPrefixRelease): Likewise.
727
42164a71
L		 7282012-02-08 H.J. Lu <hongjiu.lu@intel.com>
729
730 * i386-dis.c (HLE_Fixup1): New.
731 (HLE_Fixup2): Likewise.
732 (HLE_Fixup3): Likewise.
733 (Ebh1): Likewise.
734 (Evh1): Likewise.
735 (Ebh2): Likewise.
736 (Evh2): Likewise.
737 (Ebh3): Likewise.
738 (Evh3): Likewise.
739 (MOD_C6_REG_7): Likewise.
740 (MOD_C7_REG_7): Likewise.
741 (RM_C6_REG_7): Likewise.
742 (RM_C7_REG_7): Likewise.
743 (XACQUIRE_PREFIX): Likewise.
744 (XRELEASE_PREFIX): Likewise.
745 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
746 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
747 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
748 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
749 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
750 MOD_C6_REG_7 and MOD_C7_REG_7.
751 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
752 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
753 xtest.
754 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
755 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
756
757 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
758 CPU_RTM_FLAGS.
759 (cpu_flags): Add CpuHLE and CpuRTM.
760 (opcode_modifiers): Add HLEPrefixOk.
761
762 * i386-opc.h (CpuHLE): New.
763 (CpuRTM): Likewise.
764 (HLEPrefixOk): Likewise.
765 (i386_cpu_flags): Add cpuhle and cpurtm.
766 (i386_opcode_modifier): Add hleprefixok.
767
768 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
769 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
770 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
771 operand. Add xacquire, xrelease, xabort, xbegin, xend and
772 xtest.
773 * i386-init.h: Regenerated.
774 * i386-tbl.h: Likewise.
775
21abe33a
DD		 7762012-01-24 DJ Delorie <dj@redhat.com>
777
778 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
779 * rl78-decode.c: Regenerate.
780
e20cc039
AM		 7812012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
782
783 PR binutils/10173
784 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
785
e143d25c
AS		 7862012-01-17 Andreas Schwab <schwab@linux-m68k.org>
787
788 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
789 register and move them after pmove with PSR/PCSR register.
790
8729a6f6
L		 7912012-01-13 H.J. Lu <hongjiu.lu@intel.com>
792
793 * i386-dis.c (mod_table): Add vmfunc.
794
795 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
796 (cpu_flags): CpuVMFUNC.
797
798 * i386-opc.h (CpuVMFUNC): New.
799 (i386_cpu_flags): Add cpuvmfunc.
800
801 * i386-opc.tbl: Add vmfunc.
802 * i386-init.h: Regenerated.
803 * i386-tbl.h: Likewise.
5011093d 804
23e1d329 805For older changes see ChangeLog-2011
252b5132
RH		 806\f
807Local Variables:
2f6d2f85
NC		 808mode: change-log
809left-margin: 8
810fill-column: 74
252b5132
RH		 811version-control: never
812End:
GDB Binutils - Deliverables
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