Commit | Line | Data |
---|---|---|
32e31ad7 JB |
1 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
2 | ||
3 | * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0, | |
4 | REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0, | |
5 | MOD_VEX_0FXOP_09_12): Rename to ... | |
6 | (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0, | |
7 | REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these. | |
8 | (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT, | |
9 | RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26, | |
10 | X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, | |
11 | X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move. | |
12 | (reg_table): Adjust comments. | |
13 | (x86_64_table): Move X86_64_0F24, X86_64_0F26, | |
14 | X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, | |
15 | X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries. | |
16 | (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries. | |
17 | (vex_len_table): Adjust opcode 0A_12 entry. | |
18 | (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, | |
19 | MOD_C5_32BIT, and MOD_XOP_09_12 entries. | |
20 | (rm_table): Move hreset entry. | |
21 | ||
85ba7507 JB |
22 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
23 | ||
24 | * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1, | |
25 | EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6, | |
26 | EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15, | |
27 | EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20, | |
28 | EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete. | |
29 | (EVEX_LEN_0F3816, EVEX_W_0FD6): New. | |
30 | (get_valid_dis386): Also handle 512-bit vector length when | |
31 | vectoring into vex_len_table[]. | |
32 | * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5, | |
33 | 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 | |
34 | entries. | |
35 | * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6, | |
36 | 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries. | |
37 | * i386-dis-evex-prefix.h: Adjust 0F7E entry. | |
38 | * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21 | |
39 | entries. | |
40 | ||
066f82b9 JB |
41 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
42 | ||
43 | * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1): | |
44 | Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively. | |
45 | EVEX_W_0F3A00, EVEX_W_0F3A01): Delete. | |
46 | * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01 | |
47 | entries. | |
48 | * i386-dis-evex-len.h (evex_len_table): Likewise. | |
49 | * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries. | |
50 | ||
fc681dd6 JB |
51 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
52 | ||
53 | * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7, | |
54 | MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, | |
55 | MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, | |
56 | MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1, | |
57 | MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, | |
58 | MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, | |
59 | MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, | |
60 | MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6 | |
61 | EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1, | |
62 | EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0, | |
63 | EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0, | |
64 | EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0, | |
65 | EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0, | |
66 | EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0, | |
67 | EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0, | |
68 | EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1, | |
69 | EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1, | |
70 | EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1, | |
71 | EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1, | |
72 | EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0, | |
73 | EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1, | |
74 | EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0, | |
75 | EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1, | |
76 | EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0, | |
77 | EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1, | |
78 | EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819, | |
79 | EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B, | |
80 | EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0, | |
81 | EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0, | |
82 | EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B, | |
83 | EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A, | |
84 | EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete. | |
85 | REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0, | |
86 | REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A, | |
87 | MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B, | |
88 | MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819, | |
89 | EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0, | |
90 | EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0, | |
91 | EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0, | |
92 | EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A, | |
93 | EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38, | |
94 | EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B, | |
95 | EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n, | |
96 | EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n, | |
97 | EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2, | |
98 | EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2, | |
99 | EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n, | |
100 | EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2, | |
101 | EVEX_W_0F3A43_L_n): New. | |
102 | * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A, | |
103 | 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, | |
104 | 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries. | |
105 | * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[] | |
106 | for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7, | |
107 | 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A, | |
108 | 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6. | |
109 | * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A, | |
110 | 0F385B, 0F38C6, and 0F38C7 entries. | |
111 | * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes | |
112 | 0F38C6 and 0F38C7. | |
113 | * i386-dis-evex-w.h: No longer link to evex_len_table[] for | |
114 | opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, | |
115 | 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to | |
116 | evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B. | |
117 | ||
13954a31 JB |
118 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
119 | ||
120 | * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1, | |
121 | MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, | |
122 | MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, | |
123 | MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, | |
124 | MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, | |
125 | MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, | |
126 | MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, | |
127 | MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, | |
128 | MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, | |
129 | MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, | |
130 | MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, | |
131 | MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, | |
132 | MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
133 | MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
134 | MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
135 | MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
136 | MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, | |
137 | MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, | |
138 | MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, | |
139 | MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, | |
140 | MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0, | |
141 | MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, | |
142 | MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, | |
143 | MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, | |
144 | MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, | |
145 | PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, | |
146 | PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, | |
147 | PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, | |
148 | PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, | |
149 | PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0, | |
150 | VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2, | |
151 | VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0, | |
152 | VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2, | |
153 | VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, | |
154 | VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, | |
155 | VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0, | |
156 | VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2, | |
157 | VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2, | |
158 | VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2, | |
159 | VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1, | |
160 | VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, | |
161 | VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0, | |
162 | VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1, | |
163 | VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1, | |
164 | VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1, | |
165 | VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, | |
166 | VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, | |
167 | VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, | |
168 | VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, | |
169 | VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, | |
170 | VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0, | |
171 | VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0, | |
172 | VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, | |
173 | VEX_W_0F99_P_2_LEN_0): Delete. | |
174 | MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0, | |
175 | MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1, | |
176 | MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0, | |
177 | MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0, | |
178 | MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0, | |
179 | PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0, | |
180 | PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0, | |
181 | PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0, | |
182 | PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0, | |
183 | PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0, | |
184 | PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0, | |
185 | PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0, | |
186 | PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0, | |
187 | PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0, | |
188 | PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0, | |
189 | PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0, | |
190 | PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0, | |
191 | PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0, | |
192 | PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42, | |
193 | VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47, | |
194 | VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91, | |
195 | VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99, | |
196 | VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1, | |
197 | VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1, | |
198 | VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0, | |
199 | VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1, | |
200 | VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New. | |
201 | (prefix_table): No longer link to vex_len_table[] for opcodes | |
202 | 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, | |
203 | 0F92, 0F93, 0F98, and 0F99. | |
204 | (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42, | |
205 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
206 | 0F98, and 0F99. | |
207 | (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42, | |
208 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
209 | 0F98, and 0F99. | |
210 | (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42, | |
211 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
212 | 0F98, and 0F99. | |
213 | (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42, | |
214 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
215 | 0F98, and 0F99. | |
216 | ||
14d10c6c JB |
217 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
218 | ||
219 | * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73): | |
220 | Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and | |
221 | REG_VEX_0F73_M_0 respectively. | |
222 | (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6, | |
223 | MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6, | |
224 | MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6, | |
225 | MOD_VEX_0F73_REG_7): Delete. | |
226 | (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New. | |
227 | (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7, | |
228 | PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0, | |
229 | PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, | |
230 | PREFIX_VEX_0F3AF0_L_0 respectively. | |
231 | (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3, | |
232 | VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3, | |
233 | VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1, | |
234 | VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete. | |
235 | (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6, | |
236 | VEX_LEN_0F38F7): New. | |
237 | (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0. | |
238 | (reg_table): No longer link to mod_table[] for VEX opcodes 0F71, | |
239 | 0F72, and 0F73. No longer link to vex_len_table[] for opcode | |
240 | 0F38F3. | |
241 | (prefix_table): No longer link to vex_len_table[] for opcodes | |
242 | 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. | |
243 | (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and | |
244 | 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5, | |
245 | 0F38F6, 0F38F7, and 0F3AF0. | |
246 | (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to | |
247 | prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. | |
248 | (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and | |
249 | 0F73. | |
250 | ||
00ec1875 JB |
251 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
252 | ||
253 | * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to | |
254 | REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively. | |
255 | (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2, | |
256 | MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3, | |
257 | MOD_0F73_REG_6, MOD_0F73_REG_7): Delete. | |
258 | (MOD_0F71, MOD_0F72, MOD_0F73): New. | |
259 | (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and | |
260 | 73. | |
261 | (reg_table): No longer link to mod_table[] for opcodes 0F71, | |
262 | 0F72, and 0F73. | |
263 | (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and | |
264 | 0F73. | |
265 | ||
31941983 JB |
266 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
267 | ||
268 | * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5, | |
269 | MOD_0F18_REG_6, MOD_0F18_REG_7): Delete. | |
270 | (reg_table): Don't link to mod_table[] where not needed. Add | |
271 | PREFIX_IGNORED to nop entries. | |
272 | (prefix_table): Replace PREFIX_OPCODE in nop entries. | |
273 | (mod_table): Add nop entries next to prefetch ones. Drop | |
274 | MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and | |
275 | MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries. | |
276 | (rm_table): Add PREFIX_IGNORED to nop entries. Drop | |
277 | PREFIX_OPCODE from endbr* entries. | |
278 | (get_valid_dis386): Also consider entry's name when zapping | |
279 | vindex. | |
280 | (print_insn): Handle PREFIX_IGNORED. | |
281 | ||
742732c7 JB |
282 | 2021-03-09 Jan Beulich <jbeulich@suse.com> |
283 | ||
284 | * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk, | |
285 | IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk | |
286 | element. | |
287 | * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone, | |
288 | HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete. | |
289 | (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack, | |
290 | PrefixLock, PrefixHLELock, PrefixHLEAny): Define. | |
291 | (struct i386_opcode_modifier): Delete notrackprefixok, | |
292 | islockable, hleprefixok, and repprefixok fields. Add prefixok | |
293 | field. | |
294 | * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny, | |
295 | HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define. | |
296 | (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg, | |
297 | not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b): | |
298 | Replace HLEPrefixOk. | |
299 | * opcodes/i386-tbl.h: Re-generate. | |
300 | ||
e93a3b27 JB |
301 | 2021-03-09 Jan Beulich <jbeulich@suse.com> |
302 | ||
303 | * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit. | |
304 | * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from | |
305 | 64-bit form. | |
306 | * opcodes/i386-tbl.h: Re-generate. | |
307 | ||
75363b6d JB |
308 | 2021-03-03 Jan Beulich <jbeulich@suse.com> |
309 | ||
310 | * i386-gen.c (output_i386_opcode): Don't get operand count. Look | |
311 | for {} instead of {0}. Don't look for '0'. | |
312 | * i386-opc.tbl: Drop operand count field. Drop redundant operand | |
313 | size specifiers. | |
314 | ||
5a9f5403 NC |
315 | 2021-02-19 Nelson Chu <nelson.chu@sifive.com> |
316 | ||
317 | PR 27158 | |
318 | * riscv-dis.c (print_insn_args): Updated encoding macros. | |
319 | * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. | |
320 | (match_c_addi16sp): Updated encoding macros. | |
321 | (match_c_lui): Likewise. | |
322 | (match_c_lui_with_hint): Likewise. | |
323 | (match_c_addi4spn): Likewise. | |
324 | (match_c_slli): Likewise. | |
325 | (match_slli_as_c_slli): Likewise. | |
326 | (match_c_slli64): Likewise. | |
327 | (match_srxi_as_c_srxi): Likewise. | |
328 | (riscv_insn_types): Added .insn css/cl/cs. | |
329 | ||
3d73d29e NC |
330 | 2021-02-18 Nelson Chu <nelson.chu@sifive.com> |
331 | ||
332 | * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. | |
333 | (default_priv_spec): Updated type to riscv_spec_class. | |
334 | (parse_riscv_dis_option): Updated. | |
335 | * riscv-opc.c: Moved stuff and make the file tidy. | |
336 | ||
b9b204b3 AM |
337 | 2021-02-17 Alan Modra <amodra@gmail.com> |
338 | ||
339 | * wasm32-dis.c: Include limits.h. | |
340 | (CHAR_BIT): Provide backup define. | |
341 | (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. | |
342 | Correct signed overflow checking. | |
343 | ||
394ae71f JB |
344 | 2021-02-16 Jan Beulich <jbeulich@suse.com> |
345 | ||
346 | * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant. | |
347 | * i386-tbl.h: Re-generate. | |
348 | ||
b818b220 JB |
349 | 2021-02-16 Jan Beulich <jbeulich@suse.com> |
350 | ||
351 | * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor | |
352 | Oword. | |
353 | * i386-opc.tbl (CpuFP, Mmword, Oword): Define. | |
354 | ||
ba2b480f AK |
355 | 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com> |
356 | ||
357 | * s390-mkopc.c (main): Accept arch14 as cpu string. | |
358 | * s390-opc.txt: Add new arch14 instructions. | |
359 | ||
95148614 NA |
360 | 2021-02-04 Nick Alcock <nick.alcock@oracle.com> |
361 | ||
362 | * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in | |
363 | favour of LIBINTL. | |
364 | * configure: Regenerated. | |
365 | ||
bfd428bc MF |
366 | 2021-02-08 Mike Frysinger <vapier@gentoo.org> |
367 | ||
368 | * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs. | |
369 | * tic54x-opc.c (regs): Rename to ... | |
370 | (tic54x_regs): ... this. | |
371 | (mmregs): Rename to ... | |
372 | (tic54x_mmregs): ... this. | |
373 | (condition_codes): Rename to ... | |
374 | (tic54x_condition_codes): ... this. | |
375 | (cc2_codes): Rename to ... | |
376 | (tic54x_cc2_codes): ... this. | |
377 | (cc3_codes): Rename to ... | |
378 | (tic54x_cc3_codes): ... this. | |
379 | (status_bits): Rename to ... | |
380 | (tic54x_status_bits): ... this. | |
381 | (misc_symbols): Rename to ... | |
382 | (tic54x_misc_symbols): ... this. | |
383 | ||
24075dcc NC |
384 | 2021-02-04 Nelson Chu <nelson.chu@sifive.com> |
385 | ||
386 | * riscv-opc.c (MASK_RVB_IMM): Removed. | |
387 | (riscv_opcodes): Removed zb* instructions. | |
388 | (riscv_ext_version_table): Removed versions for zb*. | |
389 | ||
c3ffb8f3 AM |
390 | 2021-01-26 Alan Modra <amodra@gmail.com> |
391 | ||
392 | * i386-gen.c (parse_template): Ensure entire template_instance | |
393 | is initialised. | |
394 | ||
1942a048 NC |
395 | 2021-01-15 Nelson Chu <nelson.chu@sifive.com> |
396 | ||
397 | * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. | |
398 | (riscv_fpr_names_abi): Likewise. | |
399 | (riscv_opcodes): Likewise. | |
400 | (riscv_insn_types): Likewise. | |
401 | ||
b800637e NC |
402 | 2021-01-15 Nelson Chu <nelson.chu@sifive.com> |
403 | ||
404 | * riscv-dis.c (parse_riscv_dis_option): Fix typos of message. | |
405 | ||
dcd709e0 NC |
406 | 2021-01-15 Nelson Chu <nelson.chu@sifive.com> |
407 | ||
408 | * riscv-dis.c: Comments tidy and improvement. | |
409 | * riscv-opc.c: Likewise. | |
410 | ||
5347ed60 AM |
411 | 2021-01-13 Alan Modra <amodra@gmail.com> |
412 | ||
413 | * Makefile.in: Regenerate. | |
414 | ||
d546b610 L |
415 | 2021-01-12 H.J. Lu <hongjiu.lu@intel.com> |
416 | ||
417 | PR binutils/26792 | |
418 | * configure.ac: Use GNU_MAKE_JOBSERVER. | |
419 | * aclocal.m4: Regenerated. | |
420 | * configure: Likewise. | |
421 | ||
6d104cac NC |
422 | 2021-01-12 Nick Clifton <nickc@redhat.com> |
423 | ||
424 | * po/sr.po: Updated Serbian translation. | |
425 | ||
83b33c6c L |
426 | 2021-01-11 H.J. Lu <hongjiu.lu@intel.com> |
427 | ||
428 | PR ld/27173 | |
429 | * configure: Regenerated. | |
430 | ||
82c70b08 KT |
431 | 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
432 | ||
433 | * aarch64-asm-2.c: Regenerate. | |
434 | * aarch64-dis-2.c: Likewise. | |
435 | * aarch64-opc-2.c: Likewise. | |
436 | * aarch64-opc.c (aarch64_print_operand): | |
437 | Delete handling of AARCH64_OPND_CSRE_CSR. | |
438 | * aarch64-tbl.h (aarch64_feature_csre): Delete. | |
439 | (CSRE): Likewise. | |
440 | (_CSRE_INSN): Likewise. | |
441 | (aarch64_opcode_table): Delete csr. | |
442 | ||
a8aa72b9 NC |
443 | 2021-01-11 Nick Clifton <nickc@redhat.com> |
444 | ||
445 | * po/de.po: Updated German translation. | |
446 | * po/fr.po: Updated French translation. | |
447 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
448 | * po/sv.po: Updated Swedish translation. | |
449 | * po/uk.po: Updated Ukranian translation. | |
450 | ||
a4966cd9 L |
451 | 2021-01-09 H.J. Lu <hongjiu.lu@intel.com> |
452 | ||
453 | * configure: Regenerated. | |
454 | ||
573fe3fb NC |
455 | 2021-01-09 Nick Clifton <nickc@redhat.com> |
456 | ||
457 | * configure: Regenerate. | |
458 | * po/opcodes.pot: Regenerate. | |
459 | ||
055bc77a NC |
460 | 2021-01-09 Nick Clifton <nickc@redhat.com> |
461 | ||
462 | * 2.36 release branch crated. | |
463 | ||
aae7fcb8 PB |
464 | 2021-01-08 Peter Bergner <bergner@linux.ibm.com> |
465 | ||
466 | * ppc-opc.c (insert_dw, (extract_dw): New functions. | |
467 | (DW, (XRC_MASK): Define. | |
468 | (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. | |
469 | ||
64307045 AM |
470 | 2021-01-09 Alan Modra <amodra@gmail.com> |
471 | ||
472 | * configure: Regenerate. | |
473 | ||
ed205222 NC |
474 | 2021-01-08 Nick Clifton <nickc@redhat.com> |
475 | ||
476 | * po/sv.po: Updated Swedish translation. | |
477 | ||
fb932b57 NC |
478 | 2021-01-08 Nick Clifton <nickc@redhat.com> |
479 | ||
e84c8716 NC |
480 | PR 27129 |
481 | * aarch64-dis.c (determine_disassembling_preference): Move call to | |
482 | aarch64_match_operands_constraint outside of the assertion. | |
483 | * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. | |
484 | Replace with a return of FALSE. | |
485 | ||
fb932b57 NC |
486 | PR 27139 |
487 | * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a | |
488 | core system register. | |
489 | ||
f4782128 ST |
490 | 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org> |
491 | ||
492 | * configure: Regenerate. | |
493 | ||
1b0927db NC |
494 | 2021-01-07 Nick Clifton <nickc@redhat.com> |
495 | ||
496 | * po/fr.po: Updated French translation. | |
497 | ||
3b288c8e FN |
498 | 2021-01-07 Fredrik Noring <noring@nocrew.org> |
499 | ||
500 | * m68k-opc.c (chkl): Change minimum architecture requirement to | |
501 | m68020. | |
502 | ||
aa881ecd PT |
503 | 2021-01-07 Philipp Tomsich <prt@gnu.org> |
504 | ||
505 | * riscv-opc.c (riscv_opcodes): Add pause hint instruction. | |
506 | ||
2652cfad CXW |
507 | 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> |
508 | Jim Wilson <jimw@sifive.com> | |
509 | Andrew Waterman <andrew@sifive.com> | |
510 | Maxim Blinov <maxim.blinov@embecosm.com> | |
511 | Kito Cheng <kito.cheng@sifive.com> | |
512 | Nelson Chu <nelson.chu@sifive.com> | |
513 | ||
514 | * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. | |
515 | (MASK_RVB_IMM): Used for rev8 and orc.b encoding. | |
516 | ||
250d07de AM |
517 | 2021-01-01 Alan Modra <amodra@gmail.com> |
518 | ||
519 | Update year range in copyright notice of all files. | |
520 | ||
c2795844 | 521 | For older changes see ChangeLog-2020 |
3499769a | 522 | \f |
c2795844 | 523 | Copyright (C) 2021 Free Software Foundation, Inc. |
3499769a AM |
524 | |
525 | Copying and distribution of this file, with or without modification, | |
526 | are permitted in any medium without royalty provided the copyright | |
527 | notice and this notice are preserved. | |
528 | ||
529 | Local Variables: | |
530 | mode: change-log | |
531 | left-margin: 8 | |
532 | fill-column: 74 | |
533 | version-control: never | |
534 | End: |