Commit | Line | Data |
---|---|---|
344c74a6 RS |
1 | 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> |
2 | ||
3 | * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d | |
4 | for the single-operand forms of JALR and JALR.HB. | |
5 | * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB | |
6 | and JALRS.HB. | |
7 | ||
41989114 RS |
8 | 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> |
9 | ||
10 | * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector | |
11 | instructions. Fix them to use WR_MACC instead of WR_CC and | |
12 | add missing RD_MACCs. | |
13 | ||
6d075bce RS |
14 | 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com> |
15 | ||
16 | * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address. | |
17 | ||
4f6ffcd3 PB |
18 | 2013-07-29 Peter Bergner <bergner@vnet.ibm.com> |
19 | ||
20 | * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect. | |
21 | ||
43234a1e L |
22 | 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> |
23 | Alexander Ivchenko <alexander.ivchenko@intel.com> | |
24 | Maxim Kuznetsov <maxim.kuznetsov@intel.com> | |
25 | Sergey Lega <sergey.s.lega@intel.com> | |
26 | Anna Tikhonova <anna.tikhonova@intel.com> | |
27 | Ilya Tocar <ilya.tocar@intel.com> | |
28 | Andrey Turetskiy <andrey.turetskiy@intel.com> | |
29 | Ilya Verbin <ilya.verbin@intel.com> | |
30 | Kirill Yukhin <kirill.yukhin@intel.com> | |
31 | Michael Zolotukhin <michael.v.zolotukhin@intel.com> | |
32 | ||
33 | * i386-dis-evex.h: New. | |
34 | * i386-dis.c (OP_Rounding): New. | |
35 | (VPCMP_Fixup): New. | |
36 | (OP_Mask): New. | |
37 | (Rdq): New. | |
38 | (XMxmmq): New. | |
39 | (EXdScalarS): New. | |
40 | (EXymm): New. | |
41 | (EXEvexHalfBcstXmmq): New. | |
42 | (EXxmm_mdq): New. | |
43 | (EXEvexXGscat): New. | |
44 | (EXEvexXNoBcst): New. | |
45 | (VPCMP): New. | |
46 | (EXxEVexR): New. | |
47 | (EXxEVexS): New. | |
48 | (XMask): New. | |
49 | (MaskG): New. | |
50 | (MaskE): New. | |
51 | (MaskR): New. | |
52 | (MaskVex): New. | |
53 | (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, | |
54 | evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, | |
55 | evex_rounding_mode, evex_sae_mode, mask_mode. | |
56 | (USE_EVEX_TABLE): New. | |
57 | (EVEX_TABLE): New. | |
58 | (EVEX enum): New. | |
59 | (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, | |
60 | REG_EVEX_0F38C7. | |
61 | (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, | |
62 | MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, | |
63 | MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, | |
64 | MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, | |
65 | MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, | |
66 | MOD_EVEX_0F38C7_REG_6. | |
67 | (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, | |
68 | PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, | |
69 | PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, | |
70 | PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, | |
71 | PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, | |
72 | PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, | |
73 | PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, | |
74 | PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, | |
75 | PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, | |
76 | PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, | |
77 | PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, | |
78 | PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, | |
79 | PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, | |
80 | PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, | |
81 | PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, | |
82 | PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, | |
83 | PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, | |
84 | PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, | |
85 | PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, | |
86 | PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, | |
87 | PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, | |
88 | PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, | |
89 | PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, | |
90 | PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, | |
91 | PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, | |
92 | PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, | |
93 | PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, | |
94 | PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, | |
95 | PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, | |
96 | PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, | |
97 | PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, | |
98 | PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, | |
99 | PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, | |
100 | PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, | |
101 | PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, | |
102 | PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, | |
103 | PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, | |
104 | PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, | |
105 | PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, | |
106 | PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, | |
107 | PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, | |
108 | PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, | |
109 | PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, | |
110 | PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, | |
111 | PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, | |
112 | PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, | |
113 | PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, | |
114 | PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, | |
115 | PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, | |
116 | PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, | |
117 | PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, | |
118 | PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, | |
119 | PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, | |
120 | PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, | |
121 | PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, | |
122 | PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, | |
123 | PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, | |
124 | PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, | |
125 | PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, | |
126 | PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, | |
127 | PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, | |
128 | PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, | |
129 | PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, | |
130 | PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, | |
131 | PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, | |
132 | PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, | |
133 | PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, | |
134 | PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, | |
135 | PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, | |
136 | PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, | |
137 | PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, | |
138 | PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, | |
139 | PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, | |
140 | PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, | |
141 | PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, | |
142 | PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, | |
143 | PREFIX_EVEX_0F3A55. | |
144 | (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, | |
145 | VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, | |
146 | VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, | |
147 | VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, | |
148 | VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, | |
149 | VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, | |
150 | VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, | |
151 | VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, | |
152 | VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, | |
153 | VEX_W_0F3A32_P_2_LEN_0. | |
154 | (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, | |
155 | EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, | |
156 | EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, | |
157 | EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, | |
158 | EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, | |
159 | EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, | |
160 | EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, | |
161 | EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, | |
162 | EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, | |
163 | EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, | |
164 | EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, | |
165 | EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, | |
166 | EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, | |
167 | EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, | |
168 | EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, | |
169 | EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, | |
170 | EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, | |
171 | EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, | |
172 | EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, | |
173 | EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, | |
174 | EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, | |
175 | EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, | |
176 | EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, | |
177 | EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, | |
178 | EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, | |
179 | EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, | |
180 | EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, | |
181 | EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, | |
182 | EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, | |
183 | EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, | |
184 | EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, | |
185 | EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, | |
186 | EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, | |
187 | EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, | |
188 | EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, | |
189 | EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, | |
190 | EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, | |
191 | EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, | |
192 | EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, | |
193 | EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, | |
194 | EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, | |
195 | EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, | |
196 | EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, | |
197 | EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, | |
198 | EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, | |
199 | EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, | |
200 | EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, | |
201 | EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, | |
202 | EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, | |
203 | EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, | |
204 | EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, | |
205 | EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, | |
206 | EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, | |
207 | EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. | |
208 | (struct vex): Add fields evex, r, v, mask_register_specifier, | |
209 | zeroing, ll, b. | |
210 | (intel_names_xmm): Add upper 16 registers. | |
211 | (att_names_xmm): Ditto. | |
212 | (intel_names_ymm): Ditto. | |
213 | (att_names_ymm): Ditto. | |
214 | (names_zmm): New. | |
215 | (intel_names_zmm): Ditto. | |
216 | (att_names_zmm): Ditto. | |
217 | (names_mask): Ditto. | |
218 | (intel_names_mask): Ditto. | |
219 | (att_names_mask): Ditto. | |
220 | (names_rounding): Ditto. | |
221 | (names_broadcast): Ditto. | |
222 | (x86_64_table): Add escape to evex-table. | |
223 | (reg_table): Include reg_table evex-entries from | |
224 | i386-dis-evex.h. Fix prefetchwt1 instruction. | |
225 | (prefix_table): Add entries for new instructions. | |
226 | (vex_table): Ditto. | |
227 | (vex_len_table): Ditto. | |
228 | (vex_w_table): Ditto. | |
229 | (mod_table): Ditto. | |
230 | (get_valid_dis386): Properly handle new instructions. | |
231 | (print_insn): Handle zmm and mask registers, print mask operand. | |
232 | (intel_operand_size): Support EVEX, new modes and sizes. | |
233 | (OP_E_register): Handle new modes. | |
234 | (OP_E_memory): Ditto. | |
235 | (OP_G): Ditto. | |
236 | (OP_XMM): Ditto. | |
237 | (OP_EX): Ditto. | |
238 | (OP_VEX): Ditto. | |
239 | * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and | |
240 | CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, | |
241 | CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. | |
242 | (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, | |
243 | CpuAVX512PF and CpuVREX. | |
244 | (operand_type_init): Add OPERAND_TYPE_REGZMM, | |
245 | OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. | |
246 | (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, | |
247 | StaticRounding, SAE, Disp8MemShift, NoDefMask. | |
248 | (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. | |
249 | * i386-init.h: Regenerate. | |
250 | * i386-opc.h (CpuAVX512F): New. | |
251 | (CpuAVX512CD): New. | |
252 | (CpuAVX512ER): New. | |
253 | (CpuAVX512PF): New. | |
254 | (CpuVREX): New. | |
255 | (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, | |
256 | cpuavx512pf and cpuvrex fields. | |
257 | (VecSIB): Add VecSIB512. | |
258 | (EVex): New. | |
259 | (Masking): New. | |
260 | (VecESize): New. | |
261 | (Broadcast): New. | |
262 | (StaticRounding): New. | |
263 | (SAE): New. | |
264 | (Disp8MemShift): New. | |
265 | (NoDefMask): New. | |
266 | (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, | |
267 | staticrounding, sae, disp8memshift and nodefmask. | |
268 | (RegZMM): New. | |
269 | (Zmmword): Ditto. | |
270 | (Vec_Disp8): Ditto. | |
271 | (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 | |
272 | fields. | |
273 | (RegVRex): New. | |
274 | * i386-opc.tbl: Add AVX512 instructions. | |
275 | * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM | |
276 | registers, mask registers. | |
277 | * i386-tbl.h: Regenerate. | |
278 | ||
1d2db237 RS |
279 | 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi> |
280 | ||
281 | PR gas/15220 | |
282 | * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for | |
283 | Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps. | |
284 | ||
a0046408 L |
285 | 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> |
286 | ||
287 | * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9, | |
288 | PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD, | |
289 | PREFIX_0F3ACC. | |
290 | (prefix_table): Updated. | |
291 | (three_byte_table): Likewise. | |
292 | * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS. | |
293 | (cpu_flags): Add CpuSHA. | |
294 | (i386_cpu_flags): Add cpusha. | |
295 | * i386-init.h: Regenerate. | |
296 | * i386-opc.h (CpuSHA): New. | |
297 | (CpuUnused): Restored. | |
298 | (i386_cpu_flags): Add cpusha. | |
299 | * i386-opc.tbl: Add SHA instructions. | |
300 | * i386-tbl.h: Regenerate. | |
301 | ||
7e8b059b L |
302 | 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> |
303 | Kirill Yukhin <kirill.yukhin@intel.com> | |
304 | Michael Zolotukhin <michael.v.zolotukhin@intel.com> | |
305 | ||
306 | * i386-dis.c (BND_Fixup): New. | |
307 | (Ebnd): New. | |
308 | (Ev_bnd): New. | |
309 | (Gbnd): New. | |
310 | (BND): New. | |
311 | (v_bnd_mode): New. | |
312 | (bnd_mode): New. | |
c623f86c L |
313 | (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0, |
314 | MOD_0F1B_PREFIX_1. | |
315 | (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B. | |
7e8b059b L |
316 | (dis tables): Replace XX with BND for near branch and call |
317 | instructions. | |
318 | (prefix_table): Add new entries. | |
319 | (mod_table): Likewise. | |
320 | (names_bnd): New. | |
321 | (intel_names_bnd): New. | |
322 | (att_names_bnd): New. | |
323 | (BND_PREFIX): New. | |
324 | (prefix_name): Handle BND_PREFIX. | |
325 | (print_insn): Initialize names_bnd. | |
326 | (intel_operand_size): Handle new modes. | |
327 | (OP_E_register): Likewise. | |
328 | (OP_E_memory): Likewise. | |
329 | (OP_G): Likewise. | |
330 | * i386-gen.c (cpu_flag_init): Add CpuMPX. | |
331 | (cpu_flags): Add CpuMPX. | |
332 | (operand_type_init): Add RegBND. | |
333 | (opcode_modifiers): Add BNDPrefixOk. | |
334 | (operand_types): Add RegBND. | |
335 | * i386-init.h: Regenerate. | |
336 | * i386-opc.h (CpuMPX): New. | |
337 | (CpuUnused): Comment out. | |
338 | (i386_cpu_flags): Add cpumpx. | |
339 | (BNDPrefixOk): New. | |
340 | (i386_opcode_modifier): Add bndprefixok. | |
341 | (RegBND): New. | |
342 | (i386_operand_type): Add regbnd. | |
343 | * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets. | |
344 | Add MPX instructions and bnd prefix. | |
345 | * i386-reg.tbl: Add bnd0-bnd3 registers. | |
346 | * i386-tbl.h: Regenerate. | |
347 | ||
b56e23fb RS |
348 | 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com> |
349 | ||
350 | * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add | |
351 | ATTRIBUTE_UNUSED. | |
352 | ||
e7ae278d RS |
353 | 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> |
354 | ||
355 | * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove | |
356 | special rules. | |
357 | * Makefile.in: Regenerate. | |
358 | * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize | |
359 | all fields. Reformat. | |
360 | ||
c3c07478 RS |
361 | 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> |
362 | ||
363 | * mips16-opc.c: Include mips-formats.h. | |
364 | (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New | |
365 | static arrays. | |
366 | (decode_mips16_operand): New function. | |
367 | * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete. | |
368 | (print_insn_arg): Handle OP_ENTRY_EXIT list. | |
369 | Abort for OP_SAVE_RESTORE_LIST. | |
370 | (print_mips16_insn_arg): Change interface. Use mips_operand | |
371 | structures. Delete GET_OP_S. Move GET_OP definition to... | |
372 | (print_insn_mips16): ...here. Call init_print_arg_state. | |
373 | Update the call to print_mips16_insn_arg. | |
374 | ||
ab902481 RS |
375 | 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> |
376 | ||
377 | * mips-formats.h: New file. | |
378 | * mips-opc.c: Include mips-formats.h. | |
379 | (reg_0_map): New static array. | |
380 | (decode_mips_operand): New function. | |
381 | * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h. | |
382 | (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map) | |
383 | (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map) | |
384 | (int_c_map): New static arrays. | |
385 | (decode_micromips_operand): New function. | |
386 | * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) | |
387 | (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map) | |
388 | (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map) | |
389 | (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2) | |
390 | (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map) | |
391 | (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map) | |
392 | (micromips_imm_b_map, micromips_imm_c_map): Delete. | |
393 | (print_reg): New function. | |
394 | (mips_print_arg_state): New structure. | |
395 | (init_print_arg_state, print_insn_arg): New functions. | |
396 | (print_insn_args): Change interface and use mips_operand structures. | |
397 | Delete GET_OP_S. Move GET_OP definition to... | |
398 | (print_insn_mips): ...here. Update the call to print_insn_args. | |
399 | (print_insn_micromips): Use print_insn_args. | |
400 | ||
cc537e56 RS |
401 | 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> |
402 | ||
403 | * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands | |
404 | in macros. | |
405 | ||
7a5f87ce RS |
406 | 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com> |
407 | ||
408 | * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for | |
409 | ADDA.S, MULA.S and SUBA.S. | |
410 | ||
41741fa4 L |
411 | 2013-07-08 H.J. Lu <hongjiu.lu@intel.com> |
412 | ||
413 | PR gas/13572 | |
414 | * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi. | |
415 | * i386-tbl.h: Regenerated. | |
416 | ||
f2ae14a1 RS |
417 | 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> |
418 | ||
419 | * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD | |
420 | and SD A(B) macros up. | |
421 | * micromips-opc.c (micromips_opcodes): Likewise. | |
422 | ||
04c9d415 RS |
423 | 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> |
424 | ||
425 | * mips16-opc.c: Add entries for argumentless "entry" and "exit" | |
426 | instructions. | |
427 | ||
5c324c16 RS |
428 | 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> |
429 | ||
430 | * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400 | |
431 | MDMX-like instructions. | |
432 | * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when | |
433 | printing "Q" operands for INSN_5400 instructions. | |
434 | ||
23e69e47 RS |
435 | 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> |
436 | ||
437 | * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and | |
438 | "+S" for "cins". | |
439 | * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments. | |
440 | Combine cases. | |
441 | ||
27c5c572 RS |
442 | 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> |
443 | ||
444 | * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for | |
445 | "jalx". | |
446 | * mips16-opc.c (mips16_opcodes): Likewise. | |
447 | * micromips-opc.c (micromips_opcodes): Likewise. | |
448 | * mips-dis.c (print_insn_args, print_mips16_insn_arg) | |
449 | (print_insn_mips16): Handle "+i". | |
450 | (print_insn_micromips): Likewise. Conditionally preserve the | |
451 | ISA bit for "a" but not for "+i". | |
452 | ||
e76ff5ab RS |
453 | 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> |
454 | ||
455 | * micromips-opc.c (WR_mhi): Rename to.. | |
456 | (WR_mh): ...this. | |
457 | (micromips_opcodes): Update "movep" entry accordingly. Replace | |
458 | "mh,mi" with "mh". | |
459 | * mips-dis.c (micromips_to_32_reg_h_map): Rename to... | |
460 | (micromips_to_32_reg_h_map1): ...this. | |
461 | (micromips_to_32_reg_i_map): Rename to... | |
462 | (micromips_to_32_reg_h_map2): ...this. | |
463 | (print_micromips_insn): Remove "mi" case. Print both registers | |
464 | in the pair for "mh". | |
465 | ||
fa7616a4 RS |
466 | 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> |
467 | ||
468 | * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. | |
469 | * micromips-opc.c (micromips_opcodes): Likewise. | |
470 | * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" | |
471 | and "+T" handling. Check for a "0" suffix when deciding whether to | |
472 | use coprocessor 0 names. In that case, also check for ",H" selectors. | |
473 | ||
fb798c50 AK |
474 | 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
475 | ||
476 | * s390-opc.c (J12_12, J24_24): New macros. | |
477 | (INSTR_MII_UPI): Rename to INSTR_MII_UPP. | |
478 | (MASK_MII_UPI): Rename to MASK_MII_UPP. | |
479 | * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction. | |
480 | ||
58ae08f2 AM |
481 | 2013-07-04 Alan Modra <amodra@gmail.com> |
482 | ||
483 | * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu. | |
484 | ||
b5e04c2b NC |
485 | 2013-06-26 Nick Clifton <nickc@redhat.com> |
486 | ||
487 | * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss | |
488 | field when checking for type 2 nop. | |
489 | * rx-decode.c: Regenerate. | |
490 | ||
833794fc MR |
491 | 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com> |
492 | ||
493 | * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc" | |
494 | and "movep" macros. | |
495 | ||
1bbce132 MR |
496 | 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com> |
497 | ||
498 | * mips-dis.c (is_mips16_plt_tail): New function. | |
499 | (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address | |
500 | word. | |
501 | (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries. | |
502 | ||
34c911a4 NC |
503 | 2013-06-21 DJ Delorie <dj@redhat.com> |
504 | ||
505 | * msp430-decode.opc: New. | |
506 | * msp430-decode.c: New/generated. | |
507 | * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c. | |
508 | (MAINTAINER_CLEANFILES): Likewise. | |
509 | Add rule to build msp430-decode.c frommsp430decode.opc | |
510 | using the opc2c program. | |
511 | * Makefile.in: Regenerate. | |
512 | * configure.in: Add msp430-decode.lo to msp430 architecture files. | |
513 | * configure: Regenerate. | |
514 | ||
b9eead84 YZ |
515 | 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com> |
516 | ||
517 | * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it. | |
518 | (SYMTAB_AVAILABLE): Removed. | |
519 | (#include "elf/aarch64.h): Ditto. | |
520 | ||
7f3c4072 CM |
521 | 2013-06-17 Catherine Moore <clm@codesourcery.com> |
522 | Maciej W. Rozycki <macro@codesourcery.com> | |
523 | Chao-Ying Fu <fu@mips.com> | |
524 | ||
525 | * micromips-opc.c (EVA): Define. | |
526 | (TLBINV): Define. | |
527 | (micromips_opcodes): Add EVA opcodes. | |
528 | * mips-dis.c (mips_arch_choices): Update for ASE_EVA. | |
529 | (print_insn_args): Handle EVA offsets. | |
530 | (print_insn_micromips): Likewise. | |
531 | * mips-opc.c (EVA): Define. | |
532 | (TLBINV): Define. | |
533 | (mips_builtin_opcodes): Add EVA opcodes. | |
534 | ||
de40ceb6 AM |
535 | 2013-06-17 Alan Modra <amodra@gmail.com> |
536 | ||
537 | * Makefile.am (mips-opc.lo): Add rules to create automatic | |
538 | dependency files. Pass archdefs. | |
539 | (micromips-opc.lo, mips16-opc.lo): Likewise. | |
540 | * Makefile.in: Regenerate. | |
541 | ||
3531d549 DD |
542 | 2013-06-14 DJ Delorie <dj@redhat.com> |
543 | ||
544 | * rx-decode.opc (rx_decode_opcode): Bit operations on | |
545 | registers are 32-bit operations, not 8-bit operations. | |
546 | * rx-decode.c: Regenerate. | |
547 | ||
ba92f7fb CF |
548 | 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com> |
549 | ||
550 | * micromips-opc.c (IVIRT): New define. | |
551 | (IVIRT64): New define. | |
552 | (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, | |
553 | tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions. | |
554 | ||
555 | * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0, | |
556 | dmtgc0 to print cp0 names. | |
557 | ||
9daf7bab SL |
558 | 2013-06-09 Sandra Loosemore <sandra@codesourcery.com> |
559 | ||
560 | * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b" | |
561 | argument. | |
562 | ||
d301a56b RS |
563 | 2013-06-08 Catherine Moore <clm@codesourcery.com> |
564 | Richard Sandiford <rdsandiford@googlemail.com> | |
565 | ||
566 | * micromips-opc.c (D32, D33, MC): Update definitions. | |
567 | (micromips_opcodes): Initialize ase field. | |
568 | * mips-dis.c (mips_arch_choice): Add ase field. | |
569 | (mips_arch_choices): Initialize ase field. | |
570 | (set_default_mips_dis_options): Declare and setup mips_ase. | |
571 | * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, | |
572 | MT32, MC): Update definitions. | |
573 | (mips_builtin_opcodes): Initialize ase field. | |
574 | ||
a3dcb6c5 RS |
575 | 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com> |
576 | ||
577 | * s390-opc.txt (flogr): Require a register pair destination. | |
578 | ||
6cf1d90c AK |
579 | 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
580 | ||
581 | * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU | |
582 | instruction format. | |
583 | ||
c77c0862 RS |
584 | 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> |
585 | ||
586 | * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions. | |
587 | ||
c0637f3a PB |
588 | 2013-05-20 Peter Bergner <bergner@vnet.ibm.com> |
589 | ||
590 | * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8. | |
591 | * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK, | |
592 | XLS_MASK, PPCVSX2): New defines. | |
593 | (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb, | |
594 | fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe, | |
595 | mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp, | |
596 | mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd, | |
597 | mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx, | |
598 | vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher, | |
599 | vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd., | |
600 | vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd, | |
601 | vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw, | |
602 | vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor, | |
603 | vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh, | |
604 | vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox, | |
605 | vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, | |
606 | vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp, | |
607 | xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp, | |
608 | xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp, | |
609 | xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp, | |
610 | xssubsp, xxleqv, xxlnand, xxlorc>: New instructions. | |
611 | <lxvx, stxvx>: New extended mnemonics. | |
612 | ||
4934fdaf AM |
613 | 2013-05-17 Alan Modra <amodra@gmail.com> |
614 | ||
615 | * ia64-raw.tbl: Replace non-ASCII char. | |
616 | * ia64-waw.tbl: Likewise. | |
617 | * ia64-asmtab.c: Regenerate. | |
618 | ||
6091d651 SE |
619 | 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com> |
620 | ||
621 | * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS. | |
622 | * i386-init.h: Regenerated. | |
623 | ||
d2865ed3 YZ |
624 | 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com> |
625 | ||
626 | * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion. | |
627 | * aarch64-opc.c (operand_general_constraint_met_p): Relax the range | |
628 | check from [0, 255] to [-128, 255]. | |
629 | ||
b015e599 AP |
630 | 2013-05-09 Andrew Pinski <apinski@cavium.com> |
631 | ||
632 | * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2. | |
633 | Add INSN_VIRT and INSN_VIRT64 to mips64r2. | |
634 | (parse_mips_dis_option): Handle the virt option. | |
635 | (print_insn_args): Handle "+J". | |
636 | (print_mips_disassembler_options): Print out message about virt64. | |
637 | * mips-opc.c (IVIRT): New define. | |
638 | (IVIRT64): New define. | |
639 | (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, | |
640 | tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions. | |
641 | Move rfe to the bottom as it conflicts with tlbgp. | |
642 | ||
9f0682fe AM |
643 | 2013-05-09 Alan Modra <amodra@gmail.com> |
644 | ||
645 | * ppc-opc.c (extract_vlesi): Properly sign extend. | |
646 | (extract_vlensi): Likewise. Comment reason for setting invalid. | |
647 | ||
13761a11 NC |
648 | 2013-05-02 Nick Clifton <nickc@redhat.com> |
649 | ||
650 | * msp430-dis.c: Add support for MSP430X instructions. | |
651 | ||
e3031850 SL |
652 | 2013-04-24 Sandra Loosemore <sandra@codesourcery.com> |
653 | ||
654 | * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register | |
655 | to "eccinj". | |
656 | ||
17310e56 NC |
657 | 2013-04-17 Wei-chen Wang <cole945@gmail.com> |
658 | ||
659 | PR binutils/15369 | |
660 | * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead | |
661 | of CGEN_CPU_ENDIAN. | |
662 | (hash_insns_list): Likewise. | |
663 | ||
731df338 JK |
664 | 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com> |
665 | ||
666 | * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false | |
667 | warning workaround. | |
668 | ||
5f77db52 JB |
669 | 2013-04-08 Jan Beulich <jbeulich@suse.com> |
670 | ||
671 | * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries. | |
672 | * i386-tbl.h: Re-generate. | |
673 | ||
0afd1215 DM |
674 | 2013-04-06 David S. Miller <davem@davemloft.net> |
675 | ||
676 | * sparc-dis.c (compare_opcodes): When encountering multiple aliases | |
677 | of an opcode, prefer the one with F_PREFERRED set. | |
678 | * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa, | |
679 | lzcnt, flush with '[address]' syntax, and missing cbcond pseudo | |
680 | ops. Make 64-bit VIS logical ops have "d" suffix in their names, | |
681 | mark existing mnenomics as aliases. Add "cc" suffix to edge | |
682 | instructions generating condition codes, mark existing mnenomics | |
683 | as aliases. Add "fp" prefix to VIS compare instructions, mark | |
684 | existing mnenomics as aliases. | |
685 | ||
41702d50 NC |
686 | 2013-04-03 Nick Clifton <nickc@redhat.com> |
687 | ||
688 | * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the | |
689 | destination address by subtracting the operand from the current | |
690 | address. | |
691 | * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store | |
692 | a positive value in the insn. | |
693 | (extract_u16_loop): Do not negate the returned value. | |
694 | (D16_LOOP): Add V850_INVERSE_PCREL flag. | |
695 | ||
696 | (ceilf.sw): Remove duplicate entry. | |
697 | (cvtf.hs): New entry. | |
698 | (cvtf.sh): Likewise. | |
699 | (fmaf.s): Likewise. | |
700 | (fmsf.s): Likewise. | |
701 | (fnmaf.s): Likewise. | |
702 | (fnmsf.s): Likewise. | |
703 | (maddf.s): Restrict to E3V5 architectures. | |
704 | (msubf.s): Likewise. | |
705 | (nmaddf.s): Likewise. | |
706 | (nmsubf.s): Likewise. | |
707 | ||
55cf16e1 L |
708 | 2013-03-27 H.J. Lu <hongjiu.lu@intel.com> |
709 | ||
710 | * i386-dis.c (get_sib): Add the sizeflag argument. Properly | |
711 | check address mode. | |
712 | (print_insn): Pass sizeflag to get_sib. | |
713 | ||
51dcdd4d NC |
714 | 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> |
715 | ||
716 | PR binutils/15068 | |
717 | * tic6x-dis.c: Add support for displaying 16-bit insns. | |
718 | ||
795b8e6b NC |
719 | 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> |
720 | ||
721 | PR gas/15095 | |
722 | * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have | |
723 | individual msb and lsb halves in src1 & src2 fields. Discard the | |
724 | src1 (lsb) value and only use src2 (msb), discarding bit 0, to | |
725 | follow what Ti SDK does in that case as any value in the src1 | |
726 | field yields the same output with SDK disassembler. | |
727 | ||
314d60dd ME |
728 | 2013-03-12 Michael Eager <eager@eagercon.com> |
729 | ||
795b8e6b | 730 | * opcodes/mips-dis.c (print_insn_args): Modify def of reg. |
314d60dd | 731 | |
dad60f8e SL |
732 | 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> |
733 | ||
734 | * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs. | |
735 | ||
f5cb796a SL |
736 | 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> |
737 | ||
738 | * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs. | |
739 | ||
21fde85c SL |
740 | 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> |
741 | ||
742 | * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register. | |
743 | ||
dd5181d5 KT |
744 | 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
745 | ||
746 | * arm-dis.c (arm_opcodes): Add entries for CRC instructions. | |
747 | (thumb32_opcodes): Likewise. | |
748 | (print_insn_thumb32): Handle 'S' control char. | |
749 | ||
87a8d6cb NC |
750 | 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com> |
751 | ||
752 | * lm32-desc.c: Regenerate. | |
753 | ||
99dce992 L |
754 | 2013-03-01 H.J. Lu <hongjiu.lu@intel.com> |
755 | ||
756 | * i386-reg.tbl (riz): Add RegRex64. | |
757 | * i386-tbl.h: Regenerated. | |
758 | ||
e60bb1dd YZ |
759 | 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> |
760 | ||
761 | * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros. | |
762 | (aarch64_feature_crc): New static. | |
763 | (CRC): New macro. | |
764 | (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w, | |
765 | crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions. | |
766 | * aarch64-asm-2.c: Re-generate. | |
767 | * aarch64-dis-2.c: Ditto. | |
768 | * aarch64-opc-2.c: Ditto. | |
769 | ||
c7570fcd AM |
770 | 2013-02-27 Alan Modra <amodra@gmail.com> |
771 | ||
772 | * rl78-decode.opc (rl78_decode_opcode): Fix typo. | |
773 | * rl78-decode.c: Regenerate. | |
774 | ||
151fa98f NC |
775 | 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com> |
776 | ||
777 | * rl78-decode.opc: Fix encoding of DIVWU insn. | |
778 | * rl78-decode.c: Regenerate. | |
779 | ||
5c111e37 L |
780 | 2013-02-19 H.J. Lu <hongjiu.lu@intel.com> |
781 | ||
782 | PR gas/15159 | |
783 | * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1. | |
784 | ||
785 | * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS. | |
786 | (cpu_flags): Add CpuSMAP. | |
787 | ||
788 | * i386-opc.h (CpuSMAP): New. | |
789 | (i386_cpu_flags): Add cpusmap. | |
790 | ||
791 | * i386-opc.tbl: Add clac and stac. | |
792 | ||
793 | * i386-init.h: Regenerated. | |
794 | * i386-tbl.h: Likewise. | |
795 | ||
9d1df426 NC |
796 | 2013-02-15 Markos Chandras <markos.chandras@imgtec.com> |
797 | ||
798 | * metag-dis.c: Initialize outf->bytes_per_chunk to 4 | |
799 | which also makes the disassembler output be in little | |
800 | endian like it should be. | |
801 | ||
a1ccaec9 YZ |
802 | 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com> |
803 | ||
804 | * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name' | |
805 | fields to NULL. | |
806 | (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP. | |
807 | ||
ef068ef4 | 808 | 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com> |
5417f71e MR |
809 | |
810 | * mips-dis.c (is_compressed_mode_p): Only match symbols from the | |
811 | section disassembled. | |
812 | ||
6fe6ded9 RE |
813 | 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
814 | ||
815 | * arm-dis.c: Update strht pattern. | |
816 | ||
0aa27725 RS |
817 | 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de> |
818 | ||
819 | * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for | |
820 | single-float. Disable ll, lld, sc and scd for EE. Disable the | |
821 | trunc.w.s macro for EE. | |
822 | ||
36591ba1 SL |
823 | 2013-02-06 Sandra Loosemore <sandra@codesourcery.com> |
824 | Andrew Jenner <andrew@codesourcery.com> | |
825 | ||
826 | Based on patches from Altera Corporation. | |
827 | ||
828 | * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and | |
829 | nios2-opc.c. | |
830 | * Makefile.in: Regenerated. | |
831 | * configure.in: Add case for bfd_nios2_arch. | |
832 | * configure: Regenerated. | |
833 | * disassemble.c (ARCH_nios2): Define. | |
834 | (disassembler): Add case for bfd_arch_nios2. | |
835 | * nios2-dis.c: New file. | |
836 | * nios2-opc.c: New file. | |
837 | ||
545093a4 AM |
838 | 2013-02-04 Alan Modra <amodra@gmail.com> |
839 | ||
840 | * po/POTFILES.in: Regenerate. | |
841 | * rl78-decode.c: Regenerate. | |
842 | * rx-decode.c: Regenerate. | |
843 | ||
e30181a5 YZ |
844 | 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> |
845 | ||
846 | * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and | |
847 | ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2. | |
848 | * aarch64-asm.c (convert_xtl_to_shll): New function. | |
849 | (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by | |
850 | calling convert_xtl_to_shll. | |
851 | * aarch64-dis.c (convert_shll_to_xtl): New function. | |
852 | (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by | |
853 | calling convert_shll_to_xtl. | |
854 | * aarch64-gen.c: Update copyright year. | |
855 | * aarch64-asm-2.c: Re-generate. | |
856 | * aarch64-dis-2.c: Re-generate. | |
857 | * aarch64-opc-2.c: Re-generate. | |
858 | ||
78c8d46c NC |
859 | 2013-01-24 Nick Clifton <nickc@redhat.com> |
860 | ||
861 | * v850-dis.c: Add support for e3v5 architecture. | |
862 | * v850-opc.c: Likewise. | |
863 | ||
f5555712 YZ |
864 | 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> |
865 | ||
866 | * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. | |
867 | * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. | |
868 | * aarch64-opc.c (operand_general_constraint_met_p): For | |
78c8d46c | 869 | AARCH64_MOD_LSL, move the range check on the shift amount before the |
f5555712 YZ |
870 | alignment check; change to call set_sft_amount_out_of_range_error |
871 | instead of set_imm_out_of_range_error. | |
872 | * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. | |
873 | (aarch64_opcode_table): Remove the OP enumerator from the asimdimm | |
874 | 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to | |
875 | SIMD_IMM_SFT. | |
876 | ||
2f81ff92 L |
877 | 2013-01-16 H.J. Lu <hongjiu.lu@intel.com> |
878 | ||
879 | * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64. | |
880 | ||
881 | * i386-init.h: Regenerated. | |
882 | * i386-tbl.h: Likewise. | |
883 | ||
dd42f060 NC |
884 | 2013-01-15 Nick Clifton <nickc@redhat.com> |
885 | ||
886 | * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE | |
887 | values. | |
888 | * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute. | |
889 | ||
a4533ed8 NC |
890 | 2013-01-14 Will Newton <will.newton@imgtec.com> |
891 | ||
892 | * metag-dis.c (REG_WIDTH): Increase to 64. | |
893 | ||
5817ffd1 PB |
894 | 2013-01-10 Peter Bergner <bergner@vnet.ibm.com> |
895 | ||
896 | * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries. | |
897 | * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK, | |
898 | XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines. | |
899 | (SH6): Update. | |
900 | <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.", | |
901 | "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.", | |
902 | "treclaim.", "tsr.">: Add POWER8 HTM opcodes. | |
903 | <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes. | |
904 | ||
a3c62988 NC |
905 | 2013-01-10 Will Newton <will.newton@imgtec.com> |
906 | ||
907 | * Makefile.am: Add Meta. | |
908 | * configure.in: Add Meta. | |
909 | * disassemble.c: Add Meta support. | |
910 | * metag-dis.c: New file. | |
911 | * Makefile.in: Regenerate. | |
912 | * configure: Regenerate. | |
913 | ||
73335eae NC |
914 | 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
915 | ||
916 | * cr16-dis.c (make_instruction): Rename to cr16_make_instruction. | |
917 | (match_opcode): Rename to cr16_match_opcode. | |
918 | ||
e407c74b NC |
919 | 2013-01-04 Juergen Urban <JuergenUrban@gmx.de> |
920 | ||
921 | * mips-dis.c: Add names for CP0 registers of r5900. | |
922 | * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for | |
923 | instructions sq and lq. | |
924 | Add support for MIPS r5900 CPU. | |
925 | Add support for 128 bit MMI (Multimedia Instructions). | |
926 | Add support for EE instructions (Emotion Engine). | |
927 | Disable unsupported floating point instructions (64 bit and | |
928 | undefined compare operations). | |
929 | Enable instructions of MIPS ISA IV which are supported by r5900. | |
930 | Disable 64 bit co processor instructions. | |
931 | Disable 64 bit multiplication and division instructions. | |
932 | Disable instructions for co-processor 2 and 3, because these are | |
933 | not supported (preparation for later VU0 support (Vector Unit)). | |
934 | Disable cvt.w.s because this behaves like trunc.w.s and the | |
935 | correct execution can't be ensured on r5900. | |
936 | Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This | |
937 | will confuse less developers and compilers. | |
938 | ||
a32c3ff8 NC |
939 | 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> |
940 | ||
fb098a1e YZ |
941 | * aarch64-opc.c (aarch64_print_operand): Change to print |
942 | AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal | |
943 | in comment. | |
944 | * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag | |
945 | from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and | |
946 | OP_MOV_IMM_WIDE. | |
947 | ||
948 | 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> | |
949 | ||
950 | * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, | |
951 | PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. | |
a32c3ff8 | 952 | |
62658407 L |
953 | 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> |
954 | ||
955 | * i386-gen.c (process_copyright): Update copyright year to 2013. | |
956 | ||
bab4becb | 957 | 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
5bf135a7 | 958 | |
bab4becb NC |
959 | * cr16-dis.c (match_opcode,make_instruction): Remove static |
960 | declaration. | |
961 | (dwordU,wordU): Moved typedefs to opcode/cr16.h | |
962 | (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'. | |
5bf135a7 | 963 | |
bab4becb | 964 | For older changes see ChangeLog-2012 |
252b5132 | 965 | \f |
bab4becb | 966 | Copyright (C) 2013 Free Software Foundation, Inc. |
752937aa NC |
967 | |
968 | Copying and distribution of this file, with or without modification, | |
969 | are permitted in any medium without royalty provided the copyright | |
970 | notice and this notice are preserved. | |
971 | ||
252b5132 | 972 | Local Variables: |
2f6d2f85 NC |
973 | mode: change-log |
974 | left-margin: 8 | |
975 | fill-column: 74 | |
252b5132 RH |
976 | version-control: never |
977 | End: |