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854eb72b
NC		 12015-11-02 Nick Clifton <nickc@redhat.com>
2
3 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
4 instructions.
5 * rx-decode.c: Regenerate.
6
e292aa7a
NC		 72015-11-02 Nick Clifton <nickc@redhat.com>
8
9 * rx-decode.opc (rx_disp): If the displacement is zero, set the
10 type to RX_Operand_Zero_Indirect.
11 * rx-decode.c: Regenerate.
12 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
13
43cdf5ae
YQ		 142015-10-28 Yao Qi <yao.qi@linaro.org>
15
16 * aarch64-dis.c (aarch64_decode_insn): Add one argument
17 noaliases_p. Update comments. Pass noaliases_p rather than
18 no_aliases to aarch64_opcode_decode.
19 (print_insn_aarch64_word): Pass no_aliases to
20 aarch64_decode_insn.
21
c2f28758
VK		 222015-10-27 Vinay <Vinay.G@kpit.com>
23
24 PR binutils/19159
25 * rl78-decode.opc (MOV): Added offset to DE register in index
26 addressing mode.
27 * rl78-decode.c: Regenerate.
28
46662804
VK		 292015-10-27 Vinay Kumar <vinay.g@kpit.com>
30
31 PR binutils/19158
32 * rl78-decode.opc: Add 's' print operator to instructions that
33 access system registers.
34 * rl78-decode.c: Regenerate.
35 * rl78-dis.c (print_insn_rl78_common): Decode all system
36 registers.
37
02f12cd4
VK		 382015-10-27 Vinay Kumar <vinay.g@kpit.com>
39
40 PR binutils/19157
41 * rl78-decode.opc: Add 'a' print operator to mov instructions
42 using stack pointer plus index addressing.
43 * rl78-decode.c: Regenerate.
44
485f23cf
AK		 452015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
46
47 * s390-opc.c: Fix comment.
48 * s390-opc.txt: Change instruction type for troo, trot, trto, and
49 trtt to RRF_U0RER since the second parameter does not need to be a
50 register pair.
51
3f94e60d
NC		 522015-10-08 Nick Clifton <nickc@redhat.com>
53
54 * arc-dis.c (print_insn_arc): Initiallise insn array.
55
875880c6
YQ		 562015-10-07 Yao Qi <yao.qi@linaro.org>
57
58 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
59 'name' rather than 'template'.
60 * aarch64-opc.c (aarch64_print_operand): Likewise.
61
886a2506
NC		 622015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
63
64 * arc-dis.c: Revamped file for ARC support
65 * arc-dis.h: Likewise.
66 * arc-ext.c: Likewise.
67 * arc-ext.h: Likewise.
68 * arc-opc.c: Likewise.
69 * arc-fxi.h: New file.
70 * arc-regs.h: Likewise.
71 * arc-tbl.h: Likewise.
72
36f4aab1
YQ		 732015-10-02 Yao Qi <yao.qi@linaro.org>
74
75 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
76 argument insn type to aarch64_insn. Rename to ...
77 (aarch64_decode_insn): ... it.
78 (print_insn_aarch64_word): Caller updated.
79
7232d389
YQ		 802015-10-02 Yao Qi <yao.qi@linaro.org>
81
82 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
83 (print_insn_aarch64_word): Caller updated.
84
7ecc513a
DV		 852015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
86
87 * s390-mkopc.c (main): Parse htm and vx flag.
88 * s390-opc.txt: Mark instructions from the hardware transactional
89 memory and vector facilities with the "htm"/"vx" flag.
90
b08b78e7
NC		 912015-09-28 Nick Clifton <nickc@redhat.com>
92
93 * po/de.po: Updated German translation.
94
36f7a941
TR		 952015-09-28 Tom Rix <tom@bumblecow.com>
96
97 * ppc-opc.c (PPC500): Mark some opcodes as invalid
98
b6518b38
NC		 992015-09-23 Nick Clifton <nickc@redhat.com>
100
101 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
102 function.
103 * tic30-dis.c (print_branch): Likewise.
104 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
105 value before left shifting.
106 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
107 * hppa-dis.c (print_insn_hppa): Likewise.
108 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
109 array.
110 * msp430-dis.c (msp430_singleoperand): Likewise.
111 (msp430_doubleoperand): Likewise.
112 (print_insn_msp430): Likewise.
113 * nds32-asm.c (parse_operand): Likewise.
114 * sh-opc.h (MASK): Likewise.
115 * v850-dis.c (get_operand_value): Likewise.
116
f04265ec
NC		 1172015-09-22 Nick Clifton <nickc@redhat.com>
118
119 * rx-decode.opc (bwl): Use RX_Bad_Size.
120 (sbwl): Likewise.
121 (ubwl): Likewise. Rename to ubw.
122 (uBWL): Rename to uBW.
123 Replace all references to uBWL with uBW.
124 * rx-decode.c: Regenerate.
125 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
126 (opsize_names): Likewise.
127 (print_insn_rx): Detect and report RX_Bad_Size.
128
6dca4fd1
AB		 1292015-09-22 Anton Blanchard <anton@samba.org>
130
131 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
132
38074311
JM		 1332015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
134
135 * sparc-dis.c (print_insn_sparc): Handle the privileged register
136 %pmcdper.
137
5f40e14d
JS		 1382015-08-24 Jan Stancek <jstancek@redhat.com>
139
140 * i386-dis.c (print_insn): Fix decoding of three byte operands.
141
ab4e4ed5
AF		 1422015-08-21 Alexander Fomin <alexander.fomin@intel.com>
143
144 PR binutils/18257
145 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
146 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
147 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
148 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
149 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
150 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
151 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
152 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
153 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
154 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
155 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
156 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
157 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
158 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
159 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
160 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
161 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
162 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
163 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
164 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
165 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
166 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
167 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
168 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
169 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
170 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
171 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
172 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
173 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
174 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
175 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
176 (vex_w_table): Replace terminals with MOD_TABLE entries for
177 most of mask instructions.
178
919b75f7
AM		 1792015-08-17 Alan Modra <amodra@gmail.com>
180
181 * cgen.sh: Trim trailing space from cgen output.
182 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
183 (print_dis_table): Likewise.
184 * opc2c.c (dump_lines): Likewise.
185 (orig_filename): Warning fix.
186 * ia64-asmtab.c: Regenerate.
187
4ab90a7a
AV		 1882015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
189
190 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
191 and higher with ARM instruction set will now mark the 26-bit
192 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
193 (arm_opcodes): Fix for unpredictable nop being recognized as a
194 teq.
195
40fc1451
SD		 1962015-08-12 Simon Dardis <simon.dardis@imgtec.com>
197
198 * micromips-opc.c (micromips_opcodes): Re-order table so that move
199 based on 'or' is first.
200 * mips-opc.c (mips_builtin_opcodes): Ditto.
201
922c5db5
NC		 2022015-08-11 Nick Clifton <nickc@redhat.com>
203
204 PR 18800
205 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
206 instruction.
207
75fb7498
RS		 2082015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
209
210 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
211
36aed29d
AP		 2122015-08-07 Amit Pawar <Amit.Pawar@amd.com>
213
214 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
215 * i386-init.h: Regenerated.
216
a8484f96
L		 2172015-07-30 H.J. Lu <hongjiu.lu@intel.com>
218
219 PR binutils/13571
220 * i386-dis.c (MOD_0FC3): New.
221 (PREFIX_0FC3): Renamed to ...
222 (PREFIX_MOD_0_0FC3): This.
223 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
224 (prefix_table): Replace Ma with Ev on movntiS.
225 (mod_table): Add MOD_0FC3.
226
37a42ee9
L		 2272015-07-27 H.J. Lu <hongjiu.lu@intel.com>
228
229 * configure: Regenerated.
230
070fe95d
AM		 2312015-07-23 Alan Modra <amodra@gmail.com>
232
233 PR 18708
234 * i386-dis.c (get64): Avoid signed integer overflow.
235
20c2a615
L		 2362015-07-22 Alexander Fomin <alexander.fomin@intel.com>
237
238 PR binutils/18631
239 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
240 "EXEvexHalfBcstXmmq" for the second operand.
241 (EVEX_W_0F79_P_2): Likewise.
242 (EVEX_W_0F7A_P_2): Likewise.
243 (EVEX_W_0F7B_P_2): Likewise.
244
6f1c2142
AM		 2452015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
246
247 * arm-dis.c (print_insn_coprocessor): Added support for quarter
248 float bitfield format.
249 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
250 quarter float bitfield format.
251
8a643cc3
L		 2522015-07-14 H.J. Lu <hongjiu.lu@intel.com>
253
254 * configure: Regenerated.
255
ef5a96d5
AM		 2562015-07-03 Alan Modra <amodra@gmail.com>
257
258 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
259 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
260 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
261
c8c8175b
SL		 2622015-07-01 Sandra Loosemore <sandra@codesourcery.com>
263 Cesar Philippidis <cesar@codesourcery.com>
264
265 * nios2-dis.c (nios2_extract_opcode): New.
266 (nios2_disassembler_state): New.
267 (nios2_find_opcode_hash): Use mach parameter to select correct
268 disassembler state.
269 (nios2_print_insn_arg): Extend to support new R2 argument letters
270 and formats.
271 (print_insn_nios2): Check for 16-bit instruction at end of memory.
272 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
273 (NIOS2_NUM_OPCODES): Rename to...
274 (NIOS2_NUM_R1_OPCODES): This.
275 (nios2_r2_opcodes): New.
276 (NIOS2_NUM_R2_OPCODES): New.
277 (nios2_num_r2_opcodes): New.
278 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
279 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
280 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
281 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
282 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
283
9916071f
AP		 2842015-06-30 Amit Pawar <Amit.Pawar@amd.com>
285
286 * i386-dis.c (OP_Mwaitx): New.
287 (rm_table): Add monitorx/mwaitx.
288 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
289 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
290 (operand_type_init): Add CpuMWAITX.
291 * i386-opc.h (CpuMWAITX): New.
292 (i386_cpu_flags): Add cpumwaitx.
293 * i386-opc.tbl: Add monitorx and mwaitx.
294 * i386-init.h: Regenerated.
295 * i386-tbl.h: Likewise.
296
7b934113
PB		 2972015-06-22 Peter Bergner <bergner@vnet.ibm.com>
298
299 * ppc-opc.c (insert_ls): Test for invalid LS operands.
300 (insert_esync): New function.
301 (LS, WC): Use insert_ls.
302 (ESYNC): Use insert_esync.
303
bdc4de1b
NC		 3042015-06-22 Nick Clifton <nickc@redhat.com>
305
306 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
307 requested region lies beyond it.
308 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
309 looking for 32-bit insns.
310 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
311 data.
312 * sh-dis.c (print_insn_sh): Likewise.
313 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
314 blocks of instructions.
315 * vax-dis.c (print_insn_vax): Check that the requested address
316 does not clash with the stop_vma.
317
11a0cf2e
PB		 3182015-06-19 Peter Bergner <bergner@vnet.ibm.com>
319
070fe95d 320 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 321 * ppc-opc.c (FXM4): Add non-zero optional value.
322 (TBR): Likewise.
323 (SXL): Likewise.
324 (insert_fxm): Handle new default operand value.
325 (extract_fxm): Likewise.
326 (insert_tbr): Likewise.
327 (extract_tbr): Likewise.
328
bdfa8b95
MW		 3292015-06-16 Matthew Wahab <matthew.wahab@arm.com>
330
331 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
332
24b4cf66
SN		 3332015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
334
335 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
336
99a2c561
PB		 3372015-06-12 Peter Bergner <bergner@vnet.ibm.com>
338
339 * ppc-opc.c: Add comment accidentally removed by old commit.
340 (MTMSRD_L): Delete.
341
40f77f82
AM		 3422015-06-04 Peter Bergner <bergner@vnet.ibm.com>
343
344 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
345
13be46a2
NC		 3462015-06-04 Nick Clifton <nickc@redhat.com>
347
348 PR 18474
349 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
350
ddfded2f
MW		 3512015-06-02 Matthew Wahab <matthew.wahab@arm.com>
352
353 * arm-dis.c (arm_opcodes): Add "setpan".
354 (thumb_opcodes): Add "setpan".
355
1af1dd51
MW		 3562015-06-02 Matthew Wahab <matthew.wahab@arm.com>
357
358 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
359 macros.
360
9e1f0fa7
MW		 3612015-06-02 Matthew Wahab <matthew.wahab@arm.com>
362
363 * aarch64-tbl.h (aarch64_feature_rdma): New.
364 (RDMA): New.
365 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
366 * aarch64-asm-2.c: Regenerate.
367 * aarch64-dis-2.c: Regenerate.
368 * aarch64-opc-2.c: Regenerate.
369
290806fd
MW		 3702015-06-02 Matthew Wahab <matthew.wahab@arm.com>
371
372 * aarch64-tbl.h (aarch64_feature_lor): New.
373 (LOR): New.
374 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
375 "stllrb", "stllrh".
376 * aarch64-asm-2.c: Regenerate.
377 * aarch64-dis-2.c: Regenerate.
378 * aarch64-opc-2.c: Regenerate.
379
f21cce2c
MW		 3802015-06-01 Matthew Wahab <matthew.wahab@arm.com>
381
382 * aarch64-opc.c (F_ARCHEXT): New.
383 (aarch64_sys_regs): Add "pan".
384 (aarch64_sys_reg_supported_p): New.
385 (aarch64_pstatefields): Add "pan".
386 (aarch64_pstatefield_supported_p): New.
387
d194d186
JB		 3882015-06-01 Jan Beulich <jbeulich@suse.com>
389
390 * i386-tbl.h: Regenerate.
391
3a8547d2
JB		 3922015-06-01 Jan Beulich <jbeulich@suse.com>
393
394 * i386-dis.c (print_insn): Swap rounding mode specifier and
395 general purpose register in Intel mode.
396
015c54d5
JB		 3972015-06-01 Jan Beulich <jbeulich@suse.com>
398
399 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
400 * i386-tbl.h: Regenerate.
401
071f0063
L		 4022015-05-18 H.J. Lu <hongjiu.lu@intel.com>
403
404 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
405 * i386-init.h: Regenerated.
406
5db04b09
L		 4072015-05-15 H.J. Lu <hongjiu.lu@intel.com>
408
409 PR binutis/18386
410 * i386-dis.c: Add comments for '@'.
411 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
412 (enum x86_64_isa): New.
413 (isa64): Likewise.
414 (print_i386_disassembler_options): Add amd64 and intel64.
415 (print_insn): Handle amd64 and intel64.
416 (putop): Handle '@'.
417 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
418 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
419 * i386-opc.h (AMD64): New.
420 (CpuIntel64): Likewise.
421 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
422 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
423 Mark direct call/jmp without Disp16|Disp32 as Intel64.
424 * i386-init.h: Regenerated.
425 * i386-tbl.h: Likewise.
426
4bc0608a
PB		 4272015-05-14 Peter Bergner <bergner@vnet.ibm.com>
428
429 * ppc-opc.c (IH) New define.
430 (powerpc_opcodes) <wait>: Do not enable for POWER7.
431 <tlbie>: Add RS operand for POWER7.
432 <slbia>: Add IH operand for POWER6.
433
70cead07
L		 4342015-05-11 H.J. Lu <hongjiu.lu@intel.com>
435
436 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
437 direct branch.
438 (jmp): Likewise.
439 * i386-tbl.h: Regenerated.
440
7b6d09fb
L		 4412015-05-11 H.J. Lu <hongjiu.lu@intel.com>
442
443 * configure.ac: Support bfd_iamcu_arch.
444 * disassemble.c (disassembler): Support bfd_iamcu_arch.
445 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
446 CPU_IAMCU_COMPAT_FLAGS.
447 (cpu_flags): Add CpuIAMCU.
448 * i386-opc.h (CpuIAMCU): New.
449 (i386_cpu_flags): Add cpuiamcu.
450 * configure: Regenerated.
451 * i386-init.h: Likewise.
452 * i386-tbl.h: Likewise.
453
31955f99
L		 4542015-05-08 H.J. Lu <hongjiu.lu@intel.com>
455
456 PR binutis/18386
457 * i386-dis.c (X86_64_E8): New.
458 (X86_64_E9): Likewise.
459 Update comments on 'T', 'U', 'V'. Add comments for '^'.
460 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
461 (x86_64_table): Add X86_64_E8 and X86_64_E9.
462 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
463 (putop): Handle '^'.
464 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
465 REX_W.
466
0952813b
DD		 4672015-04-30 DJ Delorie <dj@redhat.com>
468
469 * disassemble.c (disassembler): Choose suitable disassembler based
470 on E_ABI.
471 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
472 it to decode mul/div insns.
473 * rl78-decode.c: Regenerate.
474 * rl78-dis.c (print_insn_rl78): Rename to...
475 (print_insn_rl78_common): ...this, take ISA parameter.
476 (print_insn_rl78): New.
477 (print_insn_rl78_g10): New.
478 (print_insn_rl78_g13): New.
479 (print_insn_rl78_g14): New.
480 (rl78_get_disassembler): New.
481
f9d3ecaa
NC		 4822015-04-29 Nick Clifton <nickc@redhat.com>
483
484 * po/fr.po: Updated French translation.
485
4fff86c5
PB		 4862015-04-27 Peter Bergner <bergner@vnet.ibm.com>
487
488 * ppc-opc.c (DCBT_EO): New define.
489 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
490 <lharx>: Likewise.
491 <stbcx.>: Likewise.
492 <sthcx.>: Likewise.
493 <waitrsv>: Do not enable for POWER7 and later.
494 <waitimpl>: Likewise.
495 <dcbt>: Default to the two operand form of the instruction for all
496 "old" cpus. For "new" cpus, use the operand ordering that matches
497 whether the cpu is server or embedded.
498 <dcbtst>: Likewise.
499
3b78cfe1
AK		 5002015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
501
502 * s390-opc.c: New instruction type VV0UU2.
503 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
504 and WFC.
505
04d824a4
JB		 5062015-04-23 Jan Beulich <jbeulich@suse.com>
507
508 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
509 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
510 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
511 (vfpclasspd, vfpclassps): Add %XZ.
512
09708981
L		 5132015-04-15 H.J. Lu <hongjiu.lu@intel.com>
514
515 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
516 (PREFIX_UD_REPZ): Likewise.
517 (PREFIX_UD_REPNZ): Likewise.
518 (PREFIX_UD_DATA): Likewise.
519 (PREFIX_UD_ADDR): Likewise.
520 (PREFIX_UD_LOCK): Likewise.
521
3888916d
L		 5222015-04-15 H.J. Lu <hongjiu.lu@intel.com>
523
524 * i386-dis.c (prefix_requirement): Removed.
525 (print_insn): Don't set prefix_requirement. Check
526 dp->prefix_requirement instead of prefix_requirement.
527
f24bcbaa
L		 5282015-04-15 H.J. Lu <hongjiu.lu@intel.com>
529
530 PR binutils/17898
531 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
532 (PREFIX_MOD_0_0FC7_REG_6): This.
533 (PREFIX_MOD_3_0FC7_REG_6): New.
534 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
535 (prefix_table): Replace PREFIX_0FC7_REG_6 with
536 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
537 PREFIX_MOD_3_0FC7_REG_7.
538 (mod_table): Replace PREFIX_0FC7_REG_6 with
539 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
540 PREFIX_MOD_3_0FC7_REG_7.
541
507bd325
L		 5422015-04-15 H.J. Lu <hongjiu.lu@intel.com>
543
544 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
545 (PREFIX_MANDATORY_REPNZ): Likewise.
546 (PREFIX_MANDATORY_DATA): Likewise.
547 (PREFIX_MANDATORY_ADDR): Likewise.
548 (PREFIX_MANDATORY_LOCK): Likewise.
549 (PREFIX_MANDATORY): Likewise.
550 (PREFIX_UD_SHIFT): Set to 8
551 (PREFIX_UD_REPZ): Updated.
552 (PREFIX_UD_REPNZ): Likewise.
553 (PREFIX_UD_DATA): Likewise.
554 (PREFIX_UD_ADDR): Likewise.
555 (PREFIX_UD_LOCK): Likewise.
556 (PREFIX_IGNORED_SHIFT): New.
557 (PREFIX_IGNORED_REPZ): Likewise.
558 (PREFIX_IGNORED_REPNZ): Likewise.
559 (PREFIX_IGNORED_DATA): Likewise.
560 (PREFIX_IGNORED_ADDR): Likewise.
561 (PREFIX_IGNORED_LOCK): Likewise.
562 (PREFIX_OPCODE): Likewise.
563 (PREFIX_IGNORED): Likewise.
564 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
565 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
566 (three_byte_table): Likewise.
567 (mod_table): Likewise.
568 (mandatory_prefix): Renamed to ...
569 (prefix_requirement): This.
570 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
571 Update PREFIX_90 entry.
572 (get_valid_dis386): Check prefix_requirement to see if a prefix
573 should be ignored.
574 (print_insn): Replace mandatory_prefix with prefix_requirement.
575
f0fba320
RL		 5762015-04-15 Renlin Li <renlin.li@arm.com>
577
578 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
579 use it for ssat and ssat16.
580 (print_insn_thumb32): Add handle case for 'D' control code.
581
bf890a93
IT		 5822015-04-06 Ilya Tocar <ilya.tocar@intel.com>
583 H.J. Lu <hongjiu.lu@intel.com>
584
585 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
586 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
587 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
588 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
589 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
590 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
591 Fill prefix_requirement field.
592 (struct dis386): Add prefix_requirement field.
593 (dis386): Fill prefix_requirement field.
594 (dis386_twobyte): Ditto.
595 (twobyte_has_mandatory_prefix_: Remove.
596 (reg_table): Fill prefix_requirement field.
597 (prefix_table): Ditto.
598 (x86_64_table): Ditto.
599 (three_byte_table): Ditto.
600 (xop_table): Ditto.
601 (vex_table): Ditto.
602 (vex_len_table): Ditto.
603 (vex_w_table): Ditto.
604 (mod_table): Ditto.
605 (bad_opcode): Ditto.
606 (print_insn): Use prefix_requirement.
607 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
608 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
609 (float_reg): Ditto.
610
2f783c1f
MF		 6112015-03-30 Mike Frysinger <vapier@gentoo.org>
612
613 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
614
b9d94d62
L		 6152015-03-29 H.J. Lu <hongjiu.lu@intel.com>
616
617 * Makefile.in: Regenerated.
618
27c49e9a
AB		 6192015-03-25 Anton Blanchard <anton@samba.org>
620
621 * ppc-dis.c (disassemble_init_powerpc): Only initialise
622 powerpc_opcd_indices and vle_opcd_indices once.
623
c4e676f1
AB		 6242015-03-25 Anton Blanchard <anton@samba.org>
625
626 * ppc-opc.c (powerpc_opcodes): Add slbfee.
627
823d2571
TG		 6282015-03-24 Terry Guo <terry.guo@arm.com>
629
630 * arm-dis.c (opcode32): Updated to use new arm feature struct.
631 (opcode16): Likewise.
632 (coprocessor_opcodes): Replace bit with feature struct.
633 (neon_opcodes): Likewise.
634 (arm_opcodes): Likewise.
635 (thumb_opcodes): Likewise.
636 (thumb32_opcodes): Likewise.
637 (print_insn_coprocessor): Likewise.
638 (print_insn_arm): Likewise.
639 (select_arm_features): Follow new feature struct.
640
029f3522
GG		 6412015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
642
643 * i386-dis.c (rm_table): Add clzero.
644 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
645 Add CPU_CLZERO_FLAGS.
646 (cpu_flags): Add CpuCLZERO.
647 * i386-opc.h: Add CpuCLZERO.
648 * i386-opc.tbl: Add clzero.
649 * i386-init.h: Re-generated.
650 * i386-tbl.h: Re-generated.
651
6914869a
AB		 6522015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
653
654 * mips-opc.c (decode_mips_operand): Fix constraint issues
655 with u and y operands.
656
21e20815
AB		 6572015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
658
659 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
660
6b1d7593
AK		 6612015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
662
663 * s390-opc.c: Add new IBM z13 instructions.
664 * s390-opc.txt: Likewise.
665
c8f89a34
JW		 6662015-03-10 Renlin Li <renlin.li@arm.com>
667
668 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
669 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
670 related alias.
671 * aarch64-asm-2.c: Regenerate.
672 * aarch64-dis-2.c: Likewise.
673 * aarch64-opc-2.c: Likewise.
674
d8282f0e
JW		 6752015-03-03 Jiong Wang <jiong.wang@arm.com>
676
677 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
678
ac994365
OE		 6792015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
680
681 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
682 arch_sh_up.
683 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
684 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
685
fd63f640
V		 6862015-02-23 Vinay <Vinay.G@kpit.com>
687
688 * rl78-decode.opc (MOV): Added space between two operands for
689 'mov' instruction in index addressing mode.
690 * rl78-decode.c: Regenerate.
691
f63c1776
PA		 6922015-02-19 Pedro Alves <palves@redhat.com>
693
694 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
695
07774fcc
PA		 6962015-02-10 Pedro Alves <palves@redhat.com>
697 Tom Tromey <tromey@redhat.com>
698
699 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
700 microblaze_and, microblaze_xor.
701 * microblaze-opc.h (opcodes): Adjust.
702
3f8107ab
AM		 7032015-01-28 James Bowman <james.bowman@ftdichip.com>
704
705 * Makefile.am: Add FT32 files.
706 * configure.ac: Handle FT32.
707 * disassemble.c (disassembler): Call print_insn_ft32.
708 * ft32-dis.c: New file.
709 * ft32-opc.c: New file.
710 * Makefile.in: Regenerate.
711 * configure: Regenerate.
712 * po/POTFILES.in: Regenerate.
713
e5fe4957
KLC		 7142015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
715
716 * nds32-asm.c (keyword_sr): Add new system registers.
717
1e2e8c52
AK		 7182015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
719
720 * s390-dis.c (s390_extract_operand): Support vector register
721 operands.
722 (s390_print_insn_with_opcode): Support new operands types and add
723 new handling of optional operands.
724 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
725 and include opcode/s390.h instead.
726 (struct op_struct): New field `flags'.
727 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
728 (dumpTable): Dump flags.
729 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
730 string.
731 * s390-opc.c: Add new operands types, instruction formats, and
732 instruction masks.
733 (s390_opformats): Add new formats for .insn.
734 * s390-opc.txt: Add new instructions.
735
b90efa5b 7362015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 737
b90efa5b 738 Update year range in copyright notice of all files.
bffb6004 739
b90efa5b 740For older changes see ChangeLog-2014
252b5132 741\f
b90efa5b 742Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 743
744Copying and distribution of this file, with or without modification,
745are permitted in any medium without royalty provided the copyright
746notice and this notice are preserved.
747
252b5132 748Local Variables:
2f6d2f85
NC		 749mode: change-log
750left-margin: 8
751fill-column: 74
252b5132
RH		 752version-control: never
753End:
GDB Binutils - Deliverables
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