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[aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
36f4aab1
YQ		 12015-10-02 Yao Qi <yao.qi@linaro.org>
2
3 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
4 argument insn type to aarch64_insn. Rename to ...
5 (aarch64_decode_insn): ... it.
6 (print_insn_aarch64_word): Caller updated.
7
7232d389
YQ		 82015-10-02 Yao Qi <yao.qi@linaro.org>
9
10 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
11 (print_insn_aarch64_word): Caller updated.
12
7ecc513a
DV		 132015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
14
15 * s390-mkopc.c (main): Parse htm and vx flag.
16 * s390-opc.txt: Mark instructions from the hardware transactional
17 memory and vector facilities with the "htm"/"vx" flag.
18
b08b78e7
NC		 192015-09-28 Nick Clifton <nickc@redhat.com>
20
21 * po/de.po: Updated German translation.
22
36f7a941
TR		 232015-09-28 Tom Rix <tom@bumblecow.com>
24
25 * ppc-opc.c (PPC500): Mark some opcodes as invalid
26
b6518b38
NC		 272015-09-23 Nick Clifton <nickc@redhat.com>
28
29 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
30 function.
31 * tic30-dis.c (print_branch): Likewise.
32 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
33 value before left shifting.
34 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
35 * hppa-dis.c (print_insn_hppa): Likewise.
36 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
37 array.
38 * msp430-dis.c (msp430_singleoperand): Likewise.
39 (msp430_doubleoperand): Likewise.
40 (print_insn_msp430): Likewise.
41 * nds32-asm.c (parse_operand): Likewise.
42 * sh-opc.h (MASK): Likewise.
43 * v850-dis.c (get_operand_value): Likewise.
44
f04265ec
NC		 452015-09-22 Nick Clifton <nickc@redhat.com>
46
47 * rx-decode.opc (bwl): Use RX_Bad_Size.
48 (sbwl): Likewise.
49 (ubwl): Likewise. Rename to ubw.
50 (uBWL): Rename to uBW.
51 Replace all references to uBWL with uBW.
52 * rx-decode.c: Regenerate.
53 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
54 (opsize_names): Likewise.
55 (print_insn_rx): Detect and report RX_Bad_Size.
56
6dca4fd1
AB		 572015-09-22 Anton Blanchard <anton@samba.org>
58
59 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
60
38074311
JM		 612015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
62
63 * sparc-dis.c (print_insn_sparc): Handle the privileged register
64 %pmcdper.
65
5f40e14d
JS		 662015-08-24 Jan Stancek <jstancek@redhat.com>
67
68 * i386-dis.c (print_insn): Fix decoding of three byte operands.
69
ab4e4ed5
AF		 702015-08-21 Alexander Fomin <alexander.fomin@intel.com>
71
72 PR binutils/18257
73 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
74 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
75 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
76 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
77 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
78 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
79 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
80 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
81 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
82 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
83 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
84 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
85 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
86 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
87 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
88 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
89 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
90 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
91 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
92 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
93 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
94 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
95 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
96 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
97 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
98 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
99 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
100 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
101 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
102 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
103 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
104 (vex_w_table): Replace terminals with MOD_TABLE entries for
105 most of mask instructions.
106
919b75f7
AM		 1072015-08-17 Alan Modra <amodra@gmail.com>
108
109 * cgen.sh: Trim trailing space from cgen output.
110 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
111 (print_dis_table): Likewise.
112 * opc2c.c (dump_lines): Likewise.
113 (orig_filename): Warning fix.
114 * ia64-asmtab.c: Regenerate.
115
4ab90a7a
AV		 1162015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
117
118 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
119 and higher with ARM instruction set will now mark the 26-bit
120 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
121 (arm_opcodes): Fix for unpredictable nop being recognized as a
122 teq.
123
40fc1451
SD		 1242015-08-12 Simon Dardis <simon.dardis@imgtec.com>
125
126 * micromips-opc.c (micromips_opcodes): Re-order table so that move
127 based on 'or' is first.
128 * mips-opc.c (mips_builtin_opcodes): Ditto.
129
922c5db5
NC		 1302015-08-11 Nick Clifton <nickc@redhat.com>
131
132 PR 18800
133 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
134 instruction.
135
75fb7498
RS		 1362015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
137
138 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
139
36aed29d
AP		 1402015-08-07 Amit Pawar <Amit.Pawar@amd.com>
141
142 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
143 * i386-init.h: Regenerated.
144
a8484f96
L		 1452015-07-30 H.J. Lu <hongjiu.lu@intel.com>
146
147 PR binutils/13571
148 * i386-dis.c (MOD_0FC3): New.
149 (PREFIX_0FC3): Renamed to ...
150 (PREFIX_MOD_0_0FC3): This.
151 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
152 (prefix_table): Replace Ma with Ev on movntiS.
153 (mod_table): Add MOD_0FC3.
154
37a42ee9
L		 1552015-07-27 H.J. Lu <hongjiu.lu@intel.com>
156
157 * configure: Regenerated.
158
070fe95d
AM		 1592015-07-23 Alan Modra <amodra@gmail.com>
160
161 PR 18708
162 * i386-dis.c (get64): Avoid signed integer overflow.
163
20c2a615
L		 1642015-07-22 Alexander Fomin <alexander.fomin@intel.com>
165
166 PR binutils/18631
167 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
168 "EXEvexHalfBcstXmmq" for the second operand.
169 (EVEX_W_0F79_P_2): Likewise.
170 (EVEX_W_0F7A_P_2): Likewise.
171 (EVEX_W_0F7B_P_2): Likewise.
172
6f1c2142
AM		 1732015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
174
175 * arm-dis.c (print_insn_coprocessor): Added support for quarter
176 float bitfield format.
177 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
178 quarter float bitfield format.
179
8a643cc3
L		 1802015-07-14 H.J. Lu <hongjiu.lu@intel.com>
181
182 * configure: Regenerated.
183
ef5a96d5
AM		 1842015-07-03 Alan Modra <amodra@gmail.com>
185
186 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
187 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
188 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
189
c8c8175b
SL		 1902015-07-01 Sandra Loosemore <sandra@codesourcery.com>
191 Cesar Philippidis <cesar@codesourcery.com>
192
193 * nios2-dis.c (nios2_extract_opcode): New.
194 (nios2_disassembler_state): New.
195 (nios2_find_opcode_hash): Use mach parameter to select correct
196 disassembler state.
197 (nios2_print_insn_arg): Extend to support new R2 argument letters
198 and formats.
199 (print_insn_nios2): Check for 16-bit instruction at end of memory.
200 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
201 (NIOS2_NUM_OPCODES): Rename to...
202 (NIOS2_NUM_R1_OPCODES): This.
203 (nios2_r2_opcodes): New.
204 (NIOS2_NUM_R2_OPCODES): New.
205 (nios2_num_r2_opcodes): New.
206 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
207 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
208 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
209 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
210 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
211
9916071f
AP		 2122015-06-30 Amit Pawar <Amit.Pawar@amd.com>
213
214 * i386-dis.c (OP_Mwaitx): New.
215 (rm_table): Add monitorx/mwaitx.
216 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
217 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
218 (operand_type_init): Add CpuMWAITX.
219 * i386-opc.h (CpuMWAITX): New.
220 (i386_cpu_flags): Add cpumwaitx.
221 * i386-opc.tbl: Add monitorx and mwaitx.
222 * i386-init.h: Regenerated.
223 * i386-tbl.h: Likewise.
224
7b934113
PB		 2252015-06-22 Peter Bergner <bergner@vnet.ibm.com>
226
227 * ppc-opc.c (insert_ls): Test for invalid LS operands.
228 (insert_esync): New function.
229 (LS, WC): Use insert_ls.
230 (ESYNC): Use insert_esync.
231
bdc4de1b
NC		 2322015-06-22 Nick Clifton <nickc@redhat.com>
233
234 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
235 requested region lies beyond it.
236 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
237 looking for 32-bit insns.
238 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
239 data.
240 * sh-dis.c (print_insn_sh): Likewise.
241 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
242 blocks of instructions.
243 * vax-dis.c (print_insn_vax): Check that the requested address
244 does not clash with the stop_vma.
245
11a0cf2e
PB		 2462015-06-19 Peter Bergner <bergner@vnet.ibm.com>
247
070fe95d 248 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 249 * ppc-opc.c (FXM4): Add non-zero optional value.
250 (TBR): Likewise.
251 (SXL): Likewise.
252 (insert_fxm): Handle new default operand value.
253 (extract_fxm): Likewise.
254 (insert_tbr): Likewise.
255 (extract_tbr): Likewise.
256
bdfa8b95
MW		 2572015-06-16 Matthew Wahab <matthew.wahab@arm.com>
258
259 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
260
24b4cf66
SN		 2612015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
262
263 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
264
99a2c561
PB		 2652015-06-12 Peter Bergner <bergner@vnet.ibm.com>
266
267 * ppc-opc.c: Add comment accidentally removed by old commit.
268 (MTMSRD_L): Delete.
269
40f77f82
AM		 2702015-06-04 Peter Bergner <bergner@vnet.ibm.com>
271
272 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
273
13be46a2
NC		 2742015-06-04 Nick Clifton <nickc@redhat.com>
275
276 PR 18474
277 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
278
ddfded2f
MW		 2792015-06-02 Matthew Wahab <matthew.wahab@arm.com>
280
281 * arm-dis.c (arm_opcodes): Add "setpan".
282 (thumb_opcodes): Add "setpan".
283
1af1dd51
MW		 2842015-06-02 Matthew Wahab <matthew.wahab@arm.com>
285
286 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
287 macros.
288
9e1f0fa7
MW		 2892015-06-02 Matthew Wahab <matthew.wahab@arm.com>
290
291 * aarch64-tbl.h (aarch64_feature_rdma): New.
292 (RDMA): New.
293 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
294 * aarch64-asm-2.c: Regenerate.
295 * aarch64-dis-2.c: Regenerate.
296 * aarch64-opc-2.c: Regenerate.
297
290806fd
MW		 2982015-06-02 Matthew Wahab <matthew.wahab@arm.com>
299
300 * aarch64-tbl.h (aarch64_feature_lor): New.
301 (LOR): New.
302 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
303 "stllrb", "stllrh".
304 * aarch64-asm-2.c: Regenerate.
305 * aarch64-dis-2.c: Regenerate.
306 * aarch64-opc-2.c: Regenerate.
307
f21cce2c
MW		 3082015-06-01 Matthew Wahab <matthew.wahab@arm.com>
309
310 * aarch64-opc.c (F_ARCHEXT): New.
311 (aarch64_sys_regs): Add "pan".
312 (aarch64_sys_reg_supported_p): New.
313 (aarch64_pstatefields): Add "pan".
314 (aarch64_pstatefield_supported_p): New.
315
d194d186
JB		 3162015-06-01 Jan Beulich <jbeulich@suse.com>
317
318 * i386-tbl.h: Regenerate.
319
3a8547d2
JB		 3202015-06-01 Jan Beulich <jbeulich@suse.com>
321
322 * i386-dis.c (print_insn): Swap rounding mode specifier and
323 general purpose register in Intel mode.
324
015c54d5
JB		 3252015-06-01 Jan Beulich <jbeulich@suse.com>
326
327 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
328 * i386-tbl.h: Regenerate.
329
071f0063
L		 3302015-05-18 H.J. Lu <hongjiu.lu@intel.com>
331
332 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
333 * i386-init.h: Regenerated.
334
5db04b09
L		 3352015-05-15 H.J. Lu <hongjiu.lu@intel.com>
336
337 PR binutis/18386
338 * i386-dis.c: Add comments for '@'.
339 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
340 (enum x86_64_isa): New.
341 (isa64): Likewise.
342 (print_i386_disassembler_options): Add amd64 and intel64.
343 (print_insn): Handle amd64 and intel64.
344 (putop): Handle '@'.
345 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
346 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
347 * i386-opc.h (AMD64): New.
348 (CpuIntel64): Likewise.
349 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
350 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
351 Mark direct call/jmp without Disp16|Disp32 as Intel64.
352 * i386-init.h: Regenerated.
353 * i386-tbl.h: Likewise.
354
4bc0608a
PB		 3552015-05-14 Peter Bergner <bergner@vnet.ibm.com>
356
357 * ppc-opc.c (IH) New define.
358 (powerpc_opcodes) <wait>: Do not enable for POWER7.
359 <tlbie>: Add RS operand for POWER7.
360 <slbia>: Add IH operand for POWER6.
361
70cead07
L		 3622015-05-11 H.J. Lu <hongjiu.lu@intel.com>
363
364 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
365 direct branch.
366 (jmp): Likewise.
367 * i386-tbl.h: Regenerated.
368
7b6d09fb
L		 3692015-05-11 H.J. Lu <hongjiu.lu@intel.com>
370
371 * configure.ac: Support bfd_iamcu_arch.
372 * disassemble.c (disassembler): Support bfd_iamcu_arch.
373 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
374 CPU_IAMCU_COMPAT_FLAGS.
375 (cpu_flags): Add CpuIAMCU.
376 * i386-opc.h (CpuIAMCU): New.
377 (i386_cpu_flags): Add cpuiamcu.
378 * configure: Regenerated.
379 * i386-init.h: Likewise.
380 * i386-tbl.h: Likewise.
381
31955f99
L		 3822015-05-08 H.J. Lu <hongjiu.lu@intel.com>
383
384 PR binutis/18386
385 * i386-dis.c (X86_64_E8): New.
386 (X86_64_E9): Likewise.
387 Update comments on 'T', 'U', 'V'. Add comments for '^'.
388 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
389 (x86_64_table): Add X86_64_E8 and X86_64_E9.
390 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
391 (putop): Handle '^'.
392 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
393 REX_W.
394
0952813b
DD		 3952015-04-30 DJ Delorie <dj@redhat.com>
396
397 * disassemble.c (disassembler): Choose suitable disassembler based
398 on E_ABI.
399 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
400 it to decode mul/div insns.
401 * rl78-decode.c: Regenerate.
402 * rl78-dis.c (print_insn_rl78): Rename to...
403 (print_insn_rl78_common): ...this, take ISA parameter.
404 (print_insn_rl78): New.
405 (print_insn_rl78_g10): New.
406 (print_insn_rl78_g13): New.
407 (print_insn_rl78_g14): New.
408 (rl78_get_disassembler): New.
409
f9d3ecaa
NC		 4102015-04-29 Nick Clifton <nickc@redhat.com>
411
412 * po/fr.po: Updated French translation.
413
4fff86c5
PB		 4142015-04-27 Peter Bergner <bergner@vnet.ibm.com>
415
416 * ppc-opc.c (DCBT_EO): New define.
417 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
418 <lharx>: Likewise.
419 <stbcx.>: Likewise.
420 <sthcx.>: Likewise.
421 <waitrsv>: Do not enable for POWER7 and later.
422 <waitimpl>: Likewise.
423 <dcbt>: Default to the two operand form of the instruction for all
424 "old" cpus. For "new" cpus, use the operand ordering that matches
425 whether the cpu is server or embedded.
426 <dcbtst>: Likewise.
427
3b78cfe1
AK		 4282015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
429
430 * s390-opc.c: New instruction type VV0UU2.
431 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
432 and WFC.
433
04d824a4
JB		 4342015-04-23 Jan Beulich <jbeulich@suse.com>
435
436 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
437 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
438 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
439 (vfpclasspd, vfpclassps): Add %XZ.
440
09708981
L		 4412015-04-15 H.J. Lu <hongjiu.lu@intel.com>
442
443 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
444 (PREFIX_UD_REPZ): Likewise.
445 (PREFIX_UD_REPNZ): Likewise.
446 (PREFIX_UD_DATA): Likewise.
447 (PREFIX_UD_ADDR): Likewise.
448 (PREFIX_UD_LOCK): Likewise.
449
3888916d
L		 4502015-04-15 H.J. Lu <hongjiu.lu@intel.com>
451
452 * i386-dis.c (prefix_requirement): Removed.
453 (print_insn): Don't set prefix_requirement. Check
454 dp->prefix_requirement instead of prefix_requirement.
455
f24bcbaa
L		 4562015-04-15 H.J. Lu <hongjiu.lu@intel.com>
457
458 PR binutils/17898
459 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
460 (PREFIX_MOD_0_0FC7_REG_6): This.
461 (PREFIX_MOD_3_0FC7_REG_6): New.
462 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
463 (prefix_table): Replace PREFIX_0FC7_REG_6 with
464 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
465 PREFIX_MOD_3_0FC7_REG_7.
466 (mod_table): Replace PREFIX_0FC7_REG_6 with
467 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
468 PREFIX_MOD_3_0FC7_REG_7.
469
507bd325
L		 4702015-04-15 H.J. Lu <hongjiu.lu@intel.com>
471
472 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
473 (PREFIX_MANDATORY_REPNZ): Likewise.
474 (PREFIX_MANDATORY_DATA): Likewise.
475 (PREFIX_MANDATORY_ADDR): Likewise.
476 (PREFIX_MANDATORY_LOCK): Likewise.
477 (PREFIX_MANDATORY): Likewise.
478 (PREFIX_UD_SHIFT): Set to 8
479 (PREFIX_UD_REPZ): Updated.
480 (PREFIX_UD_REPNZ): Likewise.
481 (PREFIX_UD_DATA): Likewise.
482 (PREFIX_UD_ADDR): Likewise.
483 (PREFIX_UD_LOCK): Likewise.
484 (PREFIX_IGNORED_SHIFT): New.
485 (PREFIX_IGNORED_REPZ): Likewise.
486 (PREFIX_IGNORED_REPNZ): Likewise.
487 (PREFIX_IGNORED_DATA): Likewise.
488 (PREFIX_IGNORED_ADDR): Likewise.
489 (PREFIX_IGNORED_LOCK): Likewise.
490 (PREFIX_OPCODE): Likewise.
491 (PREFIX_IGNORED): Likewise.
492 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
493 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
494 (three_byte_table): Likewise.
495 (mod_table): Likewise.
496 (mandatory_prefix): Renamed to ...
497 (prefix_requirement): This.
498 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
499 Update PREFIX_90 entry.
500 (get_valid_dis386): Check prefix_requirement to see if a prefix
501 should be ignored.
502 (print_insn): Replace mandatory_prefix with prefix_requirement.
503
f0fba320
RL		 5042015-04-15 Renlin Li <renlin.li@arm.com>
505
506 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
507 use it for ssat and ssat16.
508 (print_insn_thumb32): Add handle case for 'D' control code.
509
bf890a93
IT		 5102015-04-06 Ilya Tocar <ilya.tocar@intel.com>
511 H.J. Lu <hongjiu.lu@intel.com>
512
513 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
514 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
515 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
516 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
517 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
518 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
519 Fill prefix_requirement field.
520 (struct dis386): Add prefix_requirement field.
521 (dis386): Fill prefix_requirement field.
522 (dis386_twobyte): Ditto.
523 (twobyte_has_mandatory_prefix_: Remove.
524 (reg_table): Fill prefix_requirement field.
525 (prefix_table): Ditto.
526 (x86_64_table): Ditto.
527 (three_byte_table): Ditto.
528 (xop_table): Ditto.
529 (vex_table): Ditto.
530 (vex_len_table): Ditto.
531 (vex_w_table): Ditto.
532 (mod_table): Ditto.
533 (bad_opcode): Ditto.
534 (print_insn): Use prefix_requirement.
535 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
536 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
537 (float_reg): Ditto.
538
2f783c1f
MF		 5392015-03-30 Mike Frysinger <vapier@gentoo.org>
540
541 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
542
b9d94d62
L		 5432015-03-29 H.J. Lu <hongjiu.lu@intel.com>
544
545 * Makefile.in: Regenerated.
546
27c49e9a
AB		 5472015-03-25 Anton Blanchard <anton@samba.org>
548
549 * ppc-dis.c (disassemble_init_powerpc): Only initialise
550 powerpc_opcd_indices and vle_opcd_indices once.
551
c4e676f1
AB		 5522015-03-25 Anton Blanchard <anton@samba.org>
553
554 * ppc-opc.c (powerpc_opcodes): Add slbfee.
555
823d2571
TG		 5562015-03-24 Terry Guo <terry.guo@arm.com>
557
558 * arm-dis.c (opcode32): Updated to use new arm feature struct.
559 (opcode16): Likewise.
560 (coprocessor_opcodes): Replace bit with feature struct.
561 (neon_opcodes): Likewise.
562 (arm_opcodes): Likewise.
563 (thumb_opcodes): Likewise.
564 (thumb32_opcodes): Likewise.
565 (print_insn_coprocessor): Likewise.
566 (print_insn_arm): Likewise.
567 (select_arm_features): Follow new feature struct.
568
029f3522
GG		 5692015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
570
571 * i386-dis.c (rm_table): Add clzero.
572 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
573 Add CPU_CLZERO_FLAGS.
574 (cpu_flags): Add CpuCLZERO.
575 * i386-opc.h: Add CpuCLZERO.
576 * i386-opc.tbl: Add clzero.
577 * i386-init.h: Re-generated.
578 * i386-tbl.h: Re-generated.
579
6914869a
AB		 5802015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
581
582 * mips-opc.c (decode_mips_operand): Fix constraint issues
583 with u and y operands.
584
21e20815
AB		 5852015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
586
587 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
588
6b1d7593
AK		 5892015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
590
591 * s390-opc.c: Add new IBM z13 instructions.
592 * s390-opc.txt: Likewise.
593
c8f89a34
JW		 5942015-03-10 Renlin Li <renlin.li@arm.com>
595
596 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
597 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
598 related alias.
599 * aarch64-asm-2.c: Regenerate.
600 * aarch64-dis-2.c: Likewise.
601 * aarch64-opc-2.c: Likewise.
602
d8282f0e
JW		 6032015-03-03 Jiong Wang <jiong.wang@arm.com>
604
605 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
606
ac994365
OE		 6072015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
608
609 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
610 arch_sh_up.
611 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
612 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
613
fd63f640
V		 6142015-02-23 Vinay <Vinay.G@kpit.com>
615
616 * rl78-decode.opc (MOV): Added space between two operands for
617 'mov' instruction in index addressing mode.
618 * rl78-decode.c: Regenerate.
619
f63c1776
PA		 6202015-02-19 Pedro Alves <palves@redhat.com>
621
622 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
623
07774fcc
PA		 6242015-02-10 Pedro Alves <palves@redhat.com>
625 Tom Tromey <tromey@redhat.com>
626
627 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
628 microblaze_and, microblaze_xor.
629 * microblaze-opc.h (opcodes): Adjust.
630
3f8107ab
AM		 6312015-01-28 James Bowman <james.bowman@ftdichip.com>
632
633 * Makefile.am: Add FT32 files.
634 * configure.ac: Handle FT32.
635 * disassemble.c (disassembler): Call print_insn_ft32.
636 * ft32-dis.c: New file.
637 * ft32-opc.c: New file.
638 * Makefile.in: Regenerate.
639 * configure: Regenerate.
640 * po/POTFILES.in: Regenerate.
641
e5fe4957
KLC		 6422015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
643
644 * nds32-asm.c (keyword_sr): Add new system registers.
645
1e2e8c52
AK		 6462015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
647
648 * s390-dis.c (s390_extract_operand): Support vector register
649 operands.
650 (s390_print_insn_with_opcode): Support new operands types and add
651 new handling of optional operands.
652 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
653 and include opcode/s390.h instead.
654 (struct op_struct): New field `flags'.
655 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
656 (dumpTable): Dump flags.
657 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
658 string.
659 * s390-opc.c: Add new operands types, instruction formats, and
660 instruction masks.
661 (s390_opformats): Add new formats for .insn.
662 * s390-opc.txt: Add new instructions.
663
b90efa5b 6642015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 665
b90efa5b 666 Update year range in copyright notice of all files.
bffb6004 667
b90efa5b 668For older changes see ChangeLog-2014
252b5132 669\f
b90efa5b 670Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 671
672Copying and distribution of this file, with or without modification,
673are permitted in any medium without royalty provided the copyright
674notice and this notice are preserved.
675
252b5132 676Local Variables:
2f6d2f85
NC		 677mode: change-log
678left-margin: 8
679fill-column: 74
252b5132
RH		 680version-control: never
681End:
GDB Binutils - Deliverables
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