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x86-64: fold ILP32 test expectations
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
260cd341
LC		 12020-07-10 Lili Cui <lili.cui@intel.com>
2
3 * i386-dis.c (TMM): New.
4 (EXtmm): Likewise.
5 (VexTmm): Likewise.
6 (MVexSIBMEM): Likewise.
7 (tmm_mode): Likewise.
8 (vex_sibmem_mode): Likewise.
9 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
10 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
11 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
12 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
13 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
14 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
15 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
16 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
17 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
18 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
19 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
20 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
21 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
22 (PREFIX_VEX_0F3849_X86_64): Likewise.
23 (PREFIX_VEX_0F384B_X86_64): Likewise.
24 (PREFIX_VEX_0F385C_X86_64): Likewise.
25 (PREFIX_VEX_0F385E_X86_64): Likewise.
26 (X86_64_VEX_0F3849): Likewise.
27 (X86_64_VEX_0F384B): Likewise.
28 (X86_64_VEX_0F385C): Likewise.
29 (X86_64_VEX_0F385E): Likewise.
30 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
31 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
32 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
33 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
34 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
35 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
36 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
37 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
38 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
39 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
40 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
41 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
42 (VEX_W_0F3849_X86_64_P_0): Likewise.
43 (VEX_W_0F3849_X86_64_P_2): Likewise.
44 (VEX_W_0F3849_X86_64_P_3): Likewise.
45 (VEX_W_0F384B_X86_64_P_1): Likewise.
46 (VEX_W_0F384B_X86_64_P_2): Likewise.
47 (VEX_W_0F384B_X86_64_P_3): Likewise.
48 (VEX_W_0F385C_X86_64_P_1): Likewise.
49 (VEX_W_0F385E_X86_64_P_0): Likewise.
50 (VEX_W_0F385E_X86_64_P_1): Likewise.
51 (VEX_W_0F385E_X86_64_P_2): Likewise.
52 (VEX_W_0F385E_X86_64_P_3): Likewise.
53 (names_tmm): Likewise.
54 (att_names_tmm): Likewise.
55 (intel_operand_size): Handle void_mode.
56 (OP_XMM): Handle tmm_mode.
57 (OP_EX): Likewise.
58 (OP_VEX): Likewise.
59 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
60 CpuAMX_BF16 and CpuAMX_TILE.
61 (operand_type_shorthands): Add RegTMM.
62 (operand_type_init): Likewise.
63 (operand_types): Add Tmmword.
64 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
65 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
66 * i386-opc.h (CpuAMX_INT8): New.
67 (CpuAMX_BF16): Likewise.
68 (CpuAMX_TILE): Likewise.
69 (SIBMEM): Likewise.
70 (Tmmword): Likewise.
71 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
72 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
73 (i386_operand_type): Add tmmword.
74 * i386-opc.tbl: Add AMX instructions.
75 * i386-reg.tbl: Add AMX registers.
76 * i386-init.h: Regenerated.
77 * i386-tbl.h: Likewise.
78
467bbef0
JB		 792020-07-08 Jan Beulich <jbeulich@suse.com>
80
81 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
82 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
83 Rename to ...
84 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
85 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
86 respectively.
87 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
88 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
89 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
90 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
91 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
92 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
93 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
94 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
95 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
96 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
97 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
98 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
99 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
100 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
101 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
102 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
103 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
104 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
105 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
106 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
107 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
108 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
109 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
110 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
111 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
112 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
113 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
114 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
115 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
116 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
117 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
118 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
119 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
120 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
121 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
122 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
123 (reg_table): Re-order XOP entries. Adjust their operands.
124 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
125 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
126 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
127 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
128 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
129 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
130 entries by references ...
131 (vex_len_table): ... to resepctive new entries here. For several
132 new and existing entries reference ...
133 (vex_w_table): ... new entries here.
134 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
135
6384fd9e
JB		 1362020-07-08 Jan Beulich <jbeulich@suse.com>
137
138 * i386-dis.c (XMVexScalarI4): Define.
139 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
140 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
141 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
142 (vex_len_table): Move scalar FMA4 entries ...
143 (prefix_table): ... here.
144 (OP_REG_VexI4): Handle scalar_mode.
145 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
146 * i386-tbl.h: Re-generate.
147
e6123d0c
JB		 1482020-07-08 Jan Beulich <jbeulich@suse.com>
149
150 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
151 Vex_2src_2): Delete.
152 (OP_VexW, VexW): New.
153 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
154 for shifts and rotates by register.
155
93abb146
JB		 1562020-07-08 Jan Beulich <jbeulich@suse.com>
157
158 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
159 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
160 OP_EX_VexReg): Delete.
161 (OP_VexI4, VexI4): New.
162 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
163 (prefix_table): ... here.
164 (print_insn): Drop setting of vex_w_done.
165
b13b1bc0
JB		 1662020-07-08 Jan Beulich <jbeulich@suse.com>
167
168 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
169 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
170 (xop_table): Replace operands of 4-operand insns.
171 (OP_REG_VexI4): Move VEX.W based operand swaping here.
172
f337259f
CZ		 1732020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
174
175 * arc-opc.c (insert_rbd): New function.
176 (RBD): Define.
177 (RBDdup): Likewise.
178 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
179 instructions.
180
931452b6
JB		 1812020-07-07 Jan Beulich <jbeulich@suse.com>
182
183 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
184 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
185 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
186 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
187 Delete.
188 (putop): Handle "BW".
189 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
190 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
191 and 0F3A3F ...
192 * i386-dis-evex-prefix.h: ... here.
193
b5b098c2
JB		 1942020-07-06 Jan Beulich <jbeulich@suse.com>
195
196 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
197 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
198 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
199 VEX_W_0FXOP_09_83): New enumerators.
200 (xop_table): Reference the above.
201 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
202 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
203 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
204 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
205
21a3faeb
JB		 2062020-07-06 Jan Beulich <jbeulich@suse.com>
207
208 * i386-dis.c (EVEX_W_0F3838_P_1,
209 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
210 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
211 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
212 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
213 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
214 (putop): Centralize management of last[]. Delete SAVE_LAST.
215 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
216 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
217 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
218 * i386-dis-evex-prefix.h: here.
219
bc152a17
JB		 2202020-07-06 Jan Beulich <jbeulich@suse.com>
221
222 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
223 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
224 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
225 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
226 enumerators.
227 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
228 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
229 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
230 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
231 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
232 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
233 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
234 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
235 these, respectively.
236 * i386-dis-evex-len.h: Adjust comments.
237 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
238 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
239 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
240 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
241 MOD_EVEX_0F385B_P_2_W_1 table entries.
242 * i386-dis-evex-w.h: Reference mod_table[] for
243 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
244 EVEX_W_0F385B_P_2.
245
c82a99a0
JB		 2462020-07-06 Jan Beulich <jbeulich@suse.com>
247
248 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
249 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
250 EXymm.
251 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
252 Likewise. Mark 256-bit entries invalid.
253
fedfb81e
JB		 2542020-07-06 Jan Beulich <jbeulich@suse.com>
255
256 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
257 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
258 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
259 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
260 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
261 PREFIX_EVEX_0F382B): Delete.
262 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
263 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
264 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
265 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
266 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
267 to ...
268 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
269 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
270 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
271 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
272 respectively.
273 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
274 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
275 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
276 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
277 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
278 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
279 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
280 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
281 PREFIX_EVEX_0F382B): Remove table entries.
282 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
283 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
284 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
285
3a57774c
JB		 2862020-07-06 Jan Beulich <jbeulich@suse.com>
287
288 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
289 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
290 enumerators.
291 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
292 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
293 EVEX_LEN_0F3A01_P_2_W_1 table entries.
294 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
295 entries.
296
e74d9fa9
JB		 2972020-07-06 Jan Beulich <jbeulich@suse.com>
298
299 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
300 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
301 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
302 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
303 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
304 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
305 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
306 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
307 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
308 entries.
309
6431c801
JB		 3102020-07-06 Jan Beulich <jbeulich@suse.com>
311
312 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
313 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
314 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
315 respectively.
316 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
317 entries.
318 * i386-dis-evex.h (evex_table): Reference VEX table entry for
319 opcode 0F3A1D.
320 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
321 entry.
322 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
323
6df22cf6
JB		 3242020-07-06 Jan Beulich <jbeulich@suse.com>
325
326 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
327 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
328 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
329 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
330 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
331 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
332 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
333 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
334 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
335 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
336 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
337 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
338 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
339 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
340 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
341 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
342 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
343 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
344 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
345 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
346 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
347 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
348 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
349 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
350 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
351 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
352 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
353 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
354 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
355 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
356 (prefix_table): Add EXxEVexR to FMA table entries.
357 (OP_Rounding): Move abort() invocation.
358 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
359 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
360 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
361 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
362 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
363 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
364 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
365 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
366 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
367 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
368 0F3ACE, 0F3ACF.
369 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
370 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
371 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
372 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
373 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
374 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
375 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
376 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
377 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
378 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
379 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
380 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
381 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
382 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
383 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
384 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
385 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
386 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
387 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
388 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
389 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
390 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
391 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
392 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
393 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
394 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
395 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
396 Delete table entries.
397 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
398 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
399 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
400 Likewise.
401
39e0f456
JB		 4022020-07-06 Jan Beulich <jbeulich@suse.com>
403
404 * i386-dis.c (EXqScalarS): Delete.
405 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
406 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
407
5b872f7d
JB		 4082020-07-06 Jan Beulich <jbeulich@suse.com>
409
410 * i386-dis.c (safe-ctype.h): Include.
411 (EXdScalar, EXqScalar): Delete.
412 (d_scalar_mode, q_scalar_mode): Delete.
413 (prefix_table, vex_len_table): Use EXxmm_md in place of
414 EXdScalar and EXxmm_mq in place of EXqScalar.
415 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
416 d_scalar_mode and q_scalar_mode.
417 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
418 (vmovsd): Use EXxmm_mq.
419
ddc73fa9
NC		 4202020-07-06 Yuri Chornoivan <yurchor@ukr.net>
421
422 PR 26204
423 * arc-dis.c: Fix spelling mistake.
424 * po/opcodes.pot: Regenerate.
425
17550be7
NC		 4262020-07-06 Nick Clifton <nickc@redhat.com>
427
428 * po/pt_BR.po: Updated Brazilian Portugugese translation.
429 * po/uk.po: Updated Ukranian translation.
430
b19d852d
NC		 4312020-07-04 Nick Clifton <nickc@redhat.com>
432
433 * configure: Regenerate.
434 * po/opcodes.pot: Regenerate.
435
b115b9fd
NC		 4362020-07-04 Nick Clifton <nickc@redhat.com>
437
438 Binutils 2.35 branch created.
439
c2ecccb3
L		 4402020-07-02 H.J. Lu <hongjiu.lu@intel.com>
441
442 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
443 * i386-opc.h (VexSwapSources): New.
444 (i386_opcode_modifier): Add vexswapsources.
445 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
446 with two source operands swapped.
447 * i386-tbl.h: Regenerated.
448
08ccfccf
NC		 4492020-06-30 Nelson Chu <nelson.chu@sifive.com>
450
451 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
452 unprivileged CSR can also be initialized.
453
279edac5
AM		 4542020-06-29 Alan Modra <amodra@gmail.com>
455
456 * arm-dis.c: Use C style comments.
457 * cr16-opc.c: Likewise.
458 * ft32-dis.c: Likewise.
459 * moxie-opc.c: Likewise.
460 * tic54x-dis.c: Likewise.
461 * s12z-opc.c: Remove useless comment.
462 * xgate-dis.c: Likewise.
463
e978ad62
L		 4642020-06-26 H.J. Lu <hongjiu.lu@intel.com>
465
466 * i386-opc.tbl: Add a blank line.
467
63112cd6
L		 4682020-06-26 H.J. Lu <hongjiu.lu@intel.com>
469
470 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
471 (VecSIB128): Renamed to ...
472 (VECSIB128): This.
473 (VecSIB256): Renamed to ...
474 (VECSIB256): This.
475 (VecSIB512): Renamed to ...
476 (VECSIB512): This.
477 (VecSIB): Renamed to ...
478 (SIB): This.
479 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 480 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 481 (VecSIB256): Likewise.
482 (VecSIB512): Likewise.
79b32e73 483 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 484 and VecSIB512, respectively.
485
d1c36125
JB		 4862020-06-26 Jan Beulich <jbeulich@suse.com>
487
488 * i386-dis.c: Adjust description of I macro.
489 (x86_64_table): Drop use of I.
490 (float_mem): Replace use of I.
491 (putop): Remove handling of I. Adjust setting/clearing of "alt".
492
2a1bb84c
JB		 4932020-06-26 Jan Beulich <jbeulich@suse.com>
494
495 * i386-dis.c: (print_insn): Avoid straight assignment to
496 priv.orig_sizeflag when processing -M sub-options.
497
8f570d62
JB		 4982020-06-25 Jan Beulich <jbeulich@suse.com>
499
500 * i386-dis.c: Adjust description of J macro.
501 (dis386, x86_64_table, mod_table): Replace J.
502 (putop): Remove handling of J.
503
464dc4af
JB		 5042020-06-25 Jan Beulich <jbeulich@suse.com>
505
506 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
507
589958d6
JB		 5082020-06-25 Jan Beulich <jbeulich@suse.com>
509
510 * i386-dis.c: Adjust description of "LQ" macro.
511 (dis386_twobyte): Use LQ for sysret.
512 (putop): Adjust handling of LQ.
513
39ff0b81
NC		 5142020-06-22 Nelson Chu <nelson.chu@sifive.com>
515
516 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
517 * riscv-dis.c: Include elfxx-riscv.h.
518
d27c357a
JB		 5192020-06-18 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-dis.c (prefix_table): Revert the last vmgexit change.
522
6fde587f
CL		 5232020-06-17 Lili Cui <lili.cui@intel.com>
524
525 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
526
efe30057
L		 5272020-06-14 H.J. Lu <hongjiu.lu@intel.com>
528
529 PR gas/26115
530 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
531 * i386-opc.tbl: Likewise.
532 * i386-tbl.h: Regenerated.
533
d8af286f
NC		 5342020-06-12 Nelson Chu <nelson.chu@sifive.com>
535
536 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
537
14962256
AC		 5382020-06-11 Alex Coplan <alex.coplan@arm.com>
539
540 * aarch64-opc.c (SYSREG): New macro for describing system registers.
541 (SR_CORE): Likewise.
542 (SR_FEAT): Likewise.
543 (SR_RNG): Likewise.
544 (SR_V8_1): Likewise.
545 (SR_V8_2): Likewise.
546 (SR_V8_3): Likewise.
547 (SR_V8_4): Likewise.
548 (SR_PAN): Likewise.
549 (SR_RAS): Likewise.
550 (SR_SSBS): Likewise.
551 (SR_SVE): Likewise.
552 (SR_ID_PFR2): Likewise.
553 (SR_PROFILE): Likewise.
554 (SR_MEMTAG): Likewise.
555 (SR_SCXTNUM): Likewise.
556 (aarch64_sys_regs): Refactor to store feature information in the table.
557 (aarch64_sys_reg_supported_p): Collapse logic for system registers
558 that now describe their own features.
559 (aarch64_pstatefield_supported_p): Likewise.
560
f9630fa6
L		 5612020-06-09 H.J. Lu <hongjiu.lu@intel.com>
562
563 * i386-dis.c (prefix_table): Fix a typo in comments.
564
73239888
JB		 5652020-06-09 Jan Beulich <jbeulich@suse.com>
566
567 * i386-dis.c (rex_ignored): Delete.
568 (ckprefix): Drop rex_ignored initialization.
569 (get_valid_dis386): Drop setting of rex_ignored.
570 (print_insn): Drop checking of rex_ignored. Don't record data
571 size prefix as used with VEX-and-alike encodings.
572
18897deb
JB		 5732020-06-09 Jan Beulich <jbeulich@suse.com>
574
575 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
576 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
577 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
578 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
579 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
580 VEX_0F12, and VEX_0F16.
581 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
582 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
583 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
584 from movlps and movhlps. New MOD_0F12_PREFIX_2,
585 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
586 MOD_VEX_0F16_PREFIX_2 entries.
587
97e6786a
JB		 5882020-06-09 Jan Beulich <jbeulich@suse.com>
589
590 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
591 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
592 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
593 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
594 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
595 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
596 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
597 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
598 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
599 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
600 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
601 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
602 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
603 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
604 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
605 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
606 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
607 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
608 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
609 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
610 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
611 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
612 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
613 EVEX_W_0FC6_P_2): Delete.
614 (print_insn): Add EVEX.W vs embedded prefix consistency check
615 to prefix validation.
616 * i386-dis-evex.h (evex_table): Don't further descend for
617 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
618 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
619 and 0F2B.
620 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
621 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
622 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
623 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
624 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
625 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
626 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
627 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
628 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
629 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
630 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
631 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
632 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
633 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
634 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
635 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
636 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
637 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
638 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
639 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
640 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
641 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
642 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
643 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
644 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
645 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
646 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
647
bf926894
JB		 6482020-06-09 Jan Beulich <jbeulich@suse.com>
649
650 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
651 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
652 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
653 vmovmskpX.
654 (print_insn): Drop pointless check against bad_opcode. Split
655 prefix validation into legacy and VEX-and-alike parts.
656 (putop): Re-work 'X' macro handling.
657
a5aaedb9
JB		 6582020-06-09 Jan Beulich <jbeulich@suse.com>
659
660 * i386-dis.c (MOD_0F51): Rename to ...
661 (MOD_0F50): ... this.
662
26417f19
AC		 6632020-06-08 Alex Coplan <alex.coplan@arm.com>
664
665 * arm-dis.c (arm_opcodes): Add dfb.
666 (thumb32_opcodes): Add dfb.
667
8a6fb3f9
JB		 6682020-06-08 Jan Beulich <jbeulich@suse.com>
669
670 * i386-opc.h (reg_entry): Const-qualify reg_name field.
671
1424c35d
AM		 6722020-06-06 Alan Modra <amodra@gmail.com>
673
674 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
675
d3d1cc7b
AM		 6762020-06-05 Alan Modra <amodra@gmail.com>
677
678 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
679 size is large enough.
680
d8740be1
JM		 6812020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
682
683 * disassemble.c (disassemble_init_for_target): Set endian_code for
684 bpf targets.
685 * bpf-desc.c: Regenerate.
686 * bpf-opc.c: Likewise.
687 * bpf-dis.c: Likewise.
688
e9bffec9
JM		 6892020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
690
691 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
692 (cgen_put_insn_value): Likewise.
693 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
694 * cgen-dis.in (print_insn): Likewise.
695 * cgen-ibld.in (insert_1): Likewise.
696 (insert_1): Likewise.
697 (insert_insn_normal): Likewise.
698 (extract_1): Likewise.
699 * bpf-dis.c: Regenerate.
700 * bpf-ibld.c: Likewise.
701 * bpf-ibld.c: Likewise.
702 * cgen-dis.in: Likewise.
703 * cgen-ibld.in: Likewise.
704 * cgen-opc.c: Likewise.
705 * epiphany-dis.c: Likewise.
706 * epiphany-ibld.c: Likewise.
707 * fr30-dis.c: Likewise.
708 * fr30-ibld.c: Likewise.
709 * frv-dis.c: Likewise.
710 * frv-ibld.c: Likewise.
711 * ip2k-dis.c: Likewise.
712 * ip2k-ibld.c: Likewise.
713 * iq2000-dis.c: Likewise.
714 * iq2000-ibld.c: Likewise.
715 * lm32-dis.c: Likewise.
716 * lm32-ibld.c: Likewise.
717 * m32c-dis.c: Likewise.
718 * m32c-ibld.c: Likewise.
719 * m32r-dis.c: Likewise.
720 * m32r-ibld.c: Likewise.
721 * mep-dis.c: Likewise.
722 * mep-ibld.c: Likewise.
723 * mt-dis.c: Likewise.
724 * mt-ibld.c: Likewise.
725 * or1k-dis.c: Likewise.
726 * or1k-ibld.c: Likewise.
727 * xc16x-dis.c: Likewise.
728 * xc16x-ibld.c: Likewise.
729 * xstormy16-dis.c: Likewise.
730 * xstormy16-ibld.c: Likewise.
731
b3db6d07
JM		 7322020-06-04 Jose E. Marchesi <jemarch@gnu.org>
733
734 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
735 (print_insn_): Handle instruction endian.
736 * bpf-dis.c: Regenerate.
737 * bpf-desc.c: Regenerate.
738 * epiphany-dis.c: Likewise.
739 * epiphany-desc.c: Likewise.
740 * fr30-dis.c: Likewise.
741 * fr30-desc.c: Likewise.
742 * frv-dis.c: Likewise.
743 * frv-desc.c: Likewise.
744 * ip2k-dis.c: Likewise.
745 * ip2k-desc.c: Likewise.
746 * iq2000-dis.c: Likewise.
747 * iq2000-desc.c: Likewise.
748 * lm32-dis.c: Likewise.
749 * lm32-desc.c: Likewise.
750 * m32c-dis.c: Likewise.
751 * m32c-desc.c: Likewise.
752 * m32r-dis.c: Likewise.
753 * m32r-desc.c: Likewise.
754 * mep-dis.c: Likewise.
755 * mep-desc.c: Likewise.
756 * mt-dis.c: Likewise.
757 * mt-desc.c: Likewise.
758 * or1k-dis.c: Likewise.
759 * or1k-desc.c: Likewise.
760 * xc16x-dis.c: Likewise.
761 * xc16x-desc.c: Likewise.
762 * xstormy16-dis.c: Likewise.
763 * xstormy16-desc.c: Likewise.
764
4ee4189f
NC		 7652020-06-03 Nick Clifton <nickc@redhat.com>
766
767 * po/sr.po: Updated Serbian translation.
768
44730156
NC		 7692020-06-03 Nelson Chu <nelson.chu@sifive.com>
770
771 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
772 (riscv_get_priv_spec_class): Likewise.
773
3c3d0376
AM		 7742020-06-01 Alan Modra <amodra@gmail.com>
775
776 * bpf-desc.c: Regenerate.
777
78c1c354
JM		 7782020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
779 David Faust <david.faust@oracle.com>
780
781 * bpf-desc.c: Regenerate.
782 * bpf-opc.h: Likewise.
783 * bpf-opc.c: Likewise.
784 * bpf-dis.c: Likewise.
785
efcf5fb5
AM		 7862020-05-28 Alan Modra <amodra@gmail.com>
787
788 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
789 values.
790
ab382d64
AM		 7912020-05-28 Alan Modra <amodra@gmail.com>
792
793 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
794 immediates.
795 (print_insn_ns32k): Revert last change.
796
151f5de4
NC		 7972020-05-28 Nick Clifton <nickc@redhat.com>
798
799 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
800 static.
801
25e1eca8
SL		 8022020-05-26 Sandra Loosemore <sandra@codesourcery.com>
803
804 Fix extraction of signed constants in nios2 disassembler (again).
805
806 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
807 extractions of signed fields.
808
57b17940
SSF		 8092020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
810
811 * s390-opc.txt: Relocate vector load/store instructions with
812 additional alignment parameter and change architecture level
813 constraint from z14 to z13.
814
d96bf37b
AM		 8152020-05-21 Alan Modra <amodra@gmail.com>
816
817 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
818 * sparc-dis.c: Likewise.
819 * tic4x-dis.c: Likewise.
820 * xtensa-dis.c: Likewise.
821 * bpf-desc.c: Regenerate.
822 * epiphany-desc.c: Regenerate.
823 * fr30-desc.c: Regenerate.
824 * frv-desc.c: Regenerate.
825 * ip2k-desc.c: Regenerate.
826 * iq2000-desc.c: Regenerate.
827 * lm32-desc.c: Regenerate.
828 * m32c-desc.c: Regenerate.
829 * m32r-desc.c: Regenerate.
830 * mep-asm.c: Regenerate.
831 * mep-desc.c: Regenerate.
832 * mt-desc.c: Regenerate.
833 * or1k-desc.c: Regenerate.
834 * xc16x-desc.c: Regenerate.
835 * xstormy16-desc.c: Regenerate.
836
8f595e9b
NC		 8372020-05-20 Nelson Chu <nelson.chu@sifive.com>
838
839 * riscv-opc.c (riscv_ext_version_table): The table used to store
840 all information about the supported spec and the corresponding ISA
841 versions. Currently, only Zicsr is supported to verify the
842 correctness of Z sub extension settings. Others will be supported
843 in the future patches.
844 (struct isa_spec_t, isa_specs): List for all supported ISA spec
845 classes and the corresponding strings.
846 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
847 spec class by giving a ISA spec string.
848 * riscv-opc.c (struct priv_spec_t): New structure.
849 (struct priv_spec_t priv_specs): List for all supported privilege spec
850 classes and the corresponding strings.
851 (riscv_get_priv_spec_class): New function. Get the corresponding
852 privilege spec class by giving a spec string.
853 (riscv_get_priv_spec_name): New function. Get the corresponding
854 privilege spec string by giving a CSR version class.
855 * riscv-dis.c: Updated since DECLARE_CSR is changed.
856 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
857 according to the chosen version. Build a hash table riscv_csr_hash to
858 store the valid CSR for the chosen pirv verison. Dump the direct
859 CSR address rather than it's name if it is invalid.
860 (parse_riscv_dis_option_without_args): New function. Parse the options
861 without arguments.
862 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
863 parse the options without arguments first, and then handle the options
864 with arguments. Add the new option -Mpriv-spec, which has argument.
865 * riscv-dis.c (print_riscv_disassembler_options): Add description
866 about the new OBJDUMP option.
867
3d205eb4
PB		 8682020-05-19 Peter Bergner <bergner@linux.ibm.com>
869
870 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
871 WC values on POWER10 sync, dcbf and wait instructions.
872 (insert_pl, extract_pl): New functions.
873 (L2OPT, LS, WC): Use insert_ls and extract_ls.
874 (LS3): New , 3-bit L for sync.
875 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
876 (SC2, PL): New, 2-bit SC and PL for sync and wait.
877 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
878 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
879 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
880 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
881 <wait>: Enable PL operand on POWER10.
882 <dcbf>: Enable L3OPT operand on POWER10.
883 <sync>: Enable SC2 operand on POWER10.
884
a501eb44
SH		 8852020-05-19 Stafford Horne <shorne@gmail.com>
886
887 PR 25184
888 * or1k-asm.c: Regenerate.
889 * or1k-desc.c: Regenerate.
890 * or1k-desc.h: Regenerate.
891 * or1k-dis.c: Regenerate.
892 * or1k-ibld.c: Regenerate.
893 * or1k-opc.c: Regenerate.
894 * or1k-opc.h: Regenerate.
895 * or1k-opinst.c: Regenerate.
896
3b646889
AM		 8972020-05-11 Alan Modra <amodra@gmail.com>
898
899 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
900 xsmaxcqp, xsmincqp.
901
9cc4ce88
AM		 9022020-05-11 Alan Modra <amodra@gmail.com>
903
904 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
905 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
906
5d57bc3f
AM		 9072020-05-11 Alan Modra <amodra@gmail.com>
908
909 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
910
66ef5847
AM		 9112020-05-11 Alan Modra <amodra@gmail.com>
912
913 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
914 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
915
4f3e9537
PB		 9162020-05-11 Peter Bergner <bergner@linux.ibm.com>
917
918 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
919 mnemonics.
920
ec40e91c
AM		 9212020-05-11 Alan Modra <amodra@gmail.com>
922
923 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
924 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
925 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
926 (prefix_opcodes): Add xxeval.
927
d7e97a76
AM		 9282020-05-11 Alan Modra <amodra@gmail.com>
929
930 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
931 xxgenpcvwm, xxgenpcvdm.
932
fdefed7c
AM		 9332020-05-11 Alan Modra <amodra@gmail.com>
934
935 * ppc-opc.c (MP, VXVAM_MASK): Define.
936 (VXVAPS_MASK): Use VXVA_MASK.
937 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
938 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
939 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
940 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
941
aa3c112f
AM		 9422020-05-11 Alan Modra <amodra@gmail.com>
943 Peter Bergner <bergner@linux.ibm.com>
944
945 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
946 New functions.
947 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
948 YMSK2, XA6a, XA6ap, XB6a entries.
949 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
950 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
951 (PPCVSX4): Define.
952 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
953 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
954 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
955 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
956 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
957 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
958 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
959 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
960 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
961 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
962 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
963 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
964 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
965 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
966
6edbfd3b
AM		 9672020-05-11 Alan Modra <amodra@gmail.com>
968
969 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
970 (insert_xts, extract_xts): New functions.
971 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
972 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
973 (VXRC_MASK, VXSH_MASK): Define.
974 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
975 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
976 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
977 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
978 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
979 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
980 xxblendvh, xxblendvw, xxblendvd, xxpermx.
981
c7d7aea2
AM		 9822020-05-11 Alan Modra <amodra@gmail.com>
983
984 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
985 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
986 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
987 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
988 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
989
94ba9882
AM		 9902020-05-11 Alan Modra <amodra@gmail.com>
991
992 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
993 (XTP, DQXP, DQXP_MASK): Define.
994 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
995 (prefix_opcodes): Add plxvp and pstxvp.
996
f4791f1a
AM		 9972020-05-11 Alan Modra <amodra@gmail.com>
998
999 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1000 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1001 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1002
3ff0a5ba
PB		 10032020-05-11 Peter Bergner <bergner@linux.ibm.com>
1004
1005 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1006
afef4fe9
PB		 10072020-05-11 Peter Bergner <bergner@linux.ibm.com>
1008
1009 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1010 (L1OPT): Define.
1011 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1012
1224c05d
PB		 10132020-05-11 Peter Bergner <bergner@linux.ibm.com>
1014
1015 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1016
6bbb0c05
AM		 10172020-05-11 Alan Modra <amodra@gmail.com>
1018
1019 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1020
7c1f4227
AM		 10212020-05-11 Alan Modra <amodra@gmail.com>
1022
1023 * ppc-dis.c (ppc_opts): Add "power10" entry.
1024 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1025 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1026
73199c2b
NC		 10272020-05-11 Nick Clifton <nickc@redhat.com>
1028
1029 * po/fr.po: Updated French translation.
1030
09c1e68a
AC		 10312020-04-30 Alex Coplan <alex.coplan@arm.com>
1032
1033 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1034 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1035 (operand_general_constraint_met_p): validate
1036 AARCH64_OPND_UNDEFINED.
1037 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1038 for FLD_imm16_2.
1039 * aarch64-asm-2.c: Regenerated.
1040 * aarch64-dis-2.c: Regenerated.
1041 * aarch64-opc-2.c: Regenerated.
1042
9654d51a
NC		 10432020-04-29 Nick Clifton <nickc@redhat.com>
1044
1045 PR 22699
1046 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1047 and SETRC insns.
1048
c2e71e57
NC		 10492020-04-29 Nick Clifton <nickc@redhat.com>
1050
1051 * po/sv.po: Updated Swedish translation.
1052
5c936ef5
NC		 10532020-04-29 Nick Clifton <nickc@redhat.com>
1054
1055 PR 22699
1056 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1057 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1058 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1059 IMM0_8U case.
1060
bb2a1453
AS		 10612020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1062
1063 PR 25848
1064 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1065 cmpi only on m68020up and cpu32.
1066
c2e5c986
SD		 10672020-04-20 Sudakshina Das <sudi.das@arm.com>
1068
1069 * aarch64-asm.c (aarch64_ins_none): New.
1070 * aarch64-asm.h (ins_none): New declaration.
1071 * aarch64-dis.c (aarch64_ext_none): New.
1072 * aarch64-dis.h (ext_none): New declaration.
1073 * aarch64-opc.c (aarch64_print_operand): Update case for
1074 AARCH64_OPND_BARRIER_PSB.
1075 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1076 (AARCH64_OPERANDS): Update inserter/extracter for
1077 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1078 * aarch64-asm-2.c: Regenerated.
1079 * aarch64-dis-2.c: Regenerated.
1080 * aarch64-opc-2.c: Regenerated.
1081
8a6e1d1d
SD		 10822020-04-20 Sudakshina Das <sudi.das@arm.com>
1083
1084 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1085 (aarch64_feature_ras, RAS): Likewise.
1086 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1087 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1088 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1089 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1090 * aarch64-asm-2.c: Regenerated.
1091 * aarch64-dis-2.c: Regenerated.
1092 * aarch64-opc-2.c: Regenerated.
1093
e409955d
FS		 10942020-04-17 Fredrik Strupe <fredrik@strupe.net>
1095
1096 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1097 (print_insn_neon): Support disassembly of conditional
1098 instructions.
1099
c54a9b56
DF		 11002020-02-16 David Faust <david.faust@oracle.com>
1101
1102 * bpf-desc.c: Regenerate.
1103 * bpf-desc.h: Likewise.
1104 * bpf-opc.c: Regenerate.
1105 * bpf-opc.h: Likewise.
1106
bb651e8b
CL		 11072020-04-07 Lili Cui <lili.cui@intel.com>
1108
1109 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1110 (prefix_table): New instructions (see prefixes above).
1111 (rm_table): Likewise
1112 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1113 CPU_ANY_TSXLDTRK_FLAGS.
1114 (cpu_flags): Add CpuTSXLDTRK.
1115 * i386-opc.h (enum): Add CpuTSXLDTRK.
1116 (i386_cpu_flags): Add cputsxldtrk.
1117 * i386-opc.tbl: Add XSUSPLDTRK insns.
1118 * i386-init.h: Regenerate.
1119 * i386-tbl.h: Likewise.
1120
4b27d27c
L		 11212020-04-02 Lili Cui <lili.cui@intel.com>
1122
1123 * i386-dis.c (prefix_table): New instructions serialize.
1124 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1125 CPU_ANY_SERIALIZE_FLAGS.
1126 (cpu_flags): Add CpuSERIALIZE.
1127 * i386-opc.h (enum): Add CpuSERIALIZE.
1128 (i386_cpu_flags): Add cpuserialize.
1129 * i386-opc.tbl: Add SERIALIZE insns.
1130 * i386-init.h: Regenerate.
1131 * i386-tbl.h: Likewise.
1132
832a5807
AM		 11332020-03-26 Alan Modra <amodra@gmail.com>
1134
1135 * disassemble.h (opcodes_assert): Declare.
1136 (OPCODES_ASSERT): Define.
1137 * disassemble.c: Don't include assert.h. Include opintl.h.
1138 (opcodes_assert): New function.
1139 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1140 (bfd_h8_disassemble): Reduce size of data array. Correctly
1141 calculate maxlen. Omit insn decoding when insn length exceeds
1142 maxlen. Exit from nibble loop when looking for E, before
1143 accessing next data byte. Move processing of E outside loop.
1144 Replace tests of maxlen in loop with assertions.
1145
4c4addbe
AM		 11462020-03-26 Alan Modra <amodra@gmail.com>
1147
1148 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1149
a18cd0ca
AM		 11502020-03-25 Alan Modra <amodra@gmail.com>
1151
1152 * z80-dis.c (suffix): Init mybuf.
1153
57cb32b3
AM		 11542020-03-22 Alan Modra <amodra@gmail.com>
1155
1156 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1157 successflly read from section.
1158
beea5cc1
AM		 11592020-03-22 Alan Modra <amodra@gmail.com>
1160
1161 * arc-dis.c (find_format): Use ISO C string concatenation rather
1162 than line continuation within a string. Don't access needs_limm
1163 before testing opcode != NULL.
1164
03704c77
AM		 11652020-03-22 Alan Modra <amodra@gmail.com>
1166
1167 * ns32k-dis.c (print_insn_arg): Update comment.
1168 (print_insn_ns32k): Reduce size of index_offset array, and
1169 initialize, passing -1 to print_insn_arg for args that are not
1170 an index. Don't exit arg loop early. Abort on bad arg number.
1171
d1023b5d
AM		 11722020-03-22 Alan Modra <amodra@gmail.com>
1173
1174 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1175 * s12z-opc.c: Formatting.
1176 (operands_f): Return an int.
1177 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1178 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1179 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1180 (exg_sex_discrim): Likewise.
1181 (create_immediate_operand, create_bitfield_operand),
1182 (create_register_operand_with_size, create_register_all_operand),
1183 (create_register_all16_operand, create_simple_memory_operand),
1184 (create_memory_operand, create_memory_auto_operand): Don't
1185 segfault on malloc failure.
1186 (z_ext24_decode): Return an int status, negative on fail, zero
1187 on success.
1188 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1189 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1190 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1191 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1192 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1193 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1194 (loop_primitive_decode, shift_decode, psh_pul_decode),
1195 (bit_field_decode): Similarly.
1196 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1197 to return value, update callers.
1198 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1199 Don't segfault on NULL operand.
1200 (decode_operation): Return OP_INVALID on first fail.
1201 (decode_s12z): Check all reads, returning -1 on fail.
1202
340f3ac8
AM		 12032020-03-20 Alan Modra <amodra@gmail.com>
1204
1205 * metag-dis.c (print_insn_metag): Don't ignore status from
1206 read_memory_func.
1207
fe90ae8a
AM		 12082020-03-20 Alan Modra <amodra@gmail.com>
1209
1210 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1211 Initialize parts of buffer not written when handling a possible
1212 2-byte insn at end of section. Don't attempt decoding of such
1213 an insn by the 4-byte machinery.
1214
833d919c
AM		 12152020-03-20 Alan Modra <amodra@gmail.com>
1216
1217 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1218 partially filled buffer. Prevent lookup of 4-byte insns when
1219 only VLE 2-byte insns are possible due to section size. Print
1220 ".word" rather than ".long" for 2-byte leftovers.
1221
327ef784
NC		 12222020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1223
1224 PR 25641
1225 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1226
1673df32
JB		 12272020-03-13 Jan Beulich <jbeulich@suse.com>
1228
1229 * i386-dis.c (X86_64_0D): Rename to ...
1230 (X86_64_0E): ... this.
1231
384f3689
L		 12322020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1233
1234 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1235 * Makefile.in: Regenerated.
1236
865e2027
JB		 12372020-03-09 Jan Beulich <jbeulich@suse.com>
1238
1239 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1240 3-operand pseudos.
1241 * i386-tbl.h: Re-generate.
1242
2f13234b
JB		 12432020-03-09 Jan Beulich <jbeulich@suse.com>
1244
1245 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1246 vprot*, vpsha*, and vpshl*.
1247 * i386-tbl.h: Re-generate.
1248
3fabc179
JB		 12492020-03-09 Jan Beulich <jbeulich@suse.com>
1250
1251 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1252 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1253 * i386-tbl.h: Re-generate.
1254
3677e4c1
JB		 12552020-03-09 Jan Beulich <jbeulich@suse.com>
1256
1257 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1258 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1259 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1260 * i386-tbl.h: Re-generate.
1261
4c4898e8
JB		 12622020-03-09 Jan Beulich <jbeulich@suse.com>
1263
1264 * i386-gen.c (struct template_arg, struct template_instance,
1265 struct template_param, struct template, templates,
1266 parse_template, expand_templates): New.
1267 (process_i386_opcodes): Various local variables moved to
1268 expand_templates. Call parse_template and expand_templates.
1269 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1270 * i386-tbl.h: Re-generate.
1271
bc49bfd8
JB		 12722020-03-06 Jan Beulich <jbeulich@suse.com>
1273
1274 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1275 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1276 register and memory source templates. Replace VexW= by VexW*
1277 where applicable.
1278 * i386-tbl.h: Re-generate.
1279
4873e243
JB		 12802020-03-06 Jan Beulich <jbeulich@suse.com>
1281
1282 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1283 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1284 * i386-tbl.h: Re-generate.
1285
672a349b
JB		 12862020-03-06 Jan Beulich <jbeulich@suse.com>
1287
1288 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1289 * i386-tbl.h: Re-generate.
1290
4ed21b58
JB		 12912020-03-06 Jan Beulich <jbeulich@suse.com>
1292
1293 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1294 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1295 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1296 VexW0 on SSE2AVX variants.
1297 (vmovq): Drop NoRex64 from XMM/XMM variants.
1298 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1299 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1300 applicable use VexW0.
1301 * i386-tbl.h: Re-generate.
1302
643bb870
JB		 13032020-03-06 Jan Beulich <jbeulich@suse.com>
1304
1305 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1306 * i386-opc.h (Rex64): Delete.
1307 (struct i386_opcode_modifier): Remove rex64 field.
1308 * i386-opc.tbl (crc32): Drop Rex64.
1309 Replace Rex64 with Size64 everywhere else.
1310 * i386-tbl.h: Re-generate.
1311
a23b33b3
JB		 13122020-03-06 Jan Beulich <jbeulich@suse.com>
1313
1314 * i386-dis.c (OP_E_memory): Exclude recording of used address
1315 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1316 addressed memory operands for MPX insns.
1317
a0497384
JB		 13182020-03-06 Jan Beulich <jbeulich@suse.com>
1319
1320 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1321 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1322 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1323 (ptwrite): Split into non-64-bit and 64-bit forms.
1324 * i386-tbl.h: Re-generate.
1325
b630c145
JB		 13262020-03-06 Jan Beulich <jbeulich@suse.com>
1327
1328 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1329 template.
1330 * i386-tbl.h: Re-generate.
1331
a847e322
JB		 13322020-03-04 Jan Beulich <jbeulich@suse.com>
1333
1334 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1335 (prefix_table): Move vmmcall here. Add vmgexit.
1336 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1337 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1338 (cpu_flags): Add CpuSEV_ES entry.
1339 * i386-opc.h (CpuSEV_ES): New.
1340 (union i386_cpu_flags): Add cpusev_es field.
1341 * i386-opc.tbl (vmgexit): New.
1342 * i386-init.h, i386-tbl.h: Re-generate.
1343
3cd7f3e3
L		 13442020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1345
1346 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1347 with MnemonicSize.
1348 * i386-opc.h (IGNORESIZE): New.
1349 (DEFAULTSIZE): Likewise.
1350 (IgnoreSize): Removed.
1351 (DefaultSize): Likewise.
1352 (MnemonicSize): New.
1353 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1354 mnemonicsize.
1355 * i386-opc.tbl (IgnoreSize): New.
1356 (DefaultSize): Likewise.
1357 * i386-tbl.h: Regenerated.
1358
b8ba1385
SB		 13592020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1360
1361 PR 25627
1362 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1363 instructions.
1364
10d97a0f
L		 13652020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1366
1367 PR gas/25622
1368 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1369 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1370 * i386-tbl.h: Regenerated.
1371
dc1e8a47
AM		 13722020-02-26 Alan Modra <amodra@gmail.com>
1373
1374 * aarch64-asm.c: Indent labels correctly.
1375 * aarch64-dis.c: Likewise.
1376 * aarch64-gen.c: Likewise.
1377 * aarch64-opc.c: Likewise.
1378 * alpha-dis.c: Likewise.
1379 * i386-dis.c: Likewise.
1380 * nds32-asm.c: Likewise.
1381 * nfp-dis.c: Likewise.
1382 * visium-dis.c: Likewise.
1383
265b4673
CZ		 13842020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1385
1386 * arc-regs.h (int_vector_base): Make it available for all ARC
1387 CPUs.
1388
bd0cf5a6
NC		 13892020-02-20 Nelson Chu <nelson.chu@sifive.com>
1390
1391 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1392 changed.
1393
fa164239
JW		 13942020-02-19 Nelson Chu <nelson.chu@sifive.com>
1395
1396 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1397 c.mv/c.li if rs1 is zero.
1398
272a84b1
L		 13992020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1400
1401 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1402 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1403 CPU_POPCNT_FLAGS.
1404 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1405 * i386-opc.h (CpuABM): Removed.
1406 (CpuPOPCNT): New.
1407 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1408 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1409 popcnt. Remove CpuABM from lzcnt.
1410 * i386-init.h: Regenerated.
1411 * i386-tbl.h: Likewise.
1412
1f730c46
JB		 14132020-02-17 Jan Beulich <jbeulich@suse.com>
1414
1415 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1416 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1417 VexW1 instead of open-coding them.
1418 * i386-tbl.h: Re-generate.
1419
c8f8eebc
JB		 14202020-02-17 Jan Beulich <jbeulich@suse.com>
1421
1422 * i386-opc.tbl (AddrPrefixOpReg): Define.
1423 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1424 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1425 templates. Drop NoRex64.
1426 * i386-tbl.h: Re-generate.
1427
b9915cbc
JB		 14282020-02-17 Jan Beulich <jbeulich@suse.com>
1429
1430 PR gas/6518
1431 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1432 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1433 into Intel syntax instance (with Unpsecified) and AT&T one
1434 (without).
1435 (vcvtneps2bf16): Likewise, along with folding the two so far
1436 separate ones.
1437 * i386-tbl.h: Re-generate.
1438
ce504911
L		 14392020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1440
1441 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1442 CPU_ANY_SSE4A_FLAGS.
1443
dabec65d
AM		 14442020-02-17 Alan Modra <amodra@gmail.com>
1445
1446 * i386-gen.c (cpu_flag_init): Correct last change.
1447
af5c13b0
L		 14482020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1449
1450 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1451 CPU_ANY_SSE4_FLAGS.
1452
6867aac0
L		 14532020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1454
1455 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1456 (movzx): Likewise.
1457
65fca059
JB		 14582020-02-14 Jan Beulich <jbeulich@suse.com>
1459
1460 PR gas/25438
1461 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1462 destination for Cpu64-only variant.
1463 (movzx): Fold patterns.
1464 * i386-tbl.h: Re-generate.
1465
7deea9aa
JB		 14662020-02-13 Jan Beulich <jbeulich@suse.com>
1467
1468 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1469 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1470 CPU_ANY_SSE4_FLAGS entry.
1471 * i386-init.h: Re-generate.
1472
6c0946d0
JB		 14732020-02-12 Jan Beulich <jbeulich@suse.com>
1474
1475 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1476 with Unspecified, making the present one AT&T syntax only.
1477 * i386-tbl.h: Re-generate.
1478
ddb56fe6
JB		 14792020-02-12 Jan Beulich <jbeulich@suse.com>
1480
1481 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1482 * i386-tbl.h: Re-generate.
1483
5990e377
JB		 14842020-02-12 Jan Beulich <jbeulich@suse.com>
1485
1486 PR gas/24546
1487 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1488 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1489 Amd64 and Intel64 templates.
1490 (call, jmp): Likewise for far indirect variants. Dro
1491 Unspecified.
1492 * i386-tbl.h: Re-generate.
1493
50128d0c
JB		 14942020-02-11 Jan Beulich <jbeulich@suse.com>
1495
1496 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1497 * i386-opc.h (ShortForm): Delete.
1498 (struct i386_opcode_modifier): Remove shortform field.
1499 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1500 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1501 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1502 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1503 Drop ShortForm.
1504 * i386-tbl.h: Re-generate.
1505
1e05b5c4
JB		 15062020-02-11 Jan Beulich <jbeulich@suse.com>
1507
1508 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1509 fucompi): Drop ShortForm from operand-less templates.
1510 * i386-tbl.h: Re-generate.
1511
2f5dd314
AM		 15122020-02-11 Alan Modra <amodra@gmail.com>
1513
1514 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1515 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1516 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1517 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1518 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1519
5aae9ae9
MM		 15202020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1521
1522 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1523 (cde_opcodes): Add VCX* instructions.
1524
4934a27c
MM		 15252020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1526 Matthew Malcomson <matthew.malcomson@arm.com>
1527
1528 * arm-dis.c (struct cdeopcode32): New.
1529 (CDE_OPCODE): New macro.
1530 (cde_opcodes): New disassembly table.
1531 (regnames): New option to table.
1532 (cde_coprocs): New global variable.
1533 (print_insn_cde): New
1534 (print_insn_thumb32): Use print_insn_cde.
1535 (parse_arm_disassembler_options): Parse coprocN args.
1536
4b5aaf5f
L		 15372020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1538
1539 PR gas/25516
1540 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1541 with ISA64.
1542 * i386-opc.h (AMD64): Removed.
1543 (Intel64): Likewose.
1544 (AMD64): New.
1545 (INTEL64): Likewise.
1546 (INTEL64ONLY): Likewise.
1547 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1548 * i386-opc.tbl (Amd64): New.
1549 (Intel64): Likewise.
1550 (Intel64Only): Likewise.
1551 Replace AMD64 with Amd64. Update sysenter/sysenter with
1552 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1553 * i386-tbl.h: Regenerated.
1554
9fc0b501
SB		 15552020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1556
1557 PR 25469
1558 * z80-dis.c: Add support for GBZ80 opcodes.
1559
c5d7be0c
AM		 15602020-02-04 Alan Modra <amodra@gmail.com>
1561
1562 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1563
44e4546f
AM		 15642020-02-03 Alan Modra <amodra@gmail.com>
1565
1566 * m32c-ibld.c: Regenerate.
1567
b2b1453a
AM		 15682020-02-01 Alan Modra <amodra@gmail.com>
1569
1570 * frv-ibld.c: Regenerate.
1571
4102be5c
JB		 15722020-01-31 Jan Beulich <jbeulich@suse.com>
1573
1574 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1575 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1576 (OP_E_memory): Replace xmm_mdq_mode case label by
1577 vex_scalar_w_dq_mode one.
1578 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1579
825bd36c
JB		 15802020-01-31 Jan Beulich <jbeulich@suse.com>
1581
1582 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1583 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1584 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1585 (intel_operand_size): Drop vex_w_dq_mode case label.
1586
c3036ed0
RS		 15872020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1588
1589 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1590 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1591
0c115f84
AM		 15922020-01-30 Alan Modra <amodra@gmail.com>
1593
1594 * m32c-ibld.c: Regenerate.
1595
bd434cc4
JM		 15962020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1597
1598 * bpf-opc.c: Regenerate.
1599
aeab2b26
JB		 16002020-01-30 Jan Beulich <jbeulich@suse.com>
1601
1602 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1603 (dis386): Use them to replace C2/C3 table entries.
1604 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1605 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1606 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1607 * i386-tbl.h: Re-generate.
1608
62b3f548
JB		 16092020-01-30 Jan Beulich <jbeulich@suse.com>
1610
1611 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1612 forms.
1613 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1614 DefaultSize.
1615 * i386-tbl.h: Re-generate.
1616
1bd8ae10
AM		 16172020-01-30 Alan Modra <amodra@gmail.com>
1618
1619 * tic4x-dis.c (tic4x_dp): Make unsigned.
1620
bc31405e
L		 16212020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1622 Jan Beulich <jbeulich@suse.com>
1623
1624 PR binutils/25445
1625 * i386-dis.c (MOVSXD_Fixup): New function.
1626 (movsxd_mode): New enum.
1627 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1628 (intel_operand_size): Handle movsxd_mode.
1629 (OP_E_register): Likewise.
1630 (OP_G): Likewise.
1631 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1632 register on movsxd. Add movsxd with 16-bit destination register
1633 for AMD64 and Intel64 ISAs.
1634 * i386-tbl.h: Regenerated.
1635
7568c93b
TC		 16362020-01-27 Tamar Christina <tamar.christina@arm.com>
1637
1638 PR 25403
1639 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1640 * aarch64-asm-2.c: Regenerate
1641 * aarch64-dis-2.c: Likewise.
1642 * aarch64-opc-2.c: Likewise.
1643
c006a730
JB		 16442020-01-21 Jan Beulich <jbeulich@suse.com>
1645
1646 * i386-opc.tbl (sysret): Drop DefaultSize.
1647 * i386-tbl.h: Re-generate.
1648
c906a69a
JB		 16492020-01-21 Jan Beulich <jbeulich@suse.com>
1650
1651 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1652 Dword.
1653 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1654 * i386-tbl.h: Re-generate.
1655
26916852
NC		 16562020-01-20 Nick Clifton <nickc@redhat.com>
1657
1658 * po/de.po: Updated German translation.
1659 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1660 * po/uk.po: Updated Ukranian translation.
1661
4d6cbb64
AM		 16622020-01-20 Alan Modra <amodra@gmail.com>
1663
1664 * hppa-dis.c (fput_const): Remove useless cast.
1665
2bddb71a
AM		 16662020-01-20 Alan Modra <amodra@gmail.com>
1667
1668 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1669
1b1bb2c6
NC		 16702020-01-18 Nick Clifton <nickc@redhat.com>
1671
1672 * configure: Regenerate.
1673 * po/opcodes.pot: Regenerate.
1674
ae774686
NC		 16752020-01-18 Nick Clifton <nickc@redhat.com>
1676
1677 Binutils 2.34 branch created.
1678
07f1f3aa
CB		 16792020-01-17 Christian Biesinger <cbiesinger@google.com>
1680
1681 * opintl.h: Fix spelling error (seperate).
1682
42e04b36
L		 16832020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1684
1685 * i386-opc.tbl: Add {vex} pseudo prefix.
1686 * i386-tbl.h: Regenerated.
1687
2da2eaf4
AV		 16882020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1689
1690 PR 25376
1691 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1692 (neon_opcodes): Likewise.
1693 (select_arm_features): Make sure we enable MVE bits when selecting
1694 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1695 any architecture.
1696
d0849eed
JB		 16972020-01-16 Jan Beulich <jbeulich@suse.com>
1698
1699 * i386-opc.tbl: Drop stale comment from XOP section.
1700
9cf70a44
JB		 17012020-01-16 Jan Beulich <jbeulich@suse.com>
1702
1703 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1704 (extractps): Add VexWIG to SSE2AVX forms.
1705 * i386-tbl.h: Re-generate.
1706
4814632e
JB		 17072020-01-16 Jan Beulich <jbeulich@suse.com>
1708
1709 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1710 Size64 from and use VexW1 on SSE2AVX forms.
1711 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1712 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1713 * i386-tbl.h: Re-generate.
1714
aad09917
AM		 17152020-01-15 Alan Modra <amodra@gmail.com>
1716
1717 * tic4x-dis.c (tic4x_version): Make unsigned long.
1718 (optab, optab_special, registernames): New file scope vars.
1719 (tic4x_print_register): Set up registernames rather than
1720 malloc'd registertable.
1721 (tic4x_disassemble): Delete optable and optable_special. Use
1722 optab and optab_special instead. Throw away old optab,
1723 optab_special and registernames when info->mach changes.
1724
7a6bf3be
SB		 17252020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1726
1727 PR 25377
1728 * z80-dis.c (suffix): Use .db instruction to generate double
1729 prefix.
1730
ca1eaac0
AM		 17312020-01-14 Alan Modra <amodra@gmail.com>
1732
1733 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1734 values to unsigned before shifting.
1735
1d67fe3b
TT		 17362020-01-13 Thomas Troeger <tstroege@gmx.de>
1737
1738 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1739 flow instructions.
1740 (print_insn_thumb16, print_insn_thumb32): Likewise.
1741 (print_insn): Initialize the insn info.
1742 * i386-dis.c (print_insn): Initialize the insn info fields, and
1743 detect jumps.
1744
5e4f7e05
CZ		 17452012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1746
1747 * arc-opc.c (C_NE): Make it required.
1748
b9fe6b8a
CZ		 17492012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1750
1751 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1752 reserved register name.
1753
90dee485
AM		 17542020-01-13 Alan Modra <amodra@gmail.com>
1755
1756 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1757 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1758
febda64f
AM		 17592020-01-13 Alan Modra <amodra@gmail.com>
1760
1761 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1762 result of wasm_read_leb128 in a uint64_t and check that bits
1763 are not lost when copying to other locals. Use uint32_t for
1764 most locals. Use PRId64 when printing int64_t.
1765
df08b588
AM		 17662020-01-13 Alan Modra <amodra@gmail.com>
1767
1768 * score-dis.c: Formatting.
1769 * score7-dis.c: Formatting.
1770
b2c759ce
AM		 17712020-01-13 Alan Modra <amodra@gmail.com>
1772
1773 * score-dis.c (print_insn_score48): Use unsigned variables for
1774 unsigned values. Don't left shift negative values.
1775 (print_insn_score32): Likewise.
1776 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1777
5496abe1
AM		 17782020-01-13 Alan Modra <amodra@gmail.com>
1779
1780 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1781
202e762b
AM		 17822020-01-13 Alan Modra <amodra@gmail.com>
1783
1784 * fr30-ibld.c: Regenerate.
1785
7ef412cf
AM		 17862020-01-13 Alan Modra <amodra@gmail.com>
1787
1788 * xgate-dis.c (print_insn): Don't left shift signed value.
1789 (ripBits): Formatting, use 1u.
1790
7f578b95
AM		 17912020-01-10 Alan Modra <amodra@gmail.com>
1792
1793 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1794 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1795
441af85b
AM		 17962020-01-10 Alan Modra <amodra@gmail.com>
1797
1798 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1799 and XRREG value earlier to avoid a shift with negative exponent.
1800 * m10200-dis.c (disassemble): Similarly.
1801
bce58db4
NC		 18022020-01-09 Nick Clifton <nickc@redhat.com>
1803
1804 PR 25224
1805 * z80-dis.c (ld_ii_ii): Use correct cast.
1806
40c75bc8
SB		 18072020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1808
1809 PR 25224
1810 * z80-dis.c (ld_ii_ii): Use character constant when checking
1811 opcode byte value.
1812
d835a58b
JB		 18132020-01-09 Jan Beulich <jbeulich@suse.com>
1814
1815 * i386-dis.c (SEP_Fixup): New.
1816 (SEP): Define.
1817 (dis386_twobyte): Use it for sysenter/sysexit.
1818 (enum x86_64_isa): Change amd64 enumerator to value 1.
1819 (OP_J): Compare isa64 against intel64 instead of amd64.
1820 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1821 forms.
1822 * i386-tbl.h: Re-generate.
1823
030a2e78
AM		 18242020-01-08 Alan Modra <amodra@gmail.com>
1825
1826 * z8k-dis.c: Include libiberty.h
1827 (instr_data_s): Make max_fetched unsigned.
1828 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1829 Don't exceed byte_info bounds.
1830 (output_instr): Make num_bytes unsigned.
1831 (unpack_instr): Likewise for nibl_count and loop.
1832 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1833 idx unsigned.
1834 * z8k-opc.h: Regenerate.
1835
bb82aefe
SV		 18362020-01-07 Shahab Vahedi <shahab@synopsys.com>
1837
1838 * arc-tbl.h (llock): Use 'LLOCK' as class.
1839 (llockd): Likewise.
1840 (scond): Use 'SCOND' as class.
1841 (scondd): Likewise.
1842 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1843 (scondd): Likewise.
1844
cc6aa1a6
AM		 18452020-01-06 Alan Modra <amodra@gmail.com>
1846
1847 * m32c-ibld.c: Regenerate.
1848
660e62b1
AM		 18492020-01-06 Alan Modra <amodra@gmail.com>
1850
1851 PR 25344
1852 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1853 Peek at next byte to prevent recursion on repeated prefix bytes.
1854 Ensure uninitialised "mybuf" is not accessed.
1855 (print_insn_z80): Don't zero n_fetch and n_used here,..
1856 (print_insn_z80_buf): ..do it here instead.
1857
c9ae58fe
AM		 18582020-01-04 Alan Modra <amodra@gmail.com>
1859
1860 * m32r-ibld.c: Regenerate.
1861
5f57d4ec
AM		 18622020-01-04 Alan Modra <amodra@gmail.com>
1863
1864 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1865
2c5c1196
AM		 18662020-01-04 Alan Modra <amodra@gmail.com>
1867
1868 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1869
2e98c6c5
AM		 18702020-01-04 Alan Modra <amodra@gmail.com>
1871
1872 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1873
567dfba2
JB		 18742020-01-03 Jan Beulich <jbeulich@suse.com>
1875
5437a02a
JB		 1876 * aarch64-tbl.h (aarch64_opcode_table): Use
1877 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1878
18792020-01-03 Jan Beulich <jbeulich@suse.com>
1880
1881 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1882 forms of SUDOT and USDOT.
1883
8c45011a
JB		 18842020-01-03 Jan Beulich <jbeulich@suse.com>
1885
5437a02a 1886 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1887 uzip{1,2}.
1888 * opcodes/aarch64-dis-2.c: Re-generate.
1889
f4950f76
JB		 18902020-01-03 Jan Beulich <jbeulich@suse.com>
1891
5437a02a 1892 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1893 FMMLA encoding.
1894 * opcodes/aarch64-dis-2.c: Re-generate.
1895
6655dba2
SB		 18962020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1897
1898 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1899
b14ce8bf
AM		 19002020-01-01 Alan Modra <amodra@gmail.com>
1901
1902 Update year range in copyright notice of all files.
1903
0b114740 1904For older changes see ChangeLog-2019
3499769a 1905\f
0b114740 1906Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1907
1908Copying and distribution of this file, with or without modification,
1909are permitted in any medium without royalty provided the copyright
1910notice and this notice are preserved.
1911
1912Local Variables:
1913mode: change-log
1914left-margin: 8
1915fill-column: 74
1916version-control: never
1917End:
GDB Binutils - Deliverables
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