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RISC-V: Report warning when linking the objects with different priv specs.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
39ff0b81
NC		 12020-06-22 Nelson Chu <nelson.chu@sifive.com>
2
3 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
4 * riscv-dis.c: Include elfxx-riscv.h.
5
d27c357a
JB		 62020-06-18 H.J. Lu <hongjiu.lu@intel.com>
7
8 * i386-dis.c (prefix_table): Revert the last vmgexit change.
9
6fde587f
CL		 102020-06-17 Lili Cui <lili.cui@intel.com>
11
12 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
13
efe30057
L		 142020-06-14 H.J. Lu <hongjiu.lu@intel.com>
15
16 PR gas/26115
17 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
18 * i386-opc.tbl: Likewise.
19 * i386-tbl.h: Regenerated.
20
d8af286f
NC		 212020-06-12 Nelson Chu <nelson.chu@sifive.com>
22
23 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
24
14962256
AC		 252020-06-11 Alex Coplan <alex.coplan@arm.com>
26
27 * aarch64-opc.c (SYSREG): New macro for describing system registers.
28 (SR_CORE): Likewise.
29 (SR_FEAT): Likewise.
30 (SR_RNG): Likewise.
31 (SR_V8_1): Likewise.
32 (SR_V8_2): Likewise.
33 (SR_V8_3): Likewise.
34 (SR_V8_4): Likewise.
35 (SR_PAN): Likewise.
36 (SR_RAS): Likewise.
37 (SR_SSBS): Likewise.
38 (SR_SVE): Likewise.
39 (SR_ID_PFR2): Likewise.
40 (SR_PROFILE): Likewise.
41 (SR_MEMTAG): Likewise.
42 (SR_SCXTNUM): Likewise.
43 (aarch64_sys_regs): Refactor to store feature information in the table.
44 (aarch64_sys_reg_supported_p): Collapse logic for system registers
45 that now describe their own features.
46 (aarch64_pstatefield_supported_p): Likewise.
47
f9630fa6
L		 482020-06-09 H.J. Lu <hongjiu.lu@intel.com>
49
50 * i386-dis.c (prefix_table): Fix a typo in comments.
51
73239888
JB		 522020-06-09 Jan Beulich <jbeulich@suse.com>
53
54 * i386-dis.c (rex_ignored): Delete.
55 (ckprefix): Drop rex_ignored initialization.
56 (get_valid_dis386): Drop setting of rex_ignored.
57 (print_insn): Drop checking of rex_ignored. Don't record data
58 size prefix as used with VEX-and-alike encodings.
59
18897deb
JB		 602020-06-09 Jan Beulich <jbeulich@suse.com>
61
62 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
63 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
64 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
65 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
66 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
67 VEX_0F12, and VEX_0F16.
68 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
69 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
70 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
71 from movlps and movhlps. New MOD_0F12_PREFIX_2,
72 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
73 MOD_VEX_0F16_PREFIX_2 entries.
74
97e6786a
JB		 752020-06-09 Jan Beulich <jbeulich@suse.com>
76
77 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
78 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
79 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
80 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
81 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
82 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
83 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
84 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
85 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
86 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
87 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
88 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
89 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
90 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
91 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
92 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
93 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
94 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
95 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
96 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
97 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
98 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
99 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
100 EVEX_W_0FC6_P_2): Delete.
101 (print_insn): Add EVEX.W vs embedded prefix consistency check
102 to prefix validation.
103 * i386-dis-evex.h (evex_table): Don't further descend for
104 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
105 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
106 and 0F2B.
107 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
108 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
109 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
110 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
111 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
112 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
113 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
114 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
115 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
116 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
117 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
118 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
119 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
120 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
121 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
122 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
123 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
124 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
125 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
126 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
127 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
128 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
129 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
130 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
131 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
132 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
133 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
134
bf926894
JB		 1352020-06-09 Jan Beulich <jbeulich@suse.com>
136
137 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
138 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
139 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
140 vmovmskpX.
141 (print_insn): Drop pointless check against bad_opcode. Split
142 prefix validation into legacy and VEX-and-alike parts.
143 (putop): Re-work 'X' macro handling.
144
a5aaedb9
JB		 1452020-06-09 Jan Beulich <jbeulich@suse.com>
146
147 * i386-dis.c (MOD_0F51): Rename to ...
148 (MOD_0F50): ... this.
149
26417f19
AC		 1502020-06-08 Alex Coplan <alex.coplan@arm.com>
151
152 * arm-dis.c (arm_opcodes): Add dfb.
153 (thumb32_opcodes): Add dfb.
154
8a6fb3f9
JB		 1552020-06-08 Jan Beulich <jbeulich@suse.com>
156
157 * i386-opc.h (reg_entry): Const-qualify reg_name field.
158
1424c35d
AM		 1592020-06-06 Alan Modra <amodra@gmail.com>
160
161 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
162
d3d1cc7b
AM		 1632020-06-05 Alan Modra <amodra@gmail.com>
164
165 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
166 size is large enough.
167
d8740be1
JM		 1682020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
169
170 * disassemble.c (disassemble_init_for_target): Set endian_code for
171 bpf targets.
172 * bpf-desc.c: Regenerate.
173 * bpf-opc.c: Likewise.
174 * bpf-dis.c: Likewise.
175
e9bffec9
JM		 1762020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
177
178 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
179 (cgen_put_insn_value): Likewise.
180 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
181 * cgen-dis.in (print_insn): Likewise.
182 * cgen-ibld.in (insert_1): Likewise.
183 (insert_1): Likewise.
184 (insert_insn_normal): Likewise.
185 (extract_1): Likewise.
186 * bpf-dis.c: Regenerate.
187 * bpf-ibld.c: Likewise.
188 * bpf-ibld.c: Likewise.
189 * cgen-dis.in: Likewise.
190 * cgen-ibld.in: Likewise.
191 * cgen-opc.c: Likewise.
192 * epiphany-dis.c: Likewise.
193 * epiphany-ibld.c: Likewise.
194 * fr30-dis.c: Likewise.
195 * fr30-ibld.c: Likewise.
196 * frv-dis.c: Likewise.
197 * frv-ibld.c: Likewise.
198 * ip2k-dis.c: Likewise.
199 * ip2k-ibld.c: Likewise.
200 * iq2000-dis.c: Likewise.
201 * iq2000-ibld.c: Likewise.
202 * lm32-dis.c: Likewise.
203 * lm32-ibld.c: Likewise.
204 * m32c-dis.c: Likewise.
205 * m32c-ibld.c: Likewise.
206 * m32r-dis.c: Likewise.
207 * m32r-ibld.c: Likewise.
208 * mep-dis.c: Likewise.
209 * mep-ibld.c: Likewise.
210 * mt-dis.c: Likewise.
211 * mt-ibld.c: Likewise.
212 * or1k-dis.c: Likewise.
213 * or1k-ibld.c: Likewise.
214 * xc16x-dis.c: Likewise.
215 * xc16x-ibld.c: Likewise.
216 * xstormy16-dis.c: Likewise.
217 * xstormy16-ibld.c: Likewise.
218
b3db6d07
JM		 2192020-06-04 Jose E. Marchesi <jemarch@gnu.org>
220
221 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
222 (print_insn_): Handle instruction endian.
223 * bpf-dis.c: Regenerate.
224 * bpf-desc.c: Regenerate.
225 * epiphany-dis.c: Likewise.
226 * epiphany-desc.c: Likewise.
227 * fr30-dis.c: Likewise.
228 * fr30-desc.c: Likewise.
229 * frv-dis.c: Likewise.
230 * frv-desc.c: Likewise.
231 * ip2k-dis.c: Likewise.
232 * ip2k-desc.c: Likewise.
233 * iq2000-dis.c: Likewise.
234 * iq2000-desc.c: Likewise.
235 * lm32-dis.c: Likewise.
236 * lm32-desc.c: Likewise.
237 * m32c-dis.c: Likewise.
238 * m32c-desc.c: Likewise.
239 * m32r-dis.c: Likewise.
240 * m32r-desc.c: Likewise.
241 * mep-dis.c: Likewise.
242 * mep-desc.c: Likewise.
243 * mt-dis.c: Likewise.
244 * mt-desc.c: Likewise.
245 * or1k-dis.c: Likewise.
246 * or1k-desc.c: Likewise.
247 * xc16x-dis.c: Likewise.
248 * xc16x-desc.c: Likewise.
249 * xstormy16-dis.c: Likewise.
250 * xstormy16-desc.c: Likewise.
251
4ee4189f
NC		 2522020-06-03 Nick Clifton <nickc@redhat.com>
253
254 * po/sr.po: Updated Serbian translation.
255
44730156
NC		 2562020-06-03 Nelson Chu <nelson.chu@sifive.com>
257
258 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
259 (riscv_get_priv_spec_class): Likewise.
260
3c3d0376
AM		 2612020-06-01 Alan Modra <amodra@gmail.com>
262
263 * bpf-desc.c: Regenerate.
264
78c1c354
JM		 2652020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
266 David Faust <david.faust@oracle.com>
267
268 * bpf-desc.c: Regenerate.
269 * bpf-opc.h: Likewise.
270 * bpf-opc.c: Likewise.
271 * bpf-dis.c: Likewise.
272
efcf5fb5
AM		 2732020-05-28 Alan Modra <amodra@gmail.com>
274
275 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
276 values.
277
ab382d64
AM		 2782020-05-28 Alan Modra <amodra@gmail.com>
279
280 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
281 immediates.
282 (print_insn_ns32k): Revert last change.
283
151f5de4
NC		 2842020-05-28 Nick Clifton <nickc@redhat.com>
285
286 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
287 static.
288
25e1eca8
SL		 2892020-05-26 Sandra Loosemore <sandra@codesourcery.com>
290
291 Fix extraction of signed constants in nios2 disassembler (again).
292
293 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
294 extractions of signed fields.
295
57b17940
SSF		 2962020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
297
298 * s390-opc.txt: Relocate vector load/store instructions with
299 additional alignment parameter and change architecture level
300 constraint from z14 to z13.
301
d96bf37b
AM		 3022020-05-21 Alan Modra <amodra@gmail.com>
303
304 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
305 * sparc-dis.c: Likewise.
306 * tic4x-dis.c: Likewise.
307 * xtensa-dis.c: Likewise.
308 * bpf-desc.c: Regenerate.
309 * epiphany-desc.c: Regenerate.
310 * fr30-desc.c: Regenerate.
311 * frv-desc.c: Regenerate.
312 * ip2k-desc.c: Regenerate.
313 * iq2000-desc.c: Regenerate.
314 * lm32-desc.c: Regenerate.
315 * m32c-desc.c: Regenerate.
316 * m32r-desc.c: Regenerate.
317 * mep-asm.c: Regenerate.
318 * mep-desc.c: Regenerate.
319 * mt-desc.c: Regenerate.
320 * or1k-desc.c: Regenerate.
321 * xc16x-desc.c: Regenerate.
322 * xstormy16-desc.c: Regenerate.
323
8f595e9b
NC		 3242020-05-20 Nelson Chu <nelson.chu@sifive.com>
325
326 * riscv-opc.c (riscv_ext_version_table): The table used to store
327 all information about the supported spec and the corresponding ISA
328 versions. Currently, only Zicsr is supported to verify the
329 correctness of Z sub extension settings. Others will be supported
330 in the future patches.
331 (struct isa_spec_t, isa_specs): List for all supported ISA spec
332 classes and the corresponding strings.
333 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
334 spec class by giving a ISA spec string.
335 * riscv-opc.c (struct priv_spec_t): New structure.
336 (struct priv_spec_t priv_specs): List for all supported privilege spec
337 classes and the corresponding strings.
338 (riscv_get_priv_spec_class): New function. Get the corresponding
339 privilege spec class by giving a spec string.
340 (riscv_get_priv_spec_name): New function. Get the corresponding
341 privilege spec string by giving a CSR version class.
342 * riscv-dis.c: Updated since DECLARE_CSR is changed.
343 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
344 according to the chosen version. Build a hash table riscv_csr_hash to
345 store the valid CSR for the chosen pirv verison. Dump the direct
346 CSR address rather than it's name if it is invalid.
347 (parse_riscv_dis_option_without_args): New function. Parse the options
348 without arguments.
349 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
350 parse the options without arguments first, and then handle the options
351 with arguments. Add the new option -Mpriv-spec, which has argument.
352 * riscv-dis.c (print_riscv_disassembler_options): Add description
353 about the new OBJDUMP option.
354
3d205eb4
PB		 3552020-05-19 Peter Bergner <bergner@linux.ibm.com>
356
357 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
358 WC values on POWER10 sync, dcbf and wait instructions.
359 (insert_pl, extract_pl): New functions.
360 (L2OPT, LS, WC): Use insert_ls and extract_ls.
361 (LS3): New , 3-bit L for sync.
362 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
363 (SC2, PL): New, 2-bit SC and PL for sync and wait.
364 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
365 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
366 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
367 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
368 <wait>: Enable PL operand on POWER10.
369 <dcbf>: Enable L3OPT operand on POWER10.
370 <sync>: Enable SC2 operand on POWER10.
371
a501eb44
SH		 3722020-05-19 Stafford Horne <shorne@gmail.com>
373
374 PR 25184
375 * or1k-asm.c: Regenerate.
376 * or1k-desc.c: Regenerate.
377 * or1k-desc.h: Regenerate.
378 * or1k-dis.c: Regenerate.
379 * or1k-ibld.c: Regenerate.
380 * or1k-opc.c: Regenerate.
381 * or1k-opc.h: Regenerate.
382 * or1k-opinst.c: Regenerate.
383
3b646889
AM		 3842020-05-11 Alan Modra <amodra@gmail.com>
385
386 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
387 xsmaxcqp, xsmincqp.
388
9cc4ce88
AM		 3892020-05-11 Alan Modra <amodra@gmail.com>
390
391 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
392 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
393
5d57bc3f
AM		 3942020-05-11 Alan Modra <amodra@gmail.com>
395
396 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
397
66ef5847
AM		 3982020-05-11 Alan Modra <amodra@gmail.com>
399
400 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
401 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
402
4f3e9537
PB		 4032020-05-11 Peter Bergner <bergner@linux.ibm.com>
404
405 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
406 mnemonics.
407
ec40e91c
AM		 4082020-05-11 Alan Modra <amodra@gmail.com>
409
410 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
411 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
412 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
413 (prefix_opcodes): Add xxeval.
414
d7e97a76
AM		 4152020-05-11 Alan Modra <amodra@gmail.com>
416
417 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
418 xxgenpcvwm, xxgenpcvdm.
419
fdefed7c
AM		 4202020-05-11 Alan Modra <amodra@gmail.com>
421
422 * ppc-opc.c (MP, VXVAM_MASK): Define.
423 (VXVAPS_MASK): Use VXVA_MASK.
424 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
425 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
426 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
427 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
428
aa3c112f
AM		 4292020-05-11 Alan Modra <amodra@gmail.com>
430 Peter Bergner <bergner@linux.ibm.com>
431
432 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
433 New functions.
434 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
435 YMSK2, XA6a, XA6ap, XB6a entries.
436 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
437 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
438 (PPCVSX4): Define.
439 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
440 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
441 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
442 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
443 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
444 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
445 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
446 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
447 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
448 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
449 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
450 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
451 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
452 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
453
6edbfd3b
AM		 4542020-05-11 Alan Modra <amodra@gmail.com>
455
456 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
457 (insert_xts, extract_xts): New functions.
458 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
459 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
460 (VXRC_MASK, VXSH_MASK): Define.
461 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
462 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
463 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
464 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
465 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
466 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
467 xxblendvh, xxblendvw, xxblendvd, xxpermx.
468
c7d7aea2
AM		 4692020-05-11 Alan Modra <amodra@gmail.com>
470
471 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
472 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
473 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
474 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
475 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
476
94ba9882
AM		 4772020-05-11 Alan Modra <amodra@gmail.com>
478
479 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
480 (XTP, DQXP, DQXP_MASK): Define.
481 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
482 (prefix_opcodes): Add plxvp and pstxvp.
483
f4791f1a
AM		 4842020-05-11 Alan Modra <amodra@gmail.com>
485
486 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
487 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
488 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
489
3ff0a5ba
PB		 4902020-05-11 Peter Bergner <bergner@linux.ibm.com>
491
492 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
493
afef4fe9
PB		 4942020-05-11 Peter Bergner <bergner@linux.ibm.com>
495
496 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
497 (L1OPT): Define.
498 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
499
1224c05d
PB		 5002020-05-11 Peter Bergner <bergner@linux.ibm.com>
501
502 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
503
6bbb0c05
AM		 5042020-05-11 Alan Modra <amodra@gmail.com>
505
506 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
507
7c1f4227
AM		 5082020-05-11 Alan Modra <amodra@gmail.com>
509
510 * ppc-dis.c (ppc_opts): Add "power10" entry.
511 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
512 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
513
73199c2b
NC		 5142020-05-11 Nick Clifton <nickc@redhat.com>
515
516 * po/fr.po: Updated French translation.
517
09c1e68a
AC		 5182020-04-30 Alex Coplan <alex.coplan@arm.com>
519
520 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
521 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
522 (operand_general_constraint_met_p): validate
523 AARCH64_OPND_UNDEFINED.
524 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
525 for FLD_imm16_2.
526 * aarch64-asm-2.c: Regenerated.
527 * aarch64-dis-2.c: Regenerated.
528 * aarch64-opc-2.c: Regenerated.
529
9654d51a
NC		 5302020-04-29 Nick Clifton <nickc@redhat.com>
531
532 PR 22699
533 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
534 and SETRC insns.
535
c2e71e57
NC		 5362020-04-29 Nick Clifton <nickc@redhat.com>
537
538 * po/sv.po: Updated Swedish translation.
539
5c936ef5
NC		 5402020-04-29 Nick Clifton <nickc@redhat.com>
541
542 PR 22699
543 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
544 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
545 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
546 IMM0_8U case.
547
bb2a1453
AS		 5482020-04-21 Andreas Schwab <schwab@linux-m68k.org>
549
550 PR 25848
551 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
552 cmpi only on m68020up and cpu32.
553
c2e5c986
SD		 5542020-04-20 Sudakshina Das <sudi.das@arm.com>
555
556 * aarch64-asm.c (aarch64_ins_none): New.
557 * aarch64-asm.h (ins_none): New declaration.
558 * aarch64-dis.c (aarch64_ext_none): New.
559 * aarch64-dis.h (ext_none): New declaration.
560 * aarch64-opc.c (aarch64_print_operand): Update case for
561 AARCH64_OPND_BARRIER_PSB.
562 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
563 (AARCH64_OPERANDS): Update inserter/extracter for
564 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
565 * aarch64-asm-2.c: Regenerated.
566 * aarch64-dis-2.c: Regenerated.
567 * aarch64-opc-2.c: Regenerated.
568
8a6e1d1d
SD		 5692020-04-20 Sudakshina Das <sudi.das@arm.com>
570
571 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
572 (aarch64_feature_ras, RAS): Likewise.
573 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
574 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
575 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
576 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
577 * aarch64-asm-2.c: Regenerated.
578 * aarch64-dis-2.c: Regenerated.
579 * aarch64-opc-2.c: Regenerated.
580
e409955d
FS		 5812020-04-17 Fredrik Strupe <fredrik@strupe.net>
582
583 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
584 (print_insn_neon): Support disassembly of conditional
585 instructions.
586
c54a9b56
DF		 5872020-02-16 David Faust <david.faust@oracle.com>
588
589 * bpf-desc.c: Regenerate.
590 * bpf-desc.h: Likewise.
591 * bpf-opc.c: Regenerate.
592 * bpf-opc.h: Likewise.
593
bb651e8b
CL		 5942020-04-07 Lili Cui <lili.cui@intel.com>
595
596 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
597 (prefix_table): New instructions (see prefixes above).
598 (rm_table): Likewise
599 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
600 CPU_ANY_TSXLDTRK_FLAGS.
601 (cpu_flags): Add CpuTSXLDTRK.
602 * i386-opc.h (enum): Add CpuTSXLDTRK.
603 (i386_cpu_flags): Add cputsxldtrk.
604 * i386-opc.tbl: Add XSUSPLDTRK insns.
605 * i386-init.h: Regenerate.
606 * i386-tbl.h: Likewise.
607
4b27d27c
L		 6082020-04-02 Lili Cui <lili.cui@intel.com>
609
610 * i386-dis.c (prefix_table): New instructions serialize.
611 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
612 CPU_ANY_SERIALIZE_FLAGS.
613 (cpu_flags): Add CpuSERIALIZE.
614 * i386-opc.h (enum): Add CpuSERIALIZE.
615 (i386_cpu_flags): Add cpuserialize.
616 * i386-opc.tbl: Add SERIALIZE insns.
617 * i386-init.h: Regenerate.
618 * i386-tbl.h: Likewise.
619
832a5807
AM		 6202020-03-26 Alan Modra <amodra@gmail.com>
621
622 * disassemble.h (opcodes_assert): Declare.
623 (OPCODES_ASSERT): Define.
624 * disassemble.c: Don't include assert.h. Include opintl.h.
625 (opcodes_assert): New function.
626 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
627 (bfd_h8_disassemble): Reduce size of data array. Correctly
628 calculate maxlen. Omit insn decoding when insn length exceeds
629 maxlen. Exit from nibble loop when looking for E, before
630 accessing next data byte. Move processing of E outside loop.
631 Replace tests of maxlen in loop with assertions.
632
4c4addbe
AM		 6332020-03-26 Alan Modra <amodra@gmail.com>
634
635 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
636
a18cd0ca
AM		 6372020-03-25 Alan Modra <amodra@gmail.com>
638
639 * z80-dis.c (suffix): Init mybuf.
640
57cb32b3
AM		 6412020-03-22 Alan Modra <amodra@gmail.com>
642
643 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
644 successflly read from section.
645
beea5cc1
AM		 6462020-03-22 Alan Modra <amodra@gmail.com>
647
648 * arc-dis.c (find_format): Use ISO C string concatenation rather
649 than line continuation within a string. Don't access needs_limm
650 before testing opcode != NULL.
651
03704c77
AM		 6522020-03-22 Alan Modra <amodra@gmail.com>
653
654 * ns32k-dis.c (print_insn_arg): Update comment.
655 (print_insn_ns32k): Reduce size of index_offset array, and
656 initialize, passing -1 to print_insn_arg for args that are not
657 an index. Don't exit arg loop early. Abort on bad arg number.
658
d1023b5d
AM		 6592020-03-22 Alan Modra <amodra@gmail.com>
660
661 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
662 * s12z-opc.c: Formatting.
663 (operands_f): Return an int.
664 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
665 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
666 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
667 (exg_sex_discrim): Likewise.
668 (create_immediate_operand, create_bitfield_operand),
669 (create_register_operand_with_size, create_register_all_operand),
670 (create_register_all16_operand, create_simple_memory_operand),
671 (create_memory_operand, create_memory_auto_operand): Don't
672 segfault on malloc failure.
673 (z_ext24_decode): Return an int status, negative on fail, zero
674 on success.
675 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
676 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
677 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
678 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
679 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
680 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
681 (loop_primitive_decode, shift_decode, psh_pul_decode),
682 (bit_field_decode): Similarly.
683 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
684 to return value, update callers.
685 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
686 Don't segfault on NULL operand.
687 (decode_operation): Return OP_INVALID on first fail.
688 (decode_s12z): Check all reads, returning -1 on fail.
689
340f3ac8
AM		 6902020-03-20 Alan Modra <amodra@gmail.com>
691
692 * metag-dis.c (print_insn_metag): Don't ignore status from
693 read_memory_func.
694
fe90ae8a
AM		 6952020-03-20 Alan Modra <amodra@gmail.com>
696
697 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
698 Initialize parts of buffer not written when handling a possible
699 2-byte insn at end of section. Don't attempt decoding of such
700 an insn by the 4-byte machinery.
701
833d919c
AM		 7022020-03-20 Alan Modra <amodra@gmail.com>
703
704 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
705 partially filled buffer. Prevent lookup of 4-byte insns when
706 only VLE 2-byte insns are possible due to section size. Print
707 ".word" rather than ".long" for 2-byte leftovers.
708
327ef784
NC		 7092020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
710
711 PR 25641
712 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
713
1673df32
JB		 7142020-03-13 Jan Beulich <jbeulich@suse.com>
715
716 * i386-dis.c (X86_64_0D): Rename to ...
717 (X86_64_0E): ... this.
718
384f3689
L		 7192020-03-09 H.J. Lu <hongjiu.lu@intel.com>
720
721 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
722 * Makefile.in: Regenerated.
723
865e2027
JB		 7242020-03-09 Jan Beulich <jbeulich@suse.com>
725
726 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
727 3-operand pseudos.
728 * i386-tbl.h: Re-generate.
729
2f13234b
JB		 7302020-03-09 Jan Beulich <jbeulich@suse.com>
731
732 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
733 vprot*, vpsha*, and vpshl*.
734 * i386-tbl.h: Re-generate.
735
3fabc179
JB		 7362020-03-09 Jan Beulich <jbeulich@suse.com>
737
738 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
739 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
740 * i386-tbl.h: Re-generate.
741
3677e4c1
JB		 7422020-03-09 Jan Beulich <jbeulich@suse.com>
743
744 * i386-gen.c (set_bitfield): Ignore zero-length field names.
745 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
746 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
747 * i386-tbl.h: Re-generate.
748
4c4898e8
JB		 7492020-03-09 Jan Beulich <jbeulich@suse.com>
750
751 * i386-gen.c (struct template_arg, struct template_instance,
752 struct template_param, struct template, templates,
753 parse_template, expand_templates): New.
754 (process_i386_opcodes): Various local variables moved to
755 expand_templates. Call parse_template and expand_templates.
756 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
757 * i386-tbl.h: Re-generate.
758
bc49bfd8
JB		 7592020-03-06 Jan Beulich <jbeulich@suse.com>
760
761 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
762 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
763 register and memory source templates. Replace VexW= by VexW*
764 where applicable.
765 * i386-tbl.h: Re-generate.
766
4873e243
JB		 7672020-03-06 Jan Beulich <jbeulich@suse.com>
768
769 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
770 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
771 * i386-tbl.h: Re-generate.
772
672a349b
JB		 7732020-03-06 Jan Beulich <jbeulich@suse.com>
774
775 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
776 * i386-tbl.h: Re-generate.
777
4ed21b58
JB		 7782020-03-06 Jan Beulich <jbeulich@suse.com>
779
780 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
781 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
782 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
783 VexW0 on SSE2AVX variants.
784 (vmovq): Drop NoRex64 from XMM/XMM variants.
785 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
786 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
787 applicable use VexW0.
788 * i386-tbl.h: Re-generate.
789
643bb870
JB		 7902020-03-06 Jan Beulich <jbeulich@suse.com>
791
792 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
793 * i386-opc.h (Rex64): Delete.
794 (struct i386_opcode_modifier): Remove rex64 field.
795 * i386-opc.tbl (crc32): Drop Rex64.
796 Replace Rex64 with Size64 everywhere else.
797 * i386-tbl.h: Re-generate.
798
a23b33b3
JB		 7992020-03-06 Jan Beulich <jbeulich@suse.com>
800
801 * i386-dis.c (OP_E_memory): Exclude recording of used address
802 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
803 addressed memory operands for MPX insns.
804
a0497384
JB		 8052020-03-06 Jan Beulich <jbeulich@suse.com>
806
807 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
808 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
809 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
810 (ptwrite): Split into non-64-bit and 64-bit forms.
811 * i386-tbl.h: Re-generate.
812
b630c145
JB		 8132020-03-06 Jan Beulich <jbeulich@suse.com>
814
815 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
816 template.
817 * i386-tbl.h: Re-generate.
818
a847e322
JB		 8192020-03-04 Jan Beulich <jbeulich@suse.com>
820
821 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
822 (prefix_table): Move vmmcall here. Add vmgexit.
823 (rm_table): Replace vmmcall entry by prefix_table[] escape.
824 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
825 (cpu_flags): Add CpuSEV_ES entry.
826 * i386-opc.h (CpuSEV_ES): New.
827 (union i386_cpu_flags): Add cpusev_es field.
828 * i386-opc.tbl (vmgexit): New.
829 * i386-init.h, i386-tbl.h: Re-generate.
830
3cd7f3e3
L		 8312020-03-03 H.J. Lu <hongjiu.lu@intel.com>
832
833 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
834 with MnemonicSize.
835 * i386-opc.h (IGNORESIZE): New.
836 (DEFAULTSIZE): Likewise.
837 (IgnoreSize): Removed.
838 (DefaultSize): Likewise.
839 (MnemonicSize): New.
840 (i386_opcode_modifier): Replace ignoresize/defaultsize with
841 mnemonicsize.
842 * i386-opc.tbl (IgnoreSize): New.
843 (DefaultSize): Likewise.
844 * i386-tbl.h: Regenerated.
845
b8ba1385
SB		 8462020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
847
848 PR 25627
849 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
850 instructions.
851
10d97a0f
L		 8522020-03-03 H.J. Lu <hongjiu.lu@intel.com>
853
854 PR gas/25622
855 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
856 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
857 * i386-tbl.h: Regenerated.
858
dc1e8a47
AM		 8592020-02-26 Alan Modra <amodra@gmail.com>
860
861 * aarch64-asm.c: Indent labels correctly.
862 * aarch64-dis.c: Likewise.
863 * aarch64-gen.c: Likewise.
864 * aarch64-opc.c: Likewise.
865 * alpha-dis.c: Likewise.
866 * i386-dis.c: Likewise.
867 * nds32-asm.c: Likewise.
868 * nfp-dis.c: Likewise.
869 * visium-dis.c: Likewise.
870
265b4673
CZ		 8712020-02-25 Claudiu Zissulescu <claziss@gmail.com>
872
873 * arc-regs.h (int_vector_base): Make it available for all ARC
874 CPUs.
875
bd0cf5a6
NC		 8762020-02-20 Nelson Chu <nelson.chu@sifive.com>
877
878 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
879 changed.
880
fa164239
JW		 8812020-02-19 Nelson Chu <nelson.chu@sifive.com>
882
883 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
884 c.mv/c.li if rs1 is zero.
885
272a84b1
L		 8862020-02-17 H.J. Lu <hongjiu.lu@intel.com>
887
888 * i386-gen.c (cpu_flag_init): Replace CpuABM with
889 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
890 CPU_POPCNT_FLAGS.
891 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
892 * i386-opc.h (CpuABM): Removed.
893 (CpuPOPCNT): New.
894 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
895 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
896 popcnt. Remove CpuABM from lzcnt.
897 * i386-init.h: Regenerated.
898 * i386-tbl.h: Likewise.
899
1f730c46
JB		 9002020-02-17 Jan Beulich <jbeulich@suse.com>
901
902 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
903 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
904 VexW1 instead of open-coding them.
905 * i386-tbl.h: Re-generate.
906
c8f8eebc
JB		 9072020-02-17 Jan Beulich <jbeulich@suse.com>
908
909 * i386-opc.tbl (AddrPrefixOpReg): Define.
910 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
911 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
912 templates. Drop NoRex64.
913 * i386-tbl.h: Re-generate.
914
b9915cbc
JB		 9152020-02-17 Jan Beulich <jbeulich@suse.com>
916
917 PR gas/6518
918 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
919 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
920 into Intel syntax instance (with Unpsecified) and AT&T one
921 (without).
922 (vcvtneps2bf16): Likewise, along with folding the two so far
923 separate ones.
924 * i386-tbl.h: Re-generate.
925
ce504911
L		 9262020-02-16 H.J. Lu <hongjiu.lu@intel.com>
927
928 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
929 CPU_ANY_SSE4A_FLAGS.
930
dabec65d
AM		 9312020-02-17 Alan Modra <amodra@gmail.com>
932
933 * i386-gen.c (cpu_flag_init): Correct last change.
934
af5c13b0
L		 9352020-02-16 H.J. Lu <hongjiu.lu@intel.com>
936
937 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
938 CPU_ANY_SSE4_FLAGS.
939
6867aac0
L		 9402020-02-14 H.J. Lu <hongjiu.lu@intel.com>
941
942 * i386-opc.tbl (movsx): Remove Intel syntax comments.
943 (movzx): Likewise.
944
65fca059
JB		 9452020-02-14 Jan Beulich <jbeulich@suse.com>
946
947 PR gas/25438
948 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
949 destination for Cpu64-only variant.
950 (movzx): Fold patterns.
951 * i386-tbl.h: Re-generate.
952
7deea9aa
JB		 9532020-02-13 Jan Beulich <jbeulich@suse.com>
954
955 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
956 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
957 CPU_ANY_SSE4_FLAGS entry.
958 * i386-init.h: Re-generate.
959
6c0946d0
JB		 9602020-02-12 Jan Beulich <jbeulich@suse.com>
961
962 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
963 with Unspecified, making the present one AT&T syntax only.
964 * i386-tbl.h: Re-generate.
965
ddb56fe6
JB		 9662020-02-12 Jan Beulich <jbeulich@suse.com>
967
968 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
969 * i386-tbl.h: Re-generate.
970
5990e377
JB		 9712020-02-12 Jan Beulich <jbeulich@suse.com>
972
973 PR gas/24546
974 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
975 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
976 Amd64 and Intel64 templates.
977 (call, jmp): Likewise for far indirect variants. Dro
978 Unspecified.
979 * i386-tbl.h: Re-generate.
980
50128d0c
JB		 9812020-02-11 Jan Beulich <jbeulich@suse.com>
982
983 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
984 * i386-opc.h (ShortForm): Delete.
985 (struct i386_opcode_modifier): Remove shortform field.
986 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
987 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
988 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
989 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
990 Drop ShortForm.
991 * i386-tbl.h: Re-generate.
992
1e05b5c4
JB		 9932020-02-11 Jan Beulich <jbeulich@suse.com>
994
995 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
996 fucompi): Drop ShortForm from operand-less templates.
997 * i386-tbl.h: Re-generate.
998
2f5dd314
AM		 9992020-02-11 Alan Modra <amodra@gmail.com>
1000
1001 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1002 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1003 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1004 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1005 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1006
5aae9ae9
MM		 10072020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1008
1009 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1010 (cde_opcodes): Add VCX* instructions.
1011
4934a27c
MM		 10122020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1013 Matthew Malcomson <matthew.malcomson@arm.com>
1014
1015 * arm-dis.c (struct cdeopcode32): New.
1016 (CDE_OPCODE): New macro.
1017 (cde_opcodes): New disassembly table.
1018 (regnames): New option to table.
1019 (cde_coprocs): New global variable.
1020 (print_insn_cde): New
1021 (print_insn_thumb32): Use print_insn_cde.
1022 (parse_arm_disassembler_options): Parse coprocN args.
1023
4b5aaf5f
L		 10242020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1025
1026 PR gas/25516
1027 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1028 with ISA64.
1029 * i386-opc.h (AMD64): Removed.
1030 (Intel64): Likewose.
1031 (AMD64): New.
1032 (INTEL64): Likewise.
1033 (INTEL64ONLY): Likewise.
1034 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1035 * i386-opc.tbl (Amd64): New.
1036 (Intel64): Likewise.
1037 (Intel64Only): Likewise.
1038 Replace AMD64 with Amd64. Update sysenter/sysenter with
1039 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1040 * i386-tbl.h: Regenerated.
1041
9fc0b501
SB		 10422020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1043
1044 PR 25469
1045 * z80-dis.c: Add support for GBZ80 opcodes.
1046
c5d7be0c
AM		 10472020-02-04 Alan Modra <amodra@gmail.com>
1048
1049 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1050
44e4546f
AM		 10512020-02-03 Alan Modra <amodra@gmail.com>
1052
1053 * m32c-ibld.c: Regenerate.
1054
b2b1453a
AM		 10552020-02-01 Alan Modra <amodra@gmail.com>
1056
1057 * frv-ibld.c: Regenerate.
1058
4102be5c
JB		 10592020-01-31 Jan Beulich <jbeulich@suse.com>
1060
1061 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1062 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1063 (OP_E_memory): Replace xmm_mdq_mode case label by
1064 vex_scalar_w_dq_mode one.
1065 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1066
825bd36c
JB		 10672020-01-31 Jan Beulich <jbeulich@suse.com>
1068
1069 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1070 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1071 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1072 (intel_operand_size): Drop vex_w_dq_mode case label.
1073
c3036ed0
RS		 10742020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1075
1076 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1077 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1078
0c115f84
AM		 10792020-01-30 Alan Modra <amodra@gmail.com>
1080
1081 * m32c-ibld.c: Regenerate.
1082
bd434cc4
JM		 10832020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1084
1085 * bpf-opc.c: Regenerate.
1086
aeab2b26
JB		 10872020-01-30 Jan Beulich <jbeulich@suse.com>
1088
1089 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1090 (dis386): Use them to replace C2/C3 table entries.
1091 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1092 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1093 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1094 * i386-tbl.h: Re-generate.
1095
62b3f548
JB		 10962020-01-30 Jan Beulich <jbeulich@suse.com>
1097
1098 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1099 forms.
1100 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1101 DefaultSize.
1102 * i386-tbl.h: Re-generate.
1103
1bd8ae10
AM		 11042020-01-30 Alan Modra <amodra@gmail.com>
1105
1106 * tic4x-dis.c (tic4x_dp): Make unsigned.
1107
bc31405e
L		 11082020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1109 Jan Beulich <jbeulich@suse.com>
1110
1111 PR binutils/25445
1112 * i386-dis.c (MOVSXD_Fixup): New function.
1113 (movsxd_mode): New enum.
1114 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1115 (intel_operand_size): Handle movsxd_mode.
1116 (OP_E_register): Likewise.
1117 (OP_G): Likewise.
1118 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1119 register on movsxd. Add movsxd with 16-bit destination register
1120 for AMD64 and Intel64 ISAs.
1121 * i386-tbl.h: Regenerated.
1122
7568c93b
TC		 11232020-01-27 Tamar Christina <tamar.christina@arm.com>
1124
1125 PR 25403
1126 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1127 * aarch64-asm-2.c: Regenerate
1128 * aarch64-dis-2.c: Likewise.
1129 * aarch64-opc-2.c: Likewise.
1130
c006a730
JB		 11312020-01-21 Jan Beulich <jbeulich@suse.com>
1132
1133 * i386-opc.tbl (sysret): Drop DefaultSize.
1134 * i386-tbl.h: Re-generate.
1135
c906a69a
JB		 11362020-01-21 Jan Beulich <jbeulich@suse.com>
1137
1138 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1139 Dword.
1140 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1141 * i386-tbl.h: Re-generate.
1142
26916852
NC		 11432020-01-20 Nick Clifton <nickc@redhat.com>
1144
1145 * po/de.po: Updated German translation.
1146 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1147 * po/uk.po: Updated Ukranian translation.
1148
4d6cbb64
AM		 11492020-01-20 Alan Modra <amodra@gmail.com>
1150
1151 * hppa-dis.c (fput_const): Remove useless cast.
1152
2bddb71a
AM		 11532020-01-20 Alan Modra <amodra@gmail.com>
1154
1155 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1156
1b1bb2c6
NC		 11572020-01-18 Nick Clifton <nickc@redhat.com>
1158
1159 * configure: Regenerate.
1160 * po/opcodes.pot: Regenerate.
1161
ae774686
NC		 11622020-01-18 Nick Clifton <nickc@redhat.com>
1163
1164 Binutils 2.34 branch created.
1165
07f1f3aa
CB		 11662020-01-17 Christian Biesinger <cbiesinger@google.com>
1167
1168 * opintl.h: Fix spelling error (seperate).
1169
42e04b36
L		 11702020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1171
1172 * i386-opc.tbl: Add {vex} pseudo prefix.
1173 * i386-tbl.h: Regenerated.
1174
2da2eaf4
AV		 11752020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1176
1177 PR 25376
1178 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1179 (neon_opcodes): Likewise.
1180 (select_arm_features): Make sure we enable MVE bits when selecting
1181 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1182 any architecture.
1183
d0849eed
JB		 11842020-01-16 Jan Beulich <jbeulich@suse.com>
1185
1186 * i386-opc.tbl: Drop stale comment from XOP section.
1187
9cf70a44
JB		 11882020-01-16 Jan Beulich <jbeulich@suse.com>
1189
1190 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1191 (extractps): Add VexWIG to SSE2AVX forms.
1192 * i386-tbl.h: Re-generate.
1193
4814632e
JB		 11942020-01-16 Jan Beulich <jbeulich@suse.com>
1195
1196 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1197 Size64 from and use VexW1 on SSE2AVX forms.
1198 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1199 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1200 * i386-tbl.h: Re-generate.
1201
aad09917
AM		 12022020-01-15 Alan Modra <amodra@gmail.com>
1203
1204 * tic4x-dis.c (tic4x_version): Make unsigned long.
1205 (optab, optab_special, registernames): New file scope vars.
1206 (tic4x_print_register): Set up registernames rather than
1207 malloc'd registertable.
1208 (tic4x_disassemble): Delete optable and optable_special. Use
1209 optab and optab_special instead. Throw away old optab,
1210 optab_special and registernames when info->mach changes.
1211
7a6bf3be
SB		 12122020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1213
1214 PR 25377
1215 * z80-dis.c (suffix): Use .db instruction to generate double
1216 prefix.
1217
ca1eaac0
AM		 12182020-01-14 Alan Modra <amodra@gmail.com>
1219
1220 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1221 values to unsigned before shifting.
1222
1d67fe3b
TT		 12232020-01-13 Thomas Troeger <tstroege@gmx.de>
1224
1225 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1226 flow instructions.
1227 (print_insn_thumb16, print_insn_thumb32): Likewise.
1228 (print_insn): Initialize the insn info.
1229 * i386-dis.c (print_insn): Initialize the insn info fields, and
1230 detect jumps.
1231
5e4f7e05
CZ		 12322012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1233
1234 * arc-opc.c (C_NE): Make it required.
1235
b9fe6b8a
CZ		 12362012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1237
1238 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1239 reserved register name.
1240
90dee485
AM		 12412020-01-13 Alan Modra <amodra@gmail.com>
1242
1243 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1244 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1245
febda64f
AM		 12462020-01-13 Alan Modra <amodra@gmail.com>
1247
1248 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1249 result of wasm_read_leb128 in a uint64_t and check that bits
1250 are not lost when copying to other locals. Use uint32_t for
1251 most locals. Use PRId64 when printing int64_t.
1252
df08b588
AM		 12532020-01-13 Alan Modra <amodra@gmail.com>
1254
1255 * score-dis.c: Formatting.
1256 * score7-dis.c: Formatting.
1257
b2c759ce
AM		 12582020-01-13 Alan Modra <amodra@gmail.com>
1259
1260 * score-dis.c (print_insn_score48): Use unsigned variables for
1261 unsigned values. Don't left shift negative values.
1262 (print_insn_score32): Likewise.
1263 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1264
5496abe1
AM		 12652020-01-13 Alan Modra <amodra@gmail.com>
1266
1267 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1268
202e762b
AM		 12692020-01-13 Alan Modra <amodra@gmail.com>
1270
1271 * fr30-ibld.c: Regenerate.
1272
7ef412cf
AM		 12732020-01-13 Alan Modra <amodra@gmail.com>
1274
1275 * xgate-dis.c (print_insn): Don't left shift signed value.
1276 (ripBits): Formatting, use 1u.
1277
7f578b95
AM		 12782020-01-10 Alan Modra <amodra@gmail.com>
1279
1280 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1281 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1282
441af85b
AM		 12832020-01-10 Alan Modra <amodra@gmail.com>
1284
1285 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1286 and XRREG value earlier to avoid a shift with negative exponent.
1287 * m10200-dis.c (disassemble): Similarly.
1288
bce58db4
NC		 12892020-01-09 Nick Clifton <nickc@redhat.com>
1290
1291 PR 25224
1292 * z80-dis.c (ld_ii_ii): Use correct cast.
1293
40c75bc8
SB		 12942020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1295
1296 PR 25224
1297 * z80-dis.c (ld_ii_ii): Use character constant when checking
1298 opcode byte value.
1299
d835a58b
JB		 13002020-01-09 Jan Beulich <jbeulich@suse.com>
1301
1302 * i386-dis.c (SEP_Fixup): New.
1303 (SEP): Define.
1304 (dis386_twobyte): Use it for sysenter/sysexit.
1305 (enum x86_64_isa): Change amd64 enumerator to value 1.
1306 (OP_J): Compare isa64 against intel64 instead of amd64.
1307 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1308 forms.
1309 * i386-tbl.h: Re-generate.
1310
030a2e78
AM		 13112020-01-08 Alan Modra <amodra@gmail.com>
1312
1313 * z8k-dis.c: Include libiberty.h
1314 (instr_data_s): Make max_fetched unsigned.
1315 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1316 Don't exceed byte_info bounds.
1317 (output_instr): Make num_bytes unsigned.
1318 (unpack_instr): Likewise for nibl_count and loop.
1319 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1320 idx unsigned.
1321 * z8k-opc.h: Regenerate.
1322
bb82aefe
SV		 13232020-01-07 Shahab Vahedi <shahab@synopsys.com>
1324
1325 * arc-tbl.h (llock): Use 'LLOCK' as class.
1326 (llockd): Likewise.
1327 (scond): Use 'SCOND' as class.
1328 (scondd): Likewise.
1329 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1330 (scondd): Likewise.
1331
cc6aa1a6
AM		 13322020-01-06 Alan Modra <amodra@gmail.com>
1333
1334 * m32c-ibld.c: Regenerate.
1335
660e62b1
AM		 13362020-01-06 Alan Modra <amodra@gmail.com>
1337
1338 PR 25344
1339 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1340 Peek at next byte to prevent recursion on repeated prefix bytes.
1341 Ensure uninitialised "mybuf" is not accessed.
1342 (print_insn_z80): Don't zero n_fetch and n_used here,..
1343 (print_insn_z80_buf): ..do it here instead.
1344
c9ae58fe
AM		 13452020-01-04 Alan Modra <amodra@gmail.com>
1346
1347 * m32r-ibld.c: Regenerate.
1348
5f57d4ec
AM		 13492020-01-04 Alan Modra <amodra@gmail.com>
1350
1351 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1352
2c5c1196
AM		 13532020-01-04 Alan Modra <amodra@gmail.com>
1354
1355 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1356
2e98c6c5
AM		 13572020-01-04 Alan Modra <amodra@gmail.com>
1358
1359 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1360
567dfba2
JB		 13612020-01-03 Jan Beulich <jbeulich@suse.com>
1362
5437a02a
JB		 1363 * aarch64-tbl.h (aarch64_opcode_table): Use
1364 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1365
13662020-01-03 Jan Beulich <jbeulich@suse.com>
1367
1368 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1369 forms of SUDOT and USDOT.
1370
8c45011a
JB		 13712020-01-03 Jan Beulich <jbeulich@suse.com>
1372
5437a02a 1373 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1374 uzip{1,2}.
1375 * opcodes/aarch64-dis-2.c: Re-generate.
1376
f4950f76
JB		 13772020-01-03 Jan Beulich <jbeulich@suse.com>
1378
5437a02a 1379 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1380 FMMLA encoding.
1381 * opcodes/aarch64-dis-2.c: Re-generate.
1382
6655dba2
SB		 13832020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1384
1385 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1386
b14ce8bf
AM		 13872020-01-01 Alan Modra <amodra@gmail.com>
1388
1389 Update year range in copyright notice of all files.
1390
0b114740 1391For older changes see ChangeLog-2019
3499769a 1392\f
0b114740 1393Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1394
1395Copying and distribution of this file, with or without modification,
1396are permitted in any medium without royalty provided the copyright
1397notice and this notice are preserved.
1398
1399Local Variables:
1400mode: change-log
1401left-margin: 8
1402fill-column: 74
1403version-control: never
1404End:
GDB Binutils - Deliverables
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