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[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3bd894a7
MW		 12015-11-27 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
4 (FP_F16): New.
5
64357d2e
MW		 62015-11-27 Matthew Wahab <matthew.wahab@arm.com>
7
8 * aarch64-asm-2.c: Regenerate.
9 * aarch64-dis-2.c: Regenerate.
10 * aarch64-opc-2.c: Regenerate.
11 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
12 "rev64".
13
d685192a
MW		 142015-11-27 Matthew Wahab <matthew.wahab@arm.com>
15
16 * aarch64-asm-2.c: Regenerate.
17 * aarch64-asm.c (convert_bfc_to_bfm): New.
18 (convert_to_real): Add case for OP_BFC.
19 * aarch64-dis-2.c: Regenerate.
20 * aarch64-dis.c: (convert_bfm_to_bfc): New.
21 (convert_to_alias): Add case for OP_BFC.
22 * aarch64-opc-2.c: Regenerate.
23 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
24 to allow width operand in three-operand instructions.
25 * aarch64-tbl.h (QL_BF1): New.
26 (aarch64_feature_v8_2): New.
27 (ARMV8_2): New.
28 (aarch64_opcode_table): Add "bfc".
29
35822b38
MW		 302015-11-27 Matthew Wahab <matthew.wahab@arm.com>
31
32 * aarch64-asm-2.c: Regenerate.
33 * aarch64-dis-2.c: Regenerate.
34 * aarch64-dis.c: Weaken assert.
35 * aarch64-gen.c: Include the instruction in the list of its
36 possible aliases.
37
1a04d1a7
MW		 382015-11-27 Matthew Wahab <matthew.wahab@arm.com>
39
40 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
41 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
42 feature test.
43
e49d43ff
TG		 442015-11-23 Tristan Gingold <gingold@adacore.com>
45
46 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
47
250aafa4
MW		 482015-11-20 Matthew Wahab <matthew.wahab@arm.com>
49
50 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
51 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
52 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
53 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
54 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
55 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
56 cnthv_ctl_el2, cnthv_cval_el2.
57 (aarch64_sys_reg_supported_p): Update for the new system
58 registers.
59
a915c10f
NC		 602015-11-20 Nick Clifton <nickc@redhat.com>
61
62 PR binutils/19224
63 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
64
f8c2a965
NC		 652015-11-20 Nick Clifton <nickc@redhat.com>
66
67 * po/zh_CN.po: Updated simplified Chinese translation.
68
c2825638
MW		 692015-11-19 Matthew Wahab <matthew.wahab@arm.com>
70
71 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
72 of MSR PAN immediate operand.
73
e7286c56
NC		 742015-11-16 Nick Clifton <nickc@redhat.com>
75
76 * rx-dis.c (condition_names): Replace always and never with
77 invalid, since the always/never conditions can never be legal.
78
d8bd95ef
TG		 792015-11-13 Tristan Gingold <gingold@adacore.com>
80
81 * configure: Regenerate.
82
a680de9a
PB		 832015-11-11 Alan Modra <amodra@gmail.com>
84 Peter Bergner <bergner@vnet.ibm.com>
85
86 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
87 Add PPC_OPCODE_VSX3 to the vsx entry.
88 (powerpc_init_dialect): Set default dialect to power9.
89 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
90 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
91 extract_l1 insert_xtq6, extract_xtq6): New static functions.
92 (insert_esync): Test for illegal L operand value.
93 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
94 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
95 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
96 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
97 PPCVSX3): New defines.
98 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
99 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
100 <mcrxr>: Use XBFRARB_MASK.
101 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
102 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
103 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
104 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
105 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
106 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
107 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
108 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
109 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
110 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
111 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
112 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
113 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
114 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
115 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
116 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
117 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
118 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
119 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
120 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
121 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
122 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
123 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
124 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
125 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
126 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
127 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
128 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
129 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
130 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
131 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
132 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
133
854eb72b
NC		 1342015-11-02 Nick Clifton <nickc@redhat.com>
135
136 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
137 instructions.
138 * rx-decode.c: Regenerate.
139
e292aa7a
NC		 1402015-11-02 Nick Clifton <nickc@redhat.com>
141
142 * rx-decode.opc (rx_disp): If the displacement is zero, set the
143 type to RX_Operand_Zero_Indirect.
144 * rx-decode.c: Regenerate.
145 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
146
43cdf5ae
YQ		 1472015-10-28 Yao Qi <yao.qi@linaro.org>
148
149 * aarch64-dis.c (aarch64_decode_insn): Add one argument
150 noaliases_p. Update comments. Pass noaliases_p rather than
151 no_aliases to aarch64_opcode_decode.
152 (print_insn_aarch64_word): Pass no_aliases to
153 aarch64_decode_insn.
154
c2f28758
VK		 1552015-10-27 Vinay <Vinay.G@kpit.com>
156
157 PR binutils/19159
158 * rl78-decode.opc (MOV): Added offset to DE register in index
159 addressing mode.
160 * rl78-decode.c: Regenerate.
161
46662804
VK		 1622015-10-27 Vinay Kumar <vinay.g@kpit.com>
163
164 PR binutils/19158
165 * rl78-decode.opc: Add 's' print operator to instructions that
166 access system registers.
167 * rl78-decode.c: Regenerate.
168 * rl78-dis.c (print_insn_rl78_common): Decode all system
169 registers.
170
02f12cd4
VK		 1712015-10-27 Vinay Kumar <vinay.g@kpit.com>
172
173 PR binutils/19157
174 * rl78-decode.opc: Add 'a' print operator to mov instructions
175 using stack pointer plus index addressing.
176 * rl78-decode.c: Regenerate.
177
485f23cf
AK		 1782015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
179
180 * s390-opc.c: Fix comment.
181 * s390-opc.txt: Change instruction type for troo, trot, trto, and
182 trtt to RRF_U0RER since the second parameter does not need to be a
183 register pair.
184
3f94e60d
NC		 1852015-10-08 Nick Clifton <nickc@redhat.com>
186
187 * arc-dis.c (print_insn_arc): Initiallise insn array.
188
875880c6
YQ		 1892015-10-07 Yao Qi <yao.qi@linaro.org>
190
191 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
192 'name' rather than 'template'.
193 * aarch64-opc.c (aarch64_print_operand): Likewise.
194
886a2506
NC		 1952015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
196
197 * arc-dis.c: Revamped file for ARC support
198 * arc-dis.h: Likewise.
199 * arc-ext.c: Likewise.
200 * arc-ext.h: Likewise.
201 * arc-opc.c: Likewise.
202 * arc-fxi.h: New file.
203 * arc-regs.h: Likewise.
204 * arc-tbl.h: Likewise.
205
36f4aab1
YQ		 2062015-10-02 Yao Qi <yao.qi@linaro.org>
207
208 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
209 argument insn type to aarch64_insn. Rename to ...
210 (aarch64_decode_insn): ... it.
211 (print_insn_aarch64_word): Caller updated.
212
7232d389
YQ		 2132015-10-02 Yao Qi <yao.qi@linaro.org>
214
215 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
216 (print_insn_aarch64_word): Caller updated.
217
7ecc513a
DV		 2182015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
219
220 * s390-mkopc.c (main): Parse htm and vx flag.
221 * s390-opc.txt: Mark instructions from the hardware transactional
222 memory and vector facilities with the "htm"/"vx" flag.
223
b08b78e7
NC		 2242015-09-28 Nick Clifton <nickc@redhat.com>
225
226 * po/de.po: Updated German translation.
227
36f7a941
TR		 2282015-09-28 Tom Rix <tom@bumblecow.com>
229
230 * ppc-opc.c (PPC500): Mark some opcodes as invalid
231
b6518b38
NC		 2322015-09-23 Nick Clifton <nickc@redhat.com>
233
234 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
235 function.
236 * tic30-dis.c (print_branch): Likewise.
237 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
238 value before left shifting.
239 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
240 * hppa-dis.c (print_insn_hppa): Likewise.
241 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
242 array.
243 * msp430-dis.c (msp430_singleoperand): Likewise.
244 (msp430_doubleoperand): Likewise.
245 (print_insn_msp430): Likewise.
246 * nds32-asm.c (parse_operand): Likewise.
247 * sh-opc.h (MASK): Likewise.
248 * v850-dis.c (get_operand_value): Likewise.
249
f04265ec
NC		 2502015-09-22 Nick Clifton <nickc@redhat.com>
251
252 * rx-decode.opc (bwl): Use RX_Bad_Size.
253 (sbwl): Likewise.
254 (ubwl): Likewise. Rename to ubw.
255 (uBWL): Rename to uBW.
256 Replace all references to uBWL with uBW.
257 * rx-decode.c: Regenerate.
258 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
259 (opsize_names): Likewise.
260 (print_insn_rx): Detect and report RX_Bad_Size.
261
6dca4fd1
AB		 2622015-09-22 Anton Blanchard <anton@samba.org>
263
264 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
265
38074311
JM		 2662015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
267
268 * sparc-dis.c (print_insn_sparc): Handle the privileged register
269 %pmcdper.
270
5f40e14d
JS		 2712015-08-24 Jan Stancek <jstancek@redhat.com>
272
273 * i386-dis.c (print_insn): Fix decoding of three byte operands.
274
ab4e4ed5
AF		 2752015-08-21 Alexander Fomin <alexander.fomin@intel.com>
276
277 PR binutils/18257
278 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
279 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
280 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
281 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
282 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
283 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
284 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
285 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
286 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
287 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
288 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
289 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
290 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
291 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
292 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
293 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
294 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
295 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
296 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
297 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
298 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
299 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
300 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
301 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
302 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
303 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
304 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
305 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
306 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
307 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
308 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
309 (vex_w_table): Replace terminals with MOD_TABLE entries for
310 most of mask instructions.
311
919b75f7
AM		 3122015-08-17 Alan Modra <amodra@gmail.com>
313
314 * cgen.sh: Trim trailing space from cgen output.
315 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
316 (print_dis_table): Likewise.
317 * opc2c.c (dump_lines): Likewise.
318 (orig_filename): Warning fix.
319 * ia64-asmtab.c: Regenerate.
320
4ab90a7a
AV		 3212015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
322
323 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
324 and higher with ARM instruction set will now mark the 26-bit
325 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
326 (arm_opcodes): Fix for unpredictable nop being recognized as a
327 teq.
328
40fc1451
SD		 3292015-08-12 Simon Dardis <simon.dardis@imgtec.com>
330
331 * micromips-opc.c (micromips_opcodes): Re-order table so that move
332 based on 'or' is first.
333 * mips-opc.c (mips_builtin_opcodes): Ditto.
334
922c5db5
NC		 3352015-08-11 Nick Clifton <nickc@redhat.com>
336
337 PR 18800
338 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
339 instruction.
340
75fb7498
RS		 3412015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
342
343 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
344
36aed29d
AP		 3452015-08-07 Amit Pawar <Amit.Pawar@amd.com>
346
347 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
348 * i386-init.h: Regenerated.
349
a8484f96
L		 3502015-07-30 H.J. Lu <hongjiu.lu@intel.com>
351
352 PR binutils/13571
353 * i386-dis.c (MOD_0FC3): New.
354 (PREFIX_0FC3): Renamed to ...
355 (PREFIX_MOD_0_0FC3): This.
356 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
357 (prefix_table): Replace Ma with Ev on movntiS.
358 (mod_table): Add MOD_0FC3.
359
37a42ee9
L		 3602015-07-27 H.J. Lu <hongjiu.lu@intel.com>
361
362 * configure: Regenerated.
363
070fe95d
AM		 3642015-07-23 Alan Modra <amodra@gmail.com>
365
366 PR 18708
367 * i386-dis.c (get64): Avoid signed integer overflow.
368
20c2a615
L		 3692015-07-22 Alexander Fomin <alexander.fomin@intel.com>
370
371 PR binutils/18631
372 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
373 "EXEvexHalfBcstXmmq" for the second operand.
374 (EVEX_W_0F79_P_2): Likewise.
375 (EVEX_W_0F7A_P_2): Likewise.
376 (EVEX_W_0F7B_P_2): Likewise.
377
6f1c2142
AM		 3782015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
379
380 * arm-dis.c (print_insn_coprocessor): Added support for quarter
381 float bitfield format.
382 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
383 quarter float bitfield format.
384
8a643cc3
L		 3852015-07-14 H.J. Lu <hongjiu.lu@intel.com>
386
387 * configure: Regenerated.
388
ef5a96d5
AM		 3892015-07-03 Alan Modra <amodra@gmail.com>
390
391 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
392 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
393 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
394
c8c8175b
SL		 3952015-07-01 Sandra Loosemore <sandra@codesourcery.com>
396 Cesar Philippidis <cesar@codesourcery.com>
397
398 * nios2-dis.c (nios2_extract_opcode): New.
399 (nios2_disassembler_state): New.
400 (nios2_find_opcode_hash): Use mach parameter to select correct
401 disassembler state.
402 (nios2_print_insn_arg): Extend to support new R2 argument letters
403 and formats.
404 (print_insn_nios2): Check for 16-bit instruction at end of memory.
405 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
406 (NIOS2_NUM_OPCODES): Rename to...
407 (NIOS2_NUM_R1_OPCODES): This.
408 (nios2_r2_opcodes): New.
409 (NIOS2_NUM_R2_OPCODES): New.
410 (nios2_num_r2_opcodes): New.
411 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
412 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
413 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
414 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
415 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
416
9916071f
AP		 4172015-06-30 Amit Pawar <Amit.Pawar@amd.com>
418
419 * i386-dis.c (OP_Mwaitx): New.
420 (rm_table): Add monitorx/mwaitx.
421 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
422 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
423 (operand_type_init): Add CpuMWAITX.
424 * i386-opc.h (CpuMWAITX): New.
425 (i386_cpu_flags): Add cpumwaitx.
426 * i386-opc.tbl: Add monitorx and mwaitx.
427 * i386-init.h: Regenerated.
428 * i386-tbl.h: Likewise.
429
7b934113
PB		 4302015-06-22 Peter Bergner <bergner@vnet.ibm.com>
431
432 * ppc-opc.c (insert_ls): Test for invalid LS operands.
433 (insert_esync): New function.
434 (LS, WC): Use insert_ls.
435 (ESYNC): Use insert_esync.
436
bdc4de1b
NC		 4372015-06-22 Nick Clifton <nickc@redhat.com>
438
439 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
440 requested region lies beyond it.
441 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
442 looking for 32-bit insns.
443 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
444 data.
445 * sh-dis.c (print_insn_sh): Likewise.
446 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
447 blocks of instructions.
448 * vax-dis.c (print_insn_vax): Check that the requested address
449 does not clash with the stop_vma.
450
11a0cf2e
PB		 4512015-06-19 Peter Bergner <bergner@vnet.ibm.com>
452
070fe95d 453 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 454 * ppc-opc.c (FXM4): Add non-zero optional value.
455 (TBR): Likewise.
456 (SXL): Likewise.
457 (insert_fxm): Handle new default operand value.
458 (extract_fxm): Likewise.
459 (insert_tbr): Likewise.
460 (extract_tbr): Likewise.
461
bdfa8b95
MW		 4622015-06-16 Matthew Wahab <matthew.wahab@arm.com>
463
464 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
465
24b4cf66
SN		 4662015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
467
468 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
469
99a2c561
PB		 4702015-06-12 Peter Bergner <bergner@vnet.ibm.com>
471
472 * ppc-opc.c: Add comment accidentally removed by old commit.
473 (MTMSRD_L): Delete.
474
40f77f82
AM		 4752015-06-04 Peter Bergner <bergner@vnet.ibm.com>
476
477 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
478
13be46a2
NC		 4792015-06-04 Nick Clifton <nickc@redhat.com>
480
481 PR 18474
482 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
483
ddfded2f
MW		 4842015-06-02 Matthew Wahab <matthew.wahab@arm.com>
485
486 * arm-dis.c (arm_opcodes): Add "setpan".
487 (thumb_opcodes): Add "setpan".
488
1af1dd51
MW		 4892015-06-02 Matthew Wahab <matthew.wahab@arm.com>
490
491 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
492 macros.
493
9e1f0fa7
MW		 4942015-06-02 Matthew Wahab <matthew.wahab@arm.com>
495
496 * aarch64-tbl.h (aarch64_feature_rdma): New.
497 (RDMA): New.
498 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
499 * aarch64-asm-2.c: Regenerate.
500 * aarch64-dis-2.c: Regenerate.
501 * aarch64-opc-2.c: Regenerate.
502
290806fd
MW		 5032015-06-02 Matthew Wahab <matthew.wahab@arm.com>
504
505 * aarch64-tbl.h (aarch64_feature_lor): New.
506 (LOR): New.
507 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
508 "stllrb", "stllrh".
509 * aarch64-asm-2.c: Regenerate.
510 * aarch64-dis-2.c: Regenerate.
511 * aarch64-opc-2.c: Regenerate.
512
f21cce2c
MW		 5132015-06-01 Matthew Wahab <matthew.wahab@arm.com>
514
515 * aarch64-opc.c (F_ARCHEXT): New.
516 (aarch64_sys_regs): Add "pan".
517 (aarch64_sys_reg_supported_p): New.
518 (aarch64_pstatefields): Add "pan".
519 (aarch64_pstatefield_supported_p): New.
520
d194d186
JB		 5212015-06-01 Jan Beulich <jbeulich@suse.com>
522
523 * i386-tbl.h: Regenerate.
524
3a8547d2
JB		 5252015-06-01 Jan Beulich <jbeulich@suse.com>
526
527 * i386-dis.c (print_insn): Swap rounding mode specifier and
528 general purpose register in Intel mode.
529
015c54d5
JB		 5302015-06-01 Jan Beulich <jbeulich@suse.com>
531
532 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
533 * i386-tbl.h: Regenerate.
534
071f0063
L		 5352015-05-18 H.J. Lu <hongjiu.lu@intel.com>
536
537 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
538 * i386-init.h: Regenerated.
539
5db04b09
L		 5402015-05-15 H.J. Lu <hongjiu.lu@intel.com>
541
542 PR binutis/18386
543 * i386-dis.c: Add comments for '@'.
544 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
545 (enum x86_64_isa): New.
546 (isa64): Likewise.
547 (print_i386_disassembler_options): Add amd64 and intel64.
548 (print_insn): Handle amd64 and intel64.
549 (putop): Handle '@'.
550 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
551 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
552 * i386-opc.h (AMD64): New.
553 (CpuIntel64): Likewise.
554 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
555 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
556 Mark direct call/jmp without Disp16|Disp32 as Intel64.
557 * i386-init.h: Regenerated.
558 * i386-tbl.h: Likewise.
559
4bc0608a
PB		 5602015-05-14 Peter Bergner <bergner@vnet.ibm.com>
561
562 * ppc-opc.c (IH) New define.
563 (powerpc_opcodes) <wait>: Do not enable for POWER7.
564 <tlbie>: Add RS operand for POWER7.
565 <slbia>: Add IH operand for POWER6.
566
70cead07
L		 5672015-05-11 H.J. Lu <hongjiu.lu@intel.com>
568
569 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
570 direct branch.
571 (jmp): Likewise.
572 * i386-tbl.h: Regenerated.
573
7b6d09fb
L		 5742015-05-11 H.J. Lu <hongjiu.lu@intel.com>
575
576 * configure.ac: Support bfd_iamcu_arch.
577 * disassemble.c (disassembler): Support bfd_iamcu_arch.
578 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
579 CPU_IAMCU_COMPAT_FLAGS.
580 (cpu_flags): Add CpuIAMCU.
581 * i386-opc.h (CpuIAMCU): New.
582 (i386_cpu_flags): Add cpuiamcu.
583 * configure: Regenerated.
584 * i386-init.h: Likewise.
585 * i386-tbl.h: Likewise.
586
31955f99
L		 5872015-05-08 H.J. Lu <hongjiu.lu@intel.com>
588
589 PR binutis/18386
590 * i386-dis.c (X86_64_E8): New.
591 (X86_64_E9): Likewise.
592 Update comments on 'T', 'U', 'V'. Add comments for '^'.
593 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
594 (x86_64_table): Add X86_64_E8 and X86_64_E9.
595 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
596 (putop): Handle '^'.
597 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
598 REX_W.
599
0952813b
DD		 6002015-04-30 DJ Delorie <dj@redhat.com>
601
602 * disassemble.c (disassembler): Choose suitable disassembler based
603 on E_ABI.
604 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
605 it to decode mul/div insns.
606 * rl78-decode.c: Regenerate.
607 * rl78-dis.c (print_insn_rl78): Rename to...
608 (print_insn_rl78_common): ...this, take ISA parameter.
609 (print_insn_rl78): New.
610 (print_insn_rl78_g10): New.
611 (print_insn_rl78_g13): New.
612 (print_insn_rl78_g14): New.
613 (rl78_get_disassembler): New.
614
f9d3ecaa
NC		 6152015-04-29 Nick Clifton <nickc@redhat.com>
616
617 * po/fr.po: Updated French translation.
618
4fff86c5
PB		 6192015-04-27 Peter Bergner <bergner@vnet.ibm.com>
620
621 * ppc-opc.c (DCBT_EO): New define.
622 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
623 <lharx>: Likewise.
624 <stbcx.>: Likewise.
625 <sthcx.>: Likewise.
626 <waitrsv>: Do not enable for POWER7 and later.
627 <waitimpl>: Likewise.
628 <dcbt>: Default to the two operand form of the instruction for all
629 "old" cpus. For "new" cpus, use the operand ordering that matches
630 whether the cpu is server or embedded.
631 <dcbtst>: Likewise.
632
3b78cfe1
AK		 6332015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
634
635 * s390-opc.c: New instruction type VV0UU2.
636 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
637 and WFC.
638
04d824a4
JB		 6392015-04-23 Jan Beulich <jbeulich@suse.com>
640
641 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
642 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
643 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
644 (vfpclasspd, vfpclassps): Add %XZ.
645
09708981
L		 6462015-04-15 H.J. Lu <hongjiu.lu@intel.com>
647
648 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
649 (PREFIX_UD_REPZ): Likewise.
650 (PREFIX_UD_REPNZ): Likewise.
651 (PREFIX_UD_DATA): Likewise.
652 (PREFIX_UD_ADDR): Likewise.
653 (PREFIX_UD_LOCK): Likewise.
654
3888916d
L		 6552015-04-15 H.J. Lu <hongjiu.lu@intel.com>
656
657 * i386-dis.c (prefix_requirement): Removed.
658 (print_insn): Don't set prefix_requirement. Check
659 dp->prefix_requirement instead of prefix_requirement.
660
f24bcbaa
L		 6612015-04-15 H.J. Lu <hongjiu.lu@intel.com>
662
663 PR binutils/17898
664 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
665 (PREFIX_MOD_0_0FC7_REG_6): This.
666 (PREFIX_MOD_3_0FC7_REG_6): New.
667 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
668 (prefix_table): Replace PREFIX_0FC7_REG_6 with
669 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
670 PREFIX_MOD_3_0FC7_REG_7.
671 (mod_table): Replace PREFIX_0FC7_REG_6 with
672 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
673 PREFIX_MOD_3_0FC7_REG_7.
674
507bd325
L		 6752015-04-15 H.J. Lu <hongjiu.lu@intel.com>
676
677 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
678 (PREFIX_MANDATORY_REPNZ): Likewise.
679 (PREFIX_MANDATORY_DATA): Likewise.
680 (PREFIX_MANDATORY_ADDR): Likewise.
681 (PREFIX_MANDATORY_LOCK): Likewise.
682 (PREFIX_MANDATORY): Likewise.
683 (PREFIX_UD_SHIFT): Set to 8
684 (PREFIX_UD_REPZ): Updated.
685 (PREFIX_UD_REPNZ): Likewise.
686 (PREFIX_UD_DATA): Likewise.
687 (PREFIX_UD_ADDR): Likewise.
688 (PREFIX_UD_LOCK): Likewise.
689 (PREFIX_IGNORED_SHIFT): New.
690 (PREFIX_IGNORED_REPZ): Likewise.
691 (PREFIX_IGNORED_REPNZ): Likewise.
692 (PREFIX_IGNORED_DATA): Likewise.
693 (PREFIX_IGNORED_ADDR): Likewise.
694 (PREFIX_IGNORED_LOCK): Likewise.
695 (PREFIX_OPCODE): Likewise.
696 (PREFIX_IGNORED): Likewise.
697 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
698 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
699 (three_byte_table): Likewise.
700 (mod_table): Likewise.
701 (mandatory_prefix): Renamed to ...
702 (prefix_requirement): This.
703 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
704 Update PREFIX_90 entry.
705 (get_valid_dis386): Check prefix_requirement to see if a prefix
706 should be ignored.
707 (print_insn): Replace mandatory_prefix with prefix_requirement.
708
f0fba320
RL		 7092015-04-15 Renlin Li <renlin.li@arm.com>
710
711 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
712 use it for ssat and ssat16.
713 (print_insn_thumb32): Add handle case for 'D' control code.
714
bf890a93
IT		 7152015-04-06 Ilya Tocar <ilya.tocar@intel.com>
716 H.J. Lu <hongjiu.lu@intel.com>
717
718 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
719 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
720 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
721 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
722 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
723 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
724 Fill prefix_requirement field.
725 (struct dis386): Add prefix_requirement field.
726 (dis386): Fill prefix_requirement field.
727 (dis386_twobyte): Ditto.
728 (twobyte_has_mandatory_prefix_: Remove.
729 (reg_table): Fill prefix_requirement field.
730 (prefix_table): Ditto.
731 (x86_64_table): Ditto.
732 (three_byte_table): Ditto.
733 (xop_table): Ditto.
734 (vex_table): Ditto.
735 (vex_len_table): Ditto.
736 (vex_w_table): Ditto.
737 (mod_table): Ditto.
738 (bad_opcode): Ditto.
739 (print_insn): Use prefix_requirement.
740 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
741 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
742 (float_reg): Ditto.
743
2f783c1f
MF		 7442015-03-30 Mike Frysinger <vapier@gentoo.org>
745
746 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
747
b9d94d62
L		 7482015-03-29 H.J. Lu <hongjiu.lu@intel.com>
749
750 * Makefile.in: Regenerated.
751
27c49e9a
AB		 7522015-03-25 Anton Blanchard <anton@samba.org>
753
754 * ppc-dis.c (disassemble_init_powerpc): Only initialise
755 powerpc_opcd_indices and vle_opcd_indices once.
756
c4e676f1
AB		 7572015-03-25 Anton Blanchard <anton@samba.org>
758
759 * ppc-opc.c (powerpc_opcodes): Add slbfee.
760
823d2571
TG		 7612015-03-24 Terry Guo <terry.guo@arm.com>
762
763 * arm-dis.c (opcode32): Updated to use new arm feature struct.
764 (opcode16): Likewise.
765 (coprocessor_opcodes): Replace bit with feature struct.
766 (neon_opcodes): Likewise.
767 (arm_opcodes): Likewise.
768 (thumb_opcodes): Likewise.
769 (thumb32_opcodes): Likewise.
770 (print_insn_coprocessor): Likewise.
771 (print_insn_arm): Likewise.
772 (select_arm_features): Follow new feature struct.
773
029f3522
GG		 7742015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
775
776 * i386-dis.c (rm_table): Add clzero.
777 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
778 Add CPU_CLZERO_FLAGS.
779 (cpu_flags): Add CpuCLZERO.
780 * i386-opc.h: Add CpuCLZERO.
781 * i386-opc.tbl: Add clzero.
782 * i386-init.h: Re-generated.
783 * i386-tbl.h: Re-generated.
784
6914869a
AB		 7852015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
786
787 * mips-opc.c (decode_mips_operand): Fix constraint issues
788 with u and y operands.
789
21e20815
AB		 7902015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
791
792 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
793
6b1d7593
AK		 7942015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
795
796 * s390-opc.c: Add new IBM z13 instructions.
797 * s390-opc.txt: Likewise.
798
c8f89a34
JW		 7992015-03-10 Renlin Li <renlin.li@arm.com>
800
801 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
802 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
803 related alias.
804 * aarch64-asm-2.c: Regenerate.
805 * aarch64-dis-2.c: Likewise.
806 * aarch64-opc-2.c: Likewise.
807
d8282f0e
JW		 8082015-03-03 Jiong Wang <jiong.wang@arm.com>
809
810 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
811
ac994365
OE		 8122015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
813
814 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
815 arch_sh_up.
816 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
817 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
818
fd63f640
V		 8192015-02-23 Vinay <Vinay.G@kpit.com>
820
821 * rl78-decode.opc (MOV): Added space between two operands for
822 'mov' instruction in index addressing mode.
823 * rl78-decode.c: Regenerate.
824
f63c1776
PA		 8252015-02-19 Pedro Alves <palves@redhat.com>
826
827 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
828
07774fcc
PA		 8292015-02-10 Pedro Alves <palves@redhat.com>
830 Tom Tromey <tromey@redhat.com>
831
832 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
833 microblaze_and, microblaze_xor.
834 * microblaze-opc.h (opcodes): Adjust.
835
3f8107ab
AM		 8362015-01-28 James Bowman <james.bowman@ftdichip.com>
837
838 * Makefile.am: Add FT32 files.
839 * configure.ac: Handle FT32.
840 * disassemble.c (disassembler): Call print_insn_ft32.
841 * ft32-dis.c: New file.
842 * ft32-opc.c: New file.
843 * Makefile.in: Regenerate.
844 * configure: Regenerate.
845 * po/POTFILES.in: Regenerate.
846
e5fe4957
KLC		 8472015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
848
849 * nds32-asm.c (keyword_sr): Add new system registers.
850
1e2e8c52
AK		 8512015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
852
853 * s390-dis.c (s390_extract_operand): Support vector register
854 operands.
855 (s390_print_insn_with_opcode): Support new operands types and add
856 new handling of optional operands.
857 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
858 and include opcode/s390.h instead.
859 (struct op_struct): New field `flags'.
860 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
861 (dumpTable): Dump flags.
862 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
863 string.
864 * s390-opc.c: Add new operands types, instruction formats, and
865 instruction masks.
866 (s390_opformats): Add new formats for .insn.
867 * s390-opc.txt: Add new instructions.
868
b90efa5b 8692015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 870
b90efa5b 871 Update year range in copyright notice of all files.
bffb6004 872
b90efa5b 873For older changes see ChangeLog-2014
252b5132 874\f
b90efa5b 875Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 876
877Copying and distribution of this file, with or without modification,
878are permitted in any medium without royalty provided the copyright
879notice and this notice are preserved.
880
252b5132 881Local Variables:
2f6d2f85
NC		 882mode: change-log
883left-margin: 8
884fill-column: 74
252b5132
RH		 885version-control: never
886End:
GDB Binutils - Deliverables
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