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aarch64 and arm testsuite fixes for targets lacking shared libs
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7abb8d81
JB		 12019-11-05 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (OP_Mwaitx): Delete.
4 (prefix_table): Use OP_Mwait for mwaitx entry.
5 (OP_Mwait): Also handle mwaitx.
6
267b8516
JB		 72019-11-05 Jan Beulich <jbeulich@suse.com>
8
9 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
10 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
11 (prefix_table): Add respective entries.
12 (rm_table): Link to those entries.
13
f8687e93
JB		 142019-11-05 Jan Beulich <jbeulich@suse.com>
15
16 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
17 (REG_0F1C_P_0_MOD_0): ... this.
18 (REG_0F1E_MOD_3): Rename to ...
19 (REG_0F1E_P_1_MOD_3): ... this.
20 (RM_0F01_REG_5): Rename to ...
21 (RM_0F01_REG_5_MOD_3): ... this.
22 (RM_0F01_REG_7): Rename to ...
23 (RM_0F01_REG_7_MOD_3): ... this.
24 (RM_0F1E_MOD_3_REG_7): Rename to ...
25 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
26 (RM_0FAE_REG_6): Rename to ...
27 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
28 (RM_0FAE_REG_7): Rename to ...
29 (RM_0FAE_REG_7_MOD_3): ... this.
30 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
31 (PREFIX_0F01_REG_5_MOD_0): ... this.
32 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
33 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
34 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
35 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
36 (PREFIX_0FAE_REG_0): Rename to ...
37 (PREFIX_0FAE_REG_0_MOD_3): ... this.
38 (PREFIX_0FAE_REG_1): Rename to ...
39 (PREFIX_0FAE_REG_1_MOD_3): ... this.
40 (PREFIX_0FAE_REG_2): Rename to ...
41 (PREFIX_0FAE_REG_2_MOD_3): ... this.
42 (PREFIX_0FAE_REG_3): Rename to ...
43 (PREFIX_0FAE_REG_3_MOD_3): ... this.
44 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
45 (PREFIX_0FAE_REG_4_MOD_0): ... this.
46 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
47 (PREFIX_0FAE_REG_4_MOD_3): ... this.
48 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
49 (PREFIX_0FAE_REG_5_MOD_0): ... this.
50 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
51 (PREFIX_0FAE_REG_5_MOD_3): ... this.
52 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
53 (PREFIX_0FAE_REG_6_MOD_0): ... this.
54 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
55 (PREFIX_0FAE_REG_6_MOD_3): ... this.
56 (PREFIX_0FAE_REG_7): Rename to ...
57 (PREFIX_0FAE_REG_7_MOD_0): ... this.
58 (PREFIX_MOD_0_0FC3): Rename to ...
59 (PREFIX_0FC3_MOD_0): ... this.
60 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
61 (PREFIX_0FC7_REG_6_MOD_0): ... this.
62 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
63 (PREFIX_0FC7_REG_6_MOD_3): ... this.
64 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
65 (PREFIX_0FC7_REG_7_MOD_3): ... this.
66 (reg_table, prefix_table, mod_table, rm_table): Adjust
67 accordingly.
68
5103274f
NC		 692019-11-04 Nick Clifton <nickc@redhat.com>
70
71 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
72 of a v850 system register. Move the v850_sreg_names array into
73 this function.
74 (get_v850_reg_name): Likewise for ordinary register names.
75 (get_v850_vreg_name): Likewise for vector register names.
76 (get_v850_cc_name): Likewise for condition codes.
77 * get_v850_float_cc_name): Likewise for floating point condition
78 codes.
79 (get_v850_cacheop_name): Likewise for cache-ops.
80 (get_v850_prefop_name): Likewise for pref-ops.
81 (disassemble): Use the new accessor functions.
82
1820262b
DB		 832019-10-30 Delia Burduv <delia.burduv@arm.com>
84
85 * aarch64-opc.c (print_immediate_offset_address): Don't print the
86 immediate for the writeback form of ldraa/ldrab if it is 0.
87 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
88 * aarch64-opc-2.c: Regenerated.
89
3cc17af5
JB		 902019-10-30 Jan Beulich <jbeulich@suse.com>
91
92 * i386-gen.c (operand_type_shorthands): Delete.
93 (operand_type_init): Expand previous shorthands.
94 (set_bitfield_from_shorthand): Rename back to ...
95 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
96 of operand_type_init[].
97 (set_bitfield): Adjust call to the above function.
98 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
99 RegXMM, RegYMM, RegZMM): Define.
100 * i386-reg.tbl: Expand prior shorthands.
101
a2cebd03
JB		 1022019-10-30 Jan Beulich <jbeulich@suse.com>
103
104 * i386-gen.c (output_i386_opcode): Change order of fields
105 emitted to output.
106 * i386-opc.h (struct insn_template): Move operands field.
107 Convert extension_opcode field to unsigned short.
108 * i386-tbl.h: Re-generate.
109
507916b8
JB		 1102019-10-30 Jan Beulich <jbeulich@suse.com>
111
112 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
113 of W.
114 * i386-opc.h (W): Extend comment.
115 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
116 general purpose variants not allowing for byte operands.
117 * i386-tbl.h: Re-generate.
118
efea62b4
NC		 1192019-10-29 Nick Clifton <nickc@redhat.com>
120
121 * tic30-dis.c (print_branch): Correct size of operand array.
122
9adb2591
NC		 1232019-10-29 Nick Clifton <nickc@redhat.com>
124
125 * d30v-dis.c (print_insn): Check that operand index is valid
126 before attempting to access the operands array.
127
993a00a9
NC		 1282019-10-29 Nick Clifton <nickc@redhat.com>
129
130 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
131 locating the bit to be tested.
132
66a66a17
NC		 1332019-10-29 Nick Clifton <nickc@redhat.com>
134
135 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
136 values.
137 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
138 (print_insn_s12z): Check for illegal size values.
139
1ee3542c
NC		 1402019-10-28 Nick Clifton <nickc@redhat.com>
141
142 * csky-dis.c (csky_chars_to_number): Check for a negative
143 count. Use an unsigned integer to construct the return value.
144
bbf9a0b5
NC		 1452019-10-28 Nick Clifton <nickc@redhat.com>
146
147 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
148 operand buffer. Set value to 15 not 13.
149 (get_register_operand): Use OPERAND_BUFFER_LEN.
150 (get_indirect_operand): Likewise.
151 (print_two_operand): Likewise.
152 (print_three_operand): Likewise.
153 (print_oar_insn): Likewise.
154
d1e304bc
NC		 1552019-10-28 Nick Clifton <nickc@redhat.com>
156
157 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
158 (bit_extract_simple): Likewise.
159 (bit_copy): Likewise.
160 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
161 index_offset array are not accessed.
162
dee33451
NC		 1632019-10-28 Nick Clifton <nickc@redhat.com>
164
165 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
166 operand.
167
27cee81d
NC		 1682019-10-25 Nick Clifton <nickc@redhat.com>
169
170 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
171 access to opcodes.op array element.
172
de6d8dc2
NC		 1732019-10-23 Nick Clifton <nickc@redhat.com>
174
175 * rx-dis.c (get_register_name): Fix spelling typo in error
176 message.
177 (get_condition_name, get_flag_name, get_double_register_name)
178 (get_double_register_high_name, get_double_register_low_name)
179 (get_double_control_register_name, get_double_condition_name)
180 (get_opsize_name, get_size_name): Likewise.
181
6207ed28
NC		 1822019-10-22 Nick Clifton <nickc@redhat.com>
183
184 * rx-dis.c (get_size_name): New function. Provides safe
185 access to name array.
186 (get_opsize_name): Likewise.
187 (print_insn_rx): Use the accessor functions.
188
12234dfd
NC		 1892019-10-16 Nick Clifton <nickc@redhat.com>
190
191 * rx-dis.c (get_register_name): New function. Provides safe
192 access to name array.
193 (get_condition_name, get_flag_name, get_double_register_name)
194 (get_double_register_high_name, get_double_register_low_name)
195 (get_double_control_register_name, get_double_condition_name):
196 Likewise.
197 (print_insn_rx): Use the accessor functions.
198
1d378749
NC		 1992019-10-09 Nick Clifton <nickc@redhat.com>
200
201 PR 25041
202 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
203 instructions.
204
d241b910
JB		 2052019-10-07 Jan Beulich <jbeulich@suse.com>
206
207 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
208 (cmpsd): Likewise. Move EsSeg to other operand.
209 * opcodes/i386-tbl.h: Re-generate.
210
f5c5b7c1
AM		 2112019-09-23 Alan Modra <amodra@gmail.com>
212
213 * m68k-dis.c: Include cpu-m68k.h
214
7beeaeb8
AM		 2152019-09-23 Alan Modra <amodra@gmail.com>
216
217 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
218 "elf/mips.h" earlier.
219
3f9aad11
JB		 2202018-09-20 Jan Beulich <jbeulich@suse.com>
221
222 PR gas/25012
223 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
224 with SReg operand.
225 * i386-tbl.h: Re-generate.
226
fd361982
AM		 2272019-09-18 Alan Modra <amodra@gmail.com>
228
229 * arc-ext.c: Update throughout for bfd section macro changes.
230
e0b2a78c
SM		 2312019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
232
233 * Makefile.in: Re-generate.
234 * configure: Re-generate.
235
7e9ad3a3
JW		 2362019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
237
238 * riscv-opc.c (riscv_opcodes): Change subset field
239 to insn_class field for all instructions.
240 (riscv_insn_types): Likewise.
241
bb695960
PB		 2422019-09-16 Phil Blundell <pb@pbcl.net>
243
244 * configure: Regenerated.
245
8063ab7e
MV		 2462019-09-10 Miod Vallat <miod@online.fr>
247
248 PR 24982
249 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
250
60391a25
PB		 2512019-09-09 Phil Blundell <pb@pbcl.net>
252
253 binutils 2.33 branch created.
254
f44b758d
NC		 2552019-09-03 Nick Clifton <nickc@redhat.com>
256
257 PR 24961
258 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
259 greater than zero before indexing via (bufcnt -1).
260
1e4b5e7d
NC		 2612019-09-03 Nick Clifton <nickc@redhat.com>
262
263 PR 24958
264 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
265 (MAX_SPEC_REG_NAME_LEN): Define.
266 (struct mmix_dis_info): Use defined constants for array lengths.
267 (get_reg_name): New function.
268 (get_sprec_reg_name): New function.
269 (print_insn_mmix): Use new functions.
270
c4a23bf8
SP		 2712019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
272
273 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
274 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
275 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
276
a051e2f3
KT		 2772019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
278
279 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
280 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
281 (aarch64_sys_reg_supported_p): Update checks for the above.
282
08132bdd
SP		 2832019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
284
285 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
286 cases MVE_SQRSHRL and MVE_UQRSHLL.
287 (print_insn_mve): Add case for specifier 'k' to check
288 specific bit of the instruction.
289
d88bdcb4
PA		 2902019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
291
292 PR 24854
293 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
294 encountering an unknown machine type.
295 (print_insn_arc): Handle arc_insn_length returning 0. In error
296 cases return -1 rather than calling abort.
297
bc750500
JB		 2982019-08-07 Jan Beulich <jbeulich@suse.com>
299
300 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
301 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
302 IgnoreSize.
303 * i386-tbl.h: Re-generate.
304
23d188c7
BW		 3052019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
306
307 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
308 instructions.
309
c0d6f62f
JW		 3102019-07-30 Mel Chen <mel.chen@sifive.com>
311
312 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
313 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
314
315 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
316 fscsr.
317
0f3f7167
CZ		 3182019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
319
320 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
321 and MPY class instructions.
322 (parse_option): Add nps400 option.
323 (print_arc_disassembler_options): Add nps400 info.
324
7e126ba3
CZ		 3252019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
326
327 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
328 (bspop): Likewise.
329 (modapp): Likewise.
330 * arc-opc.c (RAD_CHK): Add.
331 * arc-tbl.h: Regenerate.
332
a028026d
KT		 3332019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
334
335 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
336 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
337
ac79ff9e
NC		 3382019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
339
340 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
341 instructions as UNPREDICTABLE.
342
231097b0
JM		 3432019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
344
345 * bpf-desc.c: Regenerated.
346
1d942ae9
JB		 3472019-07-17 Jan Beulich <jbeulich@suse.com>
348
349 * i386-gen.c (static_assert): Define.
350 (main): Use it.
351 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
352 (Opcode_Modifier_Num): ... this.
353 (Mem): Delete.
354
dfd69174
JB		 3552019-07-16 Jan Beulich <jbeulich@suse.com>
356
357 * i386-gen.c (operand_types): Move RegMem ...
358 (opcode_modifiers): ... here.
359 * i386-opc.h (RegMem): Move to opcode modifer enum.
360 (union i386_operand_type): Move regmem field ...
361 (struct i386_opcode_modifier): ... here.
362 * i386-opc.tbl (RegMem): Define.
363 (mov, movq): Move RegMem on segment, control, debug, and test
364 register flavors.
365 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
366 to non-SSE2AVX flavor.
367 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
368 Move RegMem on register only flavors. Drop IgnoreSize from
369 legacy encoding flavors.
370 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
371 flavors.
372 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
373 register only flavors.
374 (vmovd): Move RegMem and drop IgnoreSize on register only
375 flavor. Change opcode and operand order to store form.
376 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
377
21df382b
JB		 3782019-07-16 Jan Beulich <jbeulich@suse.com>
379
380 * i386-gen.c (operand_type_init, operand_types): Replace SReg
381 entries.
382 * i386-opc.h (SReg2, SReg3): Replace by ...
383 (SReg): ... this.
384 (union i386_operand_type): Replace sreg fields.
385 * i386-opc.tbl (mov, ): Use SReg.
386 (push, pop): Likewies. Drop i386 and x86-64 specific segment
387 register flavors.
388 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
389 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
390
3719fd55
JM		 3912019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
392
393 * bpf-desc.c: Regenerate.
394 * bpf-opc.c: Likewise.
395 * bpf-opc.h: Likewise.
396
92434a14
JM		 3972019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
398
399 * bpf-desc.c: Regenerate.
400 * bpf-opc.c: Likewise.
401
43dd7626
HPN		 4022019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
403
404 * arm-dis.c (print_insn_coprocessor): Rename index to
405 index_operand.
406
98602811
JW		 4072019-07-05 Kito Cheng <kito.cheng@sifive.com>
408
409 * riscv-opc.c (riscv_insn_types): Add r4 type.
410
411 * riscv-opc.c (riscv_insn_types): Add b and j type.
412
413 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
414 format for sb type and correct s type.
415
01c1ee4a
RS		 4162019-07-02 Richard Sandiford <richard.sandiford@arm.com>
417
418 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
419 SVE FMOV alias of FCPY.
420
83adff69
RS		 4212019-07-02 Richard Sandiford <richard.sandiford@arm.com>
422
423 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
424 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
425
89418844
RS		 4262019-07-02 Richard Sandiford <richard.sandiford@arm.com>
427
428 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
429 registers in an instruction prefixed by MOVPRFX.
430
41be57ca
MM		 4312019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
432
433 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
434 sve_size_13 icode to account for variant behaviour of
435 pmull{t,b}.
436 * aarch64-dis-2.c: Regenerate.
437 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
438 sve_size_13 icode to account for variant behaviour of
439 pmull{t,b}.
440 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
441 (OP_SVE_VVV_Q_D): Add new qualifier.
442 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
443 (struct aarch64_opcode): Split pmull{t,b} into those requiring
444 AES and those not.
445
9d3bf266
JB		 4462019-07-01 Jan Beulich <jbeulich@suse.com>
447
448 * opcodes/i386-gen.c (operand_type_init): Remove
449 OPERAND_TYPE_VEC_IMM4 entry.
450 (operand_types): Remove Vec_Imm4.
451 * opcodes/i386-opc.h (Vec_Imm4): Delete.
452 (union i386_operand_type): Remove vec_imm4.
453 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
454 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
455
c3949f43
JB		 4562019-07-01 Jan Beulich <jbeulich@suse.com>
457
458 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
459 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
460 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
461 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
462 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
463 monitorx, mwaitx): Drop ImmExt from operand-less forms.
464 * i386-tbl.h: Re-generate.
465
5641ec01
JB		 4662019-07-01 Jan Beulich <jbeulich@suse.com>
467
468 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
469 register operands.
470 * i386-tbl.h: Re-generate.
471
79dec6b7
JB		 4722019-07-01 Jan Beulich <jbeulich@suse.com>
473
474 * i386-opc.tbl (C): New.
475 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
476 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
477 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
478 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
479 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
480 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
481 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
482 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
483 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
484 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
485 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
486 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
487 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
488 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
489 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
490 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
491 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
492 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
493 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
494 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
495 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
496 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
497 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
498 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
499 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
500 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
501 flavors.
502 * i386-tbl.h: Re-generate.
503
a0a1771e
JB		 5042019-07-01 Jan Beulich <jbeulich@suse.com>
505
506 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
507 register operands.
508 * i386-tbl.h: Re-generate.
509
cd546e7b
JB		 5102019-07-01 Jan Beulich <jbeulich@suse.com>
511
512 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
513 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
514 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
515 * i386-tbl.h: Re-generate.
516
e3bba3fc
JB		 5172019-07-01 Jan Beulich <jbeulich@suse.com>
518
519 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
520 Disp8MemShift from register only templates.
521 * i386-tbl.h: Re-generate.
522
36cc073e
JB		 5232019-07-01 Jan Beulich <jbeulich@suse.com>
524
525 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
526 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
527 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
528 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
529 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
530 EVEX_W_0F11_P_3_M_1): Delete.
531 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
532 EVEX_W_0F11_P_3): New.
533 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
534 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
535 MOD_EVEX_0F11_PREFIX_3 table entries.
536 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
537 PREFIX_EVEX_0F11 table entries.
538 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
539 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
540 EVEX_W_0F11_P_3_M_{0,1} table entries.
541
219920a7
JB		 5422019-07-01 Jan Beulich <jbeulich@suse.com>
543
544 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
545 Delete.
546
e395f487
L		 5472019-06-27 H.J. Lu <hongjiu.lu@intel.com>
548
549 PR binutils/24719
550 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
551 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
552 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
553 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
554 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
555 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
556 EVEX_LEN_0F38C7_R_6_P_2_W_1.
557 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
558 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
559 PREFIX_EVEX_0F38C6_REG_6 entries.
560 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
561 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
562 EVEX_W_0F38C7_R_6_P_2 entries.
563 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
564 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
565 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
566 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
567 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
568 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
569 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
570
2b7bcc87
JB		 5712019-06-27 Jan Beulich <jbeulich@suse.com>
572
573 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
574 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
575 VEX_LEN_0F2D_P_3): Delete.
576 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
577 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
578 (prefix_table): ... here.
579
c1dc7af5
JB		 5802019-06-27 Jan Beulich <jbeulich@suse.com>
581
582 * i386-dis.c (Iq): Delete.
583 (Id): New.
584 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
585 TBM insns.
586 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
587 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
588 (OP_E_memory): Also honor needindex when deciding whether an
589 address size prefix needs printing.
590 (OP_I): Remove handling of q_mode. Add handling of d_mode.
591
d7560e2d
JW		 5922019-06-26 Jim Wilson <jimw@sifive.com>
593
594 PR binutils/24739
595 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
596 Set info->display_endian to info->endian_code.
597
2c703856
JB		 5982019-06-25 Jan Beulich <jbeulich@suse.com>
599
600 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
601 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
602 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
603 OPERAND_TYPE_ACC64 entries.
604 * i386-init.h: Re-generate.
605
54fbadc0
JB		 6062019-06-25 Jan Beulich <jbeulich@suse.com>
607
608 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
609 Delete.
610 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
611 of dqa_mode.
612 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
613 entries here.
614 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
615 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
616
a280ab8e
JB		 6172019-06-25 Jan Beulich <jbeulich@suse.com>
618
619 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
620 variables.
621
e1a1babd
JB		 6222019-06-25 Jan Beulich <jbeulich@suse.com>
623
624 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
625 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
626 movnti.
d7560e2d 627 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 628 * i386-tbl.h: Re-generate.
629
b8364fa7
JB		 6302019-06-25 Jan Beulich <jbeulich@suse.com>
631
632 * i386-opc.tbl (and): Mark Imm8S form for optimization.
633 * i386-tbl.h: Re-generate.
634
ad692897
L		 6352019-06-21 H.J. Lu <hongjiu.lu@intel.com>
636
637 * i386-dis-evex.h: Break into ...
638 * i386-dis-evex-len.h: New file.
639 * i386-dis-evex-mod.h: Likewise.
640 * i386-dis-evex-prefix.h: Likewise.
641 * i386-dis-evex-reg.h: Likewise.
642 * i386-dis-evex-w.h: Likewise.
643 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
644 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
645 i386-dis-evex-mod.h.
646
f0a6222e
L		 6472019-06-19 H.J. Lu <hongjiu.lu@intel.com>
648
649 PR binutils/24700
650 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
651 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
652 EVEX_W_0F385B_P_2.
653 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
654 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
655 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
656 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
657 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
658 EVEX_LEN_0F385B_P_2_W_1.
659 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
660 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
661 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
662 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
663 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
664 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
665 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
666 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
667 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
668 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
669
6e1c90b7
L		 6702019-06-17 H.J. Lu <hongjiu.lu@intel.com>
671
672 PR binutils/24691
673 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
674 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
675 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
676 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
677 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
678 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
679 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
680 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
681 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
682 EVEX_LEN_0F3A43_P_2_W_1.
683 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
684 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
685 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
686 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
687 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
688 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
689 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
690 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
691 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
692 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
693 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
694 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
695
bcc5a6eb
NC		 6962019-06-14 Nick Clifton <nickc@redhat.com>
697
698 * po/fr.po; Updated French translation.
699
e4c4ac46
SH		 7002019-06-13 Stafford Horne <shorne@gmail.com>
701
702 * or1k-asm.c: Regenerated.
703 * or1k-desc.c: Regenerated.
704 * or1k-desc.h: Regenerated.
705 * or1k-dis.c: Regenerated.
706 * or1k-ibld.c: Regenerated.
707 * or1k-opc.c: Regenerated.
708 * or1k-opc.h: Regenerated.
709 * or1k-opinst.c: Regenerated.
710
a0e44ef5
PB		 7112019-06-12 Peter Bergner <bergner@linux.ibm.com>
712
713 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
714
12efd68d
L		 7152019-06-05 H.J. Lu <hongjiu.lu@intel.com>
716
717 PR binutils/24633
718 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
719 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
720 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
721 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
722 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
723 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
724 EVEX_LEN_0F3A1B_P_2_W_1.
725 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
726 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
727 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
728 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
729 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
730 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
731 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
732 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
733
63c6fc6c
L		 7342019-06-04 H.J. Lu <hongjiu.lu@intel.com>
735
736 PR binutils/24626
737 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
738 EVEX.vvvv when disassembling VEX and EVEX instructions.
739 (OP_VEX): Set vex.register_specifier to 0 after readding
740 vex.register_specifier.
741 (OP_Vex_2src_1): Likewise.
742 (OP_Vex_2src_2): Likewise.
743 (OP_LWP_E): Likewise.
744 (OP_EX_Vex): Don't check vex.register_specifier.
745 (OP_XMM_Vex): Likewise.
746
9186c494
L		 7472019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
748 Lili Cui <lili.cui@intel.com>
749
750 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
751 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
752 instructions.
753 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
754 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
755 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
756 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
757 (i386_cpu_flags): Add cpuavx512_vp2intersect.
758 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
759 * i386-init.h: Regenerated.
760 * i386-tbl.h: Likewise.
761
5d79adc4
L		 7622019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
763 Lili Cui <lili.cui@intel.com>
764
765 * doc/c-i386.texi: Document enqcmd.
766 * testsuite/gas/i386/enqcmd-intel.d: New file.
767 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
768 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
769 * testsuite/gas/i386/enqcmd.d: Likewise.
770 * testsuite/gas/i386/enqcmd.s: Likewise.
771 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
772 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
773 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
774 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
775 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
776 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
777 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
778 and x86-64-enqcmd.
779
a9d96ab9
AH		 7802019-06-04 Alan Hayward <alan.hayward@arm.com>
781
782 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
783
4f6d070a
AM		 7842019-06-03 Alan Modra <amodra@gmail.com>
785
786 * ppc-dis.c (prefix_opcd_indices): Correct size.
787
a2f4b66c
L		 7882019-05-28 H.J. Lu <hongjiu.lu@intel.com>
789
790 PR gas/24625
791 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
792 Disp8ShiftVL.
793 * i386-tbl.h: Regenerated.
794
405b5bd8
AM		 7952019-05-24 Alan Modra <amodra@gmail.com>
796
797 * po/POTFILES.in: Regenerate.
798
8acf1435
PB		 7992019-05-24 Peter Bergner <bergner@linux.ibm.com>
800 Alan Modra <amodra@gmail.com>
801
802 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
803 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
804 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
805 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
806 XTOP>): Define and add entries.
807 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
808 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
809 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
810 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
811
dd7efa79
PB		 8122019-05-24 Peter Bergner <bergner@linux.ibm.com>
813 Alan Modra <amodra@gmail.com>
814
815 * ppc-dis.c (ppc_opts): Add "future" entry.
816 (PREFIX_OPCD_SEGS): Define.
817 (prefix_opcd_indices): New array.
818 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
819 (lookup_prefix): New function.
820 (print_insn_powerpc): Handle 64-bit prefix instructions.
821 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
822 (PMRR, POWERXX): Define.
823 (prefix_opcodes): New instruction table.
824 (prefix_num_opcodes): New constant.
825
79472b45
JM		 8262019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
827
828 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
829 * configure: Regenerated.
830 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
831 and cpu/bpf.opc.
832 (HFILES): Add bpf-desc.h and bpf-opc.h.
833 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
834 bpf-ibld.c and bpf-opc.c.
835 (BPF_DEPS): Define.
836 * Makefile.in: Regenerated.
837 * disassemble.c (ARCH_bpf): Define.
838 (disassembler): Add case for bfd_arch_bpf.
839 (disassemble_init_for_target): Likewise.
840 (enum epbf_isa_attr): Define.
841 * disassemble.h: extern print_insn_bpf.
842 * bpf-asm.c: Generated.
843 * bpf-opc.h: Likewise.
844 * bpf-opc.c: Likewise.
845 * bpf-ibld.c: Likewise.
846 * bpf-dis.c: Likewise.
847 * bpf-desc.h: Likewise.
848 * bpf-desc.c: Likewise.
849
ba6cd17f
SD		 8502019-05-21 Sudakshina Das <sudi.das@arm.com>
851
852 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
853 and VMSR with the new operands.
854
e39c1607
SD		 8552019-05-21 Sudakshina Das <sudi.das@arm.com>
856
857 * arm-dis.c (enum mve_instructions): New enum
858 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
859 and cneg.
860 (mve_opcodes): New instructions as above.
861 (is_mve_encoding_conflict): Add cases for csinc, csinv,
862 csneg and csel.
863 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
864
23d00a41
SD		 8652019-05-21 Sudakshina Das <sudi.das@arm.com>
866
867 * arm-dis.c (emun mve_instructions): Updated for new instructions.
868 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
869 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
870 uqshl, urshrl and urshr.
871 (is_mve_okay_in_it): Add new instructions to TRUE list.
872 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
873 (print_insn_mve): Updated to accept new %j,
874 %<bitfield>m and %<bitfield>n patterns.
875
cd4797ee
FS		 8762019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
877
878 * mips-opc.c (mips_builtin_opcodes): Change source register
879 constraint for DAUI.
880
999b073b
NC		 8812019-05-20 Nick Clifton <nickc@redhat.com>
882
883 * po/fr.po: Updated French translation.
884
14b456f2
AV		 8852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
886 Michael Collison <michael.collison@arm.com>
887
888 * arm-dis.c (thumb32_opcodes): Add new instructions.
889 (enum mve_instructions): Likewise.
890 (enum mve_undefined): Add new reasons.
891 (is_mve_encoding_conflict): Handle new instructions.
892 (is_mve_undefined): Likewise.
893 (is_mve_unpredictable): Likewise.
894 (print_mve_undefined): Likewise.
895 (print_mve_size): Likewise.
896
f49bb598
AV		 8972019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
898 Michael Collison <michael.collison@arm.com>
899
900 * arm-dis.c (thumb32_opcodes): Add new instructions.
901 (enum mve_instructions): Likewise.
902 (is_mve_encoding_conflict): Handle new instructions.
903 (is_mve_undefined): Likewise.
904 (is_mve_unpredictable): Likewise.
905 (print_mve_size): Likewise.
906
56858bea
AV		 9072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
908 Michael Collison <michael.collison@arm.com>
909
910 * arm-dis.c (thumb32_opcodes): Add new instructions.
911 (enum mve_instructions): Likewise.
912 (is_mve_encoding_conflict): Likewise.
913 (is_mve_unpredictable): Likewise.
914 (print_mve_size): Likewise.
915
e523f101
AV		 9162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
917 Michael Collison <michael.collison@arm.com>
918
919 * arm-dis.c (thumb32_opcodes): Add new instructions.
920 (enum mve_instructions): Likewise.
921 (is_mve_encoding_conflict): Handle new instructions.
922 (is_mve_undefined): Likewise.
923 (is_mve_unpredictable): Likewise.
924 (print_mve_size): Likewise.
925
66dcaa5d
AV		 9262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
927 Michael Collison <michael.collison@arm.com>
928
929 * arm-dis.c (thumb32_opcodes): Add new instructions.
930 (enum mve_instructions): Likewise.
931 (is_mve_encoding_conflict): Handle new instructions.
932 (is_mve_undefined): Likewise.
933 (is_mve_unpredictable): Likewise.
934 (print_mve_size): Likewise.
935 (print_insn_mve): Likewise.
936
d052b9b7
AV		 9372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
938 Michael Collison <michael.collison@arm.com>
939
940 * arm-dis.c (thumb32_opcodes): Add new instructions.
941 (print_insn_thumb32): Handle new instructions.
942
ed63aa17
AV		 9432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
944 Michael Collison <michael.collison@arm.com>
945
946 * arm-dis.c (enum mve_instructions): Add new instructions.
947 (enum mve_undefined): Add new reasons.
948 (is_mve_encoding_conflict): Handle new instructions.
949 (is_mve_undefined): Likewise.
950 (is_mve_unpredictable): Likewise.
951 (print_mve_undefined): Likewise.
952 (print_mve_size): Likewise.
953 (print_mve_shift_n): Likewise.
954 (print_insn_mve): Likewise.
955
897b9bbc
AV		 9562019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
957 Michael Collison <michael.collison@arm.com>
958
959 * arm-dis.c (enum mve_instructions): Add new instructions.
960 (is_mve_encoding_conflict): Handle new instructions.
961 (is_mve_unpredictable): Likewise.
962 (print_mve_rotate): Likewise.
963 (print_mve_size): Likewise.
964 (print_insn_mve): Likewise.
965
1c8f2df8
AV		 9662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
967 Michael Collison <michael.collison@arm.com>
968
969 * arm-dis.c (enum mve_instructions): Add new instructions.
970 (is_mve_encoding_conflict): Handle new instructions.
971 (is_mve_unpredictable): Likewise.
972 (print_mve_size): Likewise.
973 (print_insn_mve): Likewise.
974
d3b63143
AV		 9752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
976 Michael Collison <michael.collison@arm.com>
977
978 * arm-dis.c (enum mve_instructions): Add new instructions.
979 (enum mve_undefined): Add new reasons.
980 (is_mve_encoding_conflict): Handle new instructions.
981 (is_mve_undefined): Likewise.
982 (is_mve_unpredictable): Likewise.
983 (print_mve_undefined): Likewise.
984 (print_mve_size): Likewise.
985 (print_insn_mve): Likewise.
986
14925797
AV		 9872019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
988 Michael Collison <michael.collison@arm.com>
989
990 * arm-dis.c (enum mve_instructions): Add new instructions.
991 (is_mve_encoding_conflict): Handle new instructions.
992 (is_mve_undefined): Likewise.
993 (is_mve_unpredictable): Likewise.
994 (print_mve_size): Likewise.
995 (print_insn_mve): Likewise.
996
c507f10b
AV		 9972019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
998 Michael Collison <michael.collison@arm.com>
999
1000 * arm-dis.c (enum mve_instructions): Add new instructions.
1001 (enum mve_unpredictable): Add new reasons.
1002 (enum mve_undefined): Likewise.
1003 (is_mve_okay_in_it): Handle new isntructions.
1004 (is_mve_encoding_conflict): Likewise.
1005 (is_mve_undefined): Likewise.
1006 (is_mve_unpredictable): Likewise.
1007 (print_mve_vmov_index): Likewise.
1008 (print_simd_imm8): Likewise.
1009 (print_mve_undefined): Likewise.
1010 (print_mve_unpredictable): Likewise.
1011 (print_mve_size): Likewise.
1012 (print_insn_mve): Likewise.
1013
bf0b396d
AV		 10142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1015 Michael Collison <michael.collison@arm.com>
1016
1017 * arm-dis.c (enum mve_instructions): Add new instructions.
1018 (enum mve_unpredictable): Add new reasons.
1019 (enum mve_undefined): Likewise.
1020 (is_mve_encoding_conflict): Handle new instructions.
1021 (is_mve_undefined): Likewise.
1022 (is_mve_unpredictable): Likewise.
1023 (print_mve_undefined): Likewise.
1024 (print_mve_unpredictable): Likewise.
1025 (print_mve_rounding_mode): Likewise.
1026 (print_mve_vcvt_size): Likewise.
1027 (print_mve_size): Likewise.
1028 (print_insn_mve): Likewise.
1029
ef1576a1
AV		 10302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1031 Michael Collison <michael.collison@arm.com>
1032
1033 * arm-dis.c (enum mve_instructions): Add new instructions.
1034 (enum mve_unpredictable): Add new reasons.
1035 (enum mve_undefined): Likewise.
1036 (is_mve_undefined): Handle new instructions.
1037 (is_mve_unpredictable): Likewise.
1038 (print_mve_undefined): Likewise.
1039 (print_mve_unpredictable): Likewise.
1040 (print_mve_size): Likewise.
1041 (print_insn_mve): Likewise.
1042
aef6d006
AV		 10432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1044 Michael Collison <michael.collison@arm.com>
1045
1046 * arm-dis.c (enum mve_instructions): Add new instructions.
1047 (enum mve_undefined): Add new reasons.
1048 (insns): Add new instructions.
1049 (is_mve_encoding_conflict):
1050 (print_mve_vld_str_addr): New print function.
1051 (is_mve_undefined): Handle new instructions.
1052 (is_mve_unpredictable): Likewise.
1053 (print_mve_undefined): Likewise.
1054 (print_mve_size): Likewise.
1055 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1056 (print_insn_mve): Handle new operands.
1057
04d54ace
AV		 10582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1059 Michael Collison <michael.collison@arm.com>
1060
1061 * arm-dis.c (enum mve_instructions): Add new instructions.
1062 (enum mve_unpredictable): Add new reasons.
1063 (is_mve_encoding_conflict): Handle new instructions.
1064 (is_mve_unpredictable): Likewise.
1065 (mve_opcodes): Add new instructions.
1066 (print_mve_unpredictable): Handle new reasons.
1067 (print_mve_register_blocks): New print function.
1068 (print_mve_size): Handle new instructions.
1069 (print_insn_mve): Likewise.
1070
9743db03
AV		 10712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1072 Michael Collison <michael.collison@arm.com>
1073
1074 * arm-dis.c (enum mve_instructions): Add new instructions.
1075 (enum mve_unpredictable): Add new reasons.
1076 (enum mve_undefined): Likewise.
1077 (is_mve_encoding_conflict): Handle new instructions.
1078 (is_mve_undefined): Likewise.
1079 (is_mve_unpredictable): Likewise.
1080 (coprocessor_opcodes): Move NEON VDUP from here...
1081 (neon_opcodes): ... to here.
1082 (mve_opcodes): Add new instructions.
1083 (print_mve_undefined): Handle new reasons.
1084 (print_mve_unpredictable): Likewise.
1085 (print_mve_size): Handle new instructions.
1086 (print_insn_neon): Handle vdup.
1087 (print_insn_mve): Handle new operands.
1088
143275ea
AV		 10892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1090 Michael Collison <michael.collison@arm.com>
1091
1092 * arm-dis.c (enum mve_instructions): Add new instructions.
1093 (enum mve_unpredictable): Add new values.
1094 (mve_opcodes): Add new instructions.
1095 (vec_condnames): New array with vector conditions.
1096 (mve_predicatenames): New array with predicate suffixes.
1097 (mve_vec_sizename): New array with vector sizes.
1098 (enum vpt_pred_state): New enum with vector predication states.
1099 (struct vpt_block): New struct type for vpt blocks.
1100 (vpt_block_state): Global struct to keep track of state.
1101 (mve_extract_pred_mask): New helper function.
1102 (num_instructions_vpt_block): Likewise.
1103 (mark_outside_vpt_block): Likewise.
1104 (mark_inside_vpt_block): Likewise.
1105 (invert_next_predicate_state): Likewise.
1106 (update_next_predicate_state): Likewise.
1107 (update_vpt_block_state): Likewise.
1108 (is_vpt_instruction): Likewise.
1109 (is_mve_encoding_conflict): Add entries for new instructions.
1110 (is_mve_unpredictable): Likewise.
1111 (print_mve_unpredictable): Handle new cases.
1112 (print_instruction_predicate): Likewise.
1113 (print_mve_size): New function.
1114 (print_vec_condition): New function.
1115 (print_insn_mve): Handle vpt blocks and new print operands.
1116
f08d8ce3
AV		 11172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1118
1119 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1120 8, 14 and 15 for Armv8.1-M Mainline.
1121
73cd51e5
AV		 11222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1123 Michael Collison <michael.collison@arm.com>
1124
1125 * arm-dis.c (enum mve_instructions): New enum.
1126 (enum mve_unpredictable): Likewise.
1127 (enum mve_undefined): Likewise.
1128 (struct mopcode32): New struct.
1129 (is_mve_okay_in_it): New function.
1130 (is_mve_architecture): Likewise.
1131 (arm_decode_field): Likewise.
1132 (arm_decode_field_multiple): Likewise.
1133 (is_mve_encoding_conflict): Likewise.
1134 (is_mve_undefined): Likewise.
1135 (is_mve_unpredictable): Likewise.
1136 (print_mve_undefined): Likewise.
1137 (print_mve_unpredictable): Likewise.
1138 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1139 (print_insn_mve): New function.
1140 (print_insn_thumb32): Handle MVE architecture.
1141 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1142
3076e594
NC		 11432019-05-10 Nick Clifton <nickc@redhat.com>
1144
1145 PR 24538
1146 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1147 end of the table prematurely.
1148
387e7624
FS		 11492019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1150
1151 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1152 macros for R6.
1153
0067be51
AM		 11542019-05-11 Alan Modra <amodra@gmail.com>
1155
1156 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1157 when -Mraw is in effect.
1158
42e6288f
MM		 11592019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1160
1161 * aarch64-dis-2.c: Regenerate.
1162 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1163 (OP_SVE_BBB): New variant set.
1164 (OP_SVE_DDDD): New variant set.
1165 (OP_SVE_HHH): New variant set.
1166 (OP_SVE_HHHU): New variant set.
1167 (OP_SVE_SSS): New variant set.
1168 (OP_SVE_SSSU): New variant set.
1169 (OP_SVE_SHH): New variant set.
1170 (OP_SVE_SBBU): New variant set.
1171 (OP_SVE_DSS): New variant set.
1172 (OP_SVE_DHHU): New variant set.
1173 (OP_SVE_VMV_HSD_BHS): New variant set.
1174 (OP_SVE_VVU_HSD_BHS): New variant set.
1175 (OP_SVE_VVVU_SD_BH): New variant set.
1176 (OP_SVE_VVVU_BHSD): New variant set.
1177 (OP_SVE_VVV_QHD_DBS): New variant set.
1178 (OP_SVE_VVV_HSD_BHS): New variant set.
1179 (OP_SVE_VVV_HSD_BHS2): New variant set.
1180 (OP_SVE_VVV_BHS_HSD): New variant set.
1181 (OP_SVE_VV_BHS_HSD): New variant set.
1182 (OP_SVE_VVV_SD): New variant set.
1183 (OP_SVE_VVU_BHS_HSD): New variant set.
1184 (OP_SVE_VZVV_SD): New variant set.
1185 (OP_SVE_VZVV_BH): New variant set.
1186 (OP_SVE_VZV_SD): New variant set.
1187 (aarch64_opcode_table): Add sve2 instructions.
1188
28ed815a
MM		 11892019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1190
1191 * aarch64-asm-2.c: Regenerated.
1192 * aarch64-dis-2.c: Regenerated.
1193 * aarch64-opc-2.c: Regenerated.
1194 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1195 for SVE_SHLIMM_UNPRED_22.
1196 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1197 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1198 operand.
1199
fd1dc4a0
MM		 12002019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1201
1202 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1203 sve_size_tsz_bhs iclass encode.
1204 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1205 sve_size_tsz_bhs iclass decode.
1206
31e36ab3
MM		 12072019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1208
1209 * aarch64-asm-2.c: Regenerated.
1210 * aarch64-dis-2.c: Regenerated.
1211 * aarch64-opc-2.c: Regenerated.
1212 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1213 for SVE_Zm4_11_INDEX.
1214 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1215 (fields): Handle SVE_i2h field.
1216 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1217 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1218
1be5f94f
MM		 12192019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1220
1221 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1222 sve_shift_tsz_bhsd iclass encode.
1223 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1224 sve_shift_tsz_bhsd iclass decode.
1225
3c17238b
MM		 12262019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1227
1228 * aarch64-asm-2.c: Regenerated.
1229 * aarch64-dis-2.c: Regenerated.
1230 * aarch64-opc-2.c: Regenerated.
1231 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1232 (aarch64_encode_variant_using_iclass): Handle
1233 sve_shift_tsz_hsd iclass encode.
1234 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1235 sve_shift_tsz_hsd iclass decode.
1236 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1237 for SVE_SHRIMM_UNPRED_22.
1238 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1239 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1240 operand.
1241
cd50a87a
MM		 12422019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1243
1244 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1245 sve_size_013 iclass encode.
1246 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1247 sve_size_013 iclass decode.
1248
3c705960
MM		 12492019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1250
1251 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1252 sve_size_bh iclass encode.
1253 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1254 sve_size_bh iclass decode.
1255
0a57e14f
MM		 12562019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1257
1258 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1259 sve_size_sd2 iclass encode.
1260 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1261 sve_size_sd2 iclass decode.
1262 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1263 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1264
c469c864
MM		 12652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1266
1267 * aarch64-asm-2.c: Regenerated.
1268 * aarch64-dis-2.c: Regenerated.
1269 * aarch64-opc-2.c: Regenerated.
1270 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1271 for SVE_ADDR_ZX.
1272 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1273 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1274
116adc27
MM		 12752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1276
1277 * aarch64-asm-2.c: Regenerated.
1278 * aarch64-dis-2.c: Regenerated.
1279 * aarch64-opc-2.c: Regenerated.
1280 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1281 for SVE_Zm3_11_INDEX.
1282 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1283 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1284 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1285 fields.
1286 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1287
3bd82c86
MM		 12882019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1289
1290 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1291 sve_size_hsd2 iclass encode.
1292 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1293 sve_size_hsd2 iclass decode.
1294 * aarch64-opc.c (fields): Handle SVE_size field.
1295 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1296
adccc507
MM		 12972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1298
1299 * aarch64-asm-2.c: Regenerated.
1300 * aarch64-dis-2.c: Regenerated.
1301 * aarch64-opc-2.c: Regenerated.
1302 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1303 for SVE_IMM_ROT3.
1304 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1305 (fields): Handle SVE_rot3 field.
1306 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1307 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1308
5cd99750
MM		 13092019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1310
1311 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1312 instructions.
1313
7ce2460a
MM		 13142019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1315
1316 * aarch64-tbl.h
1317 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1318 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1319 aarch64_feature_sve2bitperm): New feature sets.
1320 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1321 for feature set addresses.
1322 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1323 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1324
41cee089
FS		 13252019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1326 Faraz Shahbazker <fshahbazker@wavecomp.com>
1327
1328 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1329 argument and set ASE_EVA_R6 appropriately.
1330 (set_default_mips_dis_options): Pass ISA to above.
1331 (parse_mips_dis_option): Likewise.
1332 * mips-opc.c (EVAR6): New macro.
1333 (mips_builtin_opcodes): Add llwpe, scwpe.
1334
b83b4b13
SD		 13352019-05-01 Sudakshina Das <sudi.das@arm.com>
1336
1337 * aarch64-asm-2.c: Regenerated.
1338 * aarch64-dis-2.c: Regenerated.
1339 * aarch64-opc-2.c: Regenerated.
1340 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1341 AARCH64_OPND_TME_UIMM16.
1342 (aarch64_print_operand): Likewise.
1343 * aarch64-tbl.h (QL_IMM_NIL): New.
1344 (TME): New.
1345 (_TME_INSN): New.
1346 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1347
4a90ce95
JD		 13482019-04-29 John Darrington <john@darrington.wattle.id.au>
1349
1350 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1351
a45328b9
AB		 13522019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1353 Faraz Shahbazker <fshahbazker@wavecomp.com>
1354
1355 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1356
d10be0cb
JD		 13572019-04-24 John Darrington <john@darrington.wattle.id.au>
1358
1359 * s12z-opc.h: Add extern "C" bracketing to help
1360 users who wish to use this interface in c++ code.
1361
a679f24e
JD		 13622019-04-24 John Darrington <john@darrington.wattle.id.au>
1363
1364 * s12z-opc.c (bm_decode): Handle bit map operations with the
1365 "reserved0" mode.
1366
32c36c3c
AV		 13672019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1368
1369 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1370 specifier. Add entries for VLDR and VSTR of system registers.
1371 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1372 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1373 of %J and %K format specifier.
1374
efd6b359
AV		 13752019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1376
1377 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1378 Add new entries for VSCCLRM instruction.
1379 (print_insn_coprocessor): Handle new %C format control code.
1380
6b0dd094
AV		 13812019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1382
1383 * arm-dis.c (enum isa): New enum.
1384 (struct sopcode32): New structure.
1385 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1386 set isa field of all current entries to ANY.
1387 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1388 Only match an entry if its isa field allows the current mode.
1389
4b5a202f
AV		 13902019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1391
1392 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1393 CLRM.
1394 (print_insn_thumb32): Add logic to print %n CLRM register list.
1395
60f993ce
AV		 13962019-04-15 Sudakshina Das <sudi.das@arm.com>
1397
1398 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1399 and %Q patterns.
1400
f6b2b12d
AV		 14012019-04-15 Sudakshina Das <sudi.das@arm.com>
1402
1403 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1404 (print_insn_thumb32): Edit the switch case for %Z.
1405
1889da70
AV		 14062019-04-15 Sudakshina Das <sudi.das@arm.com>
1407
1408 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1409
65d1bc05
AV		 14102019-04-15 Sudakshina Das <sudi.das@arm.com>
1411
1412 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1413
1caf72a5
AV		 14142019-04-15 Sudakshina Das <sudi.das@arm.com>
1415
1416 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1417
f1c7f421
AV		 14182019-04-15 Sudakshina Das <sudi.das@arm.com>
1419
1420 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1421 Arm register with r13 and r15 unpredictable.
1422 (thumb32_opcodes): New instructions for bfx and bflx.
1423
4389b29a
AV		 14242019-04-15 Sudakshina Das <sudi.das@arm.com>
1425
1426 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1427
e5d6e09e
AV		 14282019-04-15 Sudakshina Das <sudi.das@arm.com>
1429
1430 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1431
e12437dc
AV		 14322019-04-15 Sudakshina Das <sudi.das@arm.com>
1433
1434 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1435
031254f2
AV		 14362019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1437
1438 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1439
e5a557ac
JD		 14402019-04-12 John Darrington <john@darrington.wattle.id.au>
1441
1442 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1443 "optr". ("operator" is a reserved word in c++).
1444
bd7ceb8d
SD		 14452019-04-11 Sudakshina Das <sudi.das@arm.com>
1446
1447 * aarch64-opc.c (aarch64_print_operand): Add case for
1448 AARCH64_OPND_Rt_SP.
1449 (verify_constraints): Likewise.
1450 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1451 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1452 to accept Rt|SP as first operand.
1453 (AARCH64_OPERANDS): Add new Rt_SP.
1454 * aarch64-asm-2.c: Regenerated.
1455 * aarch64-dis-2.c: Regenerated.
1456 * aarch64-opc-2.c: Regenerated.
1457
e54010f1
SD		 14582019-04-11 Sudakshina Das <sudi.das@arm.com>
1459
1460 * aarch64-asm-2.c: Regenerated.
1461 * aarch64-dis-2.c: Likewise.
1462 * aarch64-opc-2.c: Likewise.
1463 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1464
7e96e219
RS		 14652019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1466
1467 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1468
6f2791d5
L		 14692019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1470
1471 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1472 * i386-init.h: Regenerated.
1473
e392bad3
AM		 14742019-04-07 Alan Modra <amodra@gmail.com>
1475
1476 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1477 op_separator to control printing of spaces, comma and parens
1478 rather than need_comma, need_paren and spaces vars.
1479
dffaa15c
AM		 14802019-04-07 Alan Modra <amodra@gmail.com>
1481
1482 PR 24421
1483 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1484 (print_insn_neon, print_insn_arm): Likewise.
1485
d6aab7a1
XG		 14862019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1487
1488 * i386-dis-evex.h (evex_table): Updated to support BF16
1489 instructions.
1490 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1491 and EVEX_W_0F3872_P_3.
1492 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1493 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1494 * i386-opc.h (enum): Add CpuAVX512_BF16.
1495 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1496 * i386-opc.tbl: Add AVX512 BF16 instructions.
1497 * i386-init.h: Regenerated.
1498 * i386-tbl.h: Likewise.
1499
66e85460
AM		 15002019-04-05 Alan Modra <amodra@gmail.com>
1501
1502 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1503 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1504 to favour printing of "-" branch hint when using the "y" bit.
1505 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1506
c2b1c275
AM		 15072019-04-05 Alan Modra <amodra@gmail.com>
1508
1509 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1510 opcode until first operand is output.
1511
aae9718e
PB		 15122019-04-04 Peter Bergner <bergner@linux.ibm.com>
1513
1514 PR gas/24349
1515 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1516 (valid_bo_post_v2): Add support for 'at' branch hints.
1517 (insert_bo): Only error on branch on ctr.
1518 (get_bo_hint_mask): New function.
1519 (insert_boe): Add new 'branch_taken' formal argument. Add support
1520 for inserting 'at' branch hints.
1521 (extract_boe): Add new 'branch_taken' formal argument. Add support
1522 for extracting 'at' branch hints.
1523 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1524 (BOE): Delete operand.
1525 (BOM, BOP): New operands.
1526 (RM): Update value.
1527 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1528 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1529 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1530 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1531 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1532 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1533 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1534 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1535 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1536 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1537 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1538 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1539 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1540 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1541 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1542 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1543 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1544 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1545 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1546 bttarl+>: New extended mnemonics.
1547
96a86c01
AM		 15482019-03-28 Alan Modra <amodra@gmail.com>
1549
1550 PR 24390
1551 * ppc-opc.c (BTF): Define.
1552 (powerpc_opcodes): Use for mtfsb*.
1553 * ppc-dis.c (print_insn_powerpc): Print fields with both
1554 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1555
796d6298
TC		 15562019-03-25 Tamar Christina <tamar.christina@arm.com>
1557
1558 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1559 (mapping_symbol_for_insn): Implement new algorithm.
1560 (print_insn): Remove duplicate code.
1561
60df3720
TC		 15622019-03-25 Tamar Christina <tamar.christina@arm.com>
1563
1564 * aarch64-dis.c (print_insn_aarch64):
1565 Implement override.
1566
51457761
TC		 15672019-03-25 Tamar Christina <tamar.christina@arm.com>
1568
1569 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1570 order.
1571
53b2f36b
TC		 15722019-03-25 Tamar Christina <tamar.christina@arm.com>
1573
1574 * aarch64-dis.c (last_stop_offset): New.
1575 (print_insn_aarch64): Use stop_offset.
1576
89199bb5
L		 15772019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1578
1579 PR gas/24359
1580 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1581 CPU_ANY_AVX2_FLAGS.
1582 * i386-init.h: Regenerated.
1583
97ed31ae
L		 15842019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1585
1586 PR gas/24348
1587 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1588 vmovdqu16, vmovdqu32 and vmovdqu64.
1589 * i386-tbl.h: Regenerated.
1590
0919bfe9
AK		 15912019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1592
1593 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1594 from vstrszb, vstrszh, and vstrszf.
1595
15962019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1597
1598 * s390-opc.txt: Add instruction descriptions.
1599
21820ebe
JW		 16002019-02-08 Jim Wilson <jimw@sifive.com>
1601
1602 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1603 <bne>: Likewise.
1604
f7dd2fb2
TC		 16052019-02-07 Tamar Christina <tamar.christina@arm.com>
1606
1607 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1608
6456d318
TC		 16092019-02-07 Tamar Christina <tamar.christina@arm.com>
1610
1611 PR binutils/23212
1612 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1613 * aarch64-opc.c (verify_elem_sd): New.
1614 (fields): Add FLD_sz entr.
1615 * aarch64-tbl.h (_SIMD_INSN): New.
1616 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1617 fmulx scalar and vector by element isns.
1618
4a83b610
NC		 16192019-02-07 Nick Clifton <nickc@redhat.com>
1620
1621 * po/sv.po: Updated Swedish translation.
1622
fc60b8c8
AK		 16232019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1624
1625 * s390-mkopc.c (main): Accept arch13 as cpu string.
1626 * s390-opc.c: Add new instruction formats and instruction opcode
1627 masks.
1628 * s390-opc.txt: Add new arch13 instructions.
1629
e10620d3
TC		 16302019-01-25 Sudakshina Das <sudi.das@arm.com>
1631
1632 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1633 (aarch64_opcode): Change encoding for stg, stzg
1634 st2g and st2zg.
1635 * aarch64-asm-2.c: Regenerated.
1636 * aarch64-dis-2.c: Regenerated.
1637 * aarch64-opc-2.c: Regenerated.
1638
20a4ca55
SD		 16392019-01-25 Sudakshina Das <sudi.das@arm.com>
1640
1641 * aarch64-asm-2.c: Regenerated.
1642 * aarch64-dis-2.c: Likewise.
1643 * aarch64-opc-2.c: Likewise.
1644 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1645
550fd7bf
SD		 16462019-01-25 Sudakshina Das <sudi.das@arm.com>
1647 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1648
1649 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1650 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1651 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1652 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1653 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1654 case for ldstgv_indexed.
1655 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1656 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1657 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1658 * aarch64-asm-2.c: Regenerated.
1659 * aarch64-dis-2.c: Regenerated.
1660 * aarch64-opc-2.c: Regenerated.
1661
d9938630
NC		 16622019-01-23 Nick Clifton <nickc@redhat.com>
1663
1664 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1665
375cd423
NC		 16662019-01-21 Nick Clifton <nickc@redhat.com>
1667
1668 * po/de.po: Updated German translation.
1669 * po/uk.po: Updated Ukranian translation.
1670
57299f48
CX		 16712019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1672 * mips-dis.c (mips_arch_choices): Fix typo in
1673 gs464, gs464e and gs264e descriptors.
1674
f48dfe41
NC		 16752019-01-19 Nick Clifton <nickc@redhat.com>
1676
1677 * configure: Regenerate.
1678 * po/opcodes.pot: Regenerate.
1679
f974f26c
NC		 16802018-06-24 Nick Clifton <nickc@redhat.com>
1681
1682 2.32 branch created.
1683
39f286cd
JD		 16842019-01-09 John Darrington <john@darrington.wattle.id.au>
1685
448b8ca8
JD		 1686 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1687 if it is null.
1688 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1689 zero.
1690
3107326d
AP		 16912019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1692
1693 * configure: Regenerate.
1694
7e9ca91e
AM		 16952019-01-07 Alan Modra <amodra@gmail.com>
1696
1697 * configure: Regenerate.
1698 * po/POTFILES.in: Regenerate.
1699
ef1ad42b
JD		 17002019-01-03 John Darrington <john@darrington.wattle.id.au>
1701
1702 * s12z-opc.c: New file.
1703 * s12z-opc.h: New file.
1704 * s12z-dis.c: Removed all code not directly related to display
1705 of instructions. Used the interface provided by the new files
1706 instead.
1707 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1708 * Makefile.in: Regenerate.
ef1ad42b 1709 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1710 * configure: Regenerate.
ef1ad42b 1711
82704155
AM		 17122019-01-01 Alan Modra <amodra@gmail.com>
1713
1714 Update year range in copyright notice of all files.
1715
d5c04e1b 1716For older changes see ChangeLog-2018
3499769a 1717\f
d5c04e1b 1718Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1719
1720Copying and distribution of this file, with or without modification,
1721are permitted in any medium without royalty provided the copyright
1722notice and this notice are preserved.
1723
1724Local Variables:
1725mode: change-log
1726left-margin: 8
1727fill-column: 74
1728version-control: never
1729End:
GDB Binutils - Deliverables
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