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include/opcode/
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3ccad066
RS		 12013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-formats.h (PCREL): Reorder parameters and update the definition
4 to match new mips_pcrel_operand layout.
5 (JUMP, JALX, BRANCH): Update accordingly.
6 * mips16-opc.c (decode_mips16_operand): Likewise.
7
df34fbcc
RS		 82013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
9
10 * micromips-opc.c (WR_s): Delete.
11
fc76e730
RS		 122013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
13
14 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
15 New macros.
16 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
17 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
18 (mips_builtin_opcodes): Use the new position-based read-write flags
19 instead of field-based ones. Use UDI for "udi..." instructions.
20 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
21 New macros.
22 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
23 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
24 (WR_SP, RD_16): New macros.
25 (RD_SP): Redefine as an INSN2_* flag.
26 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
27 (mips16_opcodes): Use the new position-based read-write flags
28 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
29 pinfo2 field.
30 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
31 New macros.
32 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
33 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
34 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
35 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
36 (micromips_opcodes): Use the new position-based read-write flags
37 instead of field-based ones.
38 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
39 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
40 of field-based flags.
41
26545944
RS		 422013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
43
44 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
45 (WR_SP): Replace with...
46 (MOD_SP): ...this.
47 (mips16_opcodes): Update accordingly.
48 * mips-dis.c (print_insn_mips16): Likewise.
49
a8d92fc6
RS		 502013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
51
52 * mips16-opc.c (mips16_opcodes): Reformat.
53
6a819047
RS		 542013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
55
56 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
57 for operands that are hard-coded to $0.
58 * micromips-opc.c (micromips_opcodes): Likewise.
59
344c74a6
RS		 602013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
61
62 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
63 for the single-operand forms of JALR and JALR.HB.
64 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
65 and JALRS.HB.
66
41989114
RS		 672013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
68
69 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
70 instructions. Fix them to use WR_MACC instead of WR_CC and
71 add missing RD_MACCs.
72
6d075bce
RS		 732013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
74
75 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
76
4f6ffcd3
PB		 772013-07-29 Peter Bergner <bergner@vnet.ibm.com>
78
79 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
80
43234a1e
L		 812013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
82 Alexander Ivchenko <alexander.ivchenko@intel.com>
83 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
84 Sergey Lega <sergey.s.lega@intel.com>
85 Anna Tikhonova <anna.tikhonova@intel.com>
86 Ilya Tocar <ilya.tocar@intel.com>
87 Andrey Turetskiy <andrey.turetskiy@intel.com>
88 Ilya Verbin <ilya.verbin@intel.com>
89 Kirill Yukhin <kirill.yukhin@intel.com>
90 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
91
92 * i386-dis-evex.h: New.
93 * i386-dis.c (OP_Rounding): New.
94 (VPCMP_Fixup): New.
95 (OP_Mask): New.
96 (Rdq): New.
97 (XMxmmq): New.
98 (EXdScalarS): New.
99 (EXymm): New.
100 (EXEvexHalfBcstXmmq): New.
101 (EXxmm_mdq): New.
102 (EXEvexXGscat): New.
103 (EXEvexXNoBcst): New.
104 (VPCMP): New.
105 (EXxEVexR): New.
106 (EXxEVexS): New.
107 (XMask): New.
108 (MaskG): New.
109 (MaskE): New.
110 (MaskR): New.
111 (MaskVex): New.
112 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
113 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
114 evex_rounding_mode, evex_sae_mode, mask_mode.
115 (USE_EVEX_TABLE): New.
116 (EVEX_TABLE): New.
117 (EVEX enum): New.
118 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
119 REG_EVEX_0F38C7.
120 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
121 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
122 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
123 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
124 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
125 MOD_EVEX_0F38C7_REG_6.
126 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
127 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
128 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
129 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
130 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
131 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
132 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
133 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
134 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
135 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
136 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
137 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
138 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
139 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
140 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
141 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
142 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
143 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
144 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
145 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
146 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
147 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
148 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
149 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
150 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
151 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
152 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
153 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
154 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
155 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
156 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
157 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
158 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
159 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
160 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
161 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
162 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
163 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
164 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
165 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
166 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
167 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
168 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
169 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
170 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
171 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
172 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
173 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
174 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
175 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
176 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
177 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
178 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
179 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
180 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
181 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
182 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
183 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
184 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
185 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
186 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
187 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
188 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
189 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
190 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
191 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
192 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
193 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
194 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
195 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
196 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
197 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
198 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
199 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
200 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
201 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
202 PREFIX_EVEX_0F3A55.
203 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
204 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
205 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
206 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
207 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
208 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
209 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
210 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
211 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
212 VEX_W_0F3A32_P_2_LEN_0.
213 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
214 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
215 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
216 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
217 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
218 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
219 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
220 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
221 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
222 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
223 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
224 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
225 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
226 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
227 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
228 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
229 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
230 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
231 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
232 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
233 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
234 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
235 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
236 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
237 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
238 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
239 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
240 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
241 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
242 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
243 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
244 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
245 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
246 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
247 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
248 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
249 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
250 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
251 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
252 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
253 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
254 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
255 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
256 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
257 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
258 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
259 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
260 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
261 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
262 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
263 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
264 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
265 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
266 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
267 (struct vex): Add fields evex, r, v, mask_register_specifier,
268 zeroing, ll, b.
269 (intel_names_xmm): Add upper 16 registers.
270 (att_names_xmm): Ditto.
271 (intel_names_ymm): Ditto.
272 (att_names_ymm): Ditto.
273 (names_zmm): New.
274 (intel_names_zmm): Ditto.
275 (att_names_zmm): Ditto.
276 (names_mask): Ditto.
277 (intel_names_mask): Ditto.
278 (att_names_mask): Ditto.
279 (names_rounding): Ditto.
280 (names_broadcast): Ditto.
281 (x86_64_table): Add escape to evex-table.
282 (reg_table): Include reg_table evex-entries from
283 i386-dis-evex.h. Fix prefetchwt1 instruction.
284 (prefix_table): Add entries for new instructions.
285 (vex_table): Ditto.
286 (vex_len_table): Ditto.
287 (vex_w_table): Ditto.
288 (mod_table): Ditto.
289 (get_valid_dis386): Properly handle new instructions.
290 (print_insn): Handle zmm and mask registers, print mask operand.
291 (intel_operand_size): Support EVEX, new modes and sizes.
292 (OP_E_register): Handle new modes.
293 (OP_E_memory): Ditto.
294 (OP_G): Ditto.
295 (OP_XMM): Ditto.
296 (OP_EX): Ditto.
297 (OP_VEX): Ditto.
298 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
299 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
300 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
301 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
302 CpuAVX512PF and CpuVREX.
303 (operand_type_init): Add OPERAND_TYPE_REGZMM,
304 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
305 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
306 StaticRounding, SAE, Disp8MemShift, NoDefMask.
307 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
308 * i386-init.h: Regenerate.
309 * i386-opc.h (CpuAVX512F): New.
310 (CpuAVX512CD): New.
311 (CpuAVX512ER): New.
312 (CpuAVX512PF): New.
313 (CpuVREX): New.
314 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
315 cpuavx512pf and cpuvrex fields.
316 (VecSIB): Add VecSIB512.
317 (EVex): New.
318 (Masking): New.
319 (VecESize): New.
320 (Broadcast): New.
321 (StaticRounding): New.
322 (SAE): New.
323 (Disp8MemShift): New.
324 (NoDefMask): New.
325 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
326 staticrounding, sae, disp8memshift and nodefmask.
327 (RegZMM): New.
328 (Zmmword): Ditto.
329 (Vec_Disp8): Ditto.
330 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
331 fields.
332 (RegVRex): New.
333 * i386-opc.tbl: Add AVX512 instructions.
334 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
335 registers, mask registers.
336 * i386-tbl.h: Regenerate.
337
1d2db237
RS		 3382013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
339
340 PR gas/15220
341 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
342 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
343
a0046408
L		 3442013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
345
346 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
347 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
348 PREFIX_0F3ACC.
349 (prefix_table): Updated.
350 (three_byte_table): Likewise.
351 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
352 (cpu_flags): Add CpuSHA.
353 (i386_cpu_flags): Add cpusha.
354 * i386-init.h: Regenerate.
355 * i386-opc.h (CpuSHA): New.
356 (CpuUnused): Restored.
357 (i386_cpu_flags): Add cpusha.
358 * i386-opc.tbl: Add SHA instructions.
359 * i386-tbl.h: Regenerate.
360
7e8b059b
L		 3612013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
362 Kirill Yukhin <kirill.yukhin@intel.com>
363 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
364
365 * i386-dis.c (BND_Fixup): New.
366 (Ebnd): New.
367 (Ev_bnd): New.
368 (Gbnd): New.
369 (BND): New.
370 (v_bnd_mode): New.
371 (bnd_mode): New.
c623f86c
L		 372 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
373 MOD_0F1B_PREFIX_1.
374 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 375 (dis tables): Replace XX with BND for near branch and call
376 instructions.
377 (prefix_table): Add new entries.
378 (mod_table): Likewise.
379 (names_bnd): New.
380 (intel_names_bnd): New.
381 (att_names_bnd): New.
382 (BND_PREFIX): New.
383 (prefix_name): Handle BND_PREFIX.
384 (print_insn): Initialize names_bnd.
385 (intel_operand_size): Handle new modes.
386 (OP_E_register): Likewise.
387 (OP_E_memory): Likewise.
388 (OP_G): Likewise.
389 * i386-gen.c (cpu_flag_init): Add CpuMPX.
390 (cpu_flags): Add CpuMPX.
391 (operand_type_init): Add RegBND.
392 (opcode_modifiers): Add BNDPrefixOk.
393 (operand_types): Add RegBND.
394 * i386-init.h: Regenerate.
395 * i386-opc.h (CpuMPX): New.
396 (CpuUnused): Comment out.
397 (i386_cpu_flags): Add cpumpx.
398 (BNDPrefixOk): New.
399 (i386_opcode_modifier): Add bndprefixok.
400 (RegBND): New.
401 (i386_operand_type): Add regbnd.
402 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
403 Add MPX instructions and bnd prefix.
404 * i386-reg.tbl: Add bnd0-bnd3 registers.
405 * i386-tbl.h: Regenerate.
406
b56e23fb
RS		 4072013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
408
409 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
410 ATTRIBUTE_UNUSED.
411
e7ae278d
RS		 4122013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
413
414 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
415 special rules.
416 * Makefile.in: Regenerate.
417 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
418 all fields. Reformat.
419
c3c07478
RS		 4202013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
421
422 * mips16-opc.c: Include mips-formats.h.
423 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
424 static arrays.
425 (decode_mips16_operand): New function.
426 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
427 (print_insn_arg): Handle OP_ENTRY_EXIT list.
428 Abort for OP_SAVE_RESTORE_LIST.
429 (print_mips16_insn_arg): Change interface. Use mips_operand
430 structures. Delete GET_OP_S. Move GET_OP definition to...
431 (print_insn_mips16): ...here. Call init_print_arg_state.
432 Update the call to print_mips16_insn_arg.
433
ab902481
RS		 4342013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
435
436 * mips-formats.h: New file.
437 * mips-opc.c: Include mips-formats.h.
438 (reg_0_map): New static array.
439 (decode_mips_operand): New function.
440 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
441 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
442 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
443 (int_c_map): New static arrays.
444 (decode_micromips_operand): New function.
445 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
446 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
447 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
448 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
449 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
450 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
451 (micromips_imm_b_map, micromips_imm_c_map): Delete.
452 (print_reg): New function.
453 (mips_print_arg_state): New structure.
454 (init_print_arg_state, print_insn_arg): New functions.
455 (print_insn_args): Change interface and use mips_operand structures.
456 Delete GET_OP_S. Move GET_OP definition to...
457 (print_insn_mips): ...here. Update the call to print_insn_args.
458 (print_insn_micromips): Use print_insn_args.
459
cc537e56
RS		 4602013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
461
462 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
463 in macros.
464
7a5f87ce
RS		 4652013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
466
467 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
468 ADDA.S, MULA.S and SUBA.S.
469
41741fa4
L		 4702013-07-08 H.J. Lu <hongjiu.lu@intel.com>
471
472 PR gas/13572
473 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
474 * i386-tbl.h: Regenerated.
475
f2ae14a1
RS		 4762013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
477
478 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
479 and SD A(B) macros up.
480 * micromips-opc.c (micromips_opcodes): Likewise.
481
04c9d415
RS		 4822013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
483
484 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
485 instructions.
486
5c324c16
RS		 4872013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
488
489 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
490 MDMX-like instructions.
491 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
492 printing "Q" operands for INSN_5400 instructions.
493
23e69e47
RS		 4942013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
495
496 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
497 "+S" for "cins".
498 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
499 Combine cases.
500
27c5c572
RS		 5012013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
502
503 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
504 "jalx".
505 * mips16-opc.c (mips16_opcodes): Likewise.
506 * micromips-opc.c (micromips_opcodes): Likewise.
507 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
508 (print_insn_mips16): Handle "+i".
509 (print_insn_micromips): Likewise. Conditionally preserve the
510 ISA bit for "a" but not for "+i".
511
e76ff5ab
RS		 5122013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
513
514 * micromips-opc.c (WR_mhi): Rename to..
515 (WR_mh): ...this.
516 (micromips_opcodes): Update "movep" entry accordingly. Replace
517 "mh,mi" with "mh".
518 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
519 (micromips_to_32_reg_h_map1): ...this.
520 (micromips_to_32_reg_i_map): Rename to...
521 (micromips_to_32_reg_h_map2): ...this.
522 (print_micromips_insn): Remove "mi" case. Print both registers
523 in the pair for "mh".
524
fa7616a4
RS		 5252013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
526
527 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
528 * micromips-opc.c (micromips_opcodes): Likewise.
529 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
530 and "+T" handling. Check for a "0" suffix when deciding whether to
531 use coprocessor 0 names. In that case, also check for ",H" selectors.
532
fb798c50
AK		 5332013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
534
535 * s390-opc.c (J12_12, J24_24): New macros.
536 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
537 (MASK_MII_UPI): Rename to MASK_MII_UPP.
538 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
539
58ae08f2
AM		 5402013-07-04 Alan Modra <amodra@gmail.com>
541
542 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
543
b5e04c2b
NC		 5442013-06-26 Nick Clifton <nickc@redhat.com>
545
546 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
547 field when checking for type 2 nop.
548 * rx-decode.c: Regenerate.
549
833794fc
MR		 5502013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
551
552 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
553 and "movep" macros.
554
1bbce132
MR		 5552013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
556
557 * mips-dis.c (is_mips16_plt_tail): New function.
558 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
559 word.
560 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
561
34c911a4
NC		 5622013-06-21 DJ Delorie <dj@redhat.com>
563
564 * msp430-decode.opc: New.
565 * msp430-decode.c: New/generated.
566 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
567 (MAINTAINER_CLEANFILES): Likewise.
568 Add rule to build msp430-decode.c frommsp430decode.opc
569 using the opc2c program.
570 * Makefile.in: Regenerate.
571 * configure.in: Add msp430-decode.lo to msp430 architecture files.
572 * configure: Regenerate.
573
b9eead84
YZ		 5742013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
575
576 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
577 (SYMTAB_AVAILABLE): Removed.
578 (#include "elf/aarch64.h): Ditto.
579
7f3c4072
CM		 5802013-06-17 Catherine Moore <clm@codesourcery.com>
581 Maciej W. Rozycki <macro@codesourcery.com>
582 Chao-Ying Fu <fu@mips.com>
583
584 * micromips-opc.c (EVA): Define.
585 (TLBINV): Define.
586 (micromips_opcodes): Add EVA opcodes.
587 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
588 (print_insn_args): Handle EVA offsets.
589 (print_insn_micromips): Likewise.
590 * mips-opc.c (EVA): Define.
591 (TLBINV): Define.
592 (mips_builtin_opcodes): Add EVA opcodes.
593
de40ceb6
AM		 5942013-06-17 Alan Modra <amodra@gmail.com>
595
596 * Makefile.am (mips-opc.lo): Add rules to create automatic
597 dependency files. Pass archdefs.
598 (micromips-opc.lo, mips16-opc.lo): Likewise.
599 * Makefile.in: Regenerate.
600
3531d549
DD		 6012013-06-14 DJ Delorie <dj@redhat.com>
602
603 * rx-decode.opc (rx_decode_opcode): Bit operations on
604 registers are 32-bit operations, not 8-bit operations.
605 * rx-decode.c: Regenerate.
606
ba92f7fb
CF		 6072013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
608
609 * micromips-opc.c (IVIRT): New define.
610 (IVIRT64): New define.
611 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
612 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
613
614 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
615 dmtgc0 to print cp0 names.
616
9daf7bab
SL		 6172013-06-09 Sandra Loosemore <sandra@codesourcery.com>
618
619 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
620 argument.
621
d301a56b
RS		 6222013-06-08 Catherine Moore <clm@codesourcery.com>
623 Richard Sandiford <rdsandiford@googlemail.com>
624
625 * micromips-opc.c (D32, D33, MC): Update definitions.
626 (micromips_opcodes): Initialize ase field.
627 * mips-dis.c (mips_arch_choice): Add ase field.
628 (mips_arch_choices): Initialize ase field.
629 (set_default_mips_dis_options): Declare and setup mips_ase.
630 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
631 MT32, MC): Update definitions.
632 (mips_builtin_opcodes): Initialize ase field.
633
a3dcb6c5
RS		 6342013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
635
636 * s390-opc.txt (flogr): Require a register pair destination.
637
6cf1d90c
AK		 6382013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
639
640 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
641 instruction format.
642
c77c0862
RS		 6432013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
644
645 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
646
c0637f3a
PB		 6472013-05-20 Peter Bergner <bergner@vnet.ibm.com>
648
649 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
650 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
651 XLS_MASK, PPCVSX2): New defines.
652 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
653 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
654 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
655 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
656 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
657 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
658 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
659 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
660 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
661 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
662 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
663 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
664 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
665 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
666 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
667 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
668 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
669 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
670 <lxvx, stxvx>: New extended mnemonics.
671
4934fdaf
AM		 6722013-05-17 Alan Modra <amodra@gmail.com>
673
674 * ia64-raw.tbl: Replace non-ASCII char.
675 * ia64-waw.tbl: Likewise.
676 * ia64-asmtab.c: Regenerate.
677
6091d651
SE		 6782013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
679
680 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
681 * i386-init.h: Regenerated.
682
d2865ed3
YZ		 6832013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
684
685 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
686 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
687 check from [0, 255] to [-128, 255].
688
b015e599
AP		 6892013-05-09 Andrew Pinski <apinski@cavium.com>
690
691 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
692 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
693 (parse_mips_dis_option): Handle the virt option.
694 (print_insn_args): Handle "+J".
695 (print_mips_disassembler_options): Print out message about virt64.
696 * mips-opc.c (IVIRT): New define.
697 (IVIRT64): New define.
698 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
699 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
700 Move rfe to the bottom as it conflicts with tlbgp.
701
9f0682fe
AM		 7022013-05-09 Alan Modra <amodra@gmail.com>
703
704 * ppc-opc.c (extract_vlesi): Properly sign extend.
705 (extract_vlensi): Likewise. Comment reason for setting invalid.
706
13761a11
NC		 7072013-05-02 Nick Clifton <nickc@redhat.com>
708
709 * msp430-dis.c: Add support for MSP430X instructions.
710
e3031850
SL		 7112013-04-24 Sandra Loosemore <sandra@codesourcery.com>
712
713 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
714 to "eccinj".
715
17310e56
NC		 7162013-04-17 Wei-chen Wang <cole945@gmail.com>
717
718 PR binutils/15369
719 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
720 of CGEN_CPU_ENDIAN.
721 (hash_insns_list): Likewise.
722
731df338
JK		 7232013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
724
725 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
726 warning workaround.
727
5f77db52
JB		 7282013-04-08 Jan Beulich <jbeulich@suse.com>
729
730 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
731 * i386-tbl.h: Re-generate.
732
0afd1215
DM		 7332013-04-06 David S. Miller <davem@davemloft.net>
734
735 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
736 of an opcode, prefer the one with F_PREFERRED set.
737 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
738 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
739 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
740 mark existing mnenomics as aliases. Add "cc" suffix to edge
741 instructions generating condition codes, mark existing mnenomics
742 as aliases. Add "fp" prefix to VIS compare instructions, mark
743 existing mnenomics as aliases.
744
41702d50
NC		 7452013-04-03 Nick Clifton <nickc@redhat.com>
746
747 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
748 destination address by subtracting the operand from the current
749 address.
750 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
751 a positive value in the insn.
752 (extract_u16_loop): Do not negate the returned value.
753 (D16_LOOP): Add V850_INVERSE_PCREL flag.
754
755 (ceilf.sw): Remove duplicate entry.
756 (cvtf.hs): New entry.
757 (cvtf.sh): Likewise.
758 (fmaf.s): Likewise.
759 (fmsf.s): Likewise.
760 (fnmaf.s): Likewise.
761 (fnmsf.s): Likewise.
762 (maddf.s): Restrict to E3V5 architectures.
763 (msubf.s): Likewise.
764 (nmaddf.s): Likewise.
765 (nmsubf.s): Likewise.
766
55cf16e1
L		 7672013-03-27 H.J. Lu <hongjiu.lu@intel.com>
768
769 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
770 check address mode.
771 (print_insn): Pass sizeflag to get_sib.
772
51dcdd4d
NC		 7732013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
774
775 PR binutils/15068
776 * tic6x-dis.c: Add support for displaying 16-bit insns.
777
795b8e6b
NC		 7782013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
779
780 PR gas/15095
781 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
782 individual msb and lsb halves in src1 & src2 fields. Discard the
783 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
784 follow what Ti SDK does in that case as any value in the src1
785 field yields the same output with SDK disassembler.
786
314d60dd
ME		 7872013-03-12 Michael Eager <eager@eagercon.com>
788
795b8e6b 789 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 790
dad60f8e
SL		 7912013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
792
793 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
794
f5cb796a
SL		 7952013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
796
797 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
798
21fde85c
SL		 7992013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
800
801 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
802
dd5181d5
KT		 8032013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
804
805 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
806 (thumb32_opcodes): Likewise.
807 (print_insn_thumb32): Handle 'S' control char.
808
87a8d6cb
NC		 8092013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
810
811 * lm32-desc.c: Regenerate.
812
99dce992
L		 8132013-03-01 H.J. Lu <hongjiu.lu@intel.com>
814
815 * i386-reg.tbl (riz): Add RegRex64.
816 * i386-tbl.h: Regenerated.
817
e60bb1dd
YZ		 8182013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
819
820 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
821 (aarch64_feature_crc): New static.
822 (CRC): New macro.
823 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
824 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
825 * aarch64-asm-2.c: Re-generate.
826 * aarch64-dis-2.c: Ditto.
827 * aarch64-opc-2.c: Ditto.
828
c7570fcd
AM		 8292013-02-27 Alan Modra <amodra@gmail.com>
830
831 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
832 * rl78-decode.c: Regenerate.
833
151fa98f
NC		 8342013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
835
836 * rl78-decode.opc: Fix encoding of DIVWU insn.
837 * rl78-decode.c: Regenerate.
838
5c111e37
L		 8392013-02-19 H.J. Lu <hongjiu.lu@intel.com>
840
841 PR gas/15159
842 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
843
844 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
845 (cpu_flags): Add CpuSMAP.
846
847 * i386-opc.h (CpuSMAP): New.
848 (i386_cpu_flags): Add cpusmap.
849
850 * i386-opc.tbl: Add clac and stac.
851
852 * i386-init.h: Regenerated.
853 * i386-tbl.h: Likewise.
854
9d1df426
NC		 8552013-02-15 Markos Chandras <markos.chandras@imgtec.com>
856
857 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
858 which also makes the disassembler output be in little
859 endian like it should be.
860
a1ccaec9
YZ		 8612013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
862
863 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
864 fields to NULL.
865 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
866
ef068ef4 8672013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 868
869 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
870 section disassembled.
871
6fe6ded9
RE		 8722013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
873
874 * arm-dis.c: Update strht pattern.
875
0aa27725
RS		 8762013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
877
878 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
879 single-float. Disable ll, lld, sc and scd for EE. Disable the
880 trunc.w.s macro for EE.
881
36591ba1
SL		 8822013-02-06 Sandra Loosemore <sandra@codesourcery.com>
883 Andrew Jenner <andrew@codesourcery.com>
884
885 Based on patches from Altera Corporation.
886
887 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
888 nios2-opc.c.
889 * Makefile.in: Regenerated.
890 * configure.in: Add case for bfd_nios2_arch.
891 * configure: Regenerated.
892 * disassemble.c (ARCH_nios2): Define.
893 (disassembler): Add case for bfd_arch_nios2.
894 * nios2-dis.c: New file.
895 * nios2-opc.c: New file.
896
545093a4
AM		 8972013-02-04 Alan Modra <amodra@gmail.com>
898
899 * po/POTFILES.in: Regenerate.
900 * rl78-decode.c: Regenerate.
901 * rx-decode.c: Regenerate.
902
e30181a5
YZ		 9032013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
904
905 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
906 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
907 * aarch64-asm.c (convert_xtl_to_shll): New function.
908 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
909 calling convert_xtl_to_shll.
910 * aarch64-dis.c (convert_shll_to_xtl): New function.
911 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
912 calling convert_shll_to_xtl.
913 * aarch64-gen.c: Update copyright year.
914 * aarch64-asm-2.c: Re-generate.
915 * aarch64-dis-2.c: Re-generate.
916 * aarch64-opc-2.c: Re-generate.
917
78c8d46c
NC		 9182013-01-24 Nick Clifton <nickc@redhat.com>
919
920 * v850-dis.c: Add support for e3v5 architecture.
921 * v850-opc.c: Likewise.
922
f5555712
YZ		 9232013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
924
925 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
926 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
927 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 928 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 929 alignment check; change to call set_sft_amount_out_of_range_error
930 instead of set_imm_out_of_range_error.
931 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
932 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
933 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
934 SIMD_IMM_SFT.
935
2f81ff92
L		 9362013-01-16 H.J. Lu <hongjiu.lu@intel.com>
937
938 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
939
940 * i386-init.h: Regenerated.
941 * i386-tbl.h: Likewise.
942
dd42f060
NC		 9432013-01-15 Nick Clifton <nickc@redhat.com>
944
945 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
946 values.
947 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
948
a4533ed8
NC		 9492013-01-14 Will Newton <will.newton@imgtec.com>
950
951 * metag-dis.c (REG_WIDTH): Increase to 64.
952
5817ffd1
PB		 9532013-01-10 Peter Bergner <bergner@vnet.ibm.com>
954
955 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
956 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
957 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
958 (SH6): Update.
959 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
960 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
961 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
962 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
963
a3c62988
NC		 9642013-01-10 Will Newton <will.newton@imgtec.com>
965
966 * Makefile.am: Add Meta.
967 * configure.in: Add Meta.
968 * disassemble.c: Add Meta support.
969 * metag-dis.c: New file.
970 * Makefile.in: Regenerate.
971 * configure: Regenerate.
972
73335eae
NC		 9732013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
974
975 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
976 (match_opcode): Rename to cr16_match_opcode.
977
e407c74b
NC		 9782013-01-04 Juergen Urban <JuergenUrban@gmx.de>
979
980 * mips-dis.c: Add names for CP0 registers of r5900.
981 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
982 instructions sq and lq.
983 Add support for MIPS r5900 CPU.
984 Add support for 128 bit MMI (Multimedia Instructions).
985 Add support for EE instructions (Emotion Engine).
986 Disable unsupported floating point instructions (64 bit and
987 undefined compare operations).
988 Enable instructions of MIPS ISA IV which are supported by r5900.
989 Disable 64 bit co processor instructions.
990 Disable 64 bit multiplication and division instructions.
991 Disable instructions for co-processor 2 and 3, because these are
992 not supported (preparation for later VU0 support (Vector Unit)).
993 Disable cvt.w.s because this behaves like trunc.w.s and the
994 correct execution can't be ensured on r5900.
995 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
996 will confuse less developers and compilers.
997
a32c3ff8
NC		 9982013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
999
fb098a1e
YZ		 1000 * aarch64-opc.c (aarch64_print_operand): Change to print
1001 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1002 in comment.
1003 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1004 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1005 OP_MOV_IMM_WIDE.
1006
10072013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1008
1009 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1010 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1011
62658407
L		 10122013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1013
1014 * i386-gen.c (process_copyright): Update copyright year to 2013.
1015
bab4becb 10162013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1017
bab4becb
NC		 1018 * cr16-dis.c (match_opcode,make_instruction): Remove static
1019 declaration.
1020 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1021 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1022
bab4becb 1023For older changes see ChangeLog-2012
252b5132 1024\f
bab4becb 1025Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1026
1027Copying and distribution of this file, with or without modification,
1028are permitted in any medium without royalty provided the copyright
1029notice and this notice are preserved.
1030
252b5132 1031Local Variables:
2f6d2f85
NC		 1032mode: change-log
1033left-margin: 8
1034fill-column: 74
252b5132
RH		 1035version-control: never
1036End:
GDB Binutils - Deliverables
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