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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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3d456fa1
JB		 12005-05-25 Jan Beulich <jbeulich@novell.com>
2
3 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
4 hex (but retain it being displayed as signed). Remove redundant
5 checks. Add handling of displacements for 16-bit addressing in Intel
6 mode.
7
2888cb7a
JB		 82005-05-25 Jan Beulich <jbeulich@novell.com>
9
10 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
11 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
12 masking of 'rm' in 16-bit memory address handling.
13
1ed8e1e4
AM		 142005-05-19 Anton Blanchard <anton@samba.org>
15
16 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
17 (print_ppc_disassembler_options): Document it.
18 * ppc-opc.c (SVC_LEV): Define.
19 (LEV): Allow optional operand.
20 (POWER5): Define.
21 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
22 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
23
49cc2e69
KC		 242005-05-19 Kelley Cook <kcook@gcc.gnu.org>
25
26 * Makefile.in: Regenerate.
27
c19d1205
ZW		 282005-05-17 Zack Weinberg <zack@codesourcery.com>
29
30 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
31 instructions. Adjust disassembly of some opcodes to match
32 unified syntax.
33 (thumb32_opcodes): New table.
34 (print_insn_thumb): Rename print_insn_thumb16; don't handle
35 two-halfword branches here.
36 (print_insn_thumb32): New function.
37 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
38 and print_insn_thumb32. Be consistent about order of
39 halfwords when printing 32-bit instructions.
40
003519a7
L		 412005-05-07 H.J. Lu <hongjiu.lu@intel.com>
42
43 PR 843
44 * i386-dis.c (branch_v_mode): New.
45 (indirEv): Use branch_v_mode instead of v_mode.
46 (OP_E): Handle branch_v_mode.
47
920a34a7
L		 482005-05-07 H.J. Lu <hongjiu.lu@intel.com>
49
50 * d10v-dis.c (dis_2_short): Support 64bit host.
51
5de773c1
NC		 522005-05-07 Nick Clifton <nickc@redhat.com>
53
54 * po/nl.po: Updated translation.
55
f4321104
NC		 562005-05-07 Nick Clifton <nickc@redhat.com>
57
58 * Update the address and phone number of the FSF organization in
59 the GPL notices in the following files:
60 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
61 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
62 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
63 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
64 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
65 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
66 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
67 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
68 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
69 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
70 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
71 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
72 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
73 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
74 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
75 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
76 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
77 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
78 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
79 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
80 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
81 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
82 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
83 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
84 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
85 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
86 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
87 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
88 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
89 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
90 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
91 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
92 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
93
10b076a2
JW		 942005-05-05 James E Wilson <wilson@specifixinc.com>
95
96 * ia64-opc.c: Include sysdep.h before libiberty.h.
97
022716b6
NC		 982005-05-05 Nick Clifton <nickc@redhat.com>
99
100 * configure.in (ALL_LINGUAS): Add vi.
101 * configure: Regenerate.
102 * po/vi.po: New.
103
db5152b4
JG		 1042005-04-26 Jerome Guitton <guitton@gnat.com>
105
106 * configure.in: Fix the check for basename declaration.
107 * configure: Regenerate.
108
eed0d89a
AM		 1092005-04-19 Alan Modra <amodra@bigpond.net.au>
110
111 * ppc-opc.c (RTO): Define.
112 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
113 entries to suit PPC440.
114
791fe849
MK		 1152005-04-18 Mark Kettenis <kettenis@gnu.org>
116
117 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
118 Add xcrypt-ctr.
119
ffe58f7c
NC		 1202005-04-14 Nick Clifton <nickc@redhat.com>
121
122 * po/fi.po: New translation: Finnish.
123 * configure.in (ALL_LINGUAS): Add fi.
124 * configure: Regenerate.
125
9e9b66a9
AM		 1262005-04-14 Alan Modra <amodra@bigpond.net.au>
127
128 * Makefile.am (NO_WERROR): Define.
129 * configure.in: Invoke AM_BINUTILS_WARNINGS.
130 * Makefile.in: Regenerate.
131 * aclocal.m4: Regenerate.
132 * configure: Regenerate.
133
9494d739
NC		 1342005-04-04 Nick Clifton <nickc@redhat.com>
135
136 * fr30-asm.c: Regenerate.
137 * frv-asm.c: Regenerate.
138 * iq2000-asm.c: Regenerate.
139 * m32r-asm.c: Regenerate.
140 * openrisc-asm.c: Regenerate.
141
6128c599
JB		 1422005-04-01 Jan Beulich <jbeulich@novell.com>
143
144 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
145 visible operands in Intel mode. The first operand of monitor is
146 %rax in 64-bit mode.
147
373ff435
JB		 1482005-04-01 Jan Beulich <jbeulich@novell.com>
149
150 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
151 easier future additions.
152
4bd60896
JG		 1532005-03-31 Jerome Guitton <guitton@gnat.com>
154
155 * configure.in: Check for basename.
156 * configure: Regenerate.
157 * config.in: Ditto.
158
4cc91dba
L		 1592005-03-29 H.J. Lu <hongjiu.lu@intel.com>
160
161 * i386-dis.c (SEG_Fixup): New.
162 (Sv): New.
163 (dis386): Use "Sv" for 0x8c and 0x8e.
164
ec72cfe5
NC		 1652005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
166 Nick Clifton <nickc@redhat.com>
c19d1205 167
ec72cfe5
NC		 168 * vax-dis.c: (entry_addr): New varible: An array of user supplied
169 function entry mask addresses.
170 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 171 elements in entry_addr.
ec72cfe5
NC		 172 (entry_addr_total_slots): New variable: The total number of
173 elements in entry_addr.
174 (parse_disassembler_options): New function. Fills in the entry_addr
175 array.
176 (free_entry_array): New function. Release the memory used by the
177 entry addr array. Suppressed because there is no way to call it.
178 (is_function_entry): Check if a given address is a function's
179 start address by looking at supplied entry mask addresses and
180 symbol information, if available.
181 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
182
85064c79
L		 1832005-03-23 H.J. Lu <hongjiu.lu@intel.com>
184
185 * cris-dis.c (print_with_operands): Use ~31L for long instead
186 of ~31.
187
de7141c7
L		 1882005-03-20 H.J. Lu <hongjiu.lu@intel.com>
189
190 * mmix-opc.c (O): Revert the last change.
191 (Z): Likewise.
192
e493ab45
L		 1932005-03-19 H.J. Lu <hongjiu.lu@intel.com>
194
195 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
196 (Z): Likewise.
197
d8d7c459
HPN		 1982005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
199
200 * mmix-opc.c (O, Z): Force expression as unsigned long.
201
ebdb0383
NC		 2022005-03-18 Nick Clifton <nickc@redhat.com>
203
204 * ip2k-asm.c: Regenerate.
205 * op/opcodes.pot: Regenerate.
206
1ad12f97
NC		 2072005-03-16 Nick Clifton <nickc@redhat.com>
208 Ben Elliston <bje@au.ibm.com>
209
569acd2c 210 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 211 compiler command line. Enabled by default. Disable via
569acd2c 212 --disable-werror.
1ad12f97
NC		 213 * configure: Regenerate.
214
4eb30afc
AM		 2152005-03-16 Alan Modra <amodra@bigpond.net.au>
216
217 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
218 BOOKE.
219
ea8409f7
AM		 2202005-03-15 Alan Modra <amodra@bigpond.net.au>
221
729ae8d2
AM		 222 * po/es.po: Commit new Spanish translation.
223
ea8409f7
AM		 224 * po/fr.po: Commit new French translation.
225
4f495e61
NC		 2262005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
227
228 * vax-dis.c: Fix spelling error
229 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
230 of just "Entry mask: < r1 ... >"
231
0a003adc
ZW		 2322005-03-12 Zack Weinberg <zack@codesourcery.com>
233
234 * arm-dis.c (arm_opcodes): Document %E and %V.
235 Add entries for v6T2 ARM instructions:
236 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
237 (print_insn_arm): Add support for %E and %V.
885fc257 238 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 239
da99ee72
AM		 2402005-03-10 Jeff Baker <jbaker@qnx.com>
241 Alan Modra <amodra@bigpond.net.au>
242
243 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
244 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
245 (SPRG_MASK): Delete.
246 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 247 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 248 mfsprg4..7 after msprg and consolidate.
249
220abb21
AM		 2502005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
251
252 * vax-dis.c (entry_mask_bit): New array.
253 (print_insn_vax): Decode function entry mask.
254
0e06657a
AH		 2552005-03-07 Aldy Hernandez <aldyh@redhat.com>
256
257 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
258
06647dfd
AM		 2592005-03-05 Alan Modra <amodra@bigpond.net.au>
260
261 * po/opcodes.pot: Regenerate.
262
82b829a7
RR		 2632005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
264
220abb21 265 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 266 (dsmOneArcInst): Use the enum values for the decoding class.
267 Remove redundant case in the switch for decodingClass value 11.
82b829a7 268
c4a530c5
JB		 2692005-03-02 Jan Beulich <jbeulich@novell.com>
270
271 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
272 accesses.
273 (OP_C): Consider lock prefix in non-64-bit modes.
274
47d8304e
AM		 2752005-02-24 Alan Modra <amodra@bigpond.net.au>
276
277 * cris-dis.c (format_hex): Remove ineffective warning fix.
278 * crx-dis.c (make_instruction): Warning fix.
279 * frv-asm.c: Regenerate.
280
ec36c4a4
NC		 2812005-02-23 Nick Clifton <nickc@redhat.com>
282
33b71eeb
NC		 283 * cgen-dis.in: Use bfd_byte for buffers that are passed to
284 read_memory.
06647dfd 285
33b71eeb 286 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 287
ec36c4a4
NC		 288 * crx-dis.c (make_instruction): Move argument structure into inner
289 scope and ensure that all of its fields are initialised before
290 they are used.
291
33b71eeb
NC		 292 * fr30-asm.c: Regenerate.
293 * fr30-dis.c: Regenerate.
294 * frv-asm.c: Regenerate.
295 * frv-dis.c: Regenerate.
296 * ip2k-asm.c: Regenerate.
297 * ip2k-dis.c: Regenerate.
298 * iq2000-asm.c: Regenerate.
299 * iq2000-dis.c: Regenerate.
300 * m32r-asm.c: Regenerate.
301 * m32r-dis.c: Regenerate.
302 * openrisc-asm.c: Regenerate.
303 * openrisc-dis.c: Regenerate.
304 * xstormy16-asm.c: Regenerate.
305 * xstormy16-dis.c: Regenerate.
306
53c9ebc5
AM		 3072005-02-22 Alan Modra <amodra@bigpond.net.au>
308
309 * arc-ext.c: Warning fixes.
310 * arc-ext.h: Likewise.
311 * cgen-opc.c: Likewise.
312 * ia64-gen.c: Likewise.
313 * maxq-dis.c: Likewise.
314 * ns32k-dis.c: Likewise.
315 * w65-dis.c: Likewise.
316 * ia64-asmtab.c: Regenerate.
317
610ad19b
AM		 3182005-02-22 Alan Modra <amodra@bigpond.net.au>
319
320 * fr30-desc.c: Regenerate.
321 * fr30-desc.h: Regenerate.
322 * fr30-opc.c: Regenerate.
323 * fr30-opc.h: Regenerate.
324 * frv-desc.c: Regenerate.
325 * frv-desc.h: Regenerate.
326 * frv-opc.c: Regenerate.
327 * frv-opc.h: Regenerate.
328 * ip2k-desc.c: Regenerate.
329 * ip2k-desc.h: Regenerate.
330 * ip2k-opc.c: Regenerate.
331 * ip2k-opc.h: Regenerate.
332 * iq2000-desc.c: Regenerate.
333 * iq2000-desc.h: Regenerate.
334 * iq2000-opc.c: Regenerate.
335 * iq2000-opc.h: Regenerate.
336 * m32r-desc.c: Regenerate.
337 * m32r-desc.h: Regenerate.
338 * m32r-opc.c: Regenerate.
339 * m32r-opc.h: Regenerate.
340 * m32r-opinst.c: Regenerate.
341 * openrisc-desc.c: Regenerate.
342 * openrisc-desc.h: Regenerate.
343 * openrisc-opc.c: Regenerate.
344 * openrisc-opc.h: Regenerate.
345 * xstormy16-desc.c: Regenerate.
346 * xstormy16-desc.h: Regenerate.
347 * xstormy16-opc.c: Regenerate.
348 * xstormy16-opc.h: Regenerate.
349
db9db6f2
AM		 3502005-02-21 Alan Modra <amodra@bigpond.net.au>
351
352 * Makefile.am: Run "make dep-am"
353 * Makefile.in: Regenerate.
354
bf143b25
NC		 3552005-02-15 Nick Clifton <nickc@redhat.com>
356
357 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
358 compile time warnings.
359 (print_keyword): Likewise.
360 (default_print_insn): Likewise.
361
362 * fr30-desc.c: Regenerated.
363 * fr30-desc.h: Regenerated.
364 * fr30-dis.c: Regenerated.
365 * fr30-opc.c: Regenerated.
366 * fr30-opc.h: Regenerated.
367 * frv-desc.c: Regenerated.
368 * frv-dis.c: Regenerated.
369 * frv-opc.c: Regenerated.
370 * ip2k-asm.c: Regenerated.
371 * ip2k-desc.c: Regenerated.
372 * ip2k-desc.h: Regenerated.
373 * ip2k-dis.c: Regenerated.
374 * ip2k-opc.c: Regenerated.
375 * ip2k-opc.h: Regenerated.
376 * iq2000-desc.c: Regenerated.
377 * iq2000-dis.c: Regenerated.
378 * iq2000-opc.c: Regenerated.
379 * m32r-asm.c: Regenerated.
380 * m32r-desc.c: Regenerated.
381 * m32r-desc.h: Regenerated.
382 * m32r-dis.c: Regenerated.
383 * m32r-opc.c: Regenerated.
384 * m32r-opc.h: Regenerated.
385 * m32r-opinst.c: Regenerated.
386 * openrisc-desc.c: Regenerated.
387 * openrisc-desc.h: Regenerated.
388 * openrisc-dis.c: Regenerated.
389 * openrisc-opc.c: Regenerated.
390 * openrisc-opc.h: Regenerated.
391 * xstormy16-desc.c: Regenerated.
392 * xstormy16-desc.h: Regenerated.
393 * xstormy16-dis.c: Regenerated.
394 * xstormy16-opc.c: Regenerated.
395 * xstormy16-opc.h: Regenerated.
396
d6098898
L		 3972005-02-14 H.J. Lu <hongjiu.lu@intel.com>
398
399 * dis-buf.c (perror_memory): Use sprintf_vma to print out
400 address.
401
5a84f3e0
NC		 4022005-02-11 Nick Clifton <nickc@redhat.com>
403
bc18c937
NC		 404 * iq2000-asm.c: Regenerate.
405
5a84f3e0
NC		 406 * frv-dis.c: Regenerate.
407
0a40490e
JB		 4082005-02-07 Jim Blandy <jimb@redhat.com>
409
410 * Makefile.am (CGEN): Load guile.scm before calling the main
411 application script.
412 * Makefile.in: Regenerated.
413 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
414 Simply pass the cgen-opc.scm path to ${cgen} as its first
415 argument; ${cgen} itself now contains the '-s', or whatever is
416 appropriate for the Scheme being used.
417
c46f8c51
AC		 4182005-01-31 Andrew Cagney <cagney@gnu.org>
419
420 * configure: Regenerate to track ../gettext.m4.
421
60b9a617
JB		 4222005-01-31 Jan Beulich <jbeulich@novell.com>
423
424 * ia64-gen.c (NELEMS): Define.
425 (shrink): Generate alias with missing second predicate register when
426 opcode has two outputs and these are both predicates.
427 * ia64-opc-i.c (FULL17): Define.
428 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
429 here to generate output template.
430 (TBITCM, TNATCM): Undefine after use.
431 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
432 first input. Add ld16 aliases without ar.csd as second output. Add
433 st16 aliases without ar.csd as second input. Add cmpxchg aliases
434 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
435 ar.ccv as third/fourth inputs. Consolidate through...
436 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
437 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
438 * ia64-asmtab.c: Regenerate.
439
a53bf506
AC		 4402005-01-27 Andrew Cagney <cagney@gnu.org>
441
442 * configure: Regenerate to track ../gettext.m4 change.
443
90219bd0
AO		 4442005-01-25 Alexandre Oliva <aoliva@redhat.com>
445
446 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
447 * frv-asm.c: Rebuilt.
448 * frv-desc.c: Rebuilt.
449 * frv-desc.h: Rebuilt.
450 * frv-dis.c: Rebuilt.
451 * frv-ibld.c: Rebuilt.
452 * frv-opc.c: Rebuilt.
453 * frv-opc.h: Rebuilt.
454
45181ed1
AC		 4552005-01-24 Andrew Cagney <cagney@gnu.org>
456
457 * configure: Regenerate, ../gettext.m4 was updated.
458
9e836e3d
FF		 4592005-01-21 Fred Fish <fnf@specifixinc.com>
460
461 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
462 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
463 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
464 * mips-dis.c: Ditto.
465
5e8cb021
AM		 4662005-01-20 Alan Modra <amodra@bigpond.net.au>
467
468 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
469
986e18a5
FF		 4702005-01-19 Fred Fish <fnf@specifixinc.com>
471
472 * mips-dis.c (no_aliases): New disassembly option flag.
473 (set_default_mips_dis_options): Init no_aliases to zero.
474 (parse_mips_dis_option): Handle no-aliases option.
475 (print_insn_mips): Ignore table entries that are aliases
476 if no_aliases is set.
477 (print_insn_mips16): Ditto.
478 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
479 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
480 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
481 * mips16-opc.c (mips16_opcodes): Ditto.
482
e38bc3b5
NC		 4832005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
484
485 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
486 (inheritance diagram): Add missing edge.
487 (arch_sh1_up): Rename arch_sh_up to match external name to make life
488 easier for the testsuite.
489 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
490 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 491 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 492 arch_sh2a_or_sh4_up child.
493 (sh_table): Do renaming as above.
494 Correct comment for ldc.l for gas testsuite to read.
495 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
496 Correct comments for movy.w and movy.l for gas testsuite to read.
497 Correct comments for fmov.d and fmov.s for gas testsuite to read.
498
9df48ba9
L		 4992005-01-12 H.J. Lu <hongjiu.lu@intel.com>
500
501 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
502
2033b4b9
L		 5032005-01-12 H.J. Lu <hongjiu.lu@intel.com>
504
505 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
506
0bcb06d2
AS		 5072005-01-10 Andreas Schwab <schwab@suse.de>
508
509 * disassemble.c (disassemble_init_for_target) <case
510 bfd_arch_ia64>: Set skip_zeroes to 16.
511 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
512
47add74d
TL		 5132004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
514
515 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
516
246f4c05
SS		 5172004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
518
519 * avr-dis.c: Prettyprint. Added printing of symbol names in all
520 memory references. Convert avr_operand() to C90 formatting.
521
0e1200e5
TL		 5222004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
523
524 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
525
89a649f7
TL		 5262004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
527
528 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
529 (no_op_insn): Initialize array with instructions that have no
530 operands.
531 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
532
6255809c
RE		 5332004-11-29 Richard Earnshaw <rearnsha@arm.com>
534
535 * arm-dis.c: Correct top-level comment.
536
2fbad815
RE		 5372004-11-27 Richard Earnshaw <rearnsha@arm.com>
538
539 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
540 architecuture defining the insn.
541 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 542 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
543 field.
2fbad815
RE		 544 Also include opcode/arm.h.
545 * Makefile.am (arm-dis.lo): Update dependency list.
546 * Makefile.in: Regenerate.
547
d81acc42
NC		 5482004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
549
550 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
551 reflect the change to the short immediate syntax.
552
ca4f2377
AM		 5532004-11-19 Alan Modra <amodra@bigpond.net.au>
554
5da8bf1b
AM		 555 * or32-opc.c (debug): Warning fix.
556 * po/POTFILES.in: Regenerate.
557
ca4f2377
AM		 558 * maxq-dis.c: Formatting.
559 (print_insn): Warning fix.
560
b7693d02
DJ		 5612004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
562
563 * arm-dis.c (WORD_ADDRESS): Define.
564 (print_insn): Use it. Correct big-endian end-of-section handling.
565
300dac7e
NC		 5662004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
567 Vineet Sharma <vineets@noida.hcltech.com>
568
569 * maxq-dis.c: New file.
570 * disassemble.c (ARCH_maxq): Define.
610ad19b 571 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 572 instructions..
573 * configure.in: Add case for bfd_maxq_arch.
574 * configure: Regenerate.
575 * Makefile.am: Add support for maxq-dis.c
576 * Makefile.in: Regenerate.
577 * aclocal.m4: Regenerate.
578
42048ee7
TL		 5792004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
580
581 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
582 mode.
583 * crx-dis.c: Likewise.
584
bd21e58e
HPN		 5852004-11-04 Hans-Peter Nilsson <hp@axis.com>
586
587 Generally, handle CRISv32.
588 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
589 (struct cris_disasm_data): New type.
590 (format_reg, format_hex, cris_constraint, print_flags)
591 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
592 callers changed.
593 (format_sup_reg, print_insn_crisv32_with_register_prefix)
594 (print_insn_crisv32_without_register_prefix)
595 (print_insn_crisv10_v32_with_register_prefix)
596 (print_insn_crisv10_v32_without_register_prefix)
597 (cris_parse_disassembler_options): New functions.
598 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
599 parameter. All callers changed.
600 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
601 failure.
602 (cris_constraint) <case 'Y', 'U'>: New cases.
603 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
604 for constraint 'n'.
605 (print_with_operands) <case 'Y'>: New case.
606 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
607 <case 'N', 'Y', 'Q'>: New cases.
608 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
609 (print_insn_cris_with_register_prefix)
610 (print_insn_cris_without_register_prefix): Call
611 cris_parse_disassembler_options.
612 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
613 for CRISv32 and the size of immediate operands. New v32-only
614 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
615 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
616 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
617 Change brp to be v3..v10.
618 (cris_support_regs): New vector.
619 (cris_opcodes): Update head comment. New format characters '[',
620 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
621 Add new opcodes for v32 and adjust existing opcodes to accommodate
622 differences to earlier variants.
623 (cris_cond15s): New vector.
624
9306ca4a
JB		 6252004-11-04 Jan Beulich <jbeulich@novell.com>
626
627 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
628 (indirEb): Remove.
629 (Mp): Use f_mode rather than none at all.
630 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
631 replaces what previously was x_mode; x_mode now means 128-bit SSE
632 operands.
633 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
634 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
635 pinsrw's second operand is Edqw.
636 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
637 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
638 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
639 mode when an operand size override is present or always suffixing.
640 More instructions will need to be added to this group.
641 (putop): Handle new macro chars 'C' (short/long suffix selector),
642 'I' (Intel mode override for following macro char), and 'J' (for
643 adding the 'l' prefix to far branches in AT&T mode). When an
644 alternative was specified in the template, honor macro character when
645 specified for Intel mode.
646 (OP_E): Handle new *_mode values. Correct pointer specifications for
647 memory operands. Consolidate output of index register.
648 (OP_G): Handle new *_mode values.
649 (OP_I): Handle const_1_mode.
650 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
651 respective opcode prefix bits have been consumed.
652 (OP_EM, OP_EX): Provide some default handling for generating pointer
653 specifications.
654
f39c96a9
TL		 6552004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
656
657 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
658 COP_INST macro.
659
812337be
TL		 6602004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
661
662 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
663 (getregliststring): Support HI/LO and user registers.
610ad19b 664 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 665 rearrangement done in CRX opcode header file.
666 (crx_regtab): Likewise.
667 (crx_optab): Likewise.
610ad19b 668 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 669 formats.
670 support new Co-Processor instruction 'cpi'.
671
4030fa5a
NC		 6722004-10-27 Nick Clifton <nickc@redhat.com>
673
674 * opcodes/iq2000-asm.c: Regenerate.
675 * opcodes/iq2000-desc.c: Regenerate.
676 * opcodes/iq2000-desc.h: Regenerate.
677 * opcodes/iq2000-dis.c: Regenerate.
678 * opcodes/iq2000-ibld.c: Regenerate.
679 * opcodes/iq2000-opc.c: Regenerate.
680 * opcodes/iq2000-opc.h: Regenerate.
681
fc3d45e8
TL		 6822004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
683
684 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
685 us4, us5 (respectively).
686 Remove unsupported 'popa' instruction.
687 Reverse operands order in store co-processor instructions.
688
3c55da70
AM		 6892004-10-15 Alan Modra <amodra@bigpond.net.au>
690
691 * Makefile.am: Run "make dep-am"
692 * Makefile.in: Regenerate.
693
7fa3d080
BW		 6942004-10-12 Bob Wilson <bob.wilson@acm.org>
695
696 * xtensa-dis.c: Use ISO C90 formatting.
697
e612bb4d
AM		 6982004-10-09 Alan Modra <amodra@bigpond.net.au>
699
700 * ppc-opc.c: Revert 2004-09-09 change.
701
43cd72b9
BW		 7022004-10-07 Bob Wilson <bob.wilson@acm.org>
703
704 * xtensa-dis.c (state_names): Delete.
705 (fetch_data): Use xtensa_isa_maxlength.
706 (print_xtensa_operand): Replace operand parameter with opcode/operand
707 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
708 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
709 instruction bundles. Use xmalloc instead of malloc.
710
bbac1f2a
NC		 7112004-10-07 David Gibson <david@gibson.dropbear.id.au>
712
713 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
714 initializers.
715
48c9f030
NC		 7162004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
717
718 * crx-opc.c (crx_instruction): Support Co-processor insns.
719 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
720 (getregliststring): Change function to use the above enum.
721 (print_arg): Handle CO-Processor insns.
722 (crx_cinvs): Add 'b' option to invalidate the branch-target
723 cache.
724
12c64a4e
AH		 7252004-10-06 Aldy Hernandez <aldyh@redhat.com>
726
727 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
728 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
729 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
730 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
731 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
732
14127cc4
NC		 7332004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
734
735 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
736 rather than add it.
737
0dd132b6
NC		 7382004-09-30 Paul Brook <paul@codesourcery.com>
739
740 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
741 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
742
3f85e526
L		 7432004-09-17 H.J. Lu <hongjiu.lu@intel.com>
744
745 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
746 (CONFIG_STATUS_DEPENDENCIES): New.
747 (Makefile): Removed.
748 (config.status): Likewise.
749 * Makefile.in: Regenerated.
750
8ae85421
AM		 7512004-09-17 Alan Modra <amodra@bigpond.net.au>
752
753 * Makefile.am: Run "make dep-am".
754 * Makefile.in: Regenerate.
755 * aclocal.m4: Regenerate.
756 * configure: Regenerate.
757 * po/POTFILES.in: Regenerate.
758 * po/opcodes.pot: Regenerate.
759
24443139
AS		 7602004-09-11 Andreas Schwab <schwab@suse.de>
761
762 * configure: Rebuild.
763
2a309db0
AM		 7642004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
765
766 * ppc-opc.c (L): Make this field not optional.
767
42851540
NC		 7682004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
769
770 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
771 Fix parameter to 'm[t|f]csr' insns.
772
979273e3
NN		 7732004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
774
775 * configure.in: Autoupdate to autoconf 2.59.
776 * aclocal.m4: Rebuild with aclocal 1.4p6.
777 * configure: Rebuild with autoconf 2.59.
778 * Makefile.in: Rebuild with automake 1.4p6 (picking up
779 bfd changes for autoconf 2.59 on the way).
780 * config.in: Rebuild with autoheader 2.59.
781
ac28a1cb
RS		 7822004-08-27 Richard Sandiford <rsandifo@redhat.com>
783
784 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
785
30d1c836
ML		 7862004-07-30 Michal Ludvig <mludvig@suse.cz>
787
788 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
789 (GRPPADLCK2): New define.
790 (twobyte_has_modrm): True for 0xA6.
791 (grps): GRPPADLCK2 for opcode 0xA6.
792
0b0ac059
AO		 7932004-07-29 Alexandre Oliva <aoliva@redhat.com>
794
795 Introduce SH2a support.
796 * sh-opc.h (arch_sh2a_base): Renumber.
797 (arch_sh2a_nofpu_base): Remove.
798 (arch_sh_base_mask): Adjust.
799 (arch_opann_mask): New.
800 (arch_sh2a, arch_sh2a_nofpu): Adjust.
801 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
802 (sh_table): Adjust whitespace.
803 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
804 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
805 instruction list throughout.
806 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
807 of arch_sh2a in instruction list throughout.
808 (arch_sh2e_up): Accomodate above changes.
809 (arch_sh2_up): Ditto.
810 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
811 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
812 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
813 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
814 * sh-opc.h (arch_sh2a_nofpu): New.
815 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
816 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
817 instruction.
818 2004-01-20 DJ Delorie <dj@redhat.com>
819 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
820 2003-12-29 DJ Delorie <dj@redhat.com>
821 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
822 sh_opcode_info, sh_table): Add sh2a support.
823 (arch_op32): New, to tag 32-bit opcodes.
824 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
825 2003-12-02 Michael Snyder <msnyder@redhat.com>
826 * sh-opc.h (arch_sh2a): Add.
827 * sh-dis.c (arch_sh2a): Handle.
828 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
829
670ec21d
NC		 8302004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
831
832 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
833
ed049af3
NC		 8342004-07-22 Nick Clifton <nickc@redhat.com>
835
836 PR/280
837 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
838 insns - this is done by objdump itself.
839 * h8500-dis.c (print_insn_h8500): Likewise.
840
20f0a1fc
NC		 8412004-07-21 Jan Beulich <jbeulich@novell.com>
842
843 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
844 regardless of address size prefix in effect.
845 (ptr_reg): Size or address registers does not depend on rex64, but
846 on the presence of an address size override.
847 (OP_MMX): Use rex.x only for xmm registers.
848 (OP_EM): Use rex.z only for xmm registers.
849
6f14957b
MR		 8502004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
851
852 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
853 move/branch operations to the bottom so that VR5400 multimedia
854 instructions take precedence in disassembly.
855
1586d91e
MR		 8562004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
857
858 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
859 ISA-specific "break" encoding.
860
982de27a
NC		 8612004-07-13 Elvis Chiang <elvisfb@gmail.com>
862
863 * arm-opc.h: Fix typo in comment.
864
4300ab10
AS		 8652004-07-11 Andreas Schwab <schwab@suse.de>
866
867 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
868
8577e690
AS		 8692004-07-09 Andreas Schwab <schwab@suse.de>
870
871 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
872
1fe1f39c
NC		 8732004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
874
875 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
876 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
877 (crx-dis.lo): New target.
878 (crx-opc.lo): Likewise.
879 * Makefile.in: Regenerate.
880 * configure.in: Handle bfd_crx_arch.
881 * configure: Regenerate.
882 * crx-dis.c: New file.
883 * crx-opc.c: New file.
884 * disassemble.c (ARCH_crx): Define.
885 (disassembler): Handle ARCH_crx.
886
7a33b495
JW		 8872004-06-29 James E Wilson <wilson@specifixinc.com>
888
889 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
890 * ia64-asmtab.c: Regnerate.
891
98e69875
AM		 8922004-06-28 Alan Modra <amodra@bigpond.net.au>
893
894 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
895 (extract_fxm): Don't test dialect.
896 (XFXFXM_MASK): Include the power4 bit.
897 (XFXM): Add p4 param.
898 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
899
a53b85e2
AO		 9002004-06-27 Alexandre Oliva <aoliva@redhat.com>
901
902 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
903 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
904
d0618d1c
AM		 9052004-06-26 Alan Modra <amodra@bigpond.net.au>
906
907 * ppc-opc.c (BH, XLBH_MASK): Define.
908 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
909
1d9f512f
AM		 9102004-06-24 Alan Modra <amodra@bigpond.net.au>
911
912 * i386-dis.c (x_mode): Comment.
913 (two_source_ops): File scope.
914 (float_mem): Correct fisttpll and fistpll.
915 (float_mem_mode): New table.
916 (dofloat): Use it.
917 (OP_E): Correct intel mode PTR output.
918 (ptr_reg): Use open_char and close_char.
919 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
920 operands. Set two_source_ops.
921
52886d70
AM		 9222004-06-15 Alan Modra <amodra@bigpond.net.au>
923
924 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
925 instead of _raw_size.
926
bad9ceea
JJ		 9272004-06-08 Jakub Jelinek <jakub@redhat.com>
928
929 * ia64-gen.c (in_iclass): Handle more postinc st
930 and ld variants.
931 * ia64-asmtab.c: Rebuilt.
932
0451f5df
MS		 9332004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
934
935 * s390-opc.txt: Correct architecture mask for some opcodes.
936 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
937 in the esa mode as well.
938
f6f9408f
JR		 9392004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
940
941 * sh-dis.c (target_arch): Make unsigned.
942 (print_insn_sh): Replace (most of) switch with a call to
943 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
944 * sh-opc.h: Redefine architecture flags values.
945 Add sh3-nommu architecture.
946 Reorganise <arch>_up macros so they make more visual sense.
947 (SH_MERGE_ARCH_SET): Define new macro.
948 (SH_VALID_BASE_ARCH_SET): Likewise.
949 (SH_VALID_MMU_ARCH_SET): Likewise.
950 (SH_VALID_CO_ARCH_SET): Likewise.
951 (SH_VALID_ARCH_SET): Likewise.
952 (SH_MERGE_ARCH_SET_VALID): Likewise.
953 (SH_ARCH_SET_HAS_FPU): Likewise.
954 (SH_ARCH_SET_HAS_DSP): Likewise.
955 (SH_ARCH_UNKNOWN_ARCH): Likewise.
956 (sh_get_arch_from_bfd_mach): Add prototype.
957 (sh_get_arch_up_from_bfd_mach): Likewise.
958 (sh_get_bfd_mach_from_arch_set): Likewise.
959 (sh_merge_bfd_arc): Likewise.
960
be8c092b
NC		 9612004-05-24 Peter Barada <peter@the-baradas.com>
962
963 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 964 into new match_insn_m68k function. Loop over canidate
965 matches and select first that completely matches.
be8c092b
NC		 966 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
967 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 968 to verify addressing for MAC/EMAC.
be8c092b
NC		 969 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
970 reigster halves since 'fpu' and 'spl' look misleading.
971 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
972 * m68k-opc.c: Rearragne mac/emac cases to use longest for
973 first, tighten up match masks.
974 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
975 'size' from special case code in print_insn_m68k to
976 determine decode size of insns.
977
a30e9cc4
AM		 9782004-05-19 Alan Modra <amodra@bigpond.net.au>
979
980 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
981 well as when -mpower4.
982
9598fbe5
NC		 9832004-05-13 Nick Clifton <nickc@redhat.com>
984
985 * po/fr.po: Updated French translation.
986
6b6e92f4
NC		 9872004-05-05 Peter Barada <peter@the-baradas.com>
988
989 * m68k-dis.c(print_insn_m68k): Add new chips, use core
990 variants in arch_mask. Only set m68881/68851 for 68k chips.
991 * m68k-op.c: Switch from ColdFire chips to core variants.
992
a404d431
AM		 9932004-05-05 Alan Modra <amodra@bigpond.net.au>
994
a30e9cc4 995 PR 147.
a404d431
AM		 996 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
997
f3806e43
BE		 9982004-04-29 Ben Elliston <bje@au.ibm.com>
999
520ceea4
BE		 1000 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1001 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1002
1f1799d5
KK		 10032004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1004
1005 * sh-dis.c (print_insn_sh): Print the value in constant pool
1006 as a symbol if it looks like a symbol.
1007
fd99574b
NC		 10082004-04-22 Peter Barada <peter@the-baradas.com>
1009
1010 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1011 appropriate ColdFire architectures.
1012 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1013 mask addressing.
1014 Add EMAC instructions, fix MAC instructions. Remove
1015 macmw/macml/msacmw/msacml instructions since mask addressing now
1016 supported.
1017
b4781d44
JJ		 10182004-04-20 Jakub Jelinek <jakub@redhat.com>
1019
1020 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1021 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1022 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1023 macro. Adjust all users.
1024
91809fda 10252004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1026
91809fda
NC		 1027 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1028 separately.
1029
f4453dfa
NC		 10302004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1031
1032 * m32r-asm.c: Regenerate.
1033
9b0de91a
SS		 10342004-03-29 Stan Shebs <shebs@apple.com>
1035
1036 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1037 used.
1038
e20c0b3d
AM		 10392004-03-19 Alan Modra <amodra@bigpond.net.au>
1040
1041 * aclocal.m4: Regenerate.
1042 * config.in: Regenerate.
1043 * configure: Regenerate.
1044 * po/POTFILES.in: Regenerate.
1045 * po/opcodes.pot: Regenerate.
1046
fdd12ef3
AM		 10472004-03-16 Alan Modra <amodra@bigpond.net.au>
1048
1049 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1050 PPC_OPERANDS_GPR_0.
1051 * ppc-opc.c (RA0): Define.
1052 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1053 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1054 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1055
2dc111b3 10562004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1057
1058 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1059
7bfeee7b
AM		 10602004-03-15 Alan Modra <amodra@bigpond.net.au>
1061
1062 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1063
7ffdda93
ML		 10642004-03-12 Michal Ludvig <mludvig@suse.cz>
1065
1066 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1067 (grps): Delete GRPPLOCK entry.
7ffdda93 1068
cc0ec051
AM		 10692004-03-12 Alan Modra <amodra@bigpond.net.au>
1070
1071 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1072 (M, Mp): Use OP_M.
1073 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1074 (GRPPADLCK): Define.
1075 (dis386): Use NOP_Fixup on "nop".
1076 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1077 (twobyte_has_modrm): Set for 0xa7.
1078 (padlock_table): Delete. Move to..
1079 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1080 and clflush.
1081 (print_insn): Revert PADLOCK_SPECIAL code.
1082 (OP_E): Delete sfence, lfence, mfence checks.
1083
4fd61dcb
JJ		 10842004-03-12 Jakub Jelinek <jakub@redhat.com>
1085
1086 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1087 (INVLPG_Fixup): New function.
1088 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1089
0f10071e
ML		 10902004-03-12 Michal Ludvig <mludvig@suse.cz>
1091
1092 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1093 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1094 (padlock_table): New struct with PadLock instructions.
1095 (print_insn): Handle PADLOCK_SPECIAL.
1096
c02908d2
AM		 10972004-03-12 Alan Modra <amodra@bigpond.net.au>
1098
1099 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1100 (OP_E): Twiddle clflush to sfence here.
1101
d5bb7600
NC		 11022004-03-08 Nick Clifton <nickc@redhat.com>
1103
1104 * po/de.po: Updated German translation.
1105
ae51a426
JR		 11062003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1107
1108 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1109 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1110 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1111 accordingly.
1112
676a64f4
RS		 11132004-03-01 Richard Sandiford <rsandifo@redhat.com>
1114
1115 * frv-asm.c: Regenerate.
1116 * frv-desc.c: Regenerate.
1117 * frv-desc.h: Regenerate.
1118 * frv-dis.c: Regenerate.
1119 * frv-ibld.c: Regenerate.
1120 * frv-opc.c: Regenerate.
1121 * frv-opc.h: Regenerate.
1122
c7a48b9a
RS		 11232004-03-01 Richard Sandiford <rsandifo@redhat.com>
1124
1125 * frv-desc.c, frv-opc.c: Regenerate.
1126
8ae0baa2
RS		 11272004-03-01 Richard Sandiford <rsandifo@redhat.com>
1128
1129 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1130
ce11586c
JR		 11312004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1132
1133 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1134 Also correct mistake in the comment.
1135
6a5709a5
JR		 11362004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1137
1138 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1139 ensure that double registers have even numbers.
1140 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1141 that reserved instruction 0xfffd does not decode the same
1142 as 0xfdfd (ftrv).
1143 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1144 REG_N refers to a double register.
1145 Add REG_N_B01 nibble type and use it instead of REG_NM
1146 in ftrv.
1147 Adjust the bit patterns in a few comments.
1148
e5d2b64f 11492004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1150
1151 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1152
1f04b05f
AH		 11532004-02-20 Aldy Hernandez <aldyh@redhat.com>
1154
1155 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1156
2f3b8700
AH		 11572004-02-20 Aldy Hernandez <aldyh@redhat.com>
1158
1159 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1160
f0b26da6 11612004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1162
1163 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1164 mtivor32, mtivor33, mtivor34.
f0b26da6 1165
23d59c56 11662004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1167
1168 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1169
34920d91
NC		 11702004-02-10 Petko Manolov <petkan@nucleusys.com>
1171
1172 * arm-opc.h Maverick accumulator register opcode fixes.
1173
44d86481
BE		 11742004-02-13 Ben Elliston <bje@wasabisystems.com>
1175
1176 * m32r-dis.c: Regenerate.
1177
17707c23
MS		 11782004-01-27 Michael Snyder <msnyder@redhat.com>
1179
1180 * sh-opc.h (sh_table): "fsrra", not "fssra".
1181
fe3a9bc4
NC		 11822004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1183
1184 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1185 contraints.
1186
ff24f124
JJ		 11872004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1188
1189 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1190
a02a862a
AM		 11912004-01-19 Alan Modra <amodra@bigpond.net.au>
1192
1193 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1194 1. Don't print scale factor on AT&T mode when index missing.
1195
d164ea7f
AO		 11962004-01-16 Alexandre Oliva <aoliva@redhat.com>
1197
1198 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1199 when loaded into XR registers.
1200
cb10e79a
RS		 12012004-01-14 Richard Sandiford <rsandifo@redhat.com>
1202
1203 * frv-desc.h: Regenerate.
1204 * frv-desc.c: Regenerate.
1205 * frv-opc.c: Regenerate.
1206
f532f3fa
MS		 12072004-01-13 Michael Snyder <msnyder@redhat.com>
1208
1209 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1210
e45d0630
PB		 12112004-01-09 Paul Brook <paul@codesourcery.com>
1212
1213 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1214 specific opcodes.
1215
3ba7a1aa
DJ		 12162004-01-07 Daniel Jacobowitz <drow@mvista.com>
1217
1218 * Makefile.am (libopcodes_la_DEPENDENCIES)
1219 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1220 comment about the problem.
1221 * Makefile.in: Regenerate.
1222
ba2d3f07
AO		 12232004-01-06 Alexandre Oliva <aoliva@redhat.com>
1224
1225 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1226 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1227 cut&paste errors in shifting/truncating numerical operands.
1228 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1229 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1230 (parse_uslo16): Likewise.
1231 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1232 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1233 (parse_s12): Likewise.
1234 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1235 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1236 (parse_uslo16): Likewise.
1237 (parse_uhi16): Parse gothi and gotfuncdeschi.
1238 (parse_d12): Parse got12 and gotfuncdesc12.
1239 (parse_s12): Likewise.
1240
3ab48931
NC		 12412004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1242
1243 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1244 instruction which looks similar to an 'rla' instruction.
a0bd404e 1245
c9e214e5 1246For older changes see ChangeLog-0203
252b5132
RH		 1247\f
1248Local Variables:
2f6d2f85
NC		 1249mode: change-log
1250left-margin: 8
1251fill-column: 74
252b5132
RH		 1252version-control: never
1253End:
GDB Binutils - Deliverables
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