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Fix simple gas testsuite failures.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3ee6e4fb
NC		 12016-06-15 Nick Clifton <nickc@redhat.com>
2
3 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
4 constants to match expected behaviour.
5 (nds32_parse_opcode): Likewise. Also for whitespace.
6
02f3be19
AB		 72016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
8
9 * arc-opc.c (extract_rhv1): Extract value from insn.
10
6f9f37ed 112016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 12
13 * arc-nps400-tbl.h: Add ldbit instruction.
14 * arc-opc.c: Add flag classes required for ldbit.
15
6f9f37ed 162016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 17
18 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
19 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
20 support the above instructions.
21
6f9f37ed 222016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 23
24 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
25 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
26 csma, cbba, zncv, and hofs.
27 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
28 support the above instructions.
29
302016-06-06 Graham Markall <graham.markall@embecosm.com>
31
32 * arc-nps400-tbl.h: Add andab and orab instructions.
33
342016-06-06 Graham Markall <graham.markall@embecosm.com>
35
36 * arc-nps400-tbl.h: Add addl-like instructions.
37
382016-06-06 Graham Markall <graham.markall@embecosm.com>
39
40 * arc-nps400-tbl.h: Add mxb and imxb instructions.
41
422016-06-06 Graham Markall <graham.markall@embecosm.com>
43
44 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
45 instructions.
46
b2cc3f6f
AK		 472016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
48
49 * s390-dis.c (option_use_insn_len_bits_p): New file scope
50 variable.
51 (init_disasm): Handle new command line option "insnlength".
52 (print_s390_disassembler_options): Mention new option in help
53 output.
54 (print_insn_s390): Use the encoded insn length when dumping
55 unknown instructions.
56
1857fe72
DC		 572016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
58
59 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
60 to the address and set as symbol address for LDS/ STS immediate operands.
61
14b57c7c
AM		 622016-06-07 Alan Modra <amodra@gmail.com>
63
64 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
65 cpu for "vle" to e500.
66 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
67 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
68 (PPCNONE): Delete, substitute throughout.
69 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
70 except for major opcode 4 and 31.
71 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
72
4d1464f2
MW		 732016-06-07 Matthew Wahab <matthew.wahab@arm.com>
74
75 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
76 ARM_EXT_RAS in relevant entries.
77
026122a6
PB		 782016-06-03 Peter Bergner <bergner@vnet.ibm.com>
79
80 PR binutils/20196
81 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
82 opcodes for E6500.
83
07f5af7d
L		 842016-06-03 H.J. Lu <hongjiu.lu@intel.com>
85
86 PR binutis/18386
87 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
88 (indir_v_mode): New.
89 Add comments for '&'.
90 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
91 (putop): Handle '&'.
92 (intel_operand_size): Handle indir_v_mode.
93 (OP_E_register): Likewise.
94 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
95 64-bit indirect call/jmp for AMD64.
96 * i386-tbl.h: Regenerated
97
4eb6f892
AB		 982016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
99
100 * arc-dis.c (struct arc_operand_iterator): New structure.
101 (find_format_from_table): All the old content from find_format,
102 with some minor adjustments, and parameter renaming.
103 (find_format_long_instructions): New function.
104 (find_format): Rewritten.
105 (arc_insn_length): Add LSB parameter.
106 (extract_operand_value): New function.
107 (operand_iterator_next): New function.
108 (print_insn_arc): Use new functions to find opcode, and iterator
109 over operands.
110 * arc-opc.c (insert_nps_3bit_dst_short): New function.
111 (extract_nps_3bit_dst_short): New function.
112 (insert_nps_3bit_src2_short): New function.
113 (extract_nps_3bit_src2_short): New function.
114 (insert_nps_bitop1_size): New function.
115 (extract_nps_bitop1_size): New function.
116 (insert_nps_bitop2_size): New function.
117 (extract_nps_bitop2_size): New function.
118 (insert_nps_bitop_mod4_msb): New function.
119 (extract_nps_bitop_mod4_msb): New function.
120 (insert_nps_bitop_mod4_lsb): New function.
121 (extract_nps_bitop_mod4_lsb): New function.
122 (insert_nps_bitop_dst_pos3_pos4): New function.
123 (extract_nps_bitop_dst_pos3_pos4): New function.
124 (insert_nps_bitop_ins_ext): New function.
125 (extract_nps_bitop_ins_ext): New function.
126 (arc_operands): Add new operands.
127 (arc_long_opcodes): New global array.
128 (arc_num_long_opcodes): New global.
129 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
130
1fe0971e
TS		 1312016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
132
133 * nds32-asm.h: Add extern "C".
134 * sh-opc.h: Likewise.
135
315f180f
GM		 1362016-06-01 Graham Markall <graham.markall@embecosm.com>
137
138 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
139 0,b,limm to the rflt instruction.
140
a2b5fccc
TS		 1412016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
142
143 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
144 constant.
145
0cbd0046
L		 1462016-05-29 H.J. Lu <hongjiu.lu@intel.com>
147
148 PR gas/20145
149 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
150 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
151 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
152 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
153 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
154 * i386-init.h: Regenerated.
155
1848e567
L		 1562016-05-27 H.J. Lu <hongjiu.lu@intel.com>
157
158 PR gas/20145
159 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
160 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
161 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
162 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
163 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
164 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
165 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
166 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
167 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
168 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
169 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
170 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
171 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
172 CpuRegMask for AVX512.
173 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
174 and CpuRegMask.
175 (set_bitfield_from_cpu_flag_init): New function.
176 (set_bitfield): Remove const on f. Call
177 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
178 * i386-opc.h (CpuRegMMX): New.
179 (CpuRegXMM): Likewise.
180 (CpuRegYMM): Likewise.
181 (CpuRegZMM): Likewise.
182 (CpuRegMask): Likewise.
183 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
184 and cpuregmask.
185 * i386-init.h: Regenerated.
186 * i386-tbl.h: Likewise.
187
e92bae62
L		 1882016-05-27 H.J. Lu <hongjiu.lu@intel.com>
189
190 PR gas/20154
191 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
192 (opcode_modifiers): Add AMD64 and Intel64.
193 (main): Properly verify CpuMax.
194 * i386-opc.h (CpuAMD64): Removed.
195 (CpuIntel64): Likewise.
196 (CpuMax): Set to CpuNo64.
197 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
198 (AMD64): New.
199 (Intel64): Likewise.
200 (i386_opcode_modifier): Add amd64 and intel64.
201 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
202 on call and jmp.
203 * i386-init.h: Regenerated.
204 * i386-tbl.h: Likewise.
205
e89c5eaa
L		 2062016-05-27 H.J. Lu <hongjiu.lu@intel.com>
207
208 PR gas/20154
209 * i386-gen.c (main): Fail if CpuMax is incorrect.
210 * i386-opc.h (CpuMax): Set to CpuIntel64.
211 * i386-tbl.h: Regenerated.
212
77d66e7b
NC		 2132016-05-27 Nick Clifton <nickc@redhat.com>
214
215 PR target/20150
216 * msp430-dis.c (msp430dis_read_two_bytes): New function.
217 (msp430dis_opcode_unsigned): New function.
218 (msp430dis_opcode_signed): New function.
219 (msp430_singleoperand): Use the new opcode reading functions.
220 Only disassenmble bytes if they were successfully read.
221 (msp430_doubleoperand): Likewise.
222 (msp430_branchinstr): Likewise.
223 (msp430x_callx_instr): Likewise.
224 (print_insn_msp430): Check that it is safe to read bytes before
225 attempting disassembly. Use the new opcode reading functions.
226
19dfcc89
PB		 2272016-05-26 Peter Bergner <bergner@vnet.ibm.com>
228
229 * ppc-opc.c (CY): New define. Document it.
230 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
231
f3ad7637
L		 2322016-05-25 H.J. Lu <hongjiu.lu@intel.com>
233
234 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
235 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
236 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
237 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
238 CPU_ANY_AVX_FLAGS.
239 * i386-init.h: Regenerated.
240
f1360d58
L		 2412016-05-25 H.J. Lu <hongjiu.lu@intel.com>
242
243 PR gas/20141
244 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
245 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
246 * i386-init.h: Regenerated.
247
293f5f65
L		 2482016-05-25 H.J. Lu <hongjiu.lu@intel.com>
249
250 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
251 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
252 * i386-init.h: Regenerated.
253
d9eca1df
CZ		 2542016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
255
256 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
257 information.
258 (print_insn_arc): Set insn_type information.
259 * arc-opc.c (C_CC): Add F_CLASS_COND.
260 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
261 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
262 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
263 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
264 (brne, brne_s, jeq_s, jne_s): Likewise.
265
87789e08
CZ		 2662016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
267
268 * arc-tbl.h (neg): New instruction variant.
269
c810e0b8
CZ		 2702016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
271
272 * arc-dis.c (find_format, find_format, get_auxreg)
273 (print_insn_arc): Changed.
274 * arc-ext.h (INSERT_XOP): Likewise.
275
3d207518
TS		 2762016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
277
278 * tic54x-dis.c (sprint_mmr): Adjust.
279 * tic54x-opc.c: Likewise.
280
514e58b7
AM		 2812016-05-19 Alan Modra <amodra@gmail.com>
282
283 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
284
e43de63c
AM		 2852016-05-19 Alan Modra <amodra@gmail.com>
286
287 * ppc-opc.c: Formatting.
288 (NSISIGNOPT): Define.
289 (powerpc_opcodes <subis>): Use NSISIGNOPT.
290
1401d2fe
MR		 2912016-05-18 Maciej W. Rozycki <macro@imgtec.com>
292
293 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
294 replacing references to `micromips_ase' throughout.
295 (_print_insn_mips): Don't use file-level microMIPS annotation to
296 determine the disassembly mode with the symbol table.
297
1178da44
PB		 2982016-05-13 Peter Bergner <bergner@vnet.ibm.com>
299
300 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
301
8f4f9071
MF		 3022016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
303
304 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
305 mips64r6.
306 * mips-opc.c (D34): New macro.
307 (mips_builtin_opcodes): Define bposge32c for DSPr3.
308
8bc52696
AF		 3092016-05-10 Alexander Fomin <alexander.fomin@intel.com>
310
311 * i386-dis.c (prefix_table): Add RDPID instruction.
312 * i386-gen.c (cpu_flag_init): Add RDPID flag.
313 (cpu_flags): Add RDPID bitfield.
314 * i386-opc.h (enum): Add RDPID element.
315 (i386_cpu_flags): Add RDPID field.
316 * i386-opc.tbl: Add RDPID instruction.
317 * i386-init.h: Regenerate.
318 * i386-tbl.h: Regenerate.
319
39d911fc
TP		 3202016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
321
322 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
323 branch type of a symbol.
324 (print_insn): Likewise.
325
16a1fa25
TP		 3262016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
327
328 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
329 Mainline Security Extensions instructions.
330 (thumb_opcodes): Add entries for narrow ARMv8-M Security
331 Extensions instructions.
332 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
333 instructions.
334 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
335 special registers.
336
d751b79e
JM		 3372016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
338
339 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
340
945e0f82
CZ		 3412016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
342
343 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
344 (arcExtMap_genOpcode): Likewise.
345 * arc-opc.c (arg_32bit_rc): Define new variable.
346 (arg_32bit_u6): Likewise.
347 (arg_32bit_limm): Likewise.
348
20f55f38
SN		 3492016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
350
351 * aarch64-gen.c (VERIFIER): Define.
352 * aarch64-opc.c (VERIFIER): Define.
353 (verify_ldpsw): Use static linkage.
354 * aarch64-opc.h (verify_ldpsw): Remove.
355 * aarch64-tbl.h: Use VERIFIER for verifiers.
356
4bd13cde
NC		 3572016-04-28 Nick Clifton <nickc@redhat.com>
358
359 PR target/19722
360 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
361 * aarch64-opc.c (verify_ldpsw): New function.
362 * aarch64-opc.h (verify_ldpsw): New prototype.
363 * aarch64-tbl.h: Add initialiser for verifier field.
364 (LDPSW): Set verifier to verify_ldpsw.
365
c0f92bf9
L		 3662016-04-23 H.J. Lu <hongjiu.lu@intel.com>
367
368 PR binutils/19983
369 PR binutils/19984
370 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
371 smaller than address size.
372
e6c7cdec
TS		 3732016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
374
375 * alpha-dis.c: Regenerate.
376 * crx-dis.c: Likewise.
377 * disassemble.c: Likewise.
378 * epiphany-opc.c: Likewise.
379 * fr30-opc.c: Likewise.
380 * frv-opc.c: Likewise.
381 * ip2k-opc.c: Likewise.
382 * iq2000-opc.c: Likewise.
383 * lm32-opc.c: Likewise.
384 * lm32-opinst.c: Likewise.
385 * m32c-opc.c: Likewise.
386 * m32r-opc.c: Likewise.
387 * m32r-opinst.c: Likewise.
388 * mep-opc.c: Likewise.
389 * mt-opc.c: Likewise.
390 * or1k-opc.c: Likewise.
391 * or1k-opinst.c: Likewise.
392 * tic80-opc.c: Likewise.
393 * xc16x-opc.c: Likewise.
394 * xstormy16-opc.c: Likewise.
395
537aefaf
AB		 3962016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
397
398 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
399 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
400 calcsd, and calcxd instructions.
401 * arc-opc.c (insert_nps_bitop_size): Delete.
402 (extract_nps_bitop_size): Delete.
403 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
404 (extract_nps_qcmp_m3): Define.
405 (extract_nps_qcmp_m2): Define.
406 (extract_nps_qcmp_m1): Define.
407 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
408 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
409 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
410 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
411 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
412 NPS_QCMP_M3.
413
c8f785f2
AB		 4142016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
415
416 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
417
6fd8e7c2
L		 4182016-04-15 H.J. Lu <hongjiu.lu@intel.com>
419
420 * Makefile.in: Regenerated with automake 1.11.6.
421 * aclocal.m4: Likewise.
422
4b0c052e
AB		 4232016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
424
425 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
426 instructions.
427 * arc-opc.c (insert_nps_cmem_uimm16): New function.
428 (extract_nps_cmem_uimm16): New function.
429 (arc_operands): Add NPS_XLDST_UIMM16 operand.
430
cb040366
AB		 4312016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
432
433 * arc-dis.c (arc_insn_length): New function.
434 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
435 (find_format): Change insnLen parameter to unsigned.
436
accc0180
NC		 4372016-04-13 Nick Clifton <nickc@redhat.com>
438
439 PR target/19937
440 * v850-opc.c (v850_opcodes): Correct masks for long versions of
441 the LD.B and LD.BU instructions.
442
f36e33da
CZ		 4432016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
444
445 * arc-dis.c (find_format): Check for extension flags.
446 (print_flags): New function.
447 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
448 .extAuxRegister.
449 * arc-ext.c (arcExtMap_coreRegName): Use
450 LAST_EXTENSION_CORE_REGISTER.
451 (arcExtMap_coreReadWrite): Likewise.
452 (dump_ARC_extmap): Update printing.
453 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
454 (arc_aux_regs): Add cpu field.
455 * arc-regs.h: Add cpu field, lower case name aux registers.
456
1c2e355e
CZ		 4572016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
458
459 * arc-tbl.h: Add rtsc, sleep with no arguments.
460
b99747ae
CZ		 4612016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
462
463 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
464 Initialize.
465 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
466 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
467 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
468 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
469 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
470 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
471 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
472 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
473 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
474 (arc_opcode arc_opcodes): Null terminate the array.
475 (arc_num_opcodes): Remove.
476 * arc-ext.h (INSERT_XOP): Define.
477 (extInstruction_t): Likewise.
478 (arcExtMap_instName): Delete.
479 (arcExtMap_insn): New function.
480 (arcExtMap_genOpcode): Likewise.
481 * arc-ext.c (ExtInstruction): Remove.
482 (create_map): Zero initialize instruction fields.
483 (arcExtMap_instName): Remove.
484 (arcExtMap_insn): New function.
485 (dump_ARC_extmap): More info while debuging.
486 (arcExtMap_genOpcode): New function.
487 * arc-dis.c (find_format): New function.
488 (print_insn_arc): Use find_format.
489 (arc_get_disassembler): Enable dump_ARC_extmap only when
490 debugging.
491
92708cec
MR		 4922016-04-11 Maciej W. Rozycki <macro@imgtec.com>
493
494 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
495 instruction bits out.
496
a42a4f84
AB		 4972016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
498
499 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
500 * arc-opc.c (arc_flag_operands): Add new flags.
501 (arc_flag_classes): Add new classes.
502
1328504b
AB		 5032016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
504
505 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
506
820f03ff
AB		 5072016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
508
509 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
510 encode1, rflt, crc16, and crc32 instructions.
511 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
512 (arc_flag_classes): Add C_NPS_R.
513 (insert_nps_bitop_size_2b): New function.
514 (extract_nps_bitop_size_2b): Likewise.
515 (insert_nps_bitop_uimm8): Likewise.
516 (extract_nps_bitop_uimm8): Likewise.
517 (arc_operands): Add new operand entries.
518
8ddf6b2a
CZ		 5192016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
520
b99747ae
CZ		 521 * arc-regs.h: Add a new subclass field. Add double assist
522 accumulator register values.
523 * arc-tbl.h: Use DPA subclass to mark the double assist
524 instructions. Use DPX/SPX subclas to mark the FPX instructions.
525 * arc-opc.c (RSP): Define instead of SP.
526 (arc_aux_regs): Add the subclass field.
8ddf6b2a 527
589a7d88
JW		 5282016-04-05 Jiong Wang <jiong.wang@arm.com>
529
530 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
531
0a191de9 5322016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 533
534 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
535 NPS_R_SRC1.
536
0a106562
AB		 5372016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
538
539 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
540 issues. No functional changes.
541
bd05ac5f
CZ		 5422016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
543
b99747ae
CZ		 544 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
545 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
546 (RTT): Remove duplicate.
547 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
548 (PCT_CONFIG*): Remove.
549 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 550
9885948f
CZ		 5512016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
552
b99747ae 553 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 554
f2dd8838
CZ		 5552016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
556
b99747ae
CZ		 557 * arc-tbl.h (invld07): Remove.
558 * arc-ext-tbl.h: New file.
559 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
560 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 561
0d2f91fe
JK		 5622016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
563
564 Fix -Wstack-usage warnings.
565 * aarch64-dis.c (print_operands): Substitute size.
566 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
567
a6b71f42
JM		 5682016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
569
570 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
571 to get a proper diagnostic when an invalid ASR register is used.
572
9780e045
NC		 5732016-03-22 Nick Clifton <nickc@redhat.com>
574
575 * configure: Regenerate.
576
e23e8ebe
AB		 5772016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
578
579 * arc-nps400-tbl.h: New file.
580 * arc-opc.c: Add top level comment.
581 (insert_nps_3bit_dst): New function.
582 (extract_nps_3bit_dst): New function.
583 (insert_nps_3bit_src2): New function.
584 (extract_nps_3bit_src2): New function.
585 (insert_nps_bitop_size): New function.
586 (extract_nps_bitop_size): New function.
587 (arc_flag_operands): Add nps400 entries.
588 (arc_flag_classes): Add nps400 entries.
589 (arc_operands): Add nps400 entries.
590 (arc_opcodes): Add nps400 include.
591
1ae8ab47
AB		 5922016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
593
594 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
595 the new class enum values.
596
8699fc3e
AB		 5972016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
598
599 * arc-dis.c (print_insn_arc): Handle nps400.
600
24740d83
AB		 6012016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
602
603 * arc-opc.c (BASE): Delete.
604
8678914f
NC		 6052016-03-18 Nick Clifton <nickc@redhat.com>
606
607 PR target/19721
608 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
609 of MOV insn that aliases an ORR insn.
610
cc933301
JW		 6112016-03-16 Jiong Wang <jiong.wang@arm.com>
612
613 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
614
f86f5863
TS		 6152016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
616
617 * mcore-opc.h: Add const qualifiers.
618 * microblaze-opc.h (struct op_code_struct): Likewise.
619 * sh-opc.h: Likewise.
620 * tic4x-dis.c (tic4x_print_indirect): Likewise.
621 (tic4x_print_op): Likewise.
622
62de1c63
AM		 6232016-03-02 Alan Modra <amodra@gmail.com>
624
d11698cd 625 * or1k-desc.h: Regenerate.
62de1c63 626 * fr30-ibld.c: Regenerate.
c697cf0b 627 * rl78-decode.c: Regenerate.
62de1c63 628
020efce5
NC		 6292016-03-01 Nick Clifton <nickc@redhat.com>
630
631 PR target/19747
632 * rl78-dis.c (print_insn_rl78_common): Fix typo.
633
b0c11777
RL		 6342016-02-24 Renlin Li <renlin.li@arm.com>
635
636 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
637 (print_insn_coprocessor): Support fp16 instructions.
638
3e309328
RL		 6392016-02-24 Renlin Li <renlin.li@arm.com>
640
641 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
642 vminnm, vrint(mpna).
643
8afc7bea
RL		 6442016-02-24 Renlin Li <renlin.li@arm.com>
645
646 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
647 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
648
4fd7268a
L		 6492016-02-15 H.J. Lu <hongjiu.lu@intel.com>
650
651 * i386-dis.c (print_insn): Parenthesize expression to prevent
652 truncated addresses.
653 (OP_J): Likewise.
654
4670103e
CZ		 6552016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
656 Janek van Oirschot <jvanoirs@synopsys.com>
657
b99747ae
CZ		 658 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
659 variable.
4670103e 660
c1d9289f
NC		 6612016-02-04 Nick Clifton <nickc@redhat.com>
662
663 PR target/19561
664 * msp430-dis.c (print_insn_msp430): Add a special case for
665 decoding an RRC instruction with the ZC bit set in the extension
666 word.
667
a143b004
AB		 6682016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
669
670 * cgen-ibld.in (insert_normal): Rework calculation of shift.
671 * epiphany-ibld.c: Regenerate.
672 * fr30-ibld.c: Regenerate.
673 * frv-ibld.c: Regenerate.
674 * ip2k-ibld.c: Regenerate.
675 * iq2000-ibld.c: Regenerate.
676 * lm32-ibld.c: Regenerate.
677 * m32c-ibld.c: Regenerate.
678 * m32r-ibld.c: Regenerate.
679 * mep-ibld.c: Regenerate.
680 * mt-ibld.c: Regenerate.
681 * or1k-ibld.c: Regenerate.
682 * xc16x-ibld.c: Regenerate.
683 * xstormy16-ibld.c: Regenerate.
684
b89807c6
AB		 6852016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
686
687 * epiphany-dis.c: Regenerated from latest cpu files.
688
d8c823c8
MM		 6892016-02-01 Michael McConville <mmcco@mykolab.com>
690
691 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
692 test bit.
693
5bc5ae88
RL		 6942016-01-25 Renlin Li <renlin.li@arm.com>
695
696 * arm-dis.c (mapping_symbol_for_insn): New function.
697 (find_ifthen_state): Call mapping_symbol_for_insn().
698
0bff6e2d
MW		 6992016-01-20 Matthew Wahab <matthew.wahab@arm.com>
700
701 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
702 of MSR UAO immediate operand.
703
100b4f2e
MR		 7042016-01-18 Maciej W. Rozycki <macro@imgtec.com>
705
706 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
707 instruction support.
708
5c14705f
AM		 7092016-01-17 Alan Modra <amodra@gmail.com>
710
711 * configure: Regenerate.
712
4d82fe66
NC		 7132016-01-14 Nick Clifton <nickc@redhat.com>
714
715 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
716 instructions that can support stack pointer operations.
717 * rl78-decode.c: Regenerate.
718 * rl78-dis.c: Fix display of stack pointer in MOVW based
719 instructions.
720
651657fa
MW		 7212016-01-14 Matthew Wahab <matthew.wahab@arm.com>
722
723 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
724 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
725 erxtatus_el1 and erxaddr_el1.
726
105bde57
MW		 7272016-01-12 Matthew Wahab <matthew.wahab@arm.com>
728
729 * arm-dis.c (arm_opcodes): Add "esb".
730 (thumb_opcodes): Likewise.
731
afa8d405
PB		 7322016-01-11 Peter Bergner <bergner@vnet.ibm.com>
733
734 * ppc-opc.c <xscmpnedp>: Delete.
735 <xvcmpnedp>: Likewise.
736 <xvcmpnedp.>: Likewise.
737 <xvcmpnesp>: Likewise.
738 <xvcmpnesp.>: Likewise.
739
83c3256e
AS		 7402016-01-08 Andreas Schwab <schwab@linux-m68k.org>
741
742 PR gas/13050
743 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
744 addition to ISA_A.
745
6f2750fe
AM		 7462016-01-01 Alan Modra <amodra@gmail.com>
747
748 Update year range in copyright notice of all files.
749
3499769a
AM		 750For older changes see ChangeLog-2015
751\f
752Copyright (C) 2016 Free Software Foundation, Inc.
753
754Copying and distribution of this file, with or without modification,
755are permitted in any medium without royalty provided the copyright
756notice and this notice are preserved.
757
758Local Variables:
759mode: change-log
760left-margin: 8
761fill-column: 74
762version-control: never
763End:
GDB Binutils - Deliverables
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