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[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
40d16a76
MW		 12015-12-14 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
4 (SIMD_F16): New.
5
63511907
MW		 62015-12-14 Matthew Wahab <matthew.wahab@arm.com>
7
8 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
9 removed statement.
10 (aarch64_pstatefield_supported_p): Move feature checks for AT
11 registers ..
12 (aarch64_sys_ins_reg_supported_p): .. to here.
13
b817670b
AM		 142015-12-12 Alan Modra <amodra@gmail.com>
15
16 PR 19359
17 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
18 (powerpc_opcodes): Remove single-operand mfcr.
19
9ed608f9
MW		 202015-12-11 Matthew Wahab <matthew.wahab@arm.com>
21
22 * aarch64-asm.c (aarch64_ins_hint): New.
23 * aarch64-asm.h (aarch64_ins_hint): Declare.
24 * aarch64-dis.c (aarch64_ext_hint): New.
25 * aarch64-dis.h (aarch64_ext_hint): Declare.
26 * aarch64-opc-2.c: Regenerate.
27 * aarch64-opc.c (aarch64_hint_options): New.
28 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
29
a0f7013a
MW		 302015-12-11 Matthew Wahab <matthew.wahab@arm.com>
31
32 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
33
55c144e6
MW		 342015-12-11 Matthew Wahab <matthew.wahab@arm.com>
35
36 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
37 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
38 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
39 pmscr_el2.
40 (aarch64_sys_reg_supported_p): Add architecture feature tests for
41 the new registers.
42
22a5455c
MW		 432015-12-10 Matthew Wahab <matthew.wahab@arm.com>
44
45 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
46 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
47 feature test for "s1e1rp" and "s1e1wp".
48
d6bf7ce6
MW		 492015-12-10 Matthew Wahab <matthew.wahab@arm.com>
50
51 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
52 (aarch64_sys_ins_reg_supported_p): New.
53
ea2deeec
MW		 542015-12-10 Matthew Wahab <matthew.wahab@arm.com>
55
56 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
57 with aarch64_sys_ins_reg_has_xt.
58 (aarch64_ext_sysins_op): Likewise.
59 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
60 (F_HASXT): New.
61 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
62 (aarch64_sys_regs_dc): Likewise.
63 (aarch64_sys_regs_at): Likewise.
64 (aarch64_sys_regs_tlbi): Likewise.
65 (aarch64_sys_ins_reg_has_xt): New.
66
6479e48e
MW		 672015-12-10 Matthew Wahab <matthew.wahab@arm.com>
68
69 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
70 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
71 (aarch64_pstatefields): Add "uao".
72 (aarch64_pstatefield_supported_p): Add checks for "uao".
73
47f81142
MW		 742015-12-10 Matthew Wahab <matthew.wahab@arm.com>
75
76 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
77 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
78 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
79 (aarch64_sys_reg_supported_p): Add architecture feature tests for
80 new registers.
81
c8a6db6f
MW		 822015-12-10 Matthew Wahab <matthew.wahab@arm.com>
83
84 * aarch64-asm-2.c: Regenerate.
85 * aarch64-dis-2.c: Regenerate.
86 * aarch64-tbl.h (aarch64_feature_ras): New.
87 (RAS): New.
88 (aarch64_opcode_table): Add "esb".
89
8eab4136
L		 902015-12-09 H.J. Lu <hongjiu.lu@intel.com>
91
92 * i386-dis.c (MOD_0F01_REG_5): New.
93 (RM_0F01_REG_5): Likewise.
94 (reg_table): Use MOD_0F01_REG_5.
95 (mod_table): Add MOD_0F01_REG_5.
96 (rm_table): Add RM_0F01_REG_5.
97 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
98 (cpu_flags): Add CpuOSPKE.
99 * i386-opc.h (CpuOSPKE): New.
100 (i386_cpu_flags): Add cpuospke.
101 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
102 * i386-init.h: Regenerated.
103 * i386-tbl.h: Likewise.
104
1eac08cc
DD		 1052015-12-07 DJ Delorie <dj@redhat.com>
106
107 * rl78-decode.opc: Enable MULU for all ISAs.
108 * rl78-decode.c: Regenerate.
109
dd2887fc
AM		 1102015-12-07 Alan Modra <amodra@gmail.com>
111
112 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
113 major opcode/xop.
114
24b368f8
CZ		 1152015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
116
117 * arc-dis.c (special_flag_p): Match full mnemonic.
118 * arc-opc.c (print_insn_arc): Check section size to read
119 appropriate number of bytes. Fix printing.
120 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
121 arguments.
122
3395762e
AV		 1232015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
124
125 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
126 <ldah>: ... to this.
127
622b9eb1
MW		 1282015-11-27 Matthew Wahab <matthew.wahab@arm.com>
129
130 * aarch64-asm-2.c: Regenerate.
131 * aarch64-dis-2.c: Regenerate.
132 * aarch64-opc-2.c: Regenerate.
133 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
134 (QL_INT2FP_H, QL_FP2INT_H): New.
135 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
136 (QL_DST_H): New.
137 (QL_FCCMP_H): New.
138 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
139 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
140 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
141 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
142 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
143 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
144 fcsel.
145
cf86120b
MW		 1462015-11-27 Matthew Wahab <matthew.wahab@arm.com>
147
148 * aarch64-opc.c (half_conv_t): New.
149 (expand_fp_imm): Replace is_dp flag with the parameter size to
150 specify the number of bytes for the required expansion. Treat
151 a 16-bit expansion like a 32-bit expansion. Add check for an
152 unsupported size request. Update comment.
153 (aarch64_print_operand): Update to support 16-bit floating point
154 values. Update for changes to expand_fp_imm.
155
3bd894a7
MW		 1562015-11-27 Matthew Wahab <matthew.wahab@arm.com>
157
158 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
159 (FP_F16): New.
160
64357d2e
MW		 1612015-11-27 Matthew Wahab <matthew.wahab@arm.com>
162
163 * aarch64-asm-2.c: Regenerate.
164 * aarch64-dis-2.c: Regenerate.
165 * aarch64-opc-2.c: Regenerate.
166 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
167 "rev64".
168
d685192a
MW		 1692015-11-27 Matthew Wahab <matthew.wahab@arm.com>
170
171 * aarch64-asm-2.c: Regenerate.
172 * aarch64-asm.c (convert_bfc_to_bfm): New.
173 (convert_to_real): Add case for OP_BFC.
174 * aarch64-dis-2.c: Regenerate.
175 * aarch64-dis.c: (convert_bfm_to_bfc): New.
176 (convert_to_alias): Add case for OP_BFC.
177 * aarch64-opc-2.c: Regenerate.
178 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
179 to allow width operand in three-operand instructions.
180 * aarch64-tbl.h (QL_BF1): New.
181 (aarch64_feature_v8_2): New.
182 (ARMV8_2): New.
183 (aarch64_opcode_table): Add "bfc".
184
35822b38
MW		 1852015-11-27 Matthew Wahab <matthew.wahab@arm.com>
186
187 * aarch64-asm-2.c: Regenerate.
188 * aarch64-dis-2.c: Regenerate.
189 * aarch64-dis.c: Weaken assert.
190 * aarch64-gen.c: Include the instruction in the list of its
191 possible aliases.
192
1a04d1a7
MW		 1932015-11-27 Matthew Wahab <matthew.wahab@arm.com>
194
195 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
196 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
197 feature test.
198
e49d43ff
TG		 1992015-11-23 Tristan Gingold <gingold@adacore.com>
200
201 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
202
250aafa4
MW		 2032015-11-20 Matthew Wahab <matthew.wahab@arm.com>
204
205 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
206 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
207 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
208 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
209 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
210 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
211 cnthv_ctl_el2, cnthv_cval_el2.
212 (aarch64_sys_reg_supported_p): Update for the new system
213 registers.
214
a915c10f
NC		 2152015-11-20 Nick Clifton <nickc@redhat.com>
216
217 PR binutils/19224
218 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
219
f8c2a965
NC		 2202015-11-20 Nick Clifton <nickc@redhat.com>
221
222 * po/zh_CN.po: Updated simplified Chinese translation.
223
c2825638
MW		 2242015-11-19 Matthew Wahab <matthew.wahab@arm.com>
225
226 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
227 of MSR PAN immediate operand.
228
e7286c56
NC		 2292015-11-16 Nick Clifton <nickc@redhat.com>
230
231 * rx-dis.c (condition_names): Replace always and never with
232 invalid, since the always/never conditions can never be legal.
233
d8bd95ef
TG		 2342015-11-13 Tristan Gingold <gingold@adacore.com>
235
236 * configure: Regenerate.
237
a680de9a
PB		 2382015-11-11 Alan Modra <amodra@gmail.com>
239 Peter Bergner <bergner@vnet.ibm.com>
240
241 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
242 Add PPC_OPCODE_VSX3 to the vsx entry.
243 (powerpc_init_dialect): Set default dialect to power9.
244 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
245 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
246 extract_l1 insert_xtq6, extract_xtq6): New static functions.
247 (insert_esync): Test for illegal L operand value.
248 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
249 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
250 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
251 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
252 PPCVSX3): New defines.
253 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
254 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
255 <mcrxr>: Use XBFRARB_MASK.
256 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
257 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
258 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
259 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
260 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
261 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
262 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
263 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
264 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
265 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
266 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
267 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
268 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
269 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
270 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
271 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
272 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
273 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
274 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
275 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
276 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
277 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
278 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
279 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
280 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
281 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
282 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
283 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
284 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
285 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
286 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
287 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
288
854eb72b
NC		 2892015-11-02 Nick Clifton <nickc@redhat.com>
290
291 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
292 instructions.
293 * rx-decode.c: Regenerate.
294
e292aa7a
NC		 2952015-11-02 Nick Clifton <nickc@redhat.com>
296
297 * rx-decode.opc (rx_disp): If the displacement is zero, set the
298 type to RX_Operand_Zero_Indirect.
299 * rx-decode.c: Regenerate.
300 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
301
43cdf5ae
YQ		 3022015-10-28 Yao Qi <yao.qi@linaro.org>
303
304 * aarch64-dis.c (aarch64_decode_insn): Add one argument
305 noaliases_p. Update comments. Pass noaliases_p rather than
306 no_aliases to aarch64_opcode_decode.
307 (print_insn_aarch64_word): Pass no_aliases to
308 aarch64_decode_insn.
309
c2f28758
VK		 3102015-10-27 Vinay <Vinay.G@kpit.com>
311
312 PR binutils/19159
313 * rl78-decode.opc (MOV): Added offset to DE register in index
314 addressing mode.
315 * rl78-decode.c: Regenerate.
316
46662804
VK		 3172015-10-27 Vinay Kumar <vinay.g@kpit.com>
318
319 PR binutils/19158
320 * rl78-decode.opc: Add 's' print operator to instructions that
321 access system registers.
322 * rl78-decode.c: Regenerate.
323 * rl78-dis.c (print_insn_rl78_common): Decode all system
324 registers.
325
02f12cd4
VK		 3262015-10-27 Vinay Kumar <vinay.g@kpit.com>
327
328 PR binutils/19157
329 * rl78-decode.opc: Add 'a' print operator to mov instructions
330 using stack pointer plus index addressing.
331 * rl78-decode.c: Regenerate.
332
485f23cf
AK		 3332015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
334
335 * s390-opc.c: Fix comment.
336 * s390-opc.txt: Change instruction type for troo, trot, trto, and
337 trtt to RRF_U0RER since the second parameter does not need to be a
338 register pair.
339
3f94e60d
NC		 3402015-10-08 Nick Clifton <nickc@redhat.com>
341
342 * arc-dis.c (print_insn_arc): Initiallise insn array.
343
875880c6
YQ		 3442015-10-07 Yao Qi <yao.qi@linaro.org>
345
346 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
347 'name' rather than 'template'.
348 * aarch64-opc.c (aarch64_print_operand): Likewise.
349
886a2506
NC		 3502015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
351
352 * arc-dis.c: Revamped file for ARC support
353 * arc-dis.h: Likewise.
354 * arc-ext.c: Likewise.
355 * arc-ext.h: Likewise.
356 * arc-opc.c: Likewise.
357 * arc-fxi.h: New file.
358 * arc-regs.h: Likewise.
359 * arc-tbl.h: Likewise.
360
36f4aab1
YQ		 3612015-10-02 Yao Qi <yao.qi@linaro.org>
362
363 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
364 argument insn type to aarch64_insn. Rename to ...
365 (aarch64_decode_insn): ... it.
366 (print_insn_aarch64_word): Caller updated.
367
7232d389
YQ		 3682015-10-02 Yao Qi <yao.qi@linaro.org>
369
370 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
371 (print_insn_aarch64_word): Caller updated.
372
7ecc513a
DV		 3732015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
374
375 * s390-mkopc.c (main): Parse htm and vx flag.
376 * s390-opc.txt: Mark instructions from the hardware transactional
377 memory and vector facilities with the "htm"/"vx" flag.
378
b08b78e7
NC		 3792015-09-28 Nick Clifton <nickc@redhat.com>
380
381 * po/de.po: Updated German translation.
382
36f7a941
TR		 3832015-09-28 Tom Rix <tom@bumblecow.com>
384
385 * ppc-opc.c (PPC500): Mark some opcodes as invalid
386
b6518b38
NC		 3872015-09-23 Nick Clifton <nickc@redhat.com>
388
389 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
390 function.
391 * tic30-dis.c (print_branch): Likewise.
392 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
393 value before left shifting.
394 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
395 * hppa-dis.c (print_insn_hppa): Likewise.
396 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
397 array.
398 * msp430-dis.c (msp430_singleoperand): Likewise.
399 (msp430_doubleoperand): Likewise.
400 (print_insn_msp430): Likewise.
401 * nds32-asm.c (parse_operand): Likewise.
402 * sh-opc.h (MASK): Likewise.
403 * v850-dis.c (get_operand_value): Likewise.
404
f04265ec
NC		 4052015-09-22 Nick Clifton <nickc@redhat.com>
406
407 * rx-decode.opc (bwl): Use RX_Bad_Size.
408 (sbwl): Likewise.
409 (ubwl): Likewise. Rename to ubw.
410 (uBWL): Rename to uBW.
411 Replace all references to uBWL with uBW.
412 * rx-decode.c: Regenerate.
413 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
414 (opsize_names): Likewise.
415 (print_insn_rx): Detect and report RX_Bad_Size.
416
6dca4fd1
AB		 4172015-09-22 Anton Blanchard <anton@samba.org>
418
419 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
420
38074311
JM		 4212015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
422
423 * sparc-dis.c (print_insn_sparc): Handle the privileged register
424 %pmcdper.
425
5f40e14d
JS		 4262015-08-24 Jan Stancek <jstancek@redhat.com>
427
428 * i386-dis.c (print_insn): Fix decoding of three byte operands.
429
ab4e4ed5
AF		 4302015-08-21 Alexander Fomin <alexander.fomin@intel.com>
431
432 PR binutils/18257
433 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
434 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
435 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
436 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
437 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
438 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
439 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
440 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
441 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
442 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
443 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
444 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
445 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
446 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
447 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
448 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
449 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
450 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
451 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
452 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
453 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
454 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
455 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
456 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
457 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
458 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
459 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
460 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
461 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
462 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
463 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
464 (vex_w_table): Replace terminals with MOD_TABLE entries for
465 most of mask instructions.
466
919b75f7
AM		 4672015-08-17 Alan Modra <amodra@gmail.com>
468
469 * cgen.sh: Trim trailing space from cgen output.
470 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
471 (print_dis_table): Likewise.
472 * opc2c.c (dump_lines): Likewise.
473 (orig_filename): Warning fix.
474 * ia64-asmtab.c: Regenerate.
475
4ab90a7a
AV		 4762015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
477
478 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
479 and higher with ARM instruction set will now mark the 26-bit
480 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
481 (arm_opcodes): Fix for unpredictable nop being recognized as a
482 teq.
483
40fc1451
SD		 4842015-08-12 Simon Dardis <simon.dardis@imgtec.com>
485
486 * micromips-opc.c (micromips_opcodes): Re-order table so that move
487 based on 'or' is first.
488 * mips-opc.c (mips_builtin_opcodes): Ditto.
489
922c5db5
NC		 4902015-08-11 Nick Clifton <nickc@redhat.com>
491
492 PR 18800
493 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
494 instruction.
495
75fb7498
RS		 4962015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
497
498 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
499
36aed29d
AP		 5002015-08-07 Amit Pawar <Amit.Pawar@amd.com>
501
502 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
503 * i386-init.h: Regenerated.
504
a8484f96
L		 5052015-07-30 H.J. Lu <hongjiu.lu@intel.com>
506
507 PR binutils/13571
508 * i386-dis.c (MOD_0FC3): New.
509 (PREFIX_0FC3): Renamed to ...
510 (PREFIX_MOD_0_0FC3): This.
511 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
512 (prefix_table): Replace Ma with Ev on movntiS.
513 (mod_table): Add MOD_0FC3.
514
37a42ee9
L		 5152015-07-27 H.J. Lu <hongjiu.lu@intel.com>
516
517 * configure: Regenerated.
518
070fe95d
AM		 5192015-07-23 Alan Modra <amodra@gmail.com>
520
521 PR 18708
522 * i386-dis.c (get64): Avoid signed integer overflow.
523
20c2a615
L		 5242015-07-22 Alexander Fomin <alexander.fomin@intel.com>
525
526 PR binutils/18631
527 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
528 "EXEvexHalfBcstXmmq" for the second operand.
529 (EVEX_W_0F79_P_2): Likewise.
530 (EVEX_W_0F7A_P_2): Likewise.
531 (EVEX_W_0F7B_P_2): Likewise.
532
6f1c2142
AM		 5332015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
534
535 * arm-dis.c (print_insn_coprocessor): Added support for quarter
536 float bitfield format.
537 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
538 quarter float bitfield format.
539
8a643cc3
L		 5402015-07-14 H.J. Lu <hongjiu.lu@intel.com>
541
542 * configure: Regenerated.
543
ef5a96d5
AM		 5442015-07-03 Alan Modra <amodra@gmail.com>
545
546 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
547 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
548 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
549
c8c8175b
SL		 5502015-07-01 Sandra Loosemore <sandra@codesourcery.com>
551 Cesar Philippidis <cesar@codesourcery.com>
552
553 * nios2-dis.c (nios2_extract_opcode): New.
554 (nios2_disassembler_state): New.
555 (nios2_find_opcode_hash): Use mach parameter to select correct
556 disassembler state.
557 (nios2_print_insn_arg): Extend to support new R2 argument letters
558 and formats.
559 (print_insn_nios2): Check for 16-bit instruction at end of memory.
560 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
561 (NIOS2_NUM_OPCODES): Rename to...
562 (NIOS2_NUM_R1_OPCODES): This.
563 (nios2_r2_opcodes): New.
564 (NIOS2_NUM_R2_OPCODES): New.
565 (nios2_num_r2_opcodes): New.
566 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
567 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
568 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
569 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
570 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
571
9916071f
AP		 5722015-06-30 Amit Pawar <Amit.Pawar@amd.com>
573
574 * i386-dis.c (OP_Mwaitx): New.
575 (rm_table): Add monitorx/mwaitx.
576 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
577 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
578 (operand_type_init): Add CpuMWAITX.
579 * i386-opc.h (CpuMWAITX): New.
580 (i386_cpu_flags): Add cpumwaitx.
581 * i386-opc.tbl: Add monitorx and mwaitx.
582 * i386-init.h: Regenerated.
583 * i386-tbl.h: Likewise.
584
7b934113
PB		 5852015-06-22 Peter Bergner <bergner@vnet.ibm.com>
586
587 * ppc-opc.c (insert_ls): Test for invalid LS operands.
588 (insert_esync): New function.
589 (LS, WC): Use insert_ls.
590 (ESYNC): Use insert_esync.
591
bdc4de1b
NC		 5922015-06-22 Nick Clifton <nickc@redhat.com>
593
594 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
595 requested region lies beyond it.
596 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
597 looking for 32-bit insns.
598 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
599 data.
600 * sh-dis.c (print_insn_sh): Likewise.
601 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
602 blocks of instructions.
603 * vax-dis.c (print_insn_vax): Check that the requested address
604 does not clash with the stop_vma.
605
11a0cf2e
PB		 6062015-06-19 Peter Bergner <bergner@vnet.ibm.com>
607
070fe95d 608 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 609 * ppc-opc.c (FXM4): Add non-zero optional value.
610 (TBR): Likewise.
611 (SXL): Likewise.
612 (insert_fxm): Handle new default operand value.
613 (extract_fxm): Likewise.
614 (insert_tbr): Likewise.
615 (extract_tbr): Likewise.
616
bdfa8b95
MW		 6172015-06-16 Matthew Wahab <matthew.wahab@arm.com>
618
619 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
620
24b4cf66
SN		 6212015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
622
623 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
624
99a2c561
PB		 6252015-06-12 Peter Bergner <bergner@vnet.ibm.com>
626
627 * ppc-opc.c: Add comment accidentally removed by old commit.
628 (MTMSRD_L): Delete.
629
40f77f82
AM		 6302015-06-04 Peter Bergner <bergner@vnet.ibm.com>
631
632 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
633
13be46a2
NC		 6342015-06-04 Nick Clifton <nickc@redhat.com>
635
636 PR 18474
637 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
638
ddfded2f
MW		 6392015-06-02 Matthew Wahab <matthew.wahab@arm.com>
640
641 * arm-dis.c (arm_opcodes): Add "setpan".
642 (thumb_opcodes): Add "setpan".
643
1af1dd51
MW		 6442015-06-02 Matthew Wahab <matthew.wahab@arm.com>
645
646 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
647 macros.
648
9e1f0fa7
MW		 6492015-06-02 Matthew Wahab <matthew.wahab@arm.com>
650
651 * aarch64-tbl.h (aarch64_feature_rdma): New.
652 (RDMA): New.
653 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
654 * aarch64-asm-2.c: Regenerate.
655 * aarch64-dis-2.c: Regenerate.
656 * aarch64-opc-2.c: Regenerate.
657
290806fd
MW		 6582015-06-02 Matthew Wahab <matthew.wahab@arm.com>
659
660 * aarch64-tbl.h (aarch64_feature_lor): New.
661 (LOR): New.
662 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
663 "stllrb", "stllrh".
664 * aarch64-asm-2.c: Regenerate.
665 * aarch64-dis-2.c: Regenerate.
666 * aarch64-opc-2.c: Regenerate.
667
f21cce2c
MW		 6682015-06-01 Matthew Wahab <matthew.wahab@arm.com>
669
670 * aarch64-opc.c (F_ARCHEXT): New.
671 (aarch64_sys_regs): Add "pan".
672 (aarch64_sys_reg_supported_p): New.
673 (aarch64_pstatefields): Add "pan".
674 (aarch64_pstatefield_supported_p): New.
675
d194d186
JB		 6762015-06-01 Jan Beulich <jbeulich@suse.com>
677
678 * i386-tbl.h: Regenerate.
679
3a8547d2
JB		 6802015-06-01 Jan Beulich <jbeulich@suse.com>
681
682 * i386-dis.c (print_insn): Swap rounding mode specifier and
683 general purpose register in Intel mode.
684
015c54d5
JB		 6852015-06-01 Jan Beulich <jbeulich@suse.com>
686
687 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
688 * i386-tbl.h: Regenerate.
689
071f0063
L		 6902015-05-18 H.J. Lu <hongjiu.lu@intel.com>
691
692 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
693 * i386-init.h: Regenerated.
694
5db04b09
L		 6952015-05-15 H.J. Lu <hongjiu.lu@intel.com>
696
697 PR binutis/18386
698 * i386-dis.c: Add comments for '@'.
699 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
700 (enum x86_64_isa): New.
701 (isa64): Likewise.
702 (print_i386_disassembler_options): Add amd64 and intel64.
703 (print_insn): Handle amd64 and intel64.
704 (putop): Handle '@'.
705 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
706 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
707 * i386-opc.h (AMD64): New.
708 (CpuIntel64): Likewise.
709 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
710 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
711 Mark direct call/jmp without Disp16|Disp32 as Intel64.
712 * i386-init.h: Regenerated.
713 * i386-tbl.h: Likewise.
714
4bc0608a
PB		 7152015-05-14 Peter Bergner <bergner@vnet.ibm.com>
716
717 * ppc-opc.c (IH) New define.
718 (powerpc_opcodes) <wait>: Do not enable for POWER7.
719 <tlbie>: Add RS operand for POWER7.
720 <slbia>: Add IH operand for POWER6.
721
70cead07
L		 7222015-05-11 H.J. Lu <hongjiu.lu@intel.com>
723
724 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
725 direct branch.
726 (jmp): Likewise.
727 * i386-tbl.h: Regenerated.
728
7b6d09fb
L		 7292015-05-11 H.J. Lu <hongjiu.lu@intel.com>
730
731 * configure.ac: Support bfd_iamcu_arch.
732 * disassemble.c (disassembler): Support bfd_iamcu_arch.
733 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
734 CPU_IAMCU_COMPAT_FLAGS.
735 (cpu_flags): Add CpuIAMCU.
736 * i386-opc.h (CpuIAMCU): New.
737 (i386_cpu_flags): Add cpuiamcu.
738 * configure: Regenerated.
739 * i386-init.h: Likewise.
740 * i386-tbl.h: Likewise.
741
31955f99
L		 7422015-05-08 H.J. Lu <hongjiu.lu@intel.com>
743
744 PR binutis/18386
745 * i386-dis.c (X86_64_E8): New.
746 (X86_64_E9): Likewise.
747 Update comments on 'T', 'U', 'V'. Add comments for '^'.
748 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
749 (x86_64_table): Add X86_64_E8 and X86_64_E9.
750 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
751 (putop): Handle '^'.
752 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
753 REX_W.
754
0952813b
DD		 7552015-04-30 DJ Delorie <dj@redhat.com>
756
757 * disassemble.c (disassembler): Choose suitable disassembler based
758 on E_ABI.
759 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
760 it to decode mul/div insns.
761 * rl78-decode.c: Regenerate.
762 * rl78-dis.c (print_insn_rl78): Rename to...
763 (print_insn_rl78_common): ...this, take ISA parameter.
764 (print_insn_rl78): New.
765 (print_insn_rl78_g10): New.
766 (print_insn_rl78_g13): New.
767 (print_insn_rl78_g14): New.
768 (rl78_get_disassembler): New.
769
f9d3ecaa
NC		 7702015-04-29 Nick Clifton <nickc@redhat.com>
771
772 * po/fr.po: Updated French translation.
773
4fff86c5
PB		 7742015-04-27 Peter Bergner <bergner@vnet.ibm.com>
775
776 * ppc-opc.c (DCBT_EO): New define.
777 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
778 <lharx>: Likewise.
779 <stbcx.>: Likewise.
780 <sthcx.>: Likewise.
781 <waitrsv>: Do not enable for POWER7 and later.
782 <waitimpl>: Likewise.
783 <dcbt>: Default to the two operand form of the instruction for all
784 "old" cpus. For "new" cpus, use the operand ordering that matches
785 whether the cpu is server or embedded.
786 <dcbtst>: Likewise.
787
3b78cfe1
AK		 7882015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
789
790 * s390-opc.c: New instruction type VV0UU2.
791 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
792 and WFC.
793
04d824a4
JB		 7942015-04-23 Jan Beulich <jbeulich@suse.com>
795
796 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
797 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
798 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
799 (vfpclasspd, vfpclassps): Add %XZ.
800
09708981
L		 8012015-04-15 H.J. Lu <hongjiu.lu@intel.com>
802
803 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
804 (PREFIX_UD_REPZ): Likewise.
805 (PREFIX_UD_REPNZ): Likewise.
806 (PREFIX_UD_DATA): Likewise.
807 (PREFIX_UD_ADDR): Likewise.
808 (PREFIX_UD_LOCK): Likewise.
809
3888916d
L		 8102015-04-15 H.J. Lu <hongjiu.lu@intel.com>
811
812 * i386-dis.c (prefix_requirement): Removed.
813 (print_insn): Don't set prefix_requirement. Check
814 dp->prefix_requirement instead of prefix_requirement.
815
f24bcbaa
L		 8162015-04-15 H.J. Lu <hongjiu.lu@intel.com>
817
818 PR binutils/17898
819 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
820 (PREFIX_MOD_0_0FC7_REG_6): This.
821 (PREFIX_MOD_3_0FC7_REG_6): New.
822 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
823 (prefix_table): Replace PREFIX_0FC7_REG_6 with
824 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
825 PREFIX_MOD_3_0FC7_REG_7.
826 (mod_table): Replace PREFIX_0FC7_REG_6 with
827 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
828 PREFIX_MOD_3_0FC7_REG_7.
829
507bd325
L		 8302015-04-15 H.J. Lu <hongjiu.lu@intel.com>
831
832 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
833 (PREFIX_MANDATORY_REPNZ): Likewise.
834 (PREFIX_MANDATORY_DATA): Likewise.
835 (PREFIX_MANDATORY_ADDR): Likewise.
836 (PREFIX_MANDATORY_LOCK): Likewise.
837 (PREFIX_MANDATORY): Likewise.
838 (PREFIX_UD_SHIFT): Set to 8
839 (PREFIX_UD_REPZ): Updated.
840 (PREFIX_UD_REPNZ): Likewise.
841 (PREFIX_UD_DATA): Likewise.
842 (PREFIX_UD_ADDR): Likewise.
843 (PREFIX_UD_LOCK): Likewise.
844 (PREFIX_IGNORED_SHIFT): New.
845 (PREFIX_IGNORED_REPZ): Likewise.
846 (PREFIX_IGNORED_REPNZ): Likewise.
847 (PREFIX_IGNORED_DATA): Likewise.
848 (PREFIX_IGNORED_ADDR): Likewise.
849 (PREFIX_IGNORED_LOCK): Likewise.
850 (PREFIX_OPCODE): Likewise.
851 (PREFIX_IGNORED): Likewise.
852 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
853 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
854 (three_byte_table): Likewise.
855 (mod_table): Likewise.
856 (mandatory_prefix): Renamed to ...
857 (prefix_requirement): This.
858 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
859 Update PREFIX_90 entry.
860 (get_valid_dis386): Check prefix_requirement to see if a prefix
861 should be ignored.
862 (print_insn): Replace mandatory_prefix with prefix_requirement.
863
f0fba320
RL		 8642015-04-15 Renlin Li <renlin.li@arm.com>
865
866 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
867 use it for ssat and ssat16.
868 (print_insn_thumb32): Add handle case for 'D' control code.
869
bf890a93
IT		 8702015-04-06 Ilya Tocar <ilya.tocar@intel.com>
871 H.J. Lu <hongjiu.lu@intel.com>
872
873 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
874 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
875 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
876 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
877 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
878 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
879 Fill prefix_requirement field.
880 (struct dis386): Add prefix_requirement field.
881 (dis386): Fill prefix_requirement field.
882 (dis386_twobyte): Ditto.
883 (twobyte_has_mandatory_prefix_: Remove.
884 (reg_table): Fill prefix_requirement field.
885 (prefix_table): Ditto.
886 (x86_64_table): Ditto.
887 (three_byte_table): Ditto.
888 (xop_table): Ditto.
889 (vex_table): Ditto.
890 (vex_len_table): Ditto.
891 (vex_w_table): Ditto.
892 (mod_table): Ditto.
893 (bad_opcode): Ditto.
894 (print_insn): Use prefix_requirement.
895 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
896 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
897 (float_reg): Ditto.
898
2f783c1f
MF		 8992015-03-30 Mike Frysinger <vapier@gentoo.org>
900
901 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
902
b9d94d62
L		 9032015-03-29 H.J. Lu <hongjiu.lu@intel.com>
904
905 * Makefile.in: Regenerated.
906
27c49e9a
AB		 9072015-03-25 Anton Blanchard <anton@samba.org>
908
909 * ppc-dis.c (disassemble_init_powerpc): Only initialise
910 powerpc_opcd_indices and vle_opcd_indices once.
911
c4e676f1
AB		 9122015-03-25 Anton Blanchard <anton@samba.org>
913
914 * ppc-opc.c (powerpc_opcodes): Add slbfee.
915
823d2571
TG		 9162015-03-24 Terry Guo <terry.guo@arm.com>
917
918 * arm-dis.c (opcode32): Updated to use new arm feature struct.
919 (opcode16): Likewise.
920 (coprocessor_opcodes): Replace bit with feature struct.
921 (neon_opcodes): Likewise.
922 (arm_opcodes): Likewise.
923 (thumb_opcodes): Likewise.
924 (thumb32_opcodes): Likewise.
925 (print_insn_coprocessor): Likewise.
926 (print_insn_arm): Likewise.
927 (select_arm_features): Follow new feature struct.
928
029f3522
GG		 9292015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
930
931 * i386-dis.c (rm_table): Add clzero.
932 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
933 Add CPU_CLZERO_FLAGS.
934 (cpu_flags): Add CpuCLZERO.
935 * i386-opc.h: Add CpuCLZERO.
936 * i386-opc.tbl: Add clzero.
937 * i386-init.h: Re-generated.
938 * i386-tbl.h: Re-generated.
939
6914869a
AB		 9402015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
941
942 * mips-opc.c (decode_mips_operand): Fix constraint issues
943 with u and y operands.
944
21e20815
AB		 9452015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
946
947 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
948
6b1d7593
AK		 9492015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
950
951 * s390-opc.c: Add new IBM z13 instructions.
952 * s390-opc.txt: Likewise.
953
c8f89a34
JW		 9542015-03-10 Renlin Li <renlin.li@arm.com>
955
956 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
957 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
958 related alias.
959 * aarch64-asm-2.c: Regenerate.
960 * aarch64-dis-2.c: Likewise.
961 * aarch64-opc-2.c: Likewise.
962
d8282f0e
JW		 9632015-03-03 Jiong Wang <jiong.wang@arm.com>
964
965 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
966
ac994365
OE		 9672015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
968
969 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
970 arch_sh_up.
971 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
972 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
973
fd63f640
V		 9742015-02-23 Vinay <Vinay.G@kpit.com>
975
976 * rl78-decode.opc (MOV): Added space between two operands for
977 'mov' instruction in index addressing mode.
978 * rl78-decode.c: Regenerate.
979
f63c1776
PA		 9802015-02-19 Pedro Alves <palves@redhat.com>
981
982 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
983
07774fcc
PA		 9842015-02-10 Pedro Alves <palves@redhat.com>
985 Tom Tromey <tromey@redhat.com>
986
987 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
988 microblaze_and, microblaze_xor.
989 * microblaze-opc.h (opcodes): Adjust.
990
3f8107ab
AM		 9912015-01-28 James Bowman <james.bowman@ftdichip.com>
992
993 * Makefile.am: Add FT32 files.
994 * configure.ac: Handle FT32.
995 * disassemble.c (disassembler): Call print_insn_ft32.
996 * ft32-dis.c: New file.
997 * ft32-opc.c: New file.
998 * Makefile.in: Regenerate.
999 * configure: Regenerate.
1000 * po/POTFILES.in: Regenerate.
1001
e5fe4957
KLC		 10022015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1003
1004 * nds32-asm.c (keyword_sr): Add new system registers.
1005
1e2e8c52
AK		 10062015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1007
1008 * s390-dis.c (s390_extract_operand): Support vector register
1009 operands.
1010 (s390_print_insn_with_opcode): Support new operands types and add
1011 new handling of optional operands.
1012 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1013 and include opcode/s390.h instead.
1014 (struct op_struct): New field `flags'.
1015 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1016 (dumpTable): Dump flags.
1017 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1018 string.
1019 * s390-opc.c: Add new operands types, instruction formats, and
1020 instruction masks.
1021 (s390_opformats): Add new formats for .insn.
1022 * s390-opc.txt: Add new instructions.
1023
b90efa5b 10242015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 1025
b90efa5b 1026 Update year range in copyright notice of all files.
bffb6004 1027
b90efa5b 1028For older changes see ChangeLog-2014
252b5132 1029\f
b90efa5b 1030Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 1031
1032Copying and distribution of this file, with or without modification,
1033are permitted in any medium without royalty provided the copyright
1034notice and this notice are preserved.
1035
252b5132 1036Local Variables:
2f6d2f85
NC		 1037mode: change-log
1038left-margin: 8
1039fill-column: 74
252b5132
RH		 1040version-control: never
1041End:
GDB Binutils - Deliverables
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