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2013-09-04 Muhammad Bilal <mbilal@codesourcery.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c8094e01
AK		 12013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
2
3 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
4 For the load fp integer instructions only the suppression flag was
5 new with z196 version.
6
7e105031
NC		 72013-08-28 Nick Clifton <nickc@redhat.com>
8
9 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
10 immediate is not suitable for the 32-bit ABI.
11
fb6f3895
MR		 122013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
13
14 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
15 replacing NODS.
16
9aff4b7a
NC		 172013-08-23 Yuri Chornoivan <yurchor@ukr.net>
18
19 PR binutils/15834
20 * aarch64-asm.c: Fix typos.
21 * aarch64-dis.c: Likewise.
22 * msp430-dis.c: Likewise.
23
5e0dc5ba
RS		 242013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
25
26 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
27 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
28 Use +H rather than +C for the real "dext".
29 * mips-opc.c (mips_builtin_opcodes): Likewise.
30
0f35dbc4
RS		 312013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
32
33 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
34 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
35 and OPTIONAL_MAPPED_REG.
36 * mips-opc.c (decode_mips_operand): Likewise.
37 * mips16-opc.c (decode_mips16_operand): Likewise.
38 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
39
79ceb7cb
L		 402013-08-19 H.J. Lu <hongjiu.lu@intel.com>
41
42 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
43 (PREFIX_EVEX_0F3A3F): Likewise.
44 * i386-dis-evex.h (evex_table): Updated.
45
ee5734f0
RS		 462013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
47
48 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
49 VCLIPW.
50
d6787ef9
EB		 512013-08-05 Eric Botcazou <ebotcazou@adacore.com>
52 Konrad Eisele <konrad@gaisler.com>
53
54 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
55 bfd_mach_sparc.
56 * sparc-opc.c (MASK_LEON): Define.
57 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
58 (letandleon): New macro.
59 (v9andleon): Likewise.
60 (sparc_opc): Add leon.
61 (umac): Enable for letandleon.
62 (smac): Likewise.
63 (casa): Enable for v9andleon.
64 (cas): Likewise.
65 (casl): Likewise.
66
14daeee3
RS		 672013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
68 Richard Sandiford <rdsandiford@googlemail.com>
69
70 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
71 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
72 (print_vu0_channel): New function.
73 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
74 (print_insn_args): Handle '#'.
75 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
76 * mips-opc.c (mips_vu0_channel_mask): New constant.
77 (decode_mips_operand): Handle new VU0 operand types.
78 (VU0, VU0CH): New macros.
79 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
80 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
81 Use "+6" rather than "G" for QMFC2 and QMTC2.
82
3ccad066
RS		 832013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
84
85 * mips-formats.h (PCREL): Reorder parameters and update the definition
86 to match new mips_pcrel_operand layout.
87 (JUMP, JALX, BRANCH): Update accordingly.
88 * mips16-opc.c (decode_mips16_operand): Likewise.
89
df34fbcc
RS		 902013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
91
92 * micromips-opc.c (WR_s): Delete.
93
fc76e730
RS		 942013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
95
96 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
97 New macros.
98 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
99 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
100 (mips_builtin_opcodes): Use the new position-based read-write flags
101 instead of field-based ones. Use UDI for "udi..." instructions.
102 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
103 New macros.
104 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
105 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
106 (WR_SP, RD_16): New macros.
107 (RD_SP): Redefine as an INSN2_* flag.
108 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
109 (mips16_opcodes): Use the new position-based read-write flags
110 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
111 pinfo2 field.
112 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
113 New macros.
114 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
115 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
116 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
117 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
118 (micromips_opcodes): Use the new position-based read-write flags
119 instead of field-based ones.
120 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
121 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
122 of field-based flags.
123
26545944
RS		 1242013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
125
126 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
127 (WR_SP): Replace with...
128 (MOD_SP): ...this.
129 (mips16_opcodes): Update accordingly.
130 * mips-dis.c (print_insn_mips16): Likewise.
131
a8d92fc6
RS		 1322013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
133
134 * mips16-opc.c (mips16_opcodes): Reformat.
135
6a819047
RS		 1362013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
137
138 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
139 for operands that are hard-coded to $0.
140 * micromips-opc.c (micromips_opcodes): Likewise.
141
344c74a6
RS		 1422013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
143
144 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
145 for the single-operand forms of JALR and JALR.HB.
146 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
147 and JALRS.HB.
148
41989114
RS		 1492013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
150
151 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
152 instructions. Fix them to use WR_MACC instead of WR_CC and
153 add missing RD_MACCs.
154
6d075bce
RS		 1552013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
156
157 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
158
4f6ffcd3
PB		 1592013-07-29 Peter Bergner <bergner@vnet.ibm.com>
160
161 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
162
43234a1e
L		 1632013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
164 Alexander Ivchenko <alexander.ivchenko@intel.com>
165 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
166 Sergey Lega <sergey.s.lega@intel.com>
167 Anna Tikhonova <anna.tikhonova@intel.com>
168 Ilya Tocar <ilya.tocar@intel.com>
169 Andrey Turetskiy <andrey.turetskiy@intel.com>
170 Ilya Verbin <ilya.verbin@intel.com>
171 Kirill Yukhin <kirill.yukhin@intel.com>
172 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
173
174 * i386-dis-evex.h: New.
175 * i386-dis.c (OP_Rounding): New.
176 (VPCMP_Fixup): New.
177 (OP_Mask): New.
178 (Rdq): New.
179 (XMxmmq): New.
180 (EXdScalarS): New.
181 (EXymm): New.
182 (EXEvexHalfBcstXmmq): New.
183 (EXxmm_mdq): New.
184 (EXEvexXGscat): New.
185 (EXEvexXNoBcst): New.
186 (VPCMP): New.
187 (EXxEVexR): New.
188 (EXxEVexS): New.
189 (XMask): New.
190 (MaskG): New.
191 (MaskE): New.
192 (MaskR): New.
193 (MaskVex): New.
194 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
195 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
196 evex_rounding_mode, evex_sae_mode, mask_mode.
197 (USE_EVEX_TABLE): New.
198 (EVEX_TABLE): New.
199 (EVEX enum): New.
200 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
201 REG_EVEX_0F38C7.
202 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
203 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
204 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
205 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
206 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
207 MOD_EVEX_0F38C7_REG_6.
208 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
209 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
210 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
211 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
212 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
213 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
214 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
215 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
216 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
217 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
218 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
219 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
220 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
221 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
222 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
223 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
224 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
225 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
226 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
227 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
228 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
229 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
230 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
231 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
232 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
233 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
234 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
235 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
236 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
237 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
238 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
239 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
240 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
241 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
242 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
243 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
244 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
245 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
246 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
247 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
248 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
249 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
250 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
251 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
252 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
253 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
254 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
255 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
256 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
257 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
258 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
259 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
260 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
261 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
262 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
263 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
264 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
265 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
266 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
267 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
268 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
269 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
270 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
271 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
272 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
273 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
274 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
275 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
276 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
277 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
278 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
279 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
280 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
281 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
282 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
283 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
284 PREFIX_EVEX_0F3A55.
285 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
286 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
287 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
288 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
289 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
290 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
291 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
292 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
293 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
294 VEX_W_0F3A32_P_2_LEN_0.
295 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
296 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
297 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
298 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
299 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
300 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
301 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
302 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
303 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
304 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
305 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
306 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
307 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
308 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
309 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
310 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
311 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
312 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
313 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
314 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
315 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
316 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
317 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
318 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
319 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
320 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
321 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
322 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
323 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
324 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
325 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
326 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
327 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
328 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
329 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
330 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
331 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
332 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
333 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
334 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
335 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
336 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
337 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
338 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
339 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
340 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
341 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
342 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
343 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
344 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
345 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
346 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
347 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
348 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
349 (struct vex): Add fields evex, r, v, mask_register_specifier,
350 zeroing, ll, b.
351 (intel_names_xmm): Add upper 16 registers.
352 (att_names_xmm): Ditto.
353 (intel_names_ymm): Ditto.
354 (att_names_ymm): Ditto.
355 (names_zmm): New.
356 (intel_names_zmm): Ditto.
357 (att_names_zmm): Ditto.
358 (names_mask): Ditto.
359 (intel_names_mask): Ditto.
360 (att_names_mask): Ditto.
361 (names_rounding): Ditto.
362 (names_broadcast): Ditto.
363 (x86_64_table): Add escape to evex-table.
364 (reg_table): Include reg_table evex-entries from
365 i386-dis-evex.h. Fix prefetchwt1 instruction.
366 (prefix_table): Add entries for new instructions.
367 (vex_table): Ditto.
368 (vex_len_table): Ditto.
369 (vex_w_table): Ditto.
370 (mod_table): Ditto.
371 (get_valid_dis386): Properly handle new instructions.
372 (print_insn): Handle zmm and mask registers, print mask operand.
373 (intel_operand_size): Support EVEX, new modes and sizes.
374 (OP_E_register): Handle new modes.
375 (OP_E_memory): Ditto.
376 (OP_G): Ditto.
377 (OP_XMM): Ditto.
378 (OP_EX): Ditto.
379 (OP_VEX): Ditto.
380 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
381 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
382 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
383 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
384 CpuAVX512PF and CpuVREX.
385 (operand_type_init): Add OPERAND_TYPE_REGZMM,
386 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
387 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
388 StaticRounding, SAE, Disp8MemShift, NoDefMask.
389 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
390 * i386-init.h: Regenerate.
391 * i386-opc.h (CpuAVX512F): New.
392 (CpuAVX512CD): New.
393 (CpuAVX512ER): New.
394 (CpuAVX512PF): New.
395 (CpuVREX): New.
396 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
397 cpuavx512pf and cpuvrex fields.
398 (VecSIB): Add VecSIB512.
399 (EVex): New.
400 (Masking): New.
401 (VecESize): New.
402 (Broadcast): New.
403 (StaticRounding): New.
404 (SAE): New.
405 (Disp8MemShift): New.
406 (NoDefMask): New.
407 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
408 staticrounding, sae, disp8memshift and nodefmask.
409 (RegZMM): New.
410 (Zmmword): Ditto.
411 (Vec_Disp8): Ditto.
412 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
413 fields.
414 (RegVRex): New.
415 * i386-opc.tbl: Add AVX512 instructions.
416 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
417 registers, mask registers.
418 * i386-tbl.h: Regenerate.
419
1d2db237
RS		 4202013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
421
422 PR gas/15220
423 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
424 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
425
a0046408
L		 4262013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
427
428 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
429 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
430 PREFIX_0F3ACC.
431 (prefix_table): Updated.
432 (three_byte_table): Likewise.
433 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
434 (cpu_flags): Add CpuSHA.
435 (i386_cpu_flags): Add cpusha.
436 * i386-init.h: Regenerate.
437 * i386-opc.h (CpuSHA): New.
438 (CpuUnused): Restored.
439 (i386_cpu_flags): Add cpusha.
440 * i386-opc.tbl: Add SHA instructions.
441 * i386-tbl.h: Regenerate.
442
7e8b059b
L		 4432013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
444 Kirill Yukhin <kirill.yukhin@intel.com>
445 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
446
447 * i386-dis.c (BND_Fixup): New.
448 (Ebnd): New.
449 (Ev_bnd): New.
450 (Gbnd): New.
451 (BND): New.
452 (v_bnd_mode): New.
453 (bnd_mode): New.
c623f86c
L		 454 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
455 MOD_0F1B_PREFIX_1.
456 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 457 (dis tables): Replace XX with BND for near branch and call
458 instructions.
459 (prefix_table): Add new entries.
460 (mod_table): Likewise.
461 (names_bnd): New.
462 (intel_names_bnd): New.
463 (att_names_bnd): New.
464 (BND_PREFIX): New.
465 (prefix_name): Handle BND_PREFIX.
466 (print_insn): Initialize names_bnd.
467 (intel_operand_size): Handle new modes.
468 (OP_E_register): Likewise.
469 (OP_E_memory): Likewise.
470 (OP_G): Likewise.
471 * i386-gen.c (cpu_flag_init): Add CpuMPX.
472 (cpu_flags): Add CpuMPX.
473 (operand_type_init): Add RegBND.
474 (opcode_modifiers): Add BNDPrefixOk.
475 (operand_types): Add RegBND.
476 * i386-init.h: Regenerate.
477 * i386-opc.h (CpuMPX): New.
478 (CpuUnused): Comment out.
479 (i386_cpu_flags): Add cpumpx.
480 (BNDPrefixOk): New.
481 (i386_opcode_modifier): Add bndprefixok.
482 (RegBND): New.
483 (i386_operand_type): Add regbnd.
484 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
485 Add MPX instructions and bnd prefix.
486 * i386-reg.tbl: Add bnd0-bnd3 registers.
487 * i386-tbl.h: Regenerate.
488
b56e23fb
RS		 4892013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
490
491 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
492 ATTRIBUTE_UNUSED.
493
e7ae278d
RS		 4942013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
495
496 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
497 special rules.
498 * Makefile.in: Regenerate.
499 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
500 all fields. Reformat.
501
c3c07478
RS		 5022013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
503
504 * mips16-opc.c: Include mips-formats.h.
505 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
506 static arrays.
507 (decode_mips16_operand): New function.
508 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
509 (print_insn_arg): Handle OP_ENTRY_EXIT list.
510 Abort for OP_SAVE_RESTORE_LIST.
511 (print_mips16_insn_arg): Change interface. Use mips_operand
512 structures. Delete GET_OP_S. Move GET_OP definition to...
513 (print_insn_mips16): ...here. Call init_print_arg_state.
514 Update the call to print_mips16_insn_arg.
515
ab902481
RS		 5162013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
517
518 * mips-formats.h: New file.
519 * mips-opc.c: Include mips-formats.h.
520 (reg_0_map): New static array.
521 (decode_mips_operand): New function.
522 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
523 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
524 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
525 (int_c_map): New static arrays.
526 (decode_micromips_operand): New function.
527 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
528 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
529 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
530 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
531 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
532 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
533 (micromips_imm_b_map, micromips_imm_c_map): Delete.
534 (print_reg): New function.
535 (mips_print_arg_state): New structure.
536 (init_print_arg_state, print_insn_arg): New functions.
537 (print_insn_args): Change interface and use mips_operand structures.
538 Delete GET_OP_S. Move GET_OP definition to...
539 (print_insn_mips): ...here. Update the call to print_insn_args.
540 (print_insn_micromips): Use print_insn_args.
541
cc537e56
RS		 5422013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
543
544 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
545 in macros.
546
7a5f87ce
RS		 5472013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
548
549 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
550 ADDA.S, MULA.S and SUBA.S.
551
41741fa4
L		 5522013-07-08 H.J. Lu <hongjiu.lu@intel.com>
553
554 PR gas/13572
555 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
556 * i386-tbl.h: Regenerated.
557
f2ae14a1
RS		 5582013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
559
560 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
561 and SD A(B) macros up.
562 * micromips-opc.c (micromips_opcodes): Likewise.
563
04c9d415
RS		 5642013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
565
566 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
567 instructions.
568
5c324c16
RS		 5692013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
570
571 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
572 MDMX-like instructions.
573 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
574 printing "Q" operands for INSN_5400 instructions.
575
23e69e47
RS		 5762013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
577
578 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
579 "+S" for "cins".
580 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
581 Combine cases.
582
27c5c572
RS		 5832013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
584
585 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
586 "jalx".
587 * mips16-opc.c (mips16_opcodes): Likewise.
588 * micromips-opc.c (micromips_opcodes): Likewise.
589 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
590 (print_insn_mips16): Handle "+i".
591 (print_insn_micromips): Likewise. Conditionally preserve the
592 ISA bit for "a" but not for "+i".
593
e76ff5ab
RS		 5942013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
595
596 * micromips-opc.c (WR_mhi): Rename to..
597 (WR_mh): ...this.
598 (micromips_opcodes): Update "movep" entry accordingly. Replace
599 "mh,mi" with "mh".
600 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
601 (micromips_to_32_reg_h_map1): ...this.
602 (micromips_to_32_reg_i_map): Rename to...
603 (micromips_to_32_reg_h_map2): ...this.
604 (print_micromips_insn): Remove "mi" case. Print both registers
605 in the pair for "mh".
606
fa7616a4
RS		 6072013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
608
609 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
610 * micromips-opc.c (micromips_opcodes): Likewise.
611 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
612 and "+T" handling. Check for a "0" suffix when deciding whether to
613 use coprocessor 0 names. In that case, also check for ",H" selectors.
614
fb798c50
AK		 6152013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
616
617 * s390-opc.c (J12_12, J24_24): New macros.
618 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
619 (MASK_MII_UPI): Rename to MASK_MII_UPP.
620 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
621
58ae08f2
AM		 6222013-07-04 Alan Modra <amodra@gmail.com>
623
624 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
625
b5e04c2b
NC		 6262013-06-26 Nick Clifton <nickc@redhat.com>
627
628 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
629 field when checking for type 2 nop.
630 * rx-decode.c: Regenerate.
631
833794fc
MR		 6322013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
633
634 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
635 and "movep" macros.
636
1bbce132
MR		 6372013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
638
639 * mips-dis.c (is_mips16_plt_tail): New function.
640 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
641 word.
642 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
643
34c911a4
NC		 6442013-06-21 DJ Delorie <dj@redhat.com>
645
646 * msp430-decode.opc: New.
647 * msp430-decode.c: New/generated.
648 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
649 (MAINTAINER_CLEANFILES): Likewise.
650 Add rule to build msp430-decode.c frommsp430decode.opc
651 using the opc2c program.
652 * Makefile.in: Regenerate.
653 * configure.in: Add msp430-decode.lo to msp430 architecture files.
654 * configure: Regenerate.
655
b9eead84
YZ		 6562013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
657
658 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
659 (SYMTAB_AVAILABLE): Removed.
660 (#include "elf/aarch64.h): Ditto.
661
7f3c4072
CM		 6622013-06-17 Catherine Moore <clm@codesourcery.com>
663 Maciej W. Rozycki <macro@codesourcery.com>
664 Chao-Ying Fu <fu@mips.com>
665
666 * micromips-opc.c (EVA): Define.
667 (TLBINV): Define.
668 (micromips_opcodes): Add EVA opcodes.
669 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
670 (print_insn_args): Handle EVA offsets.
671 (print_insn_micromips): Likewise.
672 * mips-opc.c (EVA): Define.
673 (TLBINV): Define.
674 (mips_builtin_opcodes): Add EVA opcodes.
675
de40ceb6
AM		 6762013-06-17 Alan Modra <amodra@gmail.com>
677
678 * Makefile.am (mips-opc.lo): Add rules to create automatic
679 dependency files. Pass archdefs.
680 (micromips-opc.lo, mips16-opc.lo): Likewise.
681 * Makefile.in: Regenerate.
682
3531d549
DD		 6832013-06-14 DJ Delorie <dj@redhat.com>
684
685 * rx-decode.opc (rx_decode_opcode): Bit operations on
686 registers are 32-bit operations, not 8-bit operations.
687 * rx-decode.c: Regenerate.
688
ba92f7fb
CF		 6892013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
690
691 * micromips-opc.c (IVIRT): New define.
692 (IVIRT64): New define.
693 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
694 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
695
696 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
697 dmtgc0 to print cp0 names.
698
9daf7bab
SL		 6992013-06-09 Sandra Loosemore <sandra@codesourcery.com>
700
701 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
702 argument.
703
d301a56b
RS		 7042013-06-08 Catherine Moore <clm@codesourcery.com>
705 Richard Sandiford <rdsandiford@googlemail.com>
706
707 * micromips-opc.c (D32, D33, MC): Update definitions.
708 (micromips_opcodes): Initialize ase field.
709 * mips-dis.c (mips_arch_choice): Add ase field.
710 (mips_arch_choices): Initialize ase field.
711 (set_default_mips_dis_options): Declare and setup mips_ase.
712 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
713 MT32, MC): Update definitions.
714 (mips_builtin_opcodes): Initialize ase field.
715
a3dcb6c5
RS		 7162013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
717
718 * s390-opc.txt (flogr): Require a register pair destination.
719
6cf1d90c
AK		 7202013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
721
722 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
723 instruction format.
724
c77c0862
RS		 7252013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
726
727 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
728
c0637f3a
PB		 7292013-05-20 Peter Bergner <bergner@vnet.ibm.com>
730
731 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
732 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
733 XLS_MASK, PPCVSX2): New defines.
734 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
735 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
736 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
737 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
738 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
739 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
740 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
741 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
742 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
743 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
744 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
745 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
746 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
747 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
748 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
749 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
750 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
751 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
752 <lxvx, stxvx>: New extended mnemonics.
753
4934fdaf
AM		 7542013-05-17 Alan Modra <amodra@gmail.com>
755
756 * ia64-raw.tbl: Replace non-ASCII char.
757 * ia64-waw.tbl: Likewise.
758 * ia64-asmtab.c: Regenerate.
759
6091d651
SE		 7602013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
761
762 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
763 * i386-init.h: Regenerated.
764
d2865ed3
YZ		 7652013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
766
767 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
768 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
769 check from [0, 255] to [-128, 255].
770
b015e599
AP		 7712013-05-09 Andrew Pinski <apinski@cavium.com>
772
773 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
774 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
775 (parse_mips_dis_option): Handle the virt option.
776 (print_insn_args): Handle "+J".
777 (print_mips_disassembler_options): Print out message about virt64.
778 * mips-opc.c (IVIRT): New define.
779 (IVIRT64): New define.
780 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
781 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
782 Move rfe to the bottom as it conflicts with tlbgp.
783
9f0682fe
AM		 7842013-05-09 Alan Modra <amodra@gmail.com>
785
786 * ppc-opc.c (extract_vlesi): Properly sign extend.
787 (extract_vlensi): Likewise. Comment reason for setting invalid.
788
13761a11
NC		 7892013-05-02 Nick Clifton <nickc@redhat.com>
790
791 * msp430-dis.c: Add support for MSP430X instructions.
792
e3031850
SL		 7932013-04-24 Sandra Loosemore <sandra@codesourcery.com>
794
795 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
796 to "eccinj".
797
17310e56
NC		 7982013-04-17 Wei-chen Wang <cole945@gmail.com>
799
800 PR binutils/15369
801 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
802 of CGEN_CPU_ENDIAN.
803 (hash_insns_list): Likewise.
804
731df338
JK		 8052013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
806
807 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
808 warning workaround.
809
5f77db52
JB		 8102013-04-08 Jan Beulich <jbeulich@suse.com>
811
812 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
813 * i386-tbl.h: Re-generate.
814
0afd1215
DM		 8152013-04-06 David S. Miller <davem@davemloft.net>
816
817 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
818 of an opcode, prefer the one with F_PREFERRED set.
819 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
820 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
821 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
822 mark existing mnenomics as aliases. Add "cc" suffix to edge
823 instructions generating condition codes, mark existing mnenomics
824 as aliases. Add "fp" prefix to VIS compare instructions, mark
825 existing mnenomics as aliases.
826
41702d50
NC		 8272013-04-03 Nick Clifton <nickc@redhat.com>
828
829 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
830 destination address by subtracting the operand from the current
831 address.
832 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
833 a positive value in the insn.
834 (extract_u16_loop): Do not negate the returned value.
835 (D16_LOOP): Add V850_INVERSE_PCREL flag.
836
837 (ceilf.sw): Remove duplicate entry.
838 (cvtf.hs): New entry.
839 (cvtf.sh): Likewise.
840 (fmaf.s): Likewise.
841 (fmsf.s): Likewise.
842 (fnmaf.s): Likewise.
843 (fnmsf.s): Likewise.
844 (maddf.s): Restrict to E3V5 architectures.
845 (msubf.s): Likewise.
846 (nmaddf.s): Likewise.
847 (nmsubf.s): Likewise.
848
55cf16e1
L		 8492013-03-27 H.J. Lu <hongjiu.lu@intel.com>
850
851 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
852 check address mode.
853 (print_insn): Pass sizeflag to get_sib.
854
51dcdd4d
NC		 8552013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
856
857 PR binutils/15068
858 * tic6x-dis.c: Add support for displaying 16-bit insns.
859
795b8e6b
NC		 8602013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
861
862 PR gas/15095
863 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
864 individual msb and lsb halves in src1 & src2 fields. Discard the
865 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
866 follow what Ti SDK does in that case as any value in the src1
867 field yields the same output with SDK disassembler.
868
314d60dd
ME		 8692013-03-12 Michael Eager <eager@eagercon.com>
870
795b8e6b 871 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 872
dad60f8e
SL		 8732013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
874
875 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
876
f5cb796a
SL		 8772013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
878
879 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
880
21fde85c
SL		 8812013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
882
883 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
884
dd5181d5
KT		 8852013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
886
887 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
888 (thumb32_opcodes): Likewise.
889 (print_insn_thumb32): Handle 'S' control char.
890
87a8d6cb
NC		 8912013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
892
893 * lm32-desc.c: Regenerate.
894
99dce992
L		 8952013-03-01 H.J. Lu <hongjiu.lu@intel.com>
896
897 * i386-reg.tbl (riz): Add RegRex64.
898 * i386-tbl.h: Regenerated.
899
e60bb1dd
YZ		 9002013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
901
902 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
903 (aarch64_feature_crc): New static.
904 (CRC): New macro.
905 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
906 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
907 * aarch64-asm-2.c: Re-generate.
908 * aarch64-dis-2.c: Ditto.
909 * aarch64-opc-2.c: Ditto.
910
c7570fcd
AM		 9112013-02-27 Alan Modra <amodra@gmail.com>
912
913 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
914 * rl78-decode.c: Regenerate.
915
151fa98f
NC		 9162013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
917
918 * rl78-decode.opc: Fix encoding of DIVWU insn.
919 * rl78-decode.c: Regenerate.
920
5c111e37
L		 9212013-02-19 H.J. Lu <hongjiu.lu@intel.com>
922
923 PR gas/15159
924 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
925
926 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
927 (cpu_flags): Add CpuSMAP.
928
929 * i386-opc.h (CpuSMAP): New.
930 (i386_cpu_flags): Add cpusmap.
931
932 * i386-opc.tbl: Add clac and stac.
933
934 * i386-init.h: Regenerated.
935 * i386-tbl.h: Likewise.
936
9d1df426
NC		 9372013-02-15 Markos Chandras <markos.chandras@imgtec.com>
938
939 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
940 which also makes the disassembler output be in little
941 endian like it should be.
942
a1ccaec9
YZ		 9432013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
944
945 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
946 fields to NULL.
947 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
948
ef068ef4 9492013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 950
951 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
952 section disassembled.
953
6fe6ded9
RE		 9542013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
955
956 * arm-dis.c: Update strht pattern.
957
0aa27725
RS		 9582013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
959
960 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
961 single-float. Disable ll, lld, sc and scd for EE. Disable the
962 trunc.w.s macro for EE.
963
36591ba1
SL		 9642013-02-06 Sandra Loosemore <sandra@codesourcery.com>
965 Andrew Jenner <andrew@codesourcery.com>
966
967 Based on patches from Altera Corporation.
968
969 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
970 nios2-opc.c.
971 * Makefile.in: Regenerated.
972 * configure.in: Add case for bfd_nios2_arch.
973 * configure: Regenerated.
974 * disassemble.c (ARCH_nios2): Define.
975 (disassembler): Add case for bfd_arch_nios2.
976 * nios2-dis.c: New file.
977 * nios2-opc.c: New file.
978
545093a4
AM		 9792013-02-04 Alan Modra <amodra@gmail.com>
980
981 * po/POTFILES.in: Regenerate.
982 * rl78-decode.c: Regenerate.
983 * rx-decode.c: Regenerate.
984
e30181a5
YZ		 9852013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
986
987 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
988 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
989 * aarch64-asm.c (convert_xtl_to_shll): New function.
990 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
991 calling convert_xtl_to_shll.
992 * aarch64-dis.c (convert_shll_to_xtl): New function.
993 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
994 calling convert_shll_to_xtl.
995 * aarch64-gen.c: Update copyright year.
996 * aarch64-asm-2.c: Re-generate.
997 * aarch64-dis-2.c: Re-generate.
998 * aarch64-opc-2.c: Re-generate.
999
78c8d46c
NC		 10002013-01-24 Nick Clifton <nickc@redhat.com>
1001
1002 * v850-dis.c: Add support for e3v5 architecture.
1003 * v850-opc.c: Likewise.
1004
f5555712
YZ		 10052013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1006
1007 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1008 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1009 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1010 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1011 alignment check; change to call set_sft_amount_out_of_range_error
1012 instead of set_imm_out_of_range_error.
1013 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1014 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1015 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1016 SIMD_IMM_SFT.
1017
2f81ff92
L		 10182013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1019
1020 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1021
1022 * i386-init.h: Regenerated.
1023 * i386-tbl.h: Likewise.
1024
dd42f060
NC		 10252013-01-15 Nick Clifton <nickc@redhat.com>
1026
1027 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1028 values.
1029 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1030
a4533ed8
NC		 10312013-01-14 Will Newton <will.newton@imgtec.com>
1032
1033 * metag-dis.c (REG_WIDTH): Increase to 64.
1034
5817ffd1
PB		 10352013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1036
1037 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1038 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1039 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1040 (SH6): Update.
1041 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1042 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1043 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1044 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1045
a3c62988
NC		 10462013-01-10 Will Newton <will.newton@imgtec.com>
1047
1048 * Makefile.am: Add Meta.
1049 * configure.in: Add Meta.
1050 * disassemble.c: Add Meta support.
1051 * metag-dis.c: New file.
1052 * Makefile.in: Regenerate.
1053 * configure: Regenerate.
1054
73335eae
NC		 10552013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1056
1057 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1058 (match_opcode): Rename to cr16_match_opcode.
1059
e407c74b
NC		 10602013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1061
1062 * mips-dis.c: Add names for CP0 registers of r5900.
1063 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1064 instructions sq and lq.
1065 Add support for MIPS r5900 CPU.
1066 Add support for 128 bit MMI (Multimedia Instructions).
1067 Add support for EE instructions (Emotion Engine).
1068 Disable unsupported floating point instructions (64 bit and
1069 undefined compare operations).
1070 Enable instructions of MIPS ISA IV which are supported by r5900.
1071 Disable 64 bit co processor instructions.
1072 Disable 64 bit multiplication and division instructions.
1073 Disable instructions for co-processor 2 and 3, because these are
1074 not supported (preparation for later VU0 support (Vector Unit)).
1075 Disable cvt.w.s because this behaves like trunc.w.s and the
1076 correct execution can't be ensured on r5900.
1077 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1078 will confuse less developers and compilers.
1079
a32c3ff8
NC		 10802013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1081
fb098a1e
YZ		 1082 * aarch64-opc.c (aarch64_print_operand): Change to print
1083 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1084 in comment.
1085 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1086 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1087 OP_MOV_IMM_WIDE.
1088
10892013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1090
1091 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1092 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1093
62658407
L		 10942013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1095
1096 * i386-gen.c (process_copyright): Update copyright year to 2013.
1097
bab4becb 10982013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1099
bab4becb
NC		 1100 * cr16-dis.c (match_opcode,make_instruction): Remove static
1101 declaration.
1102 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1103 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1104
bab4becb 1105For older changes see ChangeLog-2012
252b5132 1106\f
bab4becb 1107Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1108
1109Copying and distribution of this file, with or without modification,
1110are permitted in any medium without royalty provided the copyright
1111notice and this notice are preserved.
1112
252b5132 1113Local Variables:
2f6d2f85
NC		 1114mode: change-log
1115left-margin: 8
1116fill-column: 74
252b5132
RH		 1117version-control: never
1118End:
GDB Binutils - Deliverables
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