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ubsan: sparc: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4383e1fc
AM		 12019-12-29 Alan Modra <amodra@gmail.com>
2
3 * sparc-dis.c (SEX): Don't use left and right shift to sign extend.
4 (compare_opcodes): Avoid signed shift left overflow.
5 (print_insn_sparc): Likewise.
6
8c5e2592
AM		 72019-12-29 Alan Modra <amodra@gmail.com>
8
9 PR 25319
10 * tic4x-dis.c (tic4x_print_cond): Init all of condtable.
11
376cd056
JB		 122019-12-27 Jan Beulich <jbeulich@suse.com>
13
14 * i386-dis.c (Jdqw): Define.
15 (dqw_mode): Adjust associated comment.
16 (rm_table): Use Jdqw for XBEGIN.
17 (OP_J): Handle dqw_mode.
18
48bcea9f
JB		 192019-12-27 Jan Beulich <jbeulich@suse.com>
20
21 * i386-gen.c (process_i386_operand_type): Don't set Disp32 for
22 Cpu64 templates.
23 * i386-opc.tbl (mov): Fold two templates.
24 (jcxz, jecxz, jrcxz, loop, loope, loopne, loopnz, loopz): Drop
25 Disp16, Disp32, and Disp32S.
26 (xbegin): Add Disp32S.
27 * i386-tbl.h: Re-generate.
28
100b122f
AM		 292019-12-26 Alan Modra <amodra@gmail.com>
30
31 * crx-dis.c (get_number_of_operands): Don't access operands[]
32 out of bounds.
33
6c2ca6c2
AM		 342019-12-26 Alan Modra <amodra@gmail.com>
35
36 * v850-dis.c (disassemble): Avoid signed overflow. Don't use
37 long vars when unsigned int will do.
38
ebd1c6d1
AM		 392019-12-24 Alan Modra <amodra@gmail.com>
40
41 * arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
42
0e62b37a
JB		 432019-12-23 Jan Beulich <jbeulich@suse.com>
44
45 * ppc-dis.c (print_insn_powerpc): Rename local variable "spaces"
46 to "blanks".
47 * ppc-opc.c (D34, SI34, NSI34): Use UINT64_C().
48
7936714c
AM		 492019-12-23 Alan Modra <amodra@gmail.com>
50
51 * score-dis.c (print_insn_score32): Avoid signed overflow.
52 (print_insn_score48): Likewise. Don't cast to int when printing
53 hex values.
54
3e1056a1
AM		 552019-12-23 Alan Modra <amodra@gmail.com>
56
57 * iq2000-ibld.c: Regenerate.
58
1a1e2852
AM		 592019-12-23 Alan Modra <amodra@gmail.com>
60
61 * d30v-dis.c (extract_value): Make num param a uint64_t, constify
62 oper. Use unsigned vars.
63 (print_insn): Make num var uint64_t. Constify oper and remove now
64 unnecessary casts on extract_value calls.
65 (print_insn_d30v): Use unsigned vars. Adjust printf formats.
66
27c1c427
AM		 672019-12-23 Alan Modra <amodra@gmail.com>
68
69 * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
70 Catch value overflow. Sign extend only on terminating byte.
71
cda8d785
AM		 722019-12-20 Alan Modra <amodra@gmail.com>
73
74 PR 25281
75 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
76 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word
77 printed. Print .word in more cases.
78
bcd9f578
AM		 792019-12-20 Alan Modra <amodra@gmail.com>
80
81 * or1k-ibld.c: Regenerate.
82
15d2859f
AM		 832019-12-20 Alan Modra <amodra@gmail.com>
84
85 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
86 unsigned variables.
87
000fe1a7
AM		 882019-12-20 Alan Modra <amodra@gmail.com>
89
90 * m68hc11-dis.c (read_memory): Delete forward decls.
91 (print_indexed_operand, print_insn): Likewise.
92 (print_indexed_operand): Formatting. Don't rely on short being
93 exactly 16 bits, make sign extension explicit.
94 (print_insn): Likewise. Avoid signed overflow.
95
f0090188
AM		 962019-12-19 Alan Modra <amodra@gmail.com>
97
98 * vax-dis.c (print_insn_mode): Stop index mode recursion.
99
1d29ab86
DF		 1002019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
101
102 PR 25277
103 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
104 fdiv with "mbi_".
105 * microblaze-opc.h (opcodes): Adjust to suit.
106
2480b6fa
AM		 1072019-12-18 Alan Modra <amodra@gmail.com>
108
109 * alpha-opc.c (OP): Avoid signed overflow.
110 * arm-dis.c (print_insn): Likewise.
111 * mcore-dis.c (print_insn_mcore): Likewise.
112 * pj-dis.c (get_int): Likewise.
113 * ppc-opc.c (EBD15, EBD15BI): Likewise.
114 * score7-dis.c (s7_print_insn): Likewise.
115 * tic30-dis.c (print_insn_tic30): Likewise.
116 * v850-opc.c (insert_SELID): Likewise.
117 * vax-dis.c (print_insn_vax): Likewise.
118 * arc-ext.c (create_map): Likewise.
119 (struct ExtAuxRegister): Make "address" field unsigned int.
120 (arcExtMap_auxRegName): Pass unsigned address.
121 (dump_ARC_extmap): Adjust.
122 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
123
eb7b5046
AM		 1242019-12-17 Alan Modra <amodra@gmail.com>
125
126 * visium-dis.c (print_insn_visium): Avoid signed overflow.
127
29298bf6
AM		 1282019-12-17 Alan Modra <amodra@gmail.com>
129
130 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
131 (value_fit_unsigned_field_p): Likewise.
132 (aarch64_wide_constant_p): Likewise.
133 (operand_general_constraint_met_p): Likewise.
134 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
135
e46d79a7
AM		 1362019-12-17 Alan Modra <amodra@gmail.com>
137
138 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
139 (print_insn_nds32): Use uint64_t for "given" and "given1".
140
5b660084
AM		 1412019-12-17 Alan Modra <amodra@gmail.com>
142
143 * tic80-dis.c: Delete file.
144 * tic80-opc.c: Delete file.
145 * disassemble.c: Remove tic80 support.
146 * disassemble.h: Likewise.
147 * Makefile.am: Likewise.
148 * configure.ac: Likewise.
149 * Makefile.in: Regenerate.
150 * configure: Regenerate.
151 * po/POTFILES.in: Regenerate.
152
62e65990
AM		 1532019-12-17 Alan Modra <amodra@gmail.com>
154
155 * bpf-ibld.c: Regenerate.
156
f81e7e2d
AM		 1572019-12-16 Alan Modra <amodra@gmail.com>
158
159 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
160 conditional.
161 (aarch64_ext_imm): Avoid signed overflow.
162
488d02fe
AM		 1632019-12-16 Alan Modra <amodra@gmail.com>
164
165 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
166
8a92faab
AM		 1672019-12-16 Alan Modra <amodra@gmail.com>
168
169 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
170
e6ced26a
AM		 1712019-12-16 Alan Modra <amodra@gmail.com>
172
173 * xstormy16-ibld.c: Regenerate.
174
84e098cd
AM		 1752019-12-16 Alan Modra <amodra@gmail.com>
176
177 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
178 value adjustment so that it doesn't affect reg field too.
179
36bd8ea7
AM		 1802019-12-16 Alan Modra <amodra@gmail.com>
181
182 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
183 (get_number_of_operands, getargtype, getbits, getregname),
184 (getcopregname, getprocregname, gettrapstring, getcinvstring),
185 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
186 (powerof2, match_opcode, make_instruction, print_arguments),
187 (print_arg): Delete forward declarations, moving static to..
188 (getregname, getcopregname, getregliststring): ..these definitions.
189 (build_mask): Return unsigned int mask.
190 (match_opcode): Use unsigned int vars.
191
cedfc774
AM		 1922019-12-16 Alan Modra <amodra@gmail.com>
193
194 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
195
4bdb25fe
AM		 1962019-12-16 Alan Modra <amodra@gmail.com>
197
198 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
199 (struct objdump_disasm_info): Delete.
200 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
201 N32_IMMS to unsigned before shifting left.
202
cf950fd4
AM		 2032019-12-16 Alan Modra <amodra@gmail.com>
204
205 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
206 (print_insn_moxie): Remove unnecessary cast.
207
967354c3
AM		 2082019-12-12 Alan Modra <amodra@gmail.com>
209
210 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
211 mask.
212
1d61b032
AM		 2132019-12-11 Alan Modra <amodra@gmail.com>
214
215 * arc-dis.c (BITS): Don't truncate high bits with shifts.
216 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
217 * tic54x-dis.c (print_instruction): Likewise.
218 * tilegx-opc.c (parse_insn_tilegx): Likewise.
219 * tilepro-opc.c (parse_insn_tilepro): Likewise.
220 * visium-dis.c (disassem_class0): Likewise.
221 * pdp11-dis.c (sign_extend): Likewise.
222 (SIGN_BITS): Delete.
223 * epiphany-ibld.c: Regenerate.
224 * lm32-ibld.c: Regenerate.
225 * m32c-ibld.c: Regenerate.
226
5afa80e9
AM		 2272019-12-11 Alan Modra <amodra@gmail.com>
228
229 * ns32k-dis.c (sign_extend): Correct last patch.
230
5c05618a
AM		 2312019-12-11 Alan Modra <amodra@gmail.com>
232
233 * vax-dis.c (NEXTLONG): Avoid signed overflow.
234
2a81ccbb
AM		 2352019-12-11 Alan Modra <amodra@gmail.com>
236
237 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
238 sign extend using shifts.
239
b84f6152
AM		 2402019-12-11 Alan Modra <amodra@gmail.com>
241
242 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
243
66152f16
AM		 2442019-12-11 Alan Modra <amodra@gmail.com>
245
246 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
247 on NULL registertable entry.
248 (tic4x_hash_opcode): Use unsigned arithmetic.
249
205c426a
AM		 2502019-12-11 Alan Modra <amodra@gmail.com>
251
252 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
253
fb4cb4e2
AM		 2542019-12-11 Alan Modra <amodra@gmail.com>
255
256 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
257 (bit_extract_simple, sign_extend): Likewise.
258
96f1f604
AM		 2592019-12-11 Alan Modra <amodra@gmail.com>
260
261 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
262
8c9b4171
AM		 2632019-12-11 Alan Modra <amodra@gmail.com>
264
265 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
266
334175b6
AM		 2672019-12-11 Alan Modra <amodra@gmail.com>
268
269 * m68k-dis.c (COERCE32): Cast value first.
270 (NEXTLONG, NEXTULONG): Avoid signed overflow.
271
f8a87c78
AM		 2722019-12-11 Alan Modra <amodra@gmail.com>
273
274 * h8300-dis.c (extract_immediate): Avoid signed overflow.
275 (bfd_h8_disassemble): Likewise.
276
159653d8
AM		 2772019-12-11 Alan Modra <amodra@gmail.com>
278
279 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
280 past end of operands array.
281
d93bba9e
AM		 2822019-12-11 Alan Modra <amodra@gmail.com>
283
284 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
285 overflow when collecting bytes of a number.
286
c202f69e
AM		 2872019-12-11 Alan Modra <amodra@gmail.com>
288
289 * cris-dis.c (print_with_operands): Avoid signed integer
290 overflow when collecting bytes of a 32-bit integer.
291
0ef562a4
AM		 2922019-12-11 Alan Modra <amodra@gmail.com>
293
294 * cr16-dis.c (EXTRACT, SBM): Rewrite.
295 (cr16_match_opcode): Delete duplicate bcond test.
296
2fd2b153
AM		 2972019-12-11 Alan Modra <amodra@gmail.com>
298
299 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
300 (SIGNBIT): New.
301 (MASKBITS, SIGNEXTEND): Rewrite.
302 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
303 unsigned arithmetic, instead assign result of SIGNEXTEND back
304 to x.
305 (fmtconst_val): Use 1u in shift expression.
306
a11db3e9
AM		 3072019-12-11 Alan Modra <amodra@gmail.com>
308
309 * arc-dis.c (find_format_from_table): Use ull constant when
310 shifting by up to 32.
311
9d48687b
AM		 3122019-12-11 Alan Modra <amodra@gmail.com>
313
314 PR 25270
315 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
316 false when field is zero for sve_size_tsz_bhs.
317
b8e61daa
AM		 3182019-12-11 Alan Modra <amodra@gmail.com>
319
320 * epiphany-ibld.c: Regenerate.
321
20135676
AM		 3222019-12-10 Alan Modra <amodra@gmail.com>
323
324 PR 24960
325 * disassemble.c (disassemble_free_target): New function.
326
103ebbc3
AM		 3272019-12-10 Alan Modra <amodra@gmail.com>
328
329 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
330 * disassemble.c (disassemble_init_for_target): Likewise.
331 * bpf-dis.c: Regenerate.
332 * epiphany-dis.c: Regenerate.
333 * fr30-dis.c: Regenerate.
334 * frv-dis.c: Regenerate.
335 * ip2k-dis.c: Regenerate.
336 * iq2000-dis.c: Regenerate.
337 * lm32-dis.c: Regenerate.
338 * m32c-dis.c: Regenerate.
339 * m32r-dis.c: Regenerate.
340 * mep-dis.c: Regenerate.
341 * mt-dis.c: Regenerate.
342 * or1k-dis.c: Regenerate.
343 * xc16x-dis.c: Regenerate.
344 * xstormy16-dis.c: Regenerate.
345
6f0e0752
AM		 3462019-12-10 Alan Modra <amodra@gmail.com>
347
348 * ppc-dis.c (private): Delete variable.
349 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
350 (powerpc_init_dialect): Don't use global private.
351
e7c22a69
AM		 3522019-12-10 Alan Modra <amodra@gmail.com>
353
354 * s12z-opc.c: Formatting.
355
0a6aef6b
AM		 3562019-12-08 Alan Modra <amodra@gmail.com>
357
358 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
359 registers.
360
2dc4b12f
JB		 3612019-12-05 Jan Beulich <jbeulich@suse.com>
362
363 * aarch64-tbl.h (aarch64_feature_crypto,
364 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
365 CRYPTO_V8_2_INSN): Delete.
366
378fd436
AM		 3672019-12-05 Alan Modra <amodra@gmail.com>
368
369 PR 25249
370 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
371 (struct string_buf): New.
372 (strbuf): New function.
373 (get_field): Use strbuf rather than strdup of local temp.
374 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
375 (get_field_rfsl, get_field_imm15): Likewise.
376 (get_field_rd, get_field_r1, get_field_r2): Update macros.
377 (get_field_special): Likewise. Don't strcpy spr. Formatting.
378 (print_insn_microblaze): Formatting. Init and pass string_buf to
379 get_field functions.
380
0ba59a29
JB		 3812019-12-04 Jan Beulich <jbeulich@suse.com>
382
383 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
384 * i386-tbl.h: Re-generate.
385
77ad8092
JB		 3862019-12-04 Jan Beulich <jbeulich@suse.com>
387
388 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
389
3036c899
JB		 3902019-12-04 Jan Beulich <jbeulich@suse.com>
391
392 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
393 forms.
394 (xbegin): Drop DefaultSize.
395 * i386-tbl.h: Re-generate.
396
8b301fbb
MI		 3972019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
398
399 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
400 Change the coproc CRC conditions to use the extension
401 feature set, second word, base on ARM_EXT2_CRC.
402
6aa385b9
JB		 4032019-11-14 Jan Beulich <jbeulich@suse.com>
404
405 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
406 * i386-tbl.h: Re-generate.
407
0cfa3eb3
JB		 4082019-11-14 Jan Beulich <jbeulich@suse.com>
409
410 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
411 JumpInterSegment, and JumpAbsolute entries.
412 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
413 JUMP_ABSOLUTE): Define.
414 (struct i386_opcode_modifier): Extend jump field to 3 bits.
415 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
416 fields.
417 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
418 JumpInterSegment): Define.
419 * i386-tbl.h: Re-generate.
420
6f2f06be
JB		 4212019-11-14 Jan Beulich <jbeulich@suse.com>
422
423 * i386-gen.c (operand_type_init): Remove
424 OPERAND_TYPE_JUMPABSOLUTE entry.
425 (opcode_modifiers): Add JumpAbsolute entry.
426 (operand_types): Remove JumpAbsolute entry.
427 * i386-opc.h (JumpAbsolute): Move between enums.
428 (struct i386_opcode_modifier): Add jumpabsolute field.
429 (union i386_operand_type): Remove jumpabsolute field.
430 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
431 * i386-init.h, i386-tbl.h: Re-generate.
432
601e8564
JB		 4332019-11-14 Jan Beulich <jbeulich@suse.com>
434
435 * i386-gen.c (opcode_modifiers): Add AnySize entry.
436 (operand_types): Remove AnySize entry.
437 * i386-opc.h (AnySize): Move between enums.
438 (struct i386_opcode_modifier): Add anysize field.
439 (OTUnused): Un-comment.
440 (union i386_operand_type): Remove anysize field.
441 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
442 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
443 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
444 AnySize.
445 * i386-tbl.h: Re-generate.
446
7722d40a
JW		 4472019-11-12 Nelson Chu <nelson.chu@sifive.com>
448
449 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
450 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
451 use the floating point register (FPR).
452
ce760a76
MI		 4532019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
454
455 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
456 cmode 1101.
457 (is_mve_encoding_conflict): Update cmode conflict checks for
458 MVE_VMVN_IMM.
459
51c8edf6
JB		 4602019-11-12 Jan Beulich <jbeulich@suse.com>
461
462 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
463 entry.
464 (operand_types): Remove EsSeg entry.
465 (main): Replace stale use of OTMax.
466 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
467 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
468 (EsSeg): Delete.
469 (OTUnused): Comment out.
470 (union i386_operand_type): Remove esseg field.
471 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
472 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
473 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
474 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
475 * i386-init.h, i386-tbl.h: Re-generate.
476
474da251
JB		 4772019-11-12 Jan Beulich <jbeulich@suse.com>
478
479 * i386-gen.c (operand_instances): Add RegB entry.
480 * i386-opc.h (enum operand_instance): Add RegB.
481 * i386-opc.tbl (RegC, RegD, RegB): Define.
482 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
483 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
484 monitorx, mwaitx): Drop ImmExt and convert encodings
485 accordingly.
486 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
487 (edx, rdx): Add Instance=RegD.
488 (ebx, rbx): Add Instance=RegB.
489 * i386-tbl.h: Re-generate.
490
75e5731b
JB		 4912019-11-12 Jan Beulich <jbeulich@suse.com>
492
493 * i386-gen.c (operand_type_init): Adjust
494 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
495 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
496 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
497 (operand_instances): New.
498 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
499 (output_operand_type): New parameter "instance". Process it.
500 (process_i386_operand_type): New local variable "instance".
501 (main): Adjust static assertions.
502 * i386-opc.h (INSTANCE_WIDTH): Define.
503 (enum operand_instance): New.
504 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
505 (union i386_operand_type): Replace acc, inoutportreg, and
506 shiftcount by instance.
507 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
508 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
509 Add Instance=.
510 * i386-init.h, i386-tbl.h: Re-generate.
511
91802f3c
JB		 5122019-11-11 Jan Beulich <jbeulich@suse.com>
513
514 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
515 smaxp/sminp entries' "tied_operand" field to 2.
516
4f5fc85d
JB		 5172019-11-11 Jan Beulich <jbeulich@suse.com>
518
519 * aarch64-opc.c (operand_general_constraint_met_p): Replace
520 "index" local variable by that of the already existing "num".
521
dc2be329
L		 5222019-11-08 H.J. Lu <hongjiu.lu@intel.com>
523
524 PR gas/25167
525 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
526 * i386-tbl.h: Regenerated.
527
f74a6307
JB		 5282019-11-08 Jan Beulich <jbeulich@suse.com>
529
530 * i386-gen.c (operand_type_init): Add Class= to
531 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
532 OPERAND_TYPE_REGBND entry.
533 (operand_classes): Add RegMask and RegBND entries.
534 (operand_types): Drop RegMask and RegBND entry.
535 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
536 (RegMask, RegBND): Delete.
537 (union i386_operand_type): Remove regmask and regbnd fields.
538 * i386-opc.tbl (RegMask, RegBND): Define.
539 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
540 Class=RegBND.
541 * i386-init.h, i386-tbl.h: Re-generate.
542
3528c362
JB		 5432019-11-08 Jan Beulich <jbeulich@suse.com>
544
545 * i386-gen.c (operand_type_init): Add Class= to
546 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
547 OPERAND_TYPE_REGZMM entries.
548 (operand_classes): Add RegMMX and RegSIMD entries.
549 (operand_types): Drop RegMMX and RegSIMD entries.
550 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
551 (RegMMX, RegSIMD): Delete.
552 (union i386_operand_type): Remove regmmx and regsimd fields.
553 * i386-opc.tbl (RegMMX): Define.
554 (RegXMM, RegYMM, RegZMM): Add Class=.
555 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
556 Class=RegSIMD.
557 * i386-init.h, i386-tbl.h: Re-generate.
558
4a5c67ed
JB		 5592019-11-08 Jan Beulich <jbeulich@suse.com>
560
561 * i386-gen.c (operand_type_init): Add Class= to
562 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
563 entries.
564 (operand_classes): Add RegCR, RegDR, and RegTR entries.
565 (operand_types): Drop Control, Debug, and Test entries.
566 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
567 (Control, Debug, Test): Delete.
568 (union i386_operand_type): Remove control, debug, and test
569 fields.
570 * i386-opc.tbl (Control, Debug, Test): Define.
571 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
572 Class=RegDR, and Test by Class=RegTR.
573 * i386-init.h, i386-tbl.h: Re-generate.
574
00cee14f
JB		 5752019-11-08 Jan Beulich <jbeulich@suse.com>
576
577 * i386-gen.c (operand_type_init): Add Class= to
578 OPERAND_TYPE_SREG entry.
579 (operand_classes): Add SReg entry.
580 (operand_types): Drop SReg entry.
581 * i386-opc.h (enum operand_class): Add SReg.
582 (SReg): Delete.
583 (union i386_operand_type): Remove sreg field.
584 * i386-opc.tbl (SReg): Define.
585 * i386-reg.tbl: Replace SReg by Class=SReg.
586 * i386-init.h, i386-tbl.h: Re-generate.
587
bab6aec1
JB		 5882019-11-08 Jan Beulich <jbeulich@suse.com>
589
590 * i386-gen.c (operand_type_init): Add Class=. New
591 OPERAND_TYPE_ANYIMM entry.
592 (operand_classes): New.
593 (operand_types): Drop Reg entry.
594 (output_operand_type): New parameter "class". Process it.
595 (process_i386_operand_type): New local variable "class".
596 (main): Adjust static assertions.
597 * i386-opc.h (CLASS_WIDTH): Define.
598 (enum operand_class): New.
599 (Reg): Replace by Class. Adjust comment.
600 (union i386_operand_type): Replace reg by class.
601 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
602 Class=.
603 * i386-reg.tbl: Replace Reg by Class=Reg.
604 * i386-init.h: Re-generate.
605
1f4cd317
MM		 6062019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
607
608 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
609 (aarch64_opcode_table): Add data gathering hint mnemonic.
610 * opcodes/aarch64-dis-2.c: Account for new instruction.
611
616ce08e
MM		 6122019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
613
614 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
615
616
8382113f
MM		 6172019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
618
619 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
620 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
621 aarch64_feature_f64mm): New feature sets.
622 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
623 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
624 instructions.
625 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
626 macros.
627 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
628 (OP_SVE_QQQ): New qualifier.
629 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
630 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
631 the movprfx constraint.
632 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
633 (aarch64_opcode_table): Define new instructions smmla,
634 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
635 uzip{1/2}, trn{1/2}.
636 * aarch64-opc.c (operand_general_constraint_met_p): Handle
637 AARCH64_OPND_SVE_ADDR_RI_S4x32.
638 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
639 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
640 Account for new instructions.
641 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
642 S4x32 operand.
643 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
644
aab2c27d
MM		 6452019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6462019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
647
648 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
649 Armv8.6-A.
650 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
651 (neon_opcodes): Add bfloat SIMD instructions.
652 (print_insn_coprocessor): Add new control character %b to print
653 condition code without checking cp_num.
654 (print_insn_neon): Account for BFloat16 instructions that have no
655 special top-byte handling.
656
33593eaf
MM		 6572019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6582019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
659
660 * arm-dis.c (print_insn_coprocessor,
661 print_insn_generic_coprocessor): Create wrapper functions around
662 the implementation of the print_insn_coprocessor control codes.
663 (print_insn_coprocessor_1): Original print_insn_coprocessor
664 function that now takes which array to look at as an argument.
665 (print_insn_arm): Use both print_insn_coprocessor and
666 print_insn_generic_coprocessor.
667 (print_insn_thumb32): As above.
668
df678013
MM		 6692019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6702019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
671
672 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
673 in reglane special case.
674 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
675 aarch64_find_next_opcode): Account for new instructions.
676 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
677 in reglane special case.
678 * aarch64-opc.c (struct operand_qualifier_data): Add data for
679 new AARCH64_OPND_QLF_S_2H qualifier.
680 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
681 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
682 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
683 sets.
684 (BFLOAT_SVE, BFLOAT): New feature set macros.
685 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
686 instructions.
687 (aarch64_opcode_table): Define new instructions bfdot,
688 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
689 bfcvtn2, bfcvt.
690
8ae2d3d9
MM		 6912019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6922019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
693
694 * aarch64-tbl.h (ARMV8_6): New macro.
695
142861df
JB		 6962019-11-07 Jan Beulich <jbeulich@suse.com>
697
698 * i386-dis.c (prefix_table): Add mcommit.
699 (rm_table): Add rdpru.
700 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
701 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
702 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
703 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
704 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
705 * i386-opc.tbl (mcommit, rdpru): New.
706 * i386-init.h, i386-tbl.h: Re-generate.
707
081e283f
JB		 7082019-11-07 Jan Beulich <jbeulich@suse.com>
709
710 * i386-dis.c (OP_Mwait): Drop local variable "names", use
711 "names32" instead.
712 (OP_Monitor): Drop local variable "op1_names", re-purpose
713 "names" for it instead, and replace former "names" uses by
714 "names32" ones.
715
c050c89a
JB		 7162019-11-07 Jan Beulich <jbeulich@suse.com>
717
718 PR/gas 25167
719 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
720 operand-less forms.
721 * opcodes/i386-tbl.h: Re-generate.
722
7abb8d81
JB		 7232019-11-05 Jan Beulich <jbeulich@suse.com>
724
725 * i386-dis.c (OP_Mwaitx): Delete.
726 (prefix_table): Use OP_Mwait for mwaitx entry.
727 (OP_Mwait): Also handle mwaitx.
728
267b8516
JB		 7292019-11-05 Jan Beulich <jbeulich@suse.com>
730
731 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
732 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
733 (prefix_table): Add respective entries.
734 (rm_table): Link to those entries.
735
f8687e93
JB		 7362019-11-05 Jan Beulich <jbeulich@suse.com>
737
738 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
739 (REG_0F1C_P_0_MOD_0): ... this.
740 (REG_0F1E_MOD_3): Rename to ...
741 (REG_0F1E_P_1_MOD_3): ... this.
742 (RM_0F01_REG_5): Rename to ...
743 (RM_0F01_REG_5_MOD_3): ... this.
744 (RM_0F01_REG_7): Rename to ...
745 (RM_0F01_REG_7_MOD_3): ... this.
746 (RM_0F1E_MOD_3_REG_7): Rename to ...
747 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
748 (RM_0FAE_REG_6): Rename to ...
749 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
750 (RM_0FAE_REG_7): Rename to ...
751 (RM_0FAE_REG_7_MOD_3): ... this.
752 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
753 (PREFIX_0F01_REG_5_MOD_0): ... this.
754 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
755 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
756 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
757 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
758 (PREFIX_0FAE_REG_0): Rename to ...
759 (PREFIX_0FAE_REG_0_MOD_3): ... this.
760 (PREFIX_0FAE_REG_1): Rename to ...
761 (PREFIX_0FAE_REG_1_MOD_3): ... this.
762 (PREFIX_0FAE_REG_2): Rename to ...
763 (PREFIX_0FAE_REG_2_MOD_3): ... this.
764 (PREFIX_0FAE_REG_3): Rename to ...
765 (PREFIX_0FAE_REG_3_MOD_3): ... this.
766 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
767 (PREFIX_0FAE_REG_4_MOD_0): ... this.
768 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
769 (PREFIX_0FAE_REG_4_MOD_3): ... this.
770 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
771 (PREFIX_0FAE_REG_5_MOD_0): ... this.
772 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
773 (PREFIX_0FAE_REG_5_MOD_3): ... this.
774 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
775 (PREFIX_0FAE_REG_6_MOD_0): ... this.
776 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
777 (PREFIX_0FAE_REG_6_MOD_3): ... this.
778 (PREFIX_0FAE_REG_7): Rename to ...
779 (PREFIX_0FAE_REG_7_MOD_0): ... this.
780 (PREFIX_MOD_0_0FC3): Rename to ...
781 (PREFIX_0FC3_MOD_0): ... this.
782 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
783 (PREFIX_0FC7_REG_6_MOD_0): ... this.
784 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
785 (PREFIX_0FC7_REG_6_MOD_3): ... this.
786 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
787 (PREFIX_0FC7_REG_7_MOD_3): ... this.
788 (reg_table, prefix_table, mod_table, rm_table): Adjust
789 accordingly.
790
5103274f
NC		 7912019-11-04 Nick Clifton <nickc@redhat.com>
792
793 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
794 of a v850 system register. Move the v850_sreg_names array into
795 this function.
796 (get_v850_reg_name): Likewise for ordinary register names.
797 (get_v850_vreg_name): Likewise for vector register names.
798 (get_v850_cc_name): Likewise for condition codes.
799 * get_v850_float_cc_name): Likewise for floating point condition
800 codes.
801 (get_v850_cacheop_name): Likewise for cache-ops.
802 (get_v850_prefop_name): Likewise for pref-ops.
803 (disassemble): Use the new accessor functions.
804
1820262b
DB		 8052019-10-30 Delia Burduv <delia.burduv@arm.com>
806
807 * aarch64-opc.c (print_immediate_offset_address): Don't print the
808 immediate for the writeback form of ldraa/ldrab if it is 0.
809 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
810 * aarch64-opc-2.c: Regenerated.
811
3cc17af5
JB		 8122019-10-30 Jan Beulich <jbeulich@suse.com>
813
814 * i386-gen.c (operand_type_shorthands): Delete.
815 (operand_type_init): Expand previous shorthands.
816 (set_bitfield_from_shorthand): Rename back to ...
817 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
818 of operand_type_init[].
819 (set_bitfield): Adjust call to the above function.
820 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
821 RegXMM, RegYMM, RegZMM): Define.
822 * i386-reg.tbl: Expand prior shorthands.
823
a2cebd03
JB		 8242019-10-30 Jan Beulich <jbeulich@suse.com>
825
826 * i386-gen.c (output_i386_opcode): Change order of fields
827 emitted to output.
828 * i386-opc.h (struct insn_template): Move operands field.
829 Convert extension_opcode field to unsigned short.
830 * i386-tbl.h: Re-generate.
831
507916b8
JB		 8322019-10-30 Jan Beulich <jbeulich@suse.com>
833
834 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
835 of W.
836 * i386-opc.h (W): Extend comment.
837 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
838 general purpose variants not allowing for byte operands.
839 * i386-tbl.h: Re-generate.
840
efea62b4
NC		 8412019-10-29 Nick Clifton <nickc@redhat.com>
842
843 * tic30-dis.c (print_branch): Correct size of operand array.
844
9adb2591
NC		 8452019-10-29 Nick Clifton <nickc@redhat.com>
846
847 * d30v-dis.c (print_insn): Check that operand index is valid
848 before attempting to access the operands array.
849
993a00a9
NC		 8502019-10-29 Nick Clifton <nickc@redhat.com>
851
852 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
853 locating the bit to be tested.
854
66a66a17
NC		 8552019-10-29 Nick Clifton <nickc@redhat.com>
856
857 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
858 values.
859 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
860 (print_insn_s12z): Check for illegal size values.
861
1ee3542c
NC		 8622019-10-28 Nick Clifton <nickc@redhat.com>
863
864 * csky-dis.c (csky_chars_to_number): Check for a negative
865 count. Use an unsigned integer to construct the return value.
866
bbf9a0b5
NC		 8672019-10-28 Nick Clifton <nickc@redhat.com>
868
869 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
870 operand buffer. Set value to 15 not 13.
871 (get_register_operand): Use OPERAND_BUFFER_LEN.
872 (get_indirect_operand): Likewise.
873 (print_two_operand): Likewise.
874 (print_three_operand): Likewise.
875 (print_oar_insn): Likewise.
876
d1e304bc
NC		 8772019-10-28 Nick Clifton <nickc@redhat.com>
878
879 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
880 (bit_extract_simple): Likewise.
881 (bit_copy): Likewise.
882 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
883 index_offset array are not accessed.
884
dee33451
NC		 8852019-10-28 Nick Clifton <nickc@redhat.com>
886
887 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
888 operand.
889
27cee81d
NC		 8902019-10-25 Nick Clifton <nickc@redhat.com>
891
892 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
893 access to opcodes.op array element.
894
de6d8dc2
NC		 8952019-10-23 Nick Clifton <nickc@redhat.com>
896
897 * rx-dis.c (get_register_name): Fix spelling typo in error
898 message.
899 (get_condition_name, get_flag_name, get_double_register_name)
900 (get_double_register_high_name, get_double_register_low_name)
901 (get_double_control_register_name, get_double_condition_name)
902 (get_opsize_name, get_size_name): Likewise.
903
6207ed28
NC		 9042019-10-22 Nick Clifton <nickc@redhat.com>
905
906 * rx-dis.c (get_size_name): New function. Provides safe
907 access to name array.
908 (get_opsize_name): Likewise.
909 (print_insn_rx): Use the accessor functions.
910
12234dfd
NC		 9112019-10-16 Nick Clifton <nickc@redhat.com>
912
913 * rx-dis.c (get_register_name): New function. Provides safe
914 access to name array.
915 (get_condition_name, get_flag_name, get_double_register_name)
916 (get_double_register_high_name, get_double_register_low_name)
917 (get_double_control_register_name, get_double_condition_name):
918 Likewise.
919 (print_insn_rx): Use the accessor functions.
920
1d378749
NC		 9212019-10-09 Nick Clifton <nickc@redhat.com>
922
923 PR 25041
924 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
925 instructions.
926
d241b910
JB		 9272019-10-07 Jan Beulich <jbeulich@suse.com>
928
929 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
930 (cmpsd): Likewise. Move EsSeg to other operand.
931 * opcodes/i386-tbl.h: Re-generate.
932
f5c5b7c1
AM		 9332019-09-23 Alan Modra <amodra@gmail.com>
934
935 * m68k-dis.c: Include cpu-m68k.h
936
7beeaeb8
AM		 9372019-09-23 Alan Modra <amodra@gmail.com>
938
939 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
940 "elf/mips.h" earlier.
941
3f9aad11
JB		 9422018-09-20 Jan Beulich <jbeulich@suse.com>
943
944 PR gas/25012
945 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
946 with SReg operand.
947 * i386-tbl.h: Re-generate.
948
fd361982
AM		 9492019-09-18 Alan Modra <amodra@gmail.com>
950
951 * arc-ext.c: Update throughout for bfd section macro changes.
952
e0b2a78c
SM		 9532019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
954
955 * Makefile.in: Re-generate.
956 * configure: Re-generate.
957
7e9ad3a3
JW		 9582019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
959
960 * riscv-opc.c (riscv_opcodes): Change subset field
961 to insn_class field for all instructions.
962 (riscv_insn_types): Likewise.
963
bb695960
PB		 9642019-09-16 Phil Blundell <pb@pbcl.net>
965
966 * configure: Regenerated.
967
8063ab7e
MV		 9682019-09-10 Miod Vallat <miod@online.fr>
969
970 PR 24982
971 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
972
60391a25
PB		 9732019-09-09 Phil Blundell <pb@pbcl.net>
974
975 binutils 2.33 branch created.
976
f44b758d
NC		 9772019-09-03 Nick Clifton <nickc@redhat.com>
978
979 PR 24961
980 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
981 greater than zero before indexing via (bufcnt -1).
982
1e4b5e7d
NC		 9832019-09-03 Nick Clifton <nickc@redhat.com>
984
985 PR 24958
986 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
987 (MAX_SPEC_REG_NAME_LEN): Define.
988 (struct mmix_dis_info): Use defined constants for array lengths.
989 (get_reg_name): New function.
990 (get_sprec_reg_name): New function.
991 (print_insn_mmix): Use new functions.
992
c4a23bf8
SP		 9932019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
994
995 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
996 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
997 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
998
a051e2f3
KT		 9992019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1000
1001 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
1002 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
1003 (aarch64_sys_reg_supported_p): Update checks for the above.
1004
08132bdd
SP		 10052019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
1006
1007 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
1008 cases MVE_SQRSHRL and MVE_UQRSHLL.
1009 (print_insn_mve): Add case for specifier 'k' to check
1010 specific bit of the instruction.
1011
d88bdcb4
PA		 10122019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
1013
1014 PR 24854
1015 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
1016 encountering an unknown machine type.
1017 (print_insn_arc): Handle arc_insn_length returning 0. In error
1018 cases return -1 rather than calling abort.
1019
bc750500
JB		 10202019-08-07 Jan Beulich <jbeulich@suse.com>
1021
1022 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
1023 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
1024 IgnoreSize.
1025 * i386-tbl.h: Re-generate.
1026
23d188c7
BW		 10272019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
1028
1029 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
1030 instructions.
1031
c0d6f62f
JW		 10322019-07-30 Mel Chen <mel.chen@sifive.com>
1033
1034 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
1035 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
1036
1037 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
1038 fscsr.
1039
0f3f7167
CZ		 10402019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1041
1042 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
1043 and MPY class instructions.
1044 (parse_option): Add nps400 option.
1045 (print_arc_disassembler_options): Add nps400 info.
1046
7e126ba3
CZ		 10472019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1048
1049 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
1050 (bspop): Likewise.
1051 (modapp): Likewise.
1052 * arc-opc.c (RAD_CHK): Add.
1053 * arc-tbl.h: Regenerate.
1054
a028026d
KT		 10552019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1056
1057 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1058 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1059
ac79ff9e
NC		 10602019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
1061
1062 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1063 instructions as UNPREDICTABLE.
1064
231097b0
JM		 10652019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1066
1067 * bpf-desc.c: Regenerated.
1068
1d942ae9
JB		 10692019-07-17 Jan Beulich <jbeulich@suse.com>
1070
1071 * i386-gen.c (static_assert): Define.
1072 (main): Use it.
1073 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1074 (Opcode_Modifier_Num): ... this.
1075 (Mem): Delete.
1076
dfd69174
JB		 10772019-07-16 Jan Beulich <jbeulich@suse.com>
1078
1079 * i386-gen.c (operand_types): Move RegMem ...
1080 (opcode_modifiers): ... here.
1081 * i386-opc.h (RegMem): Move to opcode modifer enum.
1082 (union i386_operand_type): Move regmem field ...
1083 (struct i386_opcode_modifier): ... here.
1084 * i386-opc.tbl (RegMem): Define.
1085 (mov, movq): Move RegMem on segment, control, debug, and test
1086 register flavors.
1087 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1088 to non-SSE2AVX flavor.
1089 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1090 Move RegMem on register only flavors. Drop IgnoreSize from
1091 legacy encoding flavors.
1092 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1093 flavors.
1094 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1095 register only flavors.
1096 (vmovd): Move RegMem and drop IgnoreSize on register only
1097 flavor. Change opcode and operand order to store form.
1098 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1099
21df382b
JB		 11002019-07-16 Jan Beulich <jbeulich@suse.com>
1101
1102 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1103 entries.
1104 * i386-opc.h (SReg2, SReg3): Replace by ...
1105 (SReg): ... this.
1106 (union i386_operand_type): Replace sreg fields.
1107 * i386-opc.tbl (mov, ): Use SReg.
1108 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1109 register flavors.
1110 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1111 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1112
3719fd55
JM		 11132019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1114
1115 * bpf-desc.c: Regenerate.
1116 * bpf-opc.c: Likewise.
1117 * bpf-opc.h: Likewise.
1118
92434a14
JM		 11192019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1120
1121 * bpf-desc.c: Regenerate.
1122 * bpf-opc.c: Likewise.
1123
43dd7626
HPN		 11242019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1125
1126 * arm-dis.c (print_insn_coprocessor): Rename index to
1127 index_operand.
1128
98602811
JW		 11292019-07-05 Kito Cheng <kito.cheng@sifive.com>
1130
1131 * riscv-opc.c (riscv_insn_types): Add r4 type.
1132
1133 * riscv-opc.c (riscv_insn_types): Add b and j type.
1134
1135 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1136 format for sb type and correct s type.
1137
01c1ee4a
RS		 11382019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1139
1140 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1141 SVE FMOV alias of FCPY.
1142
83adff69
RS		 11432019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1144
1145 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1146 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1147
89418844
RS		 11482019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1149
1150 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1151 registers in an instruction prefixed by MOVPRFX.
1152
41be57ca
MM		 11532019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1154
1155 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1156 sve_size_13 icode to account for variant behaviour of
1157 pmull{t,b}.
1158 * aarch64-dis-2.c: Regenerate.
1159 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1160 sve_size_13 icode to account for variant behaviour of
1161 pmull{t,b}.
1162 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1163 (OP_SVE_VVV_Q_D): Add new qualifier.
1164 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1165 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1166 AES and those not.
1167
9d3bf266
JB		 11682019-07-01 Jan Beulich <jbeulich@suse.com>
1169
1170 * opcodes/i386-gen.c (operand_type_init): Remove
1171 OPERAND_TYPE_VEC_IMM4 entry.
1172 (operand_types): Remove Vec_Imm4.
1173 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1174 (union i386_operand_type): Remove vec_imm4.
1175 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1176 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1177
c3949f43
JB		 11782019-07-01 Jan Beulich <jbeulich@suse.com>
1179
1180 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1181 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1182 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1183 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1184 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1185 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1186 * i386-tbl.h: Re-generate.
1187
5641ec01
JB		 11882019-07-01 Jan Beulich <jbeulich@suse.com>
1189
1190 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1191 register operands.
1192 * i386-tbl.h: Re-generate.
1193
79dec6b7
JB		 11942019-07-01 Jan Beulich <jbeulich@suse.com>
1195
1196 * i386-opc.tbl (C): New.
1197 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1198 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1199 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1200 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1201 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1202 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1203 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1204 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1205 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1206 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1207 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1208 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1209 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1210 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1211 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1212 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1213 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1214 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1215 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1216 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1217 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1218 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1219 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1220 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1221 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1222 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1223 flavors.
1224 * i386-tbl.h: Re-generate.
1225
a0a1771e
JB		 12262019-07-01 Jan Beulich <jbeulich@suse.com>
1227
1228 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1229 register operands.
1230 * i386-tbl.h: Re-generate.
1231
cd546e7b
JB		 12322019-07-01 Jan Beulich <jbeulich@suse.com>
1233
1234 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1235 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1236 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1237 * i386-tbl.h: Re-generate.
1238
e3bba3fc
JB		 12392019-07-01 Jan Beulich <jbeulich@suse.com>
1240
1241 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1242 Disp8MemShift from register only templates.
1243 * i386-tbl.h: Re-generate.
1244
36cc073e
JB		 12452019-07-01 Jan Beulich <jbeulich@suse.com>
1246
1247 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1248 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1249 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1250 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1251 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1252 EVEX_W_0F11_P_3_M_1): Delete.
1253 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1254 EVEX_W_0F11_P_3): New.
1255 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1256 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1257 MOD_EVEX_0F11_PREFIX_3 table entries.
1258 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1259 PREFIX_EVEX_0F11 table entries.
1260 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1261 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1262 EVEX_W_0F11_P_3_M_{0,1} table entries.
1263
219920a7
JB		 12642019-07-01 Jan Beulich <jbeulich@suse.com>
1265
1266 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1267 Delete.
1268
e395f487
L		 12692019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1270
1271 PR binutils/24719
1272 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1273 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1274 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1275 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1276 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1277 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1278 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1279 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1280 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1281 PREFIX_EVEX_0F38C6_REG_6 entries.
1282 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1283 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1284 EVEX_W_0F38C7_R_6_P_2 entries.
1285 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1286 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1287 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1288 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1289 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1290 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1291 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1292
2b7bcc87
JB		 12932019-06-27 Jan Beulich <jbeulich@suse.com>
1294
1295 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1296 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1297 VEX_LEN_0F2D_P_3): Delete.
1298 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1299 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1300 (prefix_table): ... here.
1301
c1dc7af5
JB		 13022019-06-27 Jan Beulich <jbeulich@suse.com>
1303
1304 * i386-dis.c (Iq): Delete.
1305 (Id): New.
1306 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1307 TBM insns.
1308 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1309 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1310 (OP_E_memory): Also honor needindex when deciding whether an
1311 address size prefix needs printing.
1312 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1313
d7560e2d
JW		 13142019-06-26 Jim Wilson <jimw@sifive.com>
1315
1316 PR binutils/24739
1317 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1318 Set info->display_endian to info->endian_code.
1319
2c703856
JB		 13202019-06-25 Jan Beulich <jbeulich@suse.com>
1321
1322 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1323 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1324 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1325 OPERAND_TYPE_ACC64 entries.
1326 * i386-init.h: Re-generate.
1327
54fbadc0
JB		 13282019-06-25 Jan Beulich <jbeulich@suse.com>
1329
1330 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1331 Delete.
1332 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1333 of dqa_mode.
1334 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1335 entries here.
1336 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1337 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1338
a280ab8e
JB		 13392019-06-25 Jan Beulich <jbeulich@suse.com>
1340
1341 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1342 variables.
1343
e1a1babd
JB		 13442019-06-25 Jan Beulich <jbeulich@suse.com>
1345
1346 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1347 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1348 movnti.
d7560e2d 1349 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1350 * i386-tbl.h: Re-generate.
1351
b8364fa7
JB		 13522019-06-25 Jan Beulich <jbeulich@suse.com>
1353
1354 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1355 * i386-tbl.h: Re-generate.
1356
ad692897
L		 13572019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1358
1359 * i386-dis-evex.h: Break into ...
1360 * i386-dis-evex-len.h: New file.
1361 * i386-dis-evex-mod.h: Likewise.
1362 * i386-dis-evex-prefix.h: Likewise.
1363 * i386-dis-evex-reg.h: Likewise.
1364 * i386-dis-evex-w.h: Likewise.
1365 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1366 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1367 i386-dis-evex-mod.h.
1368
f0a6222e
L		 13692019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1370
1371 PR binutils/24700
1372 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1373 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1374 EVEX_W_0F385B_P_2.
1375 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1376 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1377 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1378 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1379 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1380 EVEX_LEN_0F385B_P_2_W_1.
1381 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1382 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1383 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1384 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1385 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1386 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1387 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1388 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1389 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1390 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1391
6e1c90b7
L		 13922019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1393
1394 PR binutils/24691
1395 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1396 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1397 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1398 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1399 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1400 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1401 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1402 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1403 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1404 EVEX_LEN_0F3A43_P_2_W_1.
1405 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1406 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1407 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1408 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1409 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1410 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1411 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1412 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1413 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1414 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1415 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1416 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1417
bcc5a6eb
NC		 14182019-06-14 Nick Clifton <nickc@redhat.com>
1419
1420 * po/fr.po; Updated French translation.
1421
e4c4ac46
SH		 14222019-06-13 Stafford Horne <shorne@gmail.com>
1423
1424 * or1k-asm.c: Regenerated.
1425 * or1k-desc.c: Regenerated.
1426 * or1k-desc.h: Regenerated.
1427 * or1k-dis.c: Regenerated.
1428 * or1k-ibld.c: Regenerated.
1429 * or1k-opc.c: Regenerated.
1430 * or1k-opc.h: Regenerated.
1431 * or1k-opinst.c: Regenerated.
1432
a0e44ef5
PB		 14332019-06-12 Peter Bergner <bergner@linux.ibm.com>
1434
1435 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1436
12efd68d
L		 14372019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1438
1439 PR binutils/24633
1440 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1441 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1442 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1443 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1444 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1445 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1446 EVEX_LEN_0F3A1B_P_2_W_1.
1447 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1448 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1449 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1450 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1451 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1452 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1453 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1454 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1455
63c6fc6c
L		 14562019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1457
1458 PR binutils/24626
1459 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1460 EVEX.vvvv when disassembling VEX and EVEX instructions.
1461 (OP_VEX): Set vex.register_specifier to 0 after readding
1462 vex.register_specifier.
1463 (OP_Vex_2src_1): Likewise.
1464 (OP_Vex_2src_2): Likewise.
1465 (OP_LWP_E): Likewise.
1466 (OP_EX_Vex): Don't check vex.register_specifier.
1467 (OP_XMM_Vex): Likewise.
1468
9186c494
L		 14692019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1470 Lili Cui <lili.cui@intel.com>
1471
1472 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1473 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1474 instructions.
1475 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1476 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1477 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1478 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1479 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1480 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1481 * i386-init.h: Regenerated.
1482 * i386-tbl.h: Likewise.
1483
5d79adc4
L		 14842019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1485 Lili Cui <lili.cui@intel.com>
1486
1487 * doc/c-i386.texi: Document enqcmd.
1488 * testsuite/gas/i386/enqcmd-intel.d: New file.
1489 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1490 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1491 * testsuite/gas/i386/enqcmd.d: Likewise.
1492 * testsuite/gas/i386/enqcmd.s: Likewise.
1493 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1494 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1495 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1496 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1497 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1498 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1499 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1500 and x86-64-enqcmd.
1501
a9d96ab9
AH		 15022019-06-04 Alan Hayward <alan.hayward@arm.com>
1503
1504 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1505
4f6d070a
AM		 15062019-06-03 Alan Modra <amodra@gmail.com>
1507
1508 * ppc-dis.c (prefix_opcd_indices): Correct size.
1509
a2f4b66c
L		 15102019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1511
1512 PR gas/24625
1513 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1514 Disp8ShiftVL.
1515 * i386-tbl.h: Regenerated.
1516
405b5bd8
AM		 15172019-05-24 Alan Modra <amodra@gmail.com>
1518
1519 * po/POTFILES.in: Regenerate.
1520
8acf1435
PB		 15212019-05-24 Peter Bergner <bergner@linux.ibm.com>
1522 Alan Modra <amodra@gmail.com>
1523
1524 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1525 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1526 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1527 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1528 XTOP>): Define and add entries.
1529 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1530 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1531 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1532 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1533
dd7efa79
PB		 15342019-05-24 Peter Bergner <bergner@linux.ibm.com>
1535 Alan Modra <amodra@gmail.com>
1536
1537 * ppc-dis.c (ppc_opts): Add "future" entry.
1538 (PREFIX_OPCD_SEGS): Define.
1539 (prefix_opcd_indices): New array.
1540 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1541 (lookup_prefix): New function.
1542 (print_insn_powerpc): Handle 64-bit prefix instructions.
1543 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1544 (PMRR, POWERXX): Define.
1545 (prefix_opcodes): New instruction table.
1546 (prefix_num_opcodes): New constant.
1547
79472b45
JM		 15482019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1549
1550 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1551 * configure: Regenerated.
1552 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1553 and cpu/bpf.opc.
1554 (HFILES): Add bpf-desc.h and bpf-opc.h.
1555 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1556 bpf-ibld.c and bpf-opc.c.
1557 (BPF_DEPS): Define.
1558 * Makefile.in: Regenerated.
1559 * disassemble.c (ARCH_bpf): Define.
1560 (disassembler): Add case for bfd_arch_bpf.
1561 (disassemble_init_for_target): Likewise.
1562 (enum epbf_isa_attr): Define.
1563 * disassemble.h: extern print_insn_bpf.
1564 * bpf-asm.c: Generated.
1565 * bpf-opc.h: Likewise.
1566 * bpf-opc.c: Likewise.
1567 * bpf-ibld.c: Likewise.
1568 * bpf-dis.c: Likewise.
1569 * bpf-desc.h: Likewise.
1570 * bpf-desc.c: Likewise.
1571
ba6cd17f
SD		 15722019-05-21 Sudakshina Das <sudi.das@arm.com>
1573
1574 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1575 and VMSR with the new operands.
1576
e39c1607
SD		 15772019-05-21 Sudakshina Das <sudi.das@arm.com>
1578
1579 * arm-dis.c (enum mve_instructions): New enum
1580 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1581 and cneg.
1582 (mve_opcodes): New instructions as above.
1583 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1584 csneg and csel.
1585 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1586
23d00a41
SD		 15872019-05-21 Sudakshina Das <sudi.das@arm.com>
1588
1589 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1590 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1591 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1592 uqshl, urshrl and urshr.
1593 (is_mve_okay_in_it): Add new instructions to TRUE list.
1594 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1595 (print_insn_mve): Updated to accept new %j,
1596 %<bitfield>m and %<bitfield>n patterns.
1597
cd4797ee
FS		 15982019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1599
1600 * mips-opc.c (mips_builtin_opcodes): Change source register
1601 constraint for DAUI.
1602
999b073b
NC		 16032019-05-20 Nick Clifton <nickc@redhat.com>
1604
1605 * po/fr.po: Updated French translation.
1606
14b456f2
AV		 16072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1608 Michael Collison <michael.collison@arm.com>
1609
1610 * arm-dis.c (thumb32_opcodes): Add new instructions.
1611 (enum mve_instructions): Likewise.
1612 (enum mve_undefined): Add new reasons.
1613 (is_mve_encoding_conflict): Handle new instructions.
1614 (is_mve_undefined): Likewise.
1615 (is_mve_unpredictable): Likewise.
1616 (print_mve_undefined): Likewise.
1617 (print_mve_size): Likewise.
1618
f49bb598
AV		 16192019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1620 Michael Collison <michael.collison@arm.com>
1621
1622 * arm-dis.c (thumb32_opcodes): Add new instructions.
1623 (enum mve_instructions): Likewise.
1624 (is_mve_encoding_conflict): Handle new instructions.
1625 (is_mve_undefined): Likewise.
1626 (is_mve_unpredictable): Likewise.
1627 (print_mve_size): Likewise.
1628
56858bea
AV		 16292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1630 Michael Collison <michael.collison@arm.com>
1631
1632 * arm-dis.c (thumb32_opcodes): Add new instructions.
1633 (enum mve_instructions): Likewise.
1634 (is_mve_encoding_conflict): Likewise.
1635 (is_mve_unpredictable): Likewise.
1636 (print_mve_size): Likewise.
1637
e523f101
AV		 16382019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1639 Michael Collison <michael.collison@arm.com>
1640
1641 * arm-dis.c (thumb32_opcodes): Add new instructions.
1642 (enum mve_instructions): Likewise.
1643 (is_mve_encoding_conflict): Handle new instructions.
1644 (is_mve_undefined): Likewise.
1645 (is_mve_unpredictable): Likewise.
1646 (print_mve_size): Likewise.
1647
66dcaa5d
AV		 16482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1649 Michael Collison <michael.collison@arm.com>
1650
1651 * arm-dis.c (thumb32_opcodes): Add new instructions.
1652 (enum mve_instructions): Likewise.
1653 (is_mve_encoding_conflict): Handle new instructions.
1654 (is_mve_undefined): Likewise.
1655 (is_mve_unpredictable): Likewise.
1656 (print_mve_size): Likewise.
1657 (print_insn_mve): Likewise.
1658
d052b9b7
AV		 16592019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1660 Michael Collison <michael.collison@arm.com>
1661
1662 * arm-dis.c (thumb32_opcodes): Add new instructions.
1663 (print_insn_thumb32): Handle new instructions.
1664
ed63aa17
AV		 16652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1666 Michael Collison <michael.collison@arm.com>
1667
1668 * arm-dis.c (enum mve_instructions): Add new instructions.
1669 (enum mve_undefined): Add new reasons.
1670 (is_mve_encoding_conflict): Handle new instructions.
1671 (is_mve_undefined): Likewise.
1672 (is_mve_unpredictable): Likewise.
1673 (print_mve_undefined): Likewise.
1674 (print_mve_size): Likewise.
1675 (print_mve_shift_n): Likewise.
1676 (print_insn_mve): Likewise.
1677
897b9bbc
AV		 16782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1679 Michael Collison <michael.collison@arm.com>
1680
1681 * arm-dis.c (enum mve_instructions): Add new instructions.
1682 (is_mve_encoding_conflict): Handle new instructions.
1683 (is_mve_unpredictable): Likewise.
1684 (print_mve_rotate): Likewise.
1685 (print_mve_size): Likewise.
1686 (print_insn_mve): Likewise.
1687
1c8f2df8
AV		 16882019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1689 Michael Collison <michael.collison@arm.com>
1690
1691 * arm-dis.c (enum mve_instructions): Add new instructions.
1692 (is_mve_encoding_conflict): Handle new instructions.
1693 (is_mve_unpredictable): Likewise.
1694 (print_mve_size): Likewise.
1695 (print_insn_mve): Likewise.
1696
d3b63143
AV		 16972019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1698 Michael Collison <michael.collison@arm.com>
1699
1700 * arm-dis.c (enum mve_instructions): Add new instructions.
1701 (enum mve_undefined): Add new reasons.
1702 (is_mve_encoding_conflict): Handle new instructions.
1703 (is_mve_undefined): Likewise.
1704 (is_mve_unpredictable): Likewise.
1705 (print_mve_undefined): Likewise.
1706 (print_mve_size): Likewise.
1707 (print_insn_mve): Likewise.
1708
14925797
AV		 17092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1710 Michael Collison <michael.collison@arm.com>
1711
1712 * arm-dis.c (enum mve_instructions): Add new instructions.
1713 (is_mve_encoding_conflict): Handle new instructions.
1714 (is_mve_undefined): Likewise.
1715 (is_mve_unpredictable): Likewise.
1716 (print_mve_size): Likewise.
1717 (print_insn_mve): Likewise.
1718
c507f10b
AV		 17192019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1720 Michael Collison <michael.collison@arm.com>
1721
1722 * arm-dis.c (enum mve_instructions): Add new instructions.
1723 (enum mve_unpredictable): Add new reasons.
1724 (enum mve_undefined): Likewise.
1725 (is_mve_okay_in_it): Handle new isntructions.
1726 (is_mve_encoding_conflict): Likewise.
1727 (is_mve_undefined): Likewise.
1728 (is_mve_unpredictable): Likewise.
1729 (print_mve_vmov_index): Likewise.
1730 (print_simd_imm8): Likewise.
1731 (print_mve_undefined): Likewise.
1732 (print_mve_unpredictable): Likewise.
1733 (print_mve_size): Likewise.
1734 (print_insn_mve): Likewise.
1735
bf0b396d
AV		 17362019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1737 Michael Collison <michael.collison@arm.com>
1738
1739 * arm-dis.c (enum mve_instructions): Add new instructions.
1740 (enum mve_unpredictable): Add new reasons.
1741 (enum mve_undefined): Likewise.
1742 (is_mve_encoding_conflict): Handle new instructions.
1743 (is_mve_undefined): Likewise.
1744 (is_mve_unpredictable): Likewise.
1745 (print_mve_undefined): Likewise.
1746 (print_mve_unpredictable): Likewise.
1747 (print_mve_rounding_mode): Likewise.
1748 (print_mve_vcvt_size): Likewise.
1749 (print_mve_size): Likewise.
1750 (print_insn_mve): Likewise.
1751
ef1576a1
AV		 17522019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1753 Michael Collison <michael.collison@arm.com>
1754
1755 * arm-dis.c (enum mve_instructions): Add new instructions.
1756 (enum mve_unpredictable): Add new reasons.
1757 (enum mve_undefined): Likewise.
1758 (is_mve_undefined): Handle new instructions.
1759 (is_mve_unpredictable): Likewise.
1760 (print_mve_undefined): Likewise.
1761 (print_mve_unpredictable): Likewise.
1762 (print_mve_size): Likewise.
1763 (print_insn_mve): Likewise.
1764
aef6d006
AV		 17652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1766 Michael Collison <michael.collison@arm.com>
1767
1768 * arm-dis.c (enum mve_instructions): Add new instructions.
1769 (enum mve_undefined): Add new reasons.
1770 (insns): Add new instructions.
1771 (is_mve_encoding_conflict):
1772 (print_mve_vld_str_addr): New print function.
1773 (is_mve_undefined): Handle new instructions.
1774 (is_mve_unpredictable): Likewise.
1775 (print_mve_undefined): Likewise.
1776 (print_mve_size): Likewise.
1777 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1778 (print_insn_mve): Handle new operands.
1779
04d54ace
AV		 17802019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1781 Michael Collison <michael.collison@arm.com>
1782
1783 * arm-dis.c (enum mve_instructions): Add new instructions.
1784 (enum mve_unpredictable): Add new reasons.
1785 (is_mve_encoding_conflict): Handle new instructions.
1786 (is_mve_unpredictable): Likewise.
1787 (mve_opcodes): Add new instructions.
1788 (print_mve_unpredictable): Handle new reasons.
1789 (print_mve_register_blocks): New print function.
1790 (print_mve_size): Handle new instructions.
1791 (print_insn_mve): Likewise.
1792
9743db03
AV		 17932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1794 Michael Collison <michael.collison@arm.com>
1795
1796 * arm-dis.c (enum mve_instructions): Add new instructions.
1797 (enum mve_unpredictable): Add new reasons.
1798 (enum mve_undefined): Likewise.
1799 (is_mve_encoding_conflict): Handle new instructions.
1800 (is_mve_undefined): Likewise.
1801 (is_mve_unpredictable): Likewise.
1802 (coprocessor_opcodes): Move NEON VDUP from here...
1803 (neon_opcodes): ... to here.
1804 (mve_opcodes): Add new instructions.
1805 (print_mve_undefined): Handle new reasons.
1806 (print_mve_unpredictable): Likewise.
1807 (print_mve_size): Handle new instructions.
1808 (print_insn_neon): Handle vdup.
1809 (print_insn_mve): Handle new operands.
1810
143275ea
AV		 18112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1812 Michael Collison <michael.collison@arm.com>
1813
1814 * arm-dis.c (enum mve_instructions): Add new instructions.
1815 (enum mve_unpredictable): Add new values.
1816 (mve_opcodes): Add new instructions.
1817 (vec_condnames): New array with vector conditions.
1818 (mve_predicatenames): New array with predicate suffixes.
1819 (mve_vec_sizename): New array with vector sizes.
1820 (enum vpt_pred_state): New enum with vector predication states.
1821 (struct vpt_block): New struct type for vpt blocks.
1822 (vpt_block_state): Global struct to keep track of state.
1823 (mve_extract_pred_mask): New helper function.
1824 (num_instructions_vpt_block): Likewise.
1825 (mark_outside_vpt_block): Likewise.
1826 (mark_inside_vpt_block): Likewise.
1827 (invert_next_predicate_state): Likewise.
1828 (update_next_predicate_state): Likewise.
1829 (update_vpt_block_state): Likewise.
1830 (is_vpt_instruction): Likewise.
1831 (is_mve_encoding_conflict): Add entries for new instructions.
1832 (is_mve_unpredictable): Likewise.
1833 (print_mve_unpredictable): Handle new cases.
1834 (print_instruction_predicate): Likewise.
1835 (print_mve_size): New function.
1836 (print_vec_condition): New function.
1837 (print_insn_mve): Handle vpt blocks and new print operands.
1838
f08d8ce3
AV		 18392019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1840
1841 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1842 8, 14 and 15 for Armv8.1-M Mainline.
1843
73cd51e5
AV		 18442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1845 Michael Collison <michael.collison@arm.com>
1846
1847 * arm-dis.c (enum mve_instructions): New enum.
1848 (enum mve_unpredictable): Likewise.
1849 (enum mve_undefined): Likewise.
1850 (struct mopcode32): New struct.
1851 (is_mve_okay_in_it): New function.
1852 (is_mve_architecture): Likewise.
1853 (arm_decode_field): Likewise.
1854 (arm_decode_field_multiple): Likewise.
1855 (is_mve_encoding_conflict): Likewise.
1856 (is_mve_undefined): Likewise.
1857 (is_mve_unpredictable): Likewise.
1858 (print_mve_undefined): Likewise.
1859 (print_mve_unpredictable): Likewise.
1860 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1861 (print_insn_mve): New function.
1862 (print_insn_thumb32): Handle MVE architecture.
1863 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1864
3076e594
NC		 18652019-05-10 Nick Clifton <nickc@redhat.com>
1866
1867 PR 24538
1868 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1869 end of the table prematurely.
1870
387e7624
FS		 18712019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1872
1873 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1874 macros for R6.
1875
0067be51
AM		 18762019-05-11 Alan Modra <amodra@gmail.com>
1877
1878 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1879 when -Mraw is in effect.
1880
42e6288f
MM		 18812019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1882
1883 * aarch64-dis-2.c: Regenerate.
1884 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1885 (OP_SVE_BBB): New variant set.
1886 (OP_SVE_DDDD): New variant set.
1887 (OP_SVE_HHH): New variant set.
1888 (OP_SVE_HHHU): New variant set.
1889 (OP_SVE_SSS): New variant set.
1890 (OP_SVE_SSSU): New variant set.
1891 (OP_SVE_SHH): New variant set.
1892 (OP_SVE_SBBU): New variant set.
1893 (OP_SVE_DSS): New variant set.
1894 (OP_SVE_DHHU): New variant set.
1895 (OP_SVE_VMV_HSD_BHS): New variant set.
1896 (OP_SVE_VVU_HSD_BHS): New variant set.
1897 (OP_SVE_VVVU_SD_BH): New variant set.
1898 (OP_SVE_VVVU_BHSD): New variant set.
1899 (OP_SVE_VVV_QHD_DBS): New variant set.
1900 (OP_SVE_VVV_HSD_BHS): New variant set.
1901 (OP_SVE_VVV_HSD_BHS2): New variant set.
1902 (OP_SVE_VVV_BHS_HSD): New variant set.
1903 (OP_SVE_VV_BHS_HSD): New variant set.
1904 (OP_SVE_VVV_SD): New variant set.
1905 (OP_SVE_VVU_BHS_HSD): New variant set.
1906 (OP_SVE_VZVV_SD): New variant set.
1907 (OP_SVE_VZVV_BH): New variant set.
1908 (OP_SVE_VZV_SD): New variant set.
1909 (aarch64_opcode_table): Add sve2 instructions.
1910
28ed815a
MM		 19112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1912
1913 * aarch64-asm-2.c: Regenerated.
1914 * aarch64-dis-2.c: Regenerated.
1915 * aarch64-opc-2.c: Regenerated.
1916 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1917 for SVE_SHLIMM_UNPRED_22.
1918 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1919 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1920 operand.
1921
fd1dc4a0
MM		 19222019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1923
1924 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1925 sve_size_tsz_bhs iclass encode.
1926 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1927 sve_size_tsz_bhs iclass decode.
1928
31e36ab3
MM		 19292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1930
1931 * aarch64-asm-2.c: Regenerated.
1932 * aarch64-dis-2.c: Regenerated.
1933 * aarch64-opc-2.c: Regenerated.
1934 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1935 for SVE_Zm4_11_INDEX.
1936 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1937 (fields): Handle SVE_i2h field.
1938 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1939 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1940
1be5f94f
MM		 19412019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1942
1943 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1944 sve_shift_tsz_bhsd iclass encode.
1945 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1946 sve_shift_tsz_bhsd iclass decode.
1947
3c17238b
MM		 19482019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1949
1950 * aarch64-asm-2.c: Regenerated.
1951 * aarch64-dis-2.c: Regenerated.
1952 * aarch64-opc-2.c: Regenerated.
1953 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1954 (aarch64_encode_variant_using_iclass): Handle
1955 sve_shift_tsz_hsd iclass encode.
1956 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1957 sve_shift_tsz_hsd iclass decode.
1958 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1959 for SVE_SHRIMM_UNPRED_22.
1960 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1961 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1962 operand.
1963
cd50a87a
MM		 19642019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1965
1966 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1967 sve_size_013 iclass encode.
1968 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1969 sve_size_013 iclass decode.
1970
3c705960
MM		 19712019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1972
1973 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1974 sve_size_bh iclass encode.
1975 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1976 sve_size_bh iclass decode.
1977
0a57e14f
MM		 19782019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1979
1980 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1981 sve_size_sd2 iclass encode.
1982 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1983 sve_size_sd2 iclass decode.
1984 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1985 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1986
c469c864
MM		 19872019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1988
1989 * aarch64-asm-2.c: Regenerated.
1990 * aarch64-dis-2.c: Regenerated.
1991 * aarch64-opc-2.c: Regenerated.
1992 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1993 for SVE_ADDR_ZX.
1994 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1995 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1996
116adc27
MM		 19972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1998
1999 * aarch64-asm-2.c: Regenerated.
2000 * aarch64-dis-2.c: Regenerated.
2001 * aarch64-opc-2.c: Regenerated.
2002 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
2003 for SVE_Zm3_11_INDEX.
2004 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
2005 (fields): Handle SVE_i3l and SVE_i3h2 fields.
2006 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
2007 fields.
2008 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
2009
3bd82c86
MM		 20102019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2011
2012 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
2013 sve_size_hsd2 iclass encode.
2014 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
2015 sve_size_hsd2 iclass decode.
2016 * aarch64-opc.c (fields): Handle SVE_size field.
2017 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2018
adccc507
MM		 20192019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2020
2021 * aarch64-asm-2.c: Regenerated.
2022 * aarch64-dis-2.c: Regenerated.
2023 * aarch64-opc-2.c: Regenerated.
2024 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
2025 for SVE_IMM_ROT3.
2026 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
2027 (fields): Handle SVE_rot3 field.
2028 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
2029 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2030
5cd99750
MM		 20312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2032
2033 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
2034 instructions.
2035
7ce2460a
MM		 20362019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2037
2038 * aarch64-tbl.h
2039 (aarch64_feature_sve2, aarch64_feature_sve2aes,
2040 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
2041 aarch64_feature_sve2bitperm): New feature sets.
2042 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
2043 for feature set addresses.
2044 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
2045 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2046
41cee089
FS		 20472019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
2048 Faraz Shahbazker <fshahbazker@wavecomp.com>
2049
2050 * mips-dis.c (mips_calculate_combination_ases): Add ISA
2051 argument and set ASE_EVA_R6 appropriately.
2052 (set_default_mips_dis_options): Pass ISA to above.
2053 (parse_mips_dis_option): Likewise.
2054 * mips-opc.c (EVAR6): New macro.
2055 (mips_builtin_opcodes): Add llwpe, scwpe.
2056
b83b4b13
SD		 20572019-05-01 Sudakshina Das <sudi.das@arm.com>
2058
2059 * aarch64-asm-2.c: Regenerated.
2060 * aarch64-dis-2.c: Regenerated.
2061 * aarch64-opc-2.c: Regenerated.
2062 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2063 AARCH64_OPND_TME_UIMM16.
2064 (aarch64_print_operand): Likewise.
2065 * aarch64-tbl.h (QL_IMM_NIL): New.
2066 (TME): New.
2067 (_TME_INSN): New.
2068 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2069
4a90ce95
JD		 20702019-04-29 John Darrington <john@darrington.wattle.id.au>
2071
2072 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2073
a45328b9
AB		 20742019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
2075 Faraz Shahbazker <fshahbazker@wavecomp.com>
2076
2077 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2078
d10be0cb
JD		 20792019-04-24 John Darrington <john@darrington.wattle.id.au>
2080
2081 * s12z-opc.h: Add extern "C" bracketing to help
2082 users who wish to use this interface in c++ code.
2083
a679f24e
JD		 20842019-04-24 John Darrington <john@darrington.wattle.id.au>
2085
2086 * s12z-opc.c (bm_decode): Handle bit map operations with the
2087 "reserved0" mode.
2088
32c36c3c
AV		 20892019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2090
2091 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2092 specifier. Add entries for VLDR and VSTR of system registers.
2093 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2094 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2095 of %J and %K format specifier.
2096
efd6b359
AV		 20972019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2098
2099 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2100 Add new entries for VSCCLRM instruction.
2101 (print_insn_coprocessor): Handle new %C format control code.
2102
6b0dd094
AV		 21032019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2104
2105 * arm-dis.c (enum isa): New enum.
2106 (struct sopcode32): New structure.
2107 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2108 set isa field of all current entries to ANY.
2109 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2110 Only match an entry if its isa field allows the current mode.
2111
4b5a202f
AV		 21122019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2113
2114 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2115 CLRM.
2116 (print_insn_thumb32): Add logic to print %n CLRM register list.
2117
60f993ce
AV		 21182019-04-15 Sudakshina Das <sudi.das@arm.com>
2119
2120 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2121 and %Q patterns.
2122
f6b2b12d
AV		 21232019-04-15 Sudakshina Das <sudi.das@arm.com>
2124
2125 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2126 (print_insn_thumb32): Edit the switch case for %Z.
2127
1889da70
AV		 21282019-04-15 Sudakshina Das <sudi.das@arm.com>
2129
2130 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2131
65d1bc05
AV		 21322019-04-15 Sudakshina Das <sudi.das@arm.com>
2133
2134 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2135
1caf72a5
AV		 21362019-04-15 Sudakshina Das <sudi.das@arm.com>
2137
2138 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2139
f1c7f421
AV		 21402019-04-15 Sudakshina Das <sudi.das@arm.com>
2141
2142 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2143 Arm register with r13 and r15 unpredictable.
2144 (thumb32_opcodes): New instructions for bfx and bflx.
2145
4389b29a
AV		 21462019-04-15 Sudakshina Das <sudi.das@arm.com>
2147
2148 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2149
e5d6e09e
AV		 21502019-04-15 Sudakshina Das <sudi.das@arm.com>
2151
2152 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2153
e12437dc
AV		 21542019-04-15 Sudakshina Das <sudi.das@arm.com>
2155
2156 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2157
031254f2
AV		 21582019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2159
2160 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2161
e5a557ac
JD		 21622019-04-12 John Darrington <john@darrington.wattle.id.au>
2163
2164 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2165 "optr". ("operator" is a reserved word in c++).
2166
bd7ceb8d
SD		 21672019-04-11 Sudakshina Das <sudi.das@arm.com>
2168
2169 * aarch64-opc.c (aarch64_print_operand): Add case for
2170 AARCH64_OPND_Rt_SP.
2171 (verify_constraints): Likewise.
2172 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2173 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2174 to accept Rt|SP as first operand.
2175 (AARCH64_OPERANDS): Add new Rt_SP.
2176 * aarch64-asm-2.c: Regenerated.
2177 * aarch64-dis-2.c: Regenerated.
2178 * aarch64-opc-2.c: Regenerated.
2179
e54010f1
SD		 21802019-04-11 Sudakshina Das <sudi.das@arm.com>
2181
2182 * aarch64-asm-2.c: Regenerated.
2183 * aarch64-dis-2.c: Likewise.
2184 * aarch64-opc-2.c: Likewise.
2185 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2186
7e96e219
RS		 21872019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2188
2189 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2190
6f2791d5
L		 21912019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2192
2193 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2194 * i386-init.h: Regenerated.
2195
e392bad3
AM		 21962019-04-07 Alan Modra <amodra@gmail.com>
2197
2198 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2199 op_separator to control printing of spaces, comma and parens
2200 rather than need_comma, need_paren and spaces vars.
2201
dffaa15c
AM		 22022019-04-07 Alan Modra <amodra@gmail.com>
2203
2204 PR 24421
2205 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2206 (print_insn_neon, print_insn_arm): Likewise.
2207
d6aab7a1
XG		 22082019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2209
2210 * i386-dis-evex.h (evex_table): Updated to support BF16
2211 instructions.
2212 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2213 and EVEX_W_0F3872_P_3.
2214 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2215 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2216 * i386-opc.h (enum): Add CpuAVX512_BF16.
2217 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2218 * i386-opc.tbl: Add AVX512 BF16 instructions.
2219 * i386-init.h: Regenerated.
2220 * i386-tbl.h: Likewise.
2221
66e85460
AM		 22222019-04-05 Alan Modra <amodra@gmail.com>
2223
2224 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2225 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2226 to favour printing of "-" branch hint when using the "y" bit.
2227 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2228
c2b1c275
AM		 22292019-04-05 Alan Modra <amodra@gmail.com>
2230
2231 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2232 opcode until first operand is output.
2233
aae9718e
PB		 22342019-04-04 Peter Bergner <bergner@linux.ibm.com>
2235
2236 PR gas/24349
2237 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2238 (valid_bo_post_v2): Add support for 'at' branch hints.
2239 (insert_bo): Only error on branch on ctr.
2240 (get_bo_hint_mask): New function.
2241 (insert_boe): Add new 'branch_taken' formal argument. Add support
2242 for inserting 'at' branch hints.
2243 (extract_boe): Add new 'branch_taken' formal argument. Add support
2244 for extracting 'at' branch hints.
2245 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2246 (BOE): Delete operand.
2247 (BOM, BOP): New operands.
2248 (RM): Update value.
2249 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2250 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2251 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2252 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2253 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2254 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2255 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2256 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2257 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2258 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2259 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2260 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2261 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2262 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2263 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2264 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2265 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2266 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2267 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2268 bttarl+>: New extended mnemonics.
2269
96a86c01
AM		 22702019-03-28 Alan Modra <amodra@gmail.com>
2271
2272 PR 24390
2273 * ppc-opc.c (BTF): Define.
2274 (powerpc_opcodes): Use for mtfsb*.
2275 * ppc-dis.c (print_insn_powerpc): Print fields with both
2276 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2277
796d6298
TC		 22782019-03-25 Tamar Christina <tamar.christina@arm.com>
2279
2280 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2281 (mapping_symbol_for_insn): Implement new algorithm.
2282 (print_insn): Remove duplicate code.
2283
60df3720
TC		 22842019-03-25 Tamar Christina <tamar.christina@arm.com>
2285
2286 * aarch64-dis.c (print_insn_aarch64):
2287 Implement override.
2288
51457761
TC		 22892019-03-25 Tamar Christina <tamar.christina@arm.com>
2290
2291 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2292 order.
2293
53b2f36b
TC		 22942019-03-25 Tamar Christina <tamar.christina@arm.com>
2295
2296 * aarch64-dis.c (last_stop_offset): New.
2297 (print_insn_aarch64): Use stop_offset.
2298
89199bb5
L		 22992019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2300
2301 PR gas/24359
2302 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2303 CPU_ANY_AVX2_FLAGS.
2304 * i386-init.h: Regenerated.
2305
97ed31ae
L		 23062019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2307
2308 PR gas/24348
2309 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2310 vmovdqu16, vmovdqu32 and vmovdqu64.
2311 * i386-tbl.h: Regenerated.
2312
0919bfe9
AK		 23132019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2314
2315 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2316 from vstrszb, vstrszh, and vstrszf.
2317
23182019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2319
2320 * s390-opc.txt: Add instruction descriptions.
2321
21820ebe
JW		 23222019-02-08 Jim Wilson <jimw@sifive.com>
2323
2324 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2325 <bne>: Likewise.
2326
f7dd2fb2
TC		 23272019-02-07 Tamar Christina <tamar.christina@arm.com>
2328
2329 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2330
6456d318
TC		 23312019-02-07 Tamar Christina <tamar.christina@arm.com>
2332
2333 PR binutils/23212
2334 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2335 * aarch64-opc.c (verify_elem_sd): New.
2336 (fields): Add FLD_sz entr.
2337 * aarch64-tbl.h (_SIMD_INSN): New.
2338 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2339 fmulx scalar and vector by element isns.
2340
4a83b610
NC		 23412019-02-07 Nick Clifton <nickc@redhat.com>
2342
2343 * po/sv.po: Updated Swedish translation.
2344
fc60b8c8
AK		 23452019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2346
2347 * s390-mkopc.c (main): Accept arch13 as cpu string.
2348 * s390-opc.c: Add new instruction formats and instruction opcode
2349 masks.
2350 * s390-opc.txt: Add new arch13 instructions.
2351
e10620d3
TC		 23522019-01-25 Sudakshina Das <sudi.das@arm.com>
2353
2354 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2355 (aarch64_opcode): Change encoding for stg, stzg
2356 st2g and st2zg.
2357 * aarch64-asm-2.c: Regenerated.
2358 * aarch64-dis-2.c: Regenerated.
2359 * aarch64-opc-2.c: Regenerated.
2360
20a4ca55
SD		 23612019-01-25 Sudakshina Das <sudi.das@arm.com>
2362
2363 * aarch64-asm-2.c: Regenerated.
2364 * aarch64-dis-2.c: Likewise.
2365 * aarch64-opc-2.c: Likewise.
2366 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2367
550fd7bf
SD		 23682019-01-25 Sudakshina Das <sudi.das@arm.com>
2369 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2370
2371 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2372 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2373 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2374 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2375 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2376 case for ldstgv_indexed.
2377 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2378 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2379 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2380 * aarch64-asm-2.c: Regenerated.
2381 * aarch64-dis-2.c: Regenerated.
2382 * aarch64-opc-2.c: Regenerated.
2383
d9938630
NC		 23842019-01-23 Nick Clifton <nickc@redhat.com>
2385
2386 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2387
375cd423
NC		 23882019-01-21 Nick Clifton <nickc@redhat.com>
2389
2390 * po/de.po: Updated German translation.
2391 * po/uk.po: Updated Ukranian translation.
2392
57299f48
CX		 23932019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2394 * mips-dis.c (mips_arch_choices): Fix typo in
2395 gs464, gs464e and gs264e descriptors.
2396
f48dfe41
NC		 23972019-01-19 Nick Clifton <nickc@redhat.com>
2398
2399 * configure: Regenerate.
2400 * po/opcodes.pot: Regenerate.
2401
f974f26c
NC		 24022018-06-24 Nick Clifton <nickc@redhat.com>
2403
2404 2.32 branch created.
2405
39f286cd
JD		 24062019-01-09 John Darrington <john@darrington.wattle.id.au>
2407
448b8ca8
JD		 2408 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2409 if it is null.
2410 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2411 zero.
2412
3107326d
AP		 24132019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2414
2415 * configure: Regenerate.
2416
7e9ca91e
AM		 24172019-01-07 Alan Modra <amodra@gmail.com>
2418
2419 * configure: Regenerate.
2420 * po/POTFILES.in: Regenerate.
2421
ef1ad42b
JD		 24222019-01-03 John Darrington <john@darrington.wattle.id.au>
2423
2424 * s12z-opc.c: New file.
2425 * s12z-opc.h: New file.
2426 * s12z-dis.c: Removed all code not directly related to display
2427 of instructions. Used the interface provided by the new files
2428 instead.
2429 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2430 * Makefile.in: Regenerate.
ef1ad42b 2431 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2432 * configure: Regenerate.
ef1ad42b 2433
82704155
AM		 24342019-01-01 Alan Modra <amodra@gmail.com>
2435
2436 Update year range in copyright notice of all files.
2437
d5c04e1b 2438For older changes see ChangeLog-2018
3499769a 2439\f
d5c04e1b 2440Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2441
2442Copying and distribution of this file, with or without modification,
2443are permitted in any medium without royalty provided the copyright
2444notice and this notice are preserved.
2445
2446Local Variables:
2447mode: change-log
2448left-margin: 8
2449fill-column: 74
2450version-control: never
2451End:
GDB Binutils - Deliverables
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