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Display system registers by their names when disassembling RL78 instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
46662804
VK		 12015-10-27 Vinay Kumar <vinay.g@kpit.com>
2
3 PR binutils/19158
4 * rl78-decode.opc: Add 's' print operator to instructions that
5 access system registers.
6 * rl78-decode.c: Regenerate.
7 * rl78-dis.c (print_insn_rl78_common): Decode all system
8 registers.
9
02f12cd4
VK		 102015-10-27 Vinay Kumar <vinay.g@kpit.com>
11
12 PR binutils/19157
13 * rl78-decode.opc: Add 'a' print operator to mov instructions
14 using stack pointer plus index addressing.
15 * rl78-decode.c: Regenerate.
16
485f23cf
AK		 172015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
18
19 * s390-opc.c: Fix comment.
20 * s390-opc.txt: Change instruction type for troo, trot, trto, and
21 trtt to RRF_U0RER since the second parameter does not need to be a
22 register pair.
23
3f94e60d
NC		 242015-10-08 Nick Clifton <nickc@redhat.com>
25
26 * arc-dis.c (print_insn_arc): Initiallise insn array.
27
875880c6
YQ		 282015-10-07 Yao Qi <yao.qi@linaro.org>
29
30 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
31 'name' rather than 'template'.
32 * aarch64-opc.c (aarch64_print_operand): Likewise.
33
886a2506
NC		 342015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
35
36 * arc-dis.c: Revamped file for ARC support
37 * arc-dis.h: Likewise.
38 * arc-ext.c: Likewise.
39 * arc-ext.h: Likewise.
40 * arc-opc.c: Likewise.
41 * arc-fxi.h: New file.
42 * arc-regs.h: Likewise.
43 * arc-tbl.h: Likewise.
44
36f4aab1
YQ		 452015-10-02 Yao Qi <yao.qi@linaro.org>
46
47 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
48 argument insn type to aarch64_insn. Rename to ...
49 (aarch64_decode_insn): ... it.
50 (print_insn_aarch64_word): Caller updated.
51
7232d389
YQ		 522015-10-02 Yao Qi <yao.qi@linaro.org>
53
54 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
55 (print_insn_aarch64_word): Caller updated.
56
7ecc513a
DV		 572015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
58
59 * s390-mkopc.c (main): Parse htm and vx flag.
60 * s390-opc.txt: Mark instructions from the hardware transactional
61 memory and vector facilities with the "htm"/"vx" flag.
62
b08b78e7
NC		 632015-09-28 Nick Clifton <nickc@redhat.com>
64
65 * po/de.po: Updated German translation.
66
36f7a941
TR		 672015-09-28 Tom Rix <tom@bumblecow.com>
68
69 * ppc-opc.c (PPC500): Mark some opcodes as invalid
70
b6518b38
NC		 712015-09-23 Nick Clifton <nickc@redhat.com>
72
73 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
74 function.
75 * tic30-dis.c (print_branch): Likewise.
76 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
77 value before left shifting.
78 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
79 * hppa-dis.c (print_insn_hppa): Likewise.
80 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
81 array.
82 * msp430-dis.c (msp430_singleoperand): Likewise.
83 (msp430_doubleoperand): Likewise.
84 (print_insn_msp430): Likewise.
85 * nds32-asm.c (parse_operand): Likewise.
86 * sh-opc.h (MASK): Likewise.
87 * v850-dis.c (get_operand_value): Likewise.
88
f04265ec
NC		 892015-09-22 Nick Clifton <nickc@redhat.com>
90
91 * rx-decode.opc (bwl): Use RX_Bad_Size.
92 (sbwl): Likewise.
93 (ubwl): Likewise. Rename to ubw.
94 (uBWL): Rename to uBW.
95 Replace all references to uBWL with uBW.
96 * rx-decode.c: Regenerate.
97 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
98 (opsize_names): Likewise.
99 (print_insn_rx): Detect and report RX_Bad_Size.
100
6dca4fd1
AB		 1012015-09-22 Anton Blanchard <anton@samba.org>
102
103 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
104
38074311
JM		 1052015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
106
107 * sparc-dis.c (print_insn_sparc): Handle the privileged register
108 %pmcdper.
109
5f40e14d
JS		 1102015-08-24 Jan Stancek <jstancek@redhat.com>
111
112 * i386-dis.c (print_insn): Fix decoding of three byte operands.
113
ab4e4ed5
AF		 1142015-08-21 Alexander Fomin <alexander.fomin@intel.com>
115
116 PR binutils/18257
117 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
118 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
119 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
120 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
121 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
122 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
123 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
124 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
125 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
126 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
127 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
128 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
129 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
130 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
131 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
132 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
133 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
134 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
135 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
136 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
137 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
138 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
139 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
140 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
141 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
142 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
143 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
144 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
145 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
146 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
147 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
148 (vex_w_table): Replace terminals with MOD_TABLE entries for
149 most of mask instructions.
150
919b75f7
AM		 1512015-08-17 Alan Modra <amodra@gmail.com>
152
153 * cgen.sh: Trim trailing space from cgen output.
154 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
155 (print_dis_table): Likewise.
156 * opc2c.c (dump_lines): Likewise.
157 (orig_filename): Warning fix.
158 * ia64-asmtab.c: Regenerate.
159
4ab90a7a
AV		 1602015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
161
162 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
163 and higher with ARM instruction set will now mark the 26-bit
164 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
165 (arm_opcodes): Fix for unpredictable nop being recognized as a
166 teq.
167
40fc1451
SD		 1682015-08-12 Simon Dardis <simon.dardis@imgtec.com>
169
170 * micromips-opc.c (micromips_opcodes): Re-order table so that move
171 based on 'or' is first.
172 * mips-opc.c (mips_builtin_opcodes): Ditto.
173
922c5db5
NC		 1742015-08-11 Nick Clifton <nickc@redhat.com>
175
176 PR 18800
177 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
178 instruction.
179
75fb7498
RS		 1802015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
181
182 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
183
36aed29d
AP		 1842015-08-07 Amit Pawar <Amit.Pawar@amd.com>
185
186 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
187 * i386-init.h: Regenerated.
188
a8484f96
L		 1892015-07-30 H.J. Lu <hongjiu.lu@intel.com>
190
191 PR binutils/13571
192 * i386-dis.c (MOD_0FC3): New.
193 (PREFIX_0FC3): Renamed to ...
194 (PREFIX_MOD_0_0FC3): This.
195 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
196 (prefix_table): Replace Ma with Ev on movntiS.
197 (mod_table): Add MOD_0FC3.
198
37a42ee9
L		 1992015-07-27 H.J. Lu <hongjiu.lu@intel.com>
200
201 * configure: Regenerated.
202
070fe95d
AM		 2032015-07-23 Alan Modra <amodra@gmail.com>
204
205 PR 18708
206 * i386-dis.c (get64): Avoid signed integer overflow.
207
20c2a615
L		 2082015-07-22 Alexander Fomin <alexander.fomin@intel.com>
209
210 PR binutils/18631
211 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
212 "EXEvexHalfBcstXmmq" for the second operand.
213 (EVEX_W_0F79_P_2): Likewise.
214 (EVEX_W_0F7A_P_2): Likewise.
215 (EVEX_W_0F7B_P_2): Likewise.
216
6f1c2142
AM		 2172015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
218
219 * arm-dis.c (print_insn_coprocessor): Added support for quarter
220 float bitfield format.
221 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
222 quarter float bitfield format.
223
8a643cc3
L		 2242015-07-14 H.J. Lu <hongjiu.lu@intel.com>
225
226 * configure: Regenerated.
227
ef5a96d5
AM		 2282015-07-03 Alan Modra <amodra@gmail.com>
229
230 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
231 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
232 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
233
c8c8175b
SL		 2342015-07-01 Sandra Loosemore <sandra@codesourcery.com>
235 Cesar Philippidis <cesar@codesourcery.com>
236
237 * nios2-dis.c (nios2_extract_opcode): New.
238 (nios2_disassembler_state): New.
239 (nios2_find_opcode_hash): Use mach parameter to select correct
240 disassembler state.
241 (nios2_print_insn_arg): Extend to support new R2 argument letters
242 and formats.
243 (print_insn_nios2): Check for 16-bit instruction at end of memory.
244 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
245 (NIOS2_NUM_OPCODES): Rename to...
246 (NIOS2_NUM_R1_OPCODES): This.
247 (nios2_r2_opcodes): New.
248 (NIOS2_NUM_R2_OPCODES): New.
249 (nios2_num_r2_opcodes): New.
250 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
251 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
252 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
253 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
254 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
255
9916071f
AP		 2562015-06-30 Amit Pawar <Amit.Pawar@amd.com>
257
258 * i386-dis.c (OP_Mwaitx): New.
259 (rm_table): Add monitorx/mwaitx.
260 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
261 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
262 (operand_type_init): Add CpuMWAITX.
263 * i386-opc.h (CpuMWAITX): New.
264 (i386_cpu_flags): Add cpumwaitx.
265 * i386-opc.tbl: Add monitorx and mwaitx.
266 * i386-init.h: Regenerated.
267 * i386-tbl.h: Likewise.
268
7b934113
PB		 2692015-06-22 Peter Bergner <bergner@vnet.ibm.com>
270
271 * ppc-opc.c (insert_ls): Test for invalid LS operands.
272 (insert_esync): New function.
273 (LS, WC): Use insert_ls.
274 (ESYNC): Use insert_esync.
275
bdc4de1b
NC		 2762015-06-22 Nick Clifton <nickc@redhat.com>
277
278 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
279 requested region lies beyond it.
280 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
281 looking for 32-bit insns.
282 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
283 data.
284 * sh-dis.c (print_insn_sh): Likewise.
285 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
286 blocks of instructions.
287 * vax-dis.c (print_insn_vax): Check that the requested address
288 does not clash with the stop_vma.
289
11a0cf2e
PB		 2902015-06-19 Peter Bergner <bergner@vnet.ibm.com>
291
070fe95d 292 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 293 * ppc-opc.c (FXM4): Add non-zero optional value.
294 (TBR): Likewise.
295 (SXL): Likewise.
296 (insert_fxm): Handle new default operand value.
297 (extract_fxm): Likewise.
298 (insert_tbr): Likewise.
299 (extract_tbr): Likewise.
300
bdfa8b95
MW		 3012015-06-16 Matthew Wahab <matthew.wahab@arm.com>
302
303 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
304
24b4cf66
SN		 3052015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
306
307 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
308
99a2c561
PB		 3092015-06-12 Peter Bergner <bergner@vnet.ibm.com>
310
311 * ppc-opc.c: Add comment accidentally removed by old commit.
312 (MTMSRD_L): Delete.
313
40f77f82
AM		 3142015-06-04 Peter Bergner <bergner@vnet.ibm.com>
315
316 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
317
13be46a2
NC		 3182015-06-04 Nick Clifton <nickc@redhat.com>
319
320 PR 18474
321 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
322
ddfded2f
MW		 3232015-06-02 Matthew Wahab <matthew.wahab@arm.com>
324
325 * arm-dis.c (arm_opcodes): Add "setpan".
326 (thumb_opcodes): Add "setpan".
327
1af1dd51
MW		 3282015-06-02 Matthew Wahab <matthew.wahab@arm.com>
329
330 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
331 macros.
332
9e1f0fa7
MW		 3332015-06-02 Matthew Wahab <matthew.wahab@arm.com>
334
335 * aarch64-tbl.h (aarch64_feature_rdma): New.
336 (RDMA): New.
337 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
338 * aarch64-asm-2.c: Regenerate.
339 * aarch64-dis-2.c: Regenerate.
340 * aarch64-opc-2.c: Regenerate.
341
290806fd
MW		 3422015-06-02 Matthew Wahab <matthew.wahab@arm.com>
343
344 * aarch64-tbl.h (aarch64_feature_lor): New.
345 (LOR): New.
346 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
347 "stllrb", "stllrh".
348 * aarch64-asm-2.c: Regenerate.
349 * aarch64-dis-2.c: Regenerate.
350 * aarch64-opc-2.c: Regenerate.
351
f21cce2c
MW		 3522015-06-01 Matthew Wahab <matthew.wahab@arm.com>
353
354 * aarch64-opc.c (F_ARCHEXT): New.
355 (aarch64_sys_regs): Add "pan".
356 (aarch64_sys_reg_supported_p): New.
357 (aarch64_pstatefields): Add "pan".
358 (aarch64_pstatefield_supported_p): New.
359
d194d186
JB		 3602015-06-01 Jan Beulich <jbeulich@suse.com>
361
362 * i386-tbl.h: Regenerate.
363
3a8547d2
JB		 3642015-06-01 Jan Beulich <jbeulich@suse.com>
365
366 * i386-dis.c (print_insn): Swap rounding mode specifier and
367 general purpose register in Intel mode.
368
015c54d5
JB		 3692015-06-01 Jan Beulich <jbeulich@suse.com>
370
371 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
372 * i386-tbl.h: Regenerate.
373
071f0063
L		 3742015-05-18 H.J. Lu <hongjiu.lu@intel.com>
375
376 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
377 * i386-init.h: Regenerated.
378
5db04b09
L		 3792015-05-15 H.J. Lu <hongjiu.lu@intel.com>
380
381 PR binutis/18386
382 * i386-dis.c: Add comments for '@'.
383 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
384 (enum x86_64_isa): New.
385 (isa64): Likewise.
386 (print_i386_disassembler_options): Add amd64 and intel64.
387 (print_insn): Handle amd64 and intel64.
388 (putop): Handle '@'.
389 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
390 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
391 * i386-opc.h (AMD64): New.
392 (CpuIntel64): Likewise.
393 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
394 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
395 Mark direct call/jmp without Disp16|Disp32 as Intel64.
396 * i386-init.h: Regenerated.
397 * i386-tbl.h: Likewise.
398
4bc0608a
PB		 3992015-05-14 Peter Bergner <bergner@vnet.ibm.com>
400
401 * ppc-opc.c (IH) New define.
402 (powerpc_opcodes) <wait>: Do not enable for POWER7.
403 <tlbie>: Add RS operand for POWER7.
404 <slbia>: Add IH operand for POWER6.
405
70cead07
L		 4062015-05-11 H.J. Lu <hongjiu.lu@intel.com>
407
408 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
409 direct branch.
410 (jmp): Likewise.
411 * i386-tbl.h: Regenerated.
412
7b6d09fb
L		 4132015-05-11 H.J. Lu <hongjiu.lu@intel.com>
414
415 * configure.ac: Support bfd_iamcu_arch.
416 * disassemble.c (disassembler): Support bfd_iamcu_arch.
417 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
418 CPU_IAMCU_COMPAT_FLAGS.
419 (cpu_flags): Add CpuIAMCU.
420 * i386-opc.h (CpuIAMCU): New.
421 (i386_cpu_flags): Add cpuiamcu.
422 * configure: Regenerated.
423 * i386-init.h: Likewise.
424 * i386-tbl.h: Likewise.
425
31955f99
L		 4262015-05-08 H.J. Lu <hongjiu.lu@intel.com>
427
428 PR binutis/18386
429 * i386-dis.c (X86_64_E8): New.
430 (X86_64_E9): Likewise.
431 Update comments on 'T', 'U', 'V'. Add comments for '^'.
432 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
433 (x86_64_table): Add X86_64_E8 and X86_64_E9.
434 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
435 (putop): Handle '^'.
436 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
437 REX_W.
438
0952813b
DD		 4392015-04-30 DJ Delorie <dj@redhat.com>
440
441 * disassemble.c (disassembler): Choose suitable disassembler based
442 on E_ABI.
443 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
444 it to decode mul/div insns.
445 * rl78-decode.c: Regenerate.
446 * rl78-dis.c (print_insn_rl78): Rename to...
447 (print_insn_rl78_common): ...this, take ISA parameter.
448 (print_insn_rl78): New.
449 (print_insn_rl78_g10): New.
450 (print_insn_rl78_g13): New.
451 (print_insn_rl78_g14): New.
452 (rl78_get_disassembler): New.
453
f9d3ecaa
NC		 4542015-04-29 Nick Clifton <nickc@redhat.com>
455
456 * po/fr.po: Updated French translation.
457
4fff86c5
PB		 4582015-04-27 Peter Bergner <bergner@vnet.ibm.com>
459
460 * ppc-opc.c (DCBT_EO): New define.
461 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
462 <lharx>: Likewise.
463 <stbcx.>: Likewise.
464 <sthcx.>: Likewise.
465 <waitrsv>: Do not enable for POWER7 and later.
466 <waitimpl>: Likewise.
467 <dcbt>: Default to the two operand form of the instruction for all
468 "old" cpus. For "new" cpus, use the operand ordering that matches
469 whether the cpu is server or embedded.
470 <dcbtst>: Likewise.
471
3b78cfe1
AK		 4722015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
473
474 * s390-opc.c: New instruction type VV0UU2.
475 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
476 and WFC.
477
04d824a4
JB		 4782015-04-23 Jan Beulich <jbeulich@suse.com>
479
480 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
481 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
482 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
483 (vfpclasspd, vfpclassps): Add %XZ.
484
09708981
L		 4852015-04-15 H.J. Lu <hongjiu.lu@intel.com>
486
487 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
488 (PREFIX_UD_REPZ): Likewise.
489 (PREFIX_UD_REPNZ): Likewise.
490 (PREFIX_UD_DATA): Likewise.
491 (PREFIX_UD_ADDR): Likewise.
492 (PREFIX_UD_LOCK): Likewise.
493
3888916d
L		 4942015-04-15 H.J. Lu <hongjiu.lu@intel.com>
495
496 * i386-dis.c (prefix_requirement): Removed.
497 (print_insn): Don't set prefix_requirement. Check
498 dp->prefix_requirement instead of prefix_requirement.
499
f24bcbaa
L		 5002015-04-15 H.J. Lu <hongjiu.lu@intel.com>
501
502 PR binutils/17898
503 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
504 (PREFIX_MOD_0_0FC7_REG_6): This.
505 (PREFIX_MOD_3_0FC7_REG_6): New.
506 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
507 (prefix_table): Replace PREFIX_0FC7_REG_6 with
508 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
509 PREFIX_MOD_3_0FC7_REG_7.
510 (mod_table): Replace PREFIX_0FC7_REG_6 with
511 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
512 PREFIX_MOD_3_0FC7_REG_7.
513
507bd325
L		 5142015-04-15 H.J. Lu <hongjiu.lu@intel.com>
515
516 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
517 (PREFIX_MANDATORY_REPNZ): Likewise.
518 (PREFIX_MANDATORY_DATA): Likewise.
519 (PREFIX_MANDATORY_ADDR): Likewise.
520 (PREFIX_MANDATORY_LOCK): Likewise.
521 (PREFIX_MANDATORY): Likewise.
522 (PREFIX_UD_SHIFT): Set to 8
523 (PREFIX_UD_REPZ): Updated.
524 (PREFIX_UD_REPNZ): Likewise.
525 (PREFIX_UD_DATA): Likewise.
526 (PREFIX_UD_ADDR): Likewise.
527 (PREFIX_UD_LOCK): Likewise.
528 (PREFIX_IGNORED_SHIFT): New.
529 (PREFIX_IGNORED_REPZ): Likewise.
530 (PREFIX_IGNORED_REPNZ): Likewise.
531 (PREFIX_IGNORED_DATA): Likewise.
532 (PREFIX_IGNORED_ADDR): Likewise.
533 (PREFIX_IGNORED_LOCK): Likewise.
534 (PREFIX_OPCODE): Likewise.
535 (PREFIX_IGNORED): Likewise.
536 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
537 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
538 (three_byte_table): Likewise.
539 (mod_table): Likewise.
540 (mandatory_prefix): Renamed to ...
541 (prefix_requirement): This.
542 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
543 Update PREFIX_90 entry.
544 (get_valid_dis386): Check prefix_requirement to see if a prefix
545 should be ignored.
546 (print_insn): Replace mandatory_prefix with prefix_requirement.
547
f0fba320
RL		 5482015-04-15 Renlin Li <renlin.li@arm.com>
549
550 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
551 use it for ssat and ssat16.
552 (print_insn_thumb32): Add handle case for 'D' control code.
553
bf890a93
IT		 5542015-04-06 Ilya Tocar <ilya.tocar@intel.com>
555 H.J. Lu <hongjiu.lu@intel.com>
556
557 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
558 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
559 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
560 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
561 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
562 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
563 Fill prefix_requirement field.
564 (struct dis386): Add prefix_requirement field.
565 (dis386): Fill prefix_requirement field.
566 (dis386_twobyte): Ditto.
567 (twobyte_has_mandatory_prefix_: Remove.
568 (reg_table): Fill prefix_requirement field.
569 (prefix_table): Ditto.
570 (x86_64_table): Ditto.
571 (three_byte_table): Ditto.
572 (xop_table): Ditto.
573 (vex_table): Ditto.
574 (vex_len_table): Ditto.
575 (vex_w_table): Ditto.
576 (mod_table): Ditto.
577 (bad_opcode): Ditto.
578 (print_insn): Use prefix_requirement.
579 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
580 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
581 (float_reg): Ditto.
582
2f783c1f
MF		 5832015-03-30 Mike Frysinger <vapier@gentoo.org>
584
585 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
586
b9d94d62
L		 5872015-03-29 H.J. Lu <hongjiu.lu@intel.com>
588
589 * Makefile.in: Regenerated.
590
27c49e9a
AB		 5912015-03-25 Anton Blanchard <anton@samba.org>
592
593 * ppc-dis.c (disassemble_init_powerpc): Only initialise
594 powerpc_opcd_indices and vle_opcd_indices once.
595
c4e676f1
AB		 5962015-03-25 Anton Blanchard <anton@samba.org>
597
598 * ppc-opc.c (powerpc_opcodes): Add slbfee.
599
823d2571
TG		 6002015-03-24 Terry Guo <terry.guo@arm.com>
601
602 * arm-dis.c (opcode32): Updated to use new arm feature struct.
603 (opcode16): Likewise.
604 (coprocessor_opcodes): Replace bit with feature struct.
605 (neon_opcodes): Likewise.
606 (arm_opcodes): Likewise.
607 (thumb_opcodes): Likewise.
608 (thumb32_opcodes): Likewise.
609 (print_insn_coprocessor): Likewise.
610 (print_insn_arm): Likewise.
611 (select_arm_features): Follow new feature struct.
612
029f3522
GG		 6132015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
614
615 * i386-dis.c (rm_table): Add clzero.
616 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
617 Add CPU_CLZERO_FLAGS.
618 (cpu_flags): Add CpuCLZERO.
619 * i386-opc.h: Add CpuCLZERO.
620 * i386-opc.tbl: Add clzero.
621 * i386-init.h: Re-generated.
622 * i386-tbl.h: Re-generated.
623
6914869a
AB		 6242015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
625
626 * mips-opc.c (decode_mips_operand): Fix constraint issues
627 with u and y operands.
628
21e20815
AB		 6292015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
630
631 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
632
6b1d7593
AK		 6332015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
634
635 * s390-opc.c: Add new IBM z13 instructions.
636 * s390-opc.txt: Likewise.
637
c8f89a34
JW		 6382015-03-10 Renlin Li <renlin.li@arm.com>
639
640 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
641 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
642 related alias.
643 * aarch64-asm-2.c: Regenerate.
644 * aarch64-dis-2.c: Likewise.
645 * aarch64-opc-2.c: Likewise.
646
d8282f0e
JW		 6472015-03-03 Jiong Wang <jiong.wang@arm.com>
648
649 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
650
ac994365
OE		 6512015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
652
653 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
654 arch_sh_up.
655 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
656 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
657
fd63f640
V		 6582015-02-23 Vinay <Vinay.G@kpit.com>
659
660 * rl78-decode.opc (MOV): Added space between two operands for
661 'mov' instruction in index addressing mode.
662 * rl78-decode.c: Regenerate.
663
f63c1776
PA		 6642015-02-19 Pedro Alves <palves@redhat.com>
665
666 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
667
07774fcc
PA		 6682015-02-10 Pedro Alves <palves@redhat.com>
669 Tom Tromey <tromey@redhat.com>
670
671 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
672 microblaze_and, microblaze_xor.
673 * microblaze-opc.h (opcodes): Adjust.
674
3f8107ab
AM		 6752015-01-28 James Bowman <james.bowman@ftdichip.com>
676
677 * Makefile.am: Add FT32 files.
678 * configure.ac: Handle FT32.
679 * disassemble.c (disassembler): Call print_insn_ft32.
680 * ft32-dis.c: New file.
681 * ft32-opc.c: New file.
682 * Makefile.in: Regenerate.
683 * configure: Regenerate.
684 * po/POTFILES.in: Regenerate.
685
e5fe4957
KLC		 6862015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
687
688 * nds32-asm.c (keyword_sr): Add new system registers.
689
1e2e8c52
AK		 6902015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
691
692 * s390-dis.c (s390_extract_operand): Support vector register
693 operands.
694 (s390_print_insn_with_opcode): Support new operands types and add
695 new handling of optional operands.
696 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
697 and include opcode/s390.h instead.
698 (struct op_struct): New field `flags'.
699 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
700 (dumpTable): Dump flags.
701 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
702 string.
703 * s390-opc.c: Add new operands types, instruction formats, and
704 instruction masks.
705 (s390_opformats): Add new formats for .insn.
706 * s390-opc.txt: Add new instructions.
707
b90efa5b 7082015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 709
b90efa5b 710 Update year range in copyright notice of all files.
bffb6004 711
b90efa5b 712For older changes see ChangeLog-2014
252b5132 713\f
b90efa5b 714Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 715
716Copying and distribution of this file, with or without modification,
717are permitted in any medium without royalty provided the copyright
718notice and this notice are preserved.
719
252b5132 720Local Variables:
2f6d2f85
NC		 721mode: change-log
722left-margin: 8
723fill-column: 74
252b5132
RH		 724version-control: never
725End:
GDB Binutils - Deliverables
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