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GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
471b9d15
MR		 12018-07-02 Maciej W. Rozycki <macro@mips.com>
2
3 PR tdep/8282
4 * mips-dis.c (mips_option_arg_t): New enumeration.
5 (mips_options): New variable.
6 (disassembler_options_mips): New function.
7 (print_mips_disassembler_options): Reimplement in terms of
8 `disassembler_options_mips'.
9 * arm-dis.c (disassembler_options_arm): Adapt to using the
10 `disasm_options_and_args_t' structure.
11 * ppc-dis.c (disassembler_options_powerpc): Likewise.
12 * s390-dis.c (disassembler_options_s390): Likewise.
13
c0c468d5
TP		 142018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
15
16 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
17 expected result.
18 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
19 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
20 * testsuite/ld-arm/tls-longplt.d: Likewise.
21
369c9167
TC		 222018-06-29 Tamar Christina <tamar.christina@arm.com>
23
24 PR binutils/23192
25 * aarch64-asm-2.c: Regenerate.
26 * aarch64-dis-2.c: Likewise.
27 * aarch64-opc-2.c: Likewise.
28 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
29 * aarch64-opc.c (operand_general_constraint_met_p,
30 aarch64_print_operand): Likewise.
31 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
32 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
33 fmlal2, fmlsl2.
34 (AARCH64_OPERANDS): Add Em2.
35
30aa1306
NC		 362018-06-26 Nick Clifton <nickc@redhat.com>
37
38 * po/uk.po: Updated Ukranian translation.
39 * po/de.po: Updated German translation.
40 * po/pt_BR.po: Updated Brazilian Portuguese translation.
41
eca4b721
NC		 422018-06-26 Nick Clifton <nickc@redhat.com>
43
44 * nfp-dis.c: Fix spelling mistake.
45
71300e2c
NC		 462018-06-24 Nick Clifton <nickc@redhat.com>
47
48 * configure: Regenerate.
49 * po/opcodes.pot: Regenerate.
50
719d8288
NC		 512018-06-24 Nick Clifton <nickc@redhat.com>
52
53 2.31 branch created.
54
514cd3a0
TC		 552018-06-19 Tamar Christina <tamar.christina@arm.com>
56
57 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
58 * aarch64-asm-2.c: Regenerate.
59 * aarch64-dis-2.c: Likewise.
60
385e4d0f
MR		 612018-06-21 Maciej W. Rozycki <macro@mips.com>
62
63 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
64 `-M ginv' option description.
65
160d1b3d
SH		 662018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
67
68 PR gas/23305
69 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
70 la and lla.
71
d0ac1c44
SM		 722018-06-19 Simon Marchi <simon.marchi@ericsson.com>
73
74 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
75 * configure.ac: Remove AC_PREREQ.
76 * Makefile.in: Re-generate.
77 * aclocal.m4: Re-generate.
78 * configure: Re-generate.
79
6f20c942
FS		 802018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
81
82 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
83 mips64r6 descriptors.
84 (parse_mips_ase_option): Handle -Mginv option.
85 (print_mips_disassembler_options): Document -Mginv.
86 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
87 (GINV): New macro.
88 (mips_opcodes): Define ginvi and ginvt.
89
730c3174
SE		 902018-06-13 Scott Egerton <scott.egerton@imgtec.com>
91 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
92
93 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
94 * mips-opc.c (CRC, CRC64): New macros.
95 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
96 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
97 crc32cd for CRC64.
98
cb366992
EB		 992018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
100
101 PR 20319
102 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
103 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
104
ce72cd46
AM		 1052018-06-06 Alan Modra <amodra@gmail.com>
106
107 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
108 setjmp. Move init for some other vars later too.
109
4b8e28c7
MF		 1102018-06-04 Max Filippov <jcmvbkbc@gmail.com>
111
112 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
113 (dis_private): Add new fields for property section tracking.
114 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
115 (xtensa_instruction_fits): New functions.
116 (fetch_data): Bump minimal fetch size to 4.
117 (print_insn_xtensa): Make struct dis_private static.
118 Load and prepare property table on section change.
119 Don't disassemble literals. Don't disassemble instructions that
120 cross property table boundaries.
121
55e99962
L		 1222018-06-01 H.J. Lu <hongjiu.lu@intel.com>
123
124 * configure: Regenerated.
125
733bd0ab
JB		 1262018-06-01 Jan Beulich <jbeulich@suse.com>
127
128 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
129 * i386-tbl.h: Re-generate.
130
dfd27d41
JB		 1312018-06-01 Jan Beulich <jbeulich@suse.com>
132
133 * i386-opc.tbl (sldt, str): Add NoRex64.
134 * i386-tbl.h: Re-generate.
135
64795710
JB		 1362018-06-01 Jan Beulich <jbeulich@suse.com>
137
138 * i386-opc.tbl (invpcid): Add Oword.
139 * i386-tbl.h: Re-generate.
140
030157d8
AM		 1412018-06-01 Alan Modra <amodra@gmail.com>
142
143 * sysdep.h (_bfd_error_handler): Don't declare.
144 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
145 * rl78-decode.opc: Likewise.
146 * msp430-decode.c: Regenerate.
147 * rl78-decode.c: Regenerate.
148
a9660a6f
AP		 1492018-05-30 Amit Pawar <Amit.Pawar@amd.com>
150
151 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
152 * i386-init.h : Regenerated.
153
277eb7f6
AM		 1542018-05-25 Alan Modra <amodra@gmail.com>
155
156 * Makefile.in: Regenerate.
157 * po/POTFILES.in: Regenerate.
158
98553ad3
PB		 1592018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
160
161 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
162 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
163 (insert_bab, extract_bab, insert_btab, extract_btab,
164 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
165 (BAT, BBA VBA RBS XB6S): Delete macros.
166 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
167 (BB, BD, RBX, XC6): Update for new macros.
168 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
169 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
170 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
171 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
172
7b4ae824
JD		 1732018-05-18 John Darrington <john@darrington.wattle.id.au>
174
175 * Makefile.am: Add support for s12z architecture.
176 * configure.ac: Likewise.
177 * disassemble.c: Likewise.
178 * disassemble.h: Likewise.
179 * Makefile.in: Regenerate.
180 * configure: Regenerate.
181 * s12z-dis.c: New file.
182 * s12z.h: New file.
183
29e0f0a1
AM		 1842018-05-18 Alan Modra <amodra@gmail.com>
185
186 * nfp-dis.c: Don't #include libbfd.h.
187 (init_nfp3200_priv): Use bfd_get_section_contents.
188 (nit_nfp6000_mecsr_sec): Likewise.
189
809276d2
NC		 1902018-05-17 Nick Clifton <nickc@redhat.com>
191
192 * po/zh_CN.po: Updated simplified Chinese translation.
193
ff329288
TC		 1942018-05-16 Tamar Christina <tamar.christina@arm.com>
195
196 PR binutils/23109
197 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
198 * aarch64-dis-2.c: Regenerate.
199
f9830ec1
TC		 2002018-05-15 Tamar Christina <tamar.christina@arm.com>
201
202 PR binutils/21446
203 * aarch64-asm.c (opintl.h): Include.
204 (aarch64_ins_sysreg): Enforce read/write constraints.
205 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
206 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
207 (F_REG_READ, F_REG_WRITE): New.
208 * aarch64-opc.c (aarch64_print_operand): Generate notes for
209 AARCH64_OPND_SYSREG.
210 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
211 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
212 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
213 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
214 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
215 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
216 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
217 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
218 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
219 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
220 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
221 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
222 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
223 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
224 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
225 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
226 msr (F_SYS_WRITE), mrs (F_SYS_READ).
227
7d02540a
TC		 2282018-05-15 Tamar Christina <tamar.christina@arm.com>
229
230 PR binutils/21446
231 * aarch64-dis.c (no_notes: New.
232 (parse_aarch64_dis_option): Support notes.
233 (aarch64_decode_insn, print_operands): Likewise.
234 (print_aarch64_disassembler_options): Document notes.
235 * aarch64-opc.c (aarch64_print_operand): Support notes.
236
561a72d4
TC		 2372018-05-15 Tamar Christina <tamar.christina@arm.com>
238
239 PR binutils/21446
240 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
241 and take error struct.
242 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
243 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
244 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
245 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
246 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
247 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
248 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
249 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
250 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
251 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
252 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
253 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
254 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
255 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
256 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
257 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
258 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
259 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
260 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
261 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
262 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
263 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
264 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
265 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
266 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
267 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
268 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
269 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
270 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
271 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
272 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
273 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
274 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
275 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
276 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
277 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
278 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
279 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
280 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
281 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
282 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
283 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
284 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
285 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
286 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
287 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
288 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
289 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
290 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
291 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
292 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
293 (determine_disassembling_preference, aarch64_decode_insn,
294 print_insn_aarch64_word, print_insn_data): Take errors struct.
295 (print_insn_aarch64): Use errors.
296 * aarch64-asm-2.c: Regenerate.
297 * aarch64-dis-2.c: Regenerate.
298 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
299 boolean in aarch64_insert_operan.
300 (print_operand_extractor): Likewise.
301 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
302
1678bd35
FT		 3032018-05-15 Francois H. Theron <francois.theron@netronome.com>
304
305 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
306
06cfb1c8
L		 3072018-05-09 H.J. Lu <hongjiu.lu@intel.com>
308
309 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
310
84f9f8c3
AM		 3112018-05-09 Sebastian Rasmussen <sebras@gmail.com>
312
313 * cr16-opc.c (cr16_instruction): Comment typo fix.
314 * hppa-dis.c (print_insn_hppa): Likewise.
315
e6f372ba
JW		 3162018-05-08 Jim Wilson <jimw@sifive.com>
317
318 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
319 (match_c_slli64, match_srxi_as_c_srxi): New.
320 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
321 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
322 <c.slli, c.srli, c.srai>: Use match_s_slli.
323 <c.slli64, c.srli64, c.srai64>: New.
324
f413a913
AM		 3252018-05-08 Alan Modra <amodra@gmail.com>
326
327 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
328 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
329 partition opcode space for index lookup.
330
a87a6478
PB		 3312018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
332
333 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
334 <insn_length>: ...with this. Update usage.
335 Remove duplicate call to *info->memory_error_func.
336
c0a30a9f
L		 3372018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
338 H.J. Lu <hongjiu.lu@intel.com>
339
340 * i386-dis.c (Gva): New.
341 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
342 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
343 (prefix_table): New instructions (see prefix above).
344 (mod_table): New instructions (see prefix above).
345 (OP_G): Handle va_mode.
346 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
347 CPU_MOVDIR64B_FLAGS.
348 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
349 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
350 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
351 * i386-opc.tbl: Add movidir{i,64b}.
352 * i386-init.h: Regenerated.
353 * i386-tbl.h: Likewise.
354
75c0a438
L		 3552018-05-07 H.J. Lu <hongjiu.lu@intel.com>
356
357 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
358 AddrPrefixOpReg.
359 * i386-opc.h (AddrPrefixOp0): Renamed to ...
360 (AddrPrefixOpReg): This.
361 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
362 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
363
2ceb7719
PB		 3642018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
365
366 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
367 (vle_num_opcodes): Likewise.
368 (spe2_num_opcodes): Likewise.
369 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
370 initialization loop.
371 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
372 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
373 only once.
374
b3ac5c6c
TC		 3752018-05-01 Tamar Christina <tamar.christina@arm.com>
376
377 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
378
fe944acf
FT		 3792018-04-30 Francois H. Theron <francois.theron@netronome.com>
380
381 Makefile.am: Added nfp-dis.c.
382 configure.ac: Added bfd_nfp_arch.
383 disassemble.h: Added print_insn_nfp prototype.
384 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
385 nfp-dis.c: New, for NFP support.
386 po/POTFILES.in: Added nfp-dis.c to the list.
387 Makefile.in: Regenerate.
388 configure: Regenerate.
389
e2195274
JB		 3902018-04-26 Jan Beulich <jbeulich@suse.com>
391
392 * i386-opc.tbl: Fold various non-memory operand AVX512VL
393 templates into their base ones.
394 * i386-tlb.h: Re-generate.
395
59ef5df4
JB		 3962018-04-26 Jan Beulich <jbeulich@suse.com>
397
398 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
399 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
400 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
401 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
402 * i386-init.h: Re-generate.
403
6e041cf4
JB		 4042018-04-26 Jan Beulich <jbeulich@suse.com>
405
406 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
407 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
408 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
409 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
410 comment.
411 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
412 and CpuRegMask.
413 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
414 CpuRegMask: Delete.
415 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
416 cpuregzmm, and cpuregmask.
417 * i386-init.h: Re-generate.
418 * i386-tbl.h: Re-generate.
419
0e0eea78
JB		 4202018-04-26 Jan Beulich <jbeulich@suse.com>
421
422 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
423 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
424 * i386-init.h: Re-generate.
425
2f1bada2
JB		 4262018-04-26 Jan Beulich <jbeulich@suse.com>
427
428 * i386-gen.c (VexImmExt): Delete.
429 * i386-opc.h (VexImmExt, veximmext): Delete.
430 * i386-opc.tbl: Drop all VexImmExt uses.
431 * i386-tlb.h: Re-generate.
432
bacd1457
JB		 4332018-04-25 Jan Beulich <jbeulich@suse.com>
434
435 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
436 register-only forms.
437 * i386-tlb.h: Re-generate.
438
10bba94b
TC		 4392018-04-25 Tamar Christina <tamar.christina@arm.com>
440
441 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
442
c48935d7
IT		 4432018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
444
445 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
446 PREFIX_0F1C.
447 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
448 (cpu_flags): Add CpuCLDEMOTE.
449 * i386-init.h: Regenerate.
450 * i386-opc.h (enum): Add CpuCLDEMOTE,
451 (i386_cpu_flags): Add cpucldemote.
452 * i386-opc.tbl: Add cldemote.
453 * i386-tbl.h: Regenerate.
454
211dc24b
AM		 4552018-04-16 Alan Modra <amodra@gmail.com>
456
457 * Makefile.am: Remove sh5 and sh64 support.
458 * configure.ac: Likewise.
459 * disassemble.c: Likewise.
460 * disassemble.h: Likewise.
461 * sh-dis.c: Likewise.
462 * sh64-dis.c: Delete.
463 * sh64-opc.c: Delete.
464 * sh64-opc.h: Delete.
465 * Makefile.in: Regenerate.
466 * configure: Regenerate.
467 * po/POTFILES.in: Regenerate.
468
a9a4b302
AM		 4692018-04-16 Alan Modra <amodra@gmail.com>
470
471 * Makefile.am: Remove w65 support.
472 * configure.ac: Likewise.
473 * disassemble.c: Likewise.
474 * disassemble.h: Likewise.
475 * w65-dis.c: Delete.
476 * w65-opc.h: Delete.
477 * Makefile.in: Regenerate.
478 * configure: Regenerate.
479 * po/POTFILES.in: Regenerate.
480
04cb01fd
AM		 4812018-04-16 Alan Modra <amodra@gmail.com>
482
483 * configure.ac: Remove we32k support.
484 * configure: Regenerate.
485
c2bf1eec
AM		 4862018-04-16 Alan Modra <amodra@gmail.com>
487
488 * Makefile.am: Remove m88k support.
489 * configure.ac: Likewise.
490 * disassemble.c: Likewise.
491 * disassemble.h: Likewise.
492 * m88k-dis.c: Delete.
493 * Makefile.in: Regenerate.
494 * configure: Regenerate.
495 * po/POTFILES.in: Regenerate.
496
6793974d
AM		 4972018-04-16 Alan Modra <amodra@gmail.com>
498
499 * Makefile.am: Remove i370 support.
500 * configure.ac: Likewise.
501 * disassemble.c: Likewise.
502 * disassemble.h: Likewise.
503 * i370-dis.c: Delete.
504 * i370-opc.c: Delete.
505 * Makefile.in: Regenerate.
506 * configure: Regenerate.
507 * po/POTFILES.in: Regenerate.
508
e82aa794
AM		 5092018-04-16 Alan Modra <amodra@gmail.com>
510
511 * Makefile.am: Remove h8500 support.
512 * configure.ac: Likewise.
513 * disassemble.c: Likewise.
514 * disassemble.h: Likewise.
515 * h8500-dis.c: Delete.
516 * h8500-opc.h: Delete.
517 * Makefile.in: Regenerate.
518 * configure: Regenerate.
519 * po/POTFILES.in: Regenerate.
520
fceadf09
AM		 5212018-04-16 Alan Modra <amodra@gmail.com>
522
523 * configure.ac: Remove tahoe support.
524 * configure: Regenerate.
525
ae1d3843
L		 5262018-04-15 H.J. Lu <hongjiu.lu@intel.com>
527
528 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
529 umwait.
530 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
531 64-bit mode.
532 * i386-tbl.h: Regenerated.
533
de89d0a3
IT		 5342018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
535
536 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
537 PREFIX_MOD_1_0FAE_REG_6.
538 (va_mode): New.
539 (OP_E_register): Use va_mode.
540 * i386-dis-evex.h (prefix_table):
541 New instructions (see prefixes above).
542 * i386-gen.c (cpu_flag_init): Add WAITPKG.
543 (cpu_flags): Likewise.
544 * i386-opc.h (enum): Likewise.
545 (i386_cpu_flags): Likewise.
546 * i386-opc.tbl: Add umonitor, umwait, tpause.
547 * i386-init.h: Regenerate.
548 * i386-tbl.h: Likewise.
549
a8eb42a8
AM		 5502018-04-11 Alan Modra <amodra@gmail.com>
551
552 * opcodes/i860-dis.c: Delete.
553 * opcodes/i960-dis.c: Delete.
554 * Makefile.am: Remove i860 and i960 support.
555 * configure.ac: Likewise.
556 * disassemble.c: Likewise.
557 * disassemble.h: Likewise.
558 * Makefile.in: Regenerate.
559 * configure: Regenerate.
560 * po/POTFILES.in: Regenerate.
561
caf0678c
L		 5622018-04-04 H.J. Lu <hongjiu.lu@intel.com>
563
564 PR binutils/23025
565 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
566 to 0.
567 (print_insn): Clear vex instead of vex.evex.
568
4fb0d2b9
NC		 5692018-04-04 Nick Clifton <nickc@redhat.com>
570
571 * po/es.po: Updated Spanish translation.
572
c39e5b26
JB		 5732018-03-28 Jan Beulich <jbeulich@suse.com>
574
575 * i386-gen.c (opcode_modifiers): Delete VecESize.
576 * i386-opc.h (VecESize): Delete.
577 (struct i386_opcode_modifier): Delete vecesize.
578 * i386-opc.tbl: Drop VecESize.
579 * i386-tlb.h: Re-generate.
580
8e6e0792
JB		 5812018-03-28 Jan Beulich <jbeulich@suse.com>
582
583 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
584 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
585 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
586 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
587 * i386-tlb.h: Re-generate.
588
9f123b91
JB		 5892018-03-28 Jan Beulich <jbeulich@suse.com>
590
591 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
592 Fold AVX512 forms
593 * i386-tlb.h: Re-generate.
594
9646c87b
JB		 5952018-03-28 Jan Beulich <jbeulich@suse.com>
596
597 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
598 (vex_len_table): Drop Y for vcvt*2si.
599 (putop): Replace plain 'Y' handling by abort().
600
c8d59609
NC		 6012018-03-28 Nick Clifton <nickc@redhat.com>
602
603 PR 22988
604 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
605 instructions with only a base address register.
606 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
607 handle AARHC64_OPND_SVE_ADDR_R.
608 (aarch64_print_operand): Likewise.
609 * aarch64-asm-2.c: Regenerate.
610 * aarch64_dis-2.c: Regenerate.
611 * aarch64-opc-2.c: Regenerate.
612
b8c169f3
JB		 6132018-03-22 Jan Beulich <jbeulich@suse.com>
614
615 * i386-opc.tbl: Drop VecESize from register only insn forms and
616 memory forms not allowing broadcast.
617 * i386-tlb.h: Re-generate.
618
96bc132a
JB		 6192018-03-22 Jan Beulich <jbeulich@suse.com>
620
621 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
622 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
623 sha256*): Drop Disp<N>.
624
9f79e886
JB		 6252018-03-22 Jan Beulich <jbeulich@suse.com>
626
627 * i386-dis.c (EbndS, bnd_swap_mode): New.
628 (prefix_table): Use EbndS.
629 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
630 * i386-opc.tbl (bndmov): Move misplaced Load.
631 * i386-tlb.h: Re-generate.
632
d6793fa1
JB		 6332018-03-22 Jan Beulich <jbeulich@suse.com>
634
635 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
636 templates allowing memory operands and folded ones for register
637 only flavors.
638 * i386-tlb.h: Re-generate.
639
f7768225
JB		 6402018-03-22 Jan Beulich <jbeulich@suse.com>
641
642 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
643 256-bit templates. Drop redundant leftover Disp<N>.
644 * i386-tlb.h: Re-generate.
645
0e35537d
JW		 6462018-03-14 Kito Cheng <kito.cheng@gmail.com>
647
648 * riscv-opc.c (riscv_insn_types): New.
649
b4a3689a
NC		 6502018-03-13 Nick Clifton <nickc@redhat.com>
651
652 * po/pt_BR.po: Updated Brazilian Portuguese translation.
653
d3d50934
L		 6542018-03-08 H.J. Lu <hongjiu.lu@intel.com>
655
656 * i386-opc.tbl: Add Optimize to clr.
657 * i386-tbl.h: Regenerated.
658
bd5dea88
L		 6592018-03-08 H.J. Lu <hongjiu.lu@intel.com>
660
661 * i386-gen.c (opcode_modifiers): Remove OldGcc.
662 * i386-opc.h (OldGcc): Removed.
663 (i386_opcode_modifier): Remove oldgcc.
664 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
665 instructions for old (<= 2.8.1) versions of gcc.
666 * i386-tbl.h: Regenerated.
667
e771e7c9
JB		 6682018-03-08 Jan Beulich <jbeulich@suse.com>
669
670 * i386-opc.h (EVEXDYN): New.
671 * i386-opc.tbl: Fold various AVX512VL templates.
672 * i386-tlb.h: Re-generate.
673
ed438a93
JB		 6742018-03-08 Jan Beulich <jbeulich@suse.com>
675
676 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
677 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
678 vpexpandd, vpexpandq): Fold AFX512VF templates.
679 * i386-tlb.h: Re-generate.
680
454172a9
JB		 6812018-03-08 Jan Beulich <jbeulich@suse.com>
682
683 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
684 Fold 128- and 256-bit VEX-encoded templates.
685 * i386-tlb.h: Re-generate.
686
36824150
JB		 6872018-03-08 Jan Beulich <jbeulich@suse.com>
688
689 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
690 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
691 vpexpandd, vpexpandq): Fold AVX512F templates.
692 * i386-tlb.h: Re-generate.
693
e7f5c0a9
JB		 6942018-03-08 Jan Beulich <jbeulich@suse.com>
695
696 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
697 64-bit templates. Drop Disp<N>.
698 * i386-tlb.h: Re-generate.
699
25a4277f
JB		 7002018-03-08 Jan Beulich <jbeulich@suse.com>
701
702 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
703 and 256-bit templates.
704 * i386-tlb.h: Re-generate.
705
d2224064
JB		 7062018-03-08 Jan Beulich <jbeulich@suse.com>
707
708 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
709 * i386-tlb.h: Re-generate.
710
1b193f0b
JB		 7112018-03-08 Jan Beulich <jbeulich@suse.com>
712
713 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
714 Drop NoAVX.
715 * i386-tlb.h: Re-generate.
716
f2f6a710
JB		 7172018-03-08 Jan Beulich <jbeulich@suse.com>
718
719 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
720 * i386-tlb.h: Re-generate.
721
38e314eb
JB		 7222018-03-08 Jan Beulich <jbeulich@suse.com>
723
724 * i386-gen.c (opcode_modifiers): Delete FloatD.
725 * i386-opc.h (FloatD): Delete.
726 (struct i386_opcode_modifier): Delete floatd.
727 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
728 FloatD by D.
729 * i386-tlb.h: Re-generate.
730
d53e6b98
JB		 7312018-03-08 Jan Beulich <jbeulich@suse.com>
732
733 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
734
2907c2f5
JB		 7352018-03-08 Jan Beulich <jbeulich@suse.com>
736
737 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
738 * i386-tlb.h: Re-generate.
739
73053c1f
JB		 7402018-03-08 Jan Beulich <jbeulich@suse.com>
741
742 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
743 forms.
744 * i386-tlb.h: Re-generate.
745
52fe4420
AM		 7462018-03-07 Alan Modra <amodra@gmail.com>
747
748 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
749 bfd_arch_rs6000.
750 * disassemble.h (print_insn_rs6000): Delete.
751 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
752 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
753 (print_insn_rs6000): Delete.
754
a6743a54
AM		 7552018-03-03 Alan Modra <amodra@gmail.com>
756
757 * sysdep.h (opcodes_error_handler): Define.
758 (_bfd_error_handler): Declare.
759 * Makefile.am: Remove stray #.
760 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
761 EDIT" comment.
762 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
763 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
764 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
765 opcodes_error_handler to print errors. Standardize error messages.
766 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
767 and include opintl.h.
768 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
769 * i386-gen.c: Standardize error messages.
770 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
771 * Makefile.in: Regenerate.
772 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
773 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
774 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
775 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
776 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
777 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
778 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
779 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
780 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
781 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
782 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
783 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
784 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
785
8305403a
L		 7862018-03-01 H.J. Lu <hongjiu.lu@intel.com>
787
788 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
789 vpsub[bwdq] instructions.
790 * i386-tbl.h: Regenerated.
791
e184813f
AM		 7922018-03-01 Alan Modra <amodra@gmail.com>
793
794 * configure.ac (ALL_LINGUAS): Sort.
795 * configure: Regenerate.
796
5b616bef
TP		 7972018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
798
799 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
800 macro by assignements.
801
b6f8c7c4
L		 8022018-02-27 H.J. Lu <hongjiu.lu@intel.com>
803
804 PR gas/22871
805 * i386-gen.c (opcode_modifiers): Add Optimize.
806 * i386-opc.h (Optimize): New enum.
807 (i386_opcode_modifier): Add optimize.
808 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
809 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
810 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
811 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
812 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
813 vpxord and vpxorq.
814 * i386-tbl.h: Regenerated.
815
e95b887f
AM		 8162018-02-26 Alan Modra <amodra@gmail.com>
817
818 * crx-dis.c (getregliststring): Allocate a large enough buffer
819 to silence false positive gcc8 warning.
820
0bccfb29
JW		 8212018-02-22 Shea Levy <shea@shealevy.com>
822
823 * disassemble.c (ARCH_riscv): Define if ARCH_all.
824
6b6b6807
L		 8252018-02-22 H.J. Lu <hongjiu.lu@intel.com>
826
827 * i386-opc.tbl: Add {rex},
828 * i386-tbl.h: Regenerated.
829
75f31665
MR		 8302018-02-20 Maciej W. Rozycki <macro@mips.com>
831
832 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
833 (mips16_opcodes): Replace `M' with `m' for "restore".
834
e207bc53
TP		 8352018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
836
837 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
838
87993319
MR		 8392018-02-13 Maciej W. Rozycki <macro@mips.com>
840
841 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
842 variable to `function_index'.
843
68d20676
NC		 8442018-02-13 Nick Clifton <nickc@redhat.com>
845
846 PR 22823
847 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
848 about truncation of printing.
849
d2159fdc
HW		 8502018-02-12 Henry Wong <henry@stuffedcow.net>
851
852 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
853
f174ef9f
NC		 8542018-02-05 Nick Clifton <nickc@redhat.com>
855
856 * po/pt_BR.po: Updated Brazilian Portuguese translation.
857
be3a8dca
IT		 8582018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
859
860 * i386-dis.c (enum): Add pconfig.
861 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
862 (cpu_flags): Add CpuPCONFIG.
863 * i386-opc.h (enum): Add CpuPCONFIG.
864 (i386_cpu_flags): Add cpupconfig.
865 * i386-opc.tbl: Add PCONFIG instruction.
866 * i386-init.h: Regenerate.
867 * i386-tbl.h: Likewise.
868
3233d7d0
IT		 8692018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
870
871 * i386-dis.c (enum): Add PREFIX_0F09.
872 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
873 (cpu_flags): Add CpuWBNOINVD.
874 * i386-opc.h (enum): Add CpuWBNOINVD.
875 (i386_cpu_flags): Add cpuwbnoinvd.
876 * i386-opc.tbl: Add WBNOINVD instruction.
877 * i386-init.h: Regenerate.
878 * i386-tbl.h: Likewise.
879
e925c834
JW		 8802018-01-17 Jim Wilson <jimw@sifive.com>
881
882 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
883
d777820b
IT		 8842018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
885
886 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
887 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
888 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
889 (cpu_flags): Add CpuIBT, CpuSHSTK.
890 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
891 (i386_cpu_flags): Add cpuibt, cpushstk.
892 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
893 * i386-init.h: Regenerate.
894 * i386-tbl.h: Likewise.
895
f6efed01
NC		 8962018-01-16 Nick Clifton <nickc@redhat.com>
897
898 * po/pt_BR.po: Updated Brazilian Portugese translation.
899 * po/de.po: Updated German translation.
900
2721d702
JW		 9012018-01-15 Jim Wilson <jimw@sifive.com>
902
903 * riscv-opc.c (match_c_nop): New.
904 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
905
616dcb87
NC		 9062018-01-15 Nick Clifton <nickc@redhat.com>
907
908 * po/uk.po: Updated Ukranian translation.
909
3957a496
NC		 9102018-01-13 Nick Clifton <nickc@redhat.com>
911
912 * po/opcodes.pot: Regenerated.
913
769c7ea5
NC		 9142018-01-13 Nick Clifton <nickc@redhat.com>
915
916 * configure: Regenerate.
917
faf766e3
NC		 9182018-01-13 Nick Clifton <nickc@redhat.com>
919
920 2.30 branch created.
921
888a89da
IT		 9222018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
923
924 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
925 * i386-tbl.h: Regenerate.
926
cbda583a
JB		 9272018-01-10 Jan Beulich <jbeulich@suse.com>
928
929 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
930 * i386-tbl.h: Re-generate.
931
c9e92278
JB		 9322018-01-10 Jan Beulich <jbeulich@suse.com>
933
934 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
935 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
936 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
937 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
938 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
939 Disp8MemShift of AVX512VL forms.
940 * i386-tbl.h: Re-generate.
941
35fd2b2b
JW		 9422018-01-09 Jim Wilson <jimw@sifive.com>
943
944 * riscv-dis.c (maybe_print_address): If base_reg is zero,
945 then the hi_addr value is zero.
946
91d8b670
JG		 9472018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
948
949 * arm-dis.c (arm_opcodes): Add csdb.
950 (thumb32_opcodes): Add csdb.
951
be2e7d95
JG		 9522018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
953
954 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
955 * aarch64-asm-2.c: Regenerate.
956 * aarch64-dis-2.c: Regenerate.
957 * aarch64-opc-2.c: Regenerate.
958
704a705d
L		 9592018-01-08 H.J. Lu <hongjiu.lu@intel.com>
960
961 PR gas/22681
962 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
963 Remove AVX512 vmovd with 64-bit operands.
964 * i386-tbl.h: Regenerated.
965
35eeb78f
JW		 9662018-01-05 Jim Wilson <jimw@sifive.com>
967
968 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
969 jalr.
970
219d1afa
AM		 9712018-01-03 Alan Modra <amodra@gmail.com>
972
973 Update year range in copyright notice of all files.
974
1508bbf5
JB		 9752018-01-02 Jan Beulich <jbeulich@suse.com>
976
977 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
978 and OPERAND_TYPE_REGZMM entries.
979
1e563868 980For older changes see ChangeLog-2017
3499769a 981\f
1e563868 982Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 983
984Copying and distribution of this file, with or without modification,
985are permitted in any medium without royalty provided the copyright
986notice and this notice are preserved.
987
988Local Variables:
989mode: change-log
990left-margin: 8
991fill-column: 74
992version-control: never
993End:
GDB Binutils - Deliverables
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