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x86: drop unnecessary {,No}Rex64
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
49d5d12d
JB		 12018-09-13 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
4 (vpbroadcastw, rdpid): Drop NoRex64.
5 * i386-tbl.h: Re-generate.
6
f5eb1d70
JB		 72018-09-13 Jan Beulich <jbeulich@suse.com>
8
9 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
10 store templates, adding D.
11 * i386-tbl.h: Re-generate.
12
dbbc8b7e
JB		 132018-09-13 Jan Beulich <jbeulich@suse.com>
14
15 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
16 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
17 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
18 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
19 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
20 Fold load and store templates where possible, adding D. Drop
21 IgnoreSize where it was pointlessly present. Drop redundant
22 *word.
23 * i386-tbl.h: Re-generate.
24
d276ec69
JB		 252018-09-13 Jan Beulich <jbeulich@suse.com>
26
27 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
28 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
29 (intel_operand_size): Handle v_bndmk_mode.
30 (OP_E_memory): Likewise. Produce (bad) when also riprel.
31
9da4dfd6
JD		 322018-09-08 John Darrington <john@darrington.wattle.id.au>
33
34 * disassemble.c (ARCH_s12z): Define if ARCH_all.
35
be192bc2
JW		 362018-08-31 Kito Cheng <kito@andestech.com>
37
38 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
39 compressed floating point instructions.
40
43135d3b
JW		 412018-08-30 Kito Cheng <kito@andestech.com>
42
43 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
44 riscv_opcode.xlen_requirement.
45 * riscv-opc.c (riscv_opcodes): Update for struct change.
46
df28970f
MA		 472018-08-29 Martin Aberg <maberg@gaisler.com>
48
49 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
50 psr (PWRPSR) instruction.
51
9108bc33
CX		 522018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
53
54 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
55
bd782c07
CX		 562018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
57
58 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
59
ac8cb70f
CX		 602018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
61
62 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
63 loongson3a as an alias of gs464 for compatibility.
64 * mips-opc.c (mips_opcodes): Change Comments.
65
a693765e
CX		 662018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
67
68 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
69 option.
70 (print_mips_disassembler_options): Document -M loongson-ext.
71 * mips-opc.c (LEXT2): New macro.
72 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
73
bdc6c06e
CX		 742018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
75
76 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
77 descriptors.
78 (parse_mips_ase_option): Handle -M loongson-ext option.
79 (print_mips_disassembler_options): Document -M loongson-ext.
80 * mips-opc.c (IL3A): Delete.
81 * mips-opc.c (LEXT): New macro.
82 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
83 instructions.
84
716c08de
CX		 852018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
86
87 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
88 descriptors.
89 (parse_mips_ase_option): Handle -M loongson-cam option.
90 (print_mips_disassembler_options): Document -M loongson-cam.
91 * mips-opc.c (LCAM): New macro.
92 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
93 instructions.
94
9cf7e568
AM		 952018-08-21 Alan Modra <amodra@gmail.com>
96
97 * ppc-dis.c (operand_value_powerpc): Init "invalid".
98 (skip_optional_operands): Count optional operands, and update
99 ppc_optional_operand_value call.
100 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
101 (extract_vlensi): Likewise.
102 (extract_fxm): Return default value for missing optional operand.
103 (extract_ls, extract_raq, extract_tbr): Likewise.
104 (insert_sxl, extract_sxl): New functions.
105 (insert_esync, extract_esync): Remove Power9 handling and simplify.
106 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
107 flag and extra entry.
108 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
109 extract_sxl.
110
d203b41a 1112018-08-20 Alan Modra <amodra@gmail.com>
f4107842 112
d203b41a 113 * sh-opc.h (MASK): Simplify.
f4107842 114
08a8fe2f 1152018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 116
d203b41a
AM		 117 * s12z-dis.c (bm_decode): Deal with cases where the mode is
118 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 119 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 120
08a8fe2f 1212018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 122
123 * s12z.h: Delete.
7ba3ba91 124
1bc60e56
L		 1252018-08-14 H.J. Lu <hongjiu.lu@intel.com>
126
127 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
128 address with the addr32 prefix and without base nor index
129 registers.
130
d871f3f4
L		 1312018-08-11 H.J. Lu <hongjiu.lu@intel.com>
132
133 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
134 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
135 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
136 (cpu_flags): Add CpuCMOV and CpuFXSR.
137 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
138 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
139 * i386-init.h: Regenerated.
140 * i386-tbl.h: Likewise.
141
b6523c37 1422018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
143
144 * arc-regs.h: Update auxiliary registers.
145
e968fc9b
JB		 1462018-08-06 Jan Beulich <jbeulich@suse.com>
147
148 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
149 (RegIP, RegIZ): Define.
150 * i386-reg.tbl: Adjust comments.
151 (rip): Use Qword instead of BaseIndex. Use RegIP.
152 (eip): Use Dword instead of BaseIndex. Use RegIP.
153 (riz): Add Qword. Use RegIZ.
154 (eiz): Add Dword. Use RegIZ.
155 * i386-tbl.h: Re-generate.
156
dbf8be89
JB		 1572018-08-03 Jan Beulich <jbeulich@suse.com>
158
159 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
160 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
161 vpmovzxdq, vpmovzxwd): Remove NoRex64.
162 * i386-tbl.h: Re-generate.
163
c48dadc9
JB		 1642018-08-03 Jan Beulich <jbeulich@suse.com>
165
166 * i386-gen.c (operand_types): Remove Mem field.
167 * i386-opc.h (union i386_operand_type): Remove mem field.
168 * i386-init.h, i386-tbl.h: Re-generate.
169
cb86a42a
AM		 1702018-08-01 Alan Modra <amodra@gmail.com>
171
172 * po/POTFILES.in: Regenerate.
173
07cc0450
NC		 1742018-07-31 Nick Clifton <nickc@redhat.com>
175
176 * po/sv.po: Updated Swedish translation.
177
1424ad86
JB		 1782018-07-31 Jan Beulich <jbeulich@suse.com>
179
180 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
181 * i386-init.h, i386-tbl.h: Re-generate.
182
ae2387fe
JB		 1832018-07-31 Jan Beulich <jbeulich@suse.com>
184
185 * i386-opc.h (ZEROING_MASKING) Rename to ...
186 (DYNAMIC_MASKING): ... this. Adjust comment.
187 * i386-opc.tbl (MaskingMorZ): Define.
188 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
189 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
190 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
191 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
192 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
193 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
194 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
195 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
196 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
197
6ff00b5e
JB		 1982018-07-31 Jan Beulich <jbeulich@suse.com>
199
200 * i386-opc.tbl: Use element rather than vector size for AVX512*
201 scatter/gather insns.
202 * i386-tbl.h: Re-generate.
203
e951d5ca
JB		 2042018-07-31 Jan Beulich <jbeulich@suse.com>
205
206 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
207 (cpu_flags): Drop CpuVREX.
208 * i386-opc.h (CpuVREX): Delete.
209 (union i386_cpu_flags): Remove cpuvrex.
210 * i386-init.h, i386-tbl.h: Re-generate.
211
eb41b248
JW		 2122018-07-30 Jim Wilson <jimw@sifive.com>
213
214 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
215 fields.
216 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
217
b8891f8d
AJ		 2182018-07-30 Andrew Jenner <andrew@codesourcery.com>
219
220 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
221 * Makefile.in: Regenerated.
222 * configure.ac: Add C-SKY.
223 * configure: Regenerated.
224 * csky-dis.c: New file.
225 * csky-opc.h: New file.
226 * disassemble.c (ARCH_csky): Define.
227 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
228 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
229
16065af1
AM		 2302018-07-27 Alan Modra <amodra@gmail.com>
231
232 * ppc-opc.c (insert_sprbat): Correct function parameter and
233 return type.
234 (extract_sprbat): Likewise, variable too.
235
fa758a70
AC		 2362018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
237 Alan Modra <amodra@gmail.com>
238
239 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
240 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
241 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
242 support disjointed BAT.
243 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
244 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
245 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
246
4a1b91ea
L		 2472018-07-25 H.J. Lu <hongjiu.lu@intel.com>
248 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
249
250 * i386-gen.c (adjust_broadcast_modifier): New function.
251 (process_i386_opcode_modifier): Add an argument for operands.
252 Adjust the Broadcast value based on operands.
253 (output_i386_opcode): Pass operand_types to
254 process_i386_opcode_modifier.
255 (process_i386_opcodes): Pass NULL as operands to
256 process_i386_opcode_modifier.
257 * i386-opc.h (BYTE_BROADCAST): New.
258 (WORD_BROADCAST): Likewise.
259 (DWORD_BROADCAST): Likewise.
260 (QWORD_BROADCAST): Likewise.
261 (i386_opcode_modifier): Expand broadcast to 3 bits.
262 * i386-tbl.h: Regenerated.
263
67ce483b
AM		 2642018-07-24 Alan Modra <amodra@gmail.com>
265
266 PR 23430
267 * or1k-desc.h: Regenerate.
268
4174bfff
JB		 2692018-07-24 Jan Beulich <jbeulich@suse.com>
270
271 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
272 vcvtusi2ss, and vcvtusi2sd.
273 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
274 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
275 * i386-tbl.h: Re-generate.
276
04e65276
CZ		 2772018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
278
279 * arc-opc.c (extract_w6): Fix extending the sign.
280
47e6f81c
CZ		 2812018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
282
283 * arc-tbl.h (vewt): Allow it for ARC EM family.
284
bb71536f
AM		 2852018-07-23 Alan Modra <amodra@gmail.com>
286
287 PR 23419
288 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
289 opcode variants for mtspr/mfspr encodings.
290
8095d2f7
CX		 2912018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
292 Maciej W. Rozycki <macro@mips.com>
293
294 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
295 loongson3a descriptors.
296 (parse_mips_ase_option): Handle -M loongson-mmi option.
297 (print_mips_disassembler_options): Document -M loongson-mmi.
298 * mips-opc.c (LMMI): New macro.
299 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
300 instructions.
301
5f32791e
JB		 3022018-07-19 Jan Beulich <jbeulich@suse.com>
303
304 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
305 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
306 IgnoreSize and [XYZ]MMword where applicable.
307 * i386-tbl.h: Re-generate.
308
625cbd7a
JB		 3092018-07-19 Jan Beulich <jbeulich@suse.com>
310
311 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
312 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
313 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
314 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
315 * i386-tbl.h: Re-generate.
316
86b15c32
JB		 3172018-07-19 Jan Beulich <jbeulich@suse.com>
318
319 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
320 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
321 VPCLMULQDQ templates into their respective AVX512VL counterparts
322 where possible, using Disp8ShiftVL and CheckRegSize instead of
323 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
324 * i386-tbl.h: Re-generate.
325
cf769ed5
JB		 3262018-07-19 Jan Beulich <jbeulich@suse.com>
327
328 * i386-opc.tbl: Fold AVX512DQ templates into their respective
329 AVX512VL counterparts where possible, using Disp8ShiftVL and
330 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
331 IgnoreSize) as appropriate.
332 * i386-tbl.h: Re-generate.
333
8282b7ad
JB		 3342018-07-19 Jan Beulich <jbeulich@suse.com>
335
336 * i386-opc.tbl: Fold AVX512BW templates into their respective
337 AVX512VL counterparts where possible, using Disp8ShiftVL and
338 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
339 IgnoreSize) as appropriate.
340 * i386-tbl.h: Re-generate.
341
755908cc
JB		 3422018-07-19 Jan Beulich <jbeulich@suse.com>
343
344 * i386-opc.tbl: Fold AVX512CD templates into their respective
345 AVX512VL counterparts where possible, using Disp8ShiftVL and
346 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
347 IgnoreSize) as appropriate.
348 * i386-tbl.h: Re-generate.
349
7091c612
JB		 3502018-07-19 Jan Beulich <jbeulich@suse.com>
351
352 * i386-opc.h (DISP8_SHIFT_VL): New.
353 * i386-opc.tbl (Disp8ShiftVL): Define.
354 (various): Fold AVX512VL templates into their respective
355 AVX512F counterparts where possible, using Disp8ShiftVL and
356 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
357 IgnoreSize) as appropriate.
358 * i386-tbl.h: Re-generate.
359
c30be56e
JB		 3602018-07-19 Jan Beulich <jbeulich@suse.com>
361
362 * Makefile.am: Change dependencies and rule for
363 $(srcdir)/i386-init.h.
364 * Makefile.in: Re-generate.
365 * i386-gen.c (process_i386_opcodes): New local variable
366 "marker". Drop opening of input file. Recognize marker and line
367 number directives.
368 * i386-opc.tbl (OPCODE_I386_H): Define.
369 (i386-opc.h): Include it.
370 (None): Undefine.
371
11a322db
L		 3722018-07-18 H.J. Lu <hongjiu.lu@intel.com>
373
374 PR gas/23418
375 * i386-opc.h (Byte): Update comments.
376 (Word): Likewise.
377 (Dword): Likewise.
378 (Fword): Likewise.
379 (Qword): Likewise.
380 (Tbyte): Likewise.
381 (Xmmword): Likewise.
382 (Ymmword): Likewise.
383 (Zmmword): Likewise.
384 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
385 vcvttps2uqq.
386 * i386-tbl.h: Regenerated.
387
cde3679e
NC		 3882018-07-12 Sudakshina Das <sudi.das@arm.com>
389
390 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
391 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
392 * aarch64-asm-2.c: Regenerate.
393 * aarch64-dis-2.c: Regenerate.
394 * aarch64-opc-2.c: Regenerate.
395
45a28947
TC		 3962018-07-12 Tamar Christina <tamar.christina@arm.com>
397
398 PR binutils/23192
399 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
400 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
401 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
402 sqdmulh, sqrdmulh): Use Em16.
403
c597cc3d
SD		 4042018-07-11 Sudakshina Das <sudi.das@arm.com>
405
406 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
407 csdb together with them.
408 (thumb32_opcodes): Likewise.
409
a79eaed6
JB		 4102018-07-11 Jan Beulich <jbeulich@suse.com>
411
412 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
413 requiring 32-bit registers as operands 2 and 3. Improve
414 comments.
415 (mwait, mwaitx): Fold templates. Improve comments.
416 OPERAND_TYPE_INOUTPORTREG.
417 * i386-tbl.h: Re-generate.
418
2fb5be8d
JB		 4192018-07-11 Jan Beulich <jbeulich@suse.com>
420
421 * i386-gen.c (operand_type_init): Remove
422 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
423 OPERAND_TYPE_INOUTPORTREG.
424 * i386-init.h: Re-generate.
425
7f5cad30
JB		 4262018-07-11 Jan Beulich <jbeulich@suse.com>
427
428 * i386-opc.tbl (wrssd, wrussd): Add Dword.
429 (wrssq, wrussq): Add Qword.
430 * i386-tbl.h: Re-generate.
431
f0a85b07
JB		 4322018-07-11 Jan Beulich <jbeulich@suse.com>
433
434 * i386-opc.h: Rename OTMax to OTNum.
435 (OTNumOfUints): Adjust calculation.
436 (OTUnused): Directly alias to OTNum.
437
9dcb0ba4
MR		 4382018-07-09 Maciej W. Rozycki <macro@mips.com>
439
440 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
441 `reg_xys'.
442 (lea_reg_xys): Likewise.
443 (print_insn_loop_primitive): Rename `reg' local variable to
444 `reg_dxy'.
445
f311ba7e
TC		 4462018-07-06 Tamar Christina <tamar.christina@arm.com>
447
448 PR binutils/23242
449 * aarch64-tbl.h (ldarh): Fix disassembly mask.
450
cba05feb
TC		 4512018-07-06 Tamar Christina <tamar.christina@arm.com>
452
453 PR binutils/23369
454 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
455 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
456
471b9d15
MR		 4572018-07-02 Maciej W. Rozycki <macro@mips.com>
458
459 PR tdep/8282
460 * mips-dis.c (mips_option_arg_t): New enumeration.
461 (mips_options): New variable.
462 (disassembler_options_mips): New function.
463 (print_mips_disassembler_options): Reimplement in terms of
464 `disassembler_options_mips'.
465 * arm-dis.c (disassembler_options_arm): Adapt to using the
466 `disasm_options_and_args_t' structure.
467 * ppc-dis.c (disassembler_options_powerpc): Likewise.
468 * s390-dis.c (disassembler_options_s390): Likewise.
469
c0c468d5
TP		 4702018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
471
472 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
473 expected result.
474 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
475 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
476 * testsuite/ld-arm/tls-longplt.d: Likewise.
477
369c9167
TC		 4782018-06-29 Tamar Christina <tamar.christina@arm.com>
479
480 PR binutils/23192
481 * aarch64-asm-2.c: Regenerate.
482 * aarch64-dis-2.c: Likewise.
483 * aarch64-opc-2.c: Likewise.
484 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
485 * aarch64-opc.c (operand_general_constraint_met_p,
486 aarch64_print_operand): Likewise.
487 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
488 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
489 fmlal2, fmlsl2.
490 (AARCH64_OPERANDS): Add Em2.
491
30aa1306
NC		 4922018-06-26 Nick Clifton <nickc@redhat.com>
493
494 * po/uk.po: Updated Ukranian translation.
495 * po/de.po: Updated German translation.
496 * po/pt_BR.po: Updated Brazilian Portuguese translation.
497
eca4b721
NC		 4982018-06-26 Nick Clifton <nickc@redhat.com>
499
500 * nfp-dis.c: Fix spelling mistake.
501
71300e2c
NC		 5022018-06-24 Nick Clifton <nickc@redhat.com>
503
504 * configure: Regenerate.
505 * po/opcodes.pot: Regenerate.
506
719d8288
NC		 5072018-06-24 Nick Clifton <nickc@redhat.com>
508
509 2.31 branch created.
510
514cd3a0
TC		 5112018-06-19 Tamar Christina <tamar.christina@arm.com>
512
513 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
514 * aarch64-asm-2.c: Regenerate.
515 * aarch64-dis-2.c: Likewise.
516
385e4d0f
MR		 5172018-06-21 Maciej W. Rozycki <macro@mips.com>
518
519 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
520 `-M ginv' option description.
521
160d1b3d
SH		 5222018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
523
524 PR gas/23305
525 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
526 la and lla.
527
d0ac1c44
SM		 5282018-06-19 Simon Marchi <simon.marchi@ericsson.com>
529
530 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
531 * configure.ac: Remove AC_PREREQ.
532 * Makefile.in: Re-generate.
533 * aclocal.m4: Re-generate.
534 * configure: Re-generate.
535
6f20c942
FS		 5362018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
537
538 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
539 mips64r6 descriptors.
540 (parse_mips_ase_option): Handle -Mginv option.
541 (print_mips_disassembler_options): Document -Mginv.
542 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
543 (GINV): New macro.
544 (mips_opcodes): Define ginvi and ginvt.
545
730c3174
SE		 5462018-06-13 Scott Egerton <scott.egerton@imgtec.com>
547 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
548
549 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
550 * mips-opc.c (CRC, CRC64): New macros.
551 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
552 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
553 crc32cd for CRC64.
554
cb366992
EB		 5552018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
556
557 PR 20319
558 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
559 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
560
ce72cd46
AM		 5612018-06-06 Alan Modra <amodra@gmail.com>
562
563 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
564 setjmp. Move init for some other vars later too.
565
4b8e28c7
MF		 5662018-06-04 Max Filippov <jcmvbkbc@gmail.com>
567
568 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
569 (dis_private): Add new fields for property section tracking.
570 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
571 (xtensa_instruction_fits): New functions.
572 (fetch_data): Bump minimal fetch size to 4.
573 (print_insn_xtensa): Make struct dis_private static.
574 Load and prepare property table on section change.
575 Don't disassemble literals. Don't disassemble instructions that
576 cross property table boundaries.
577
55e99962
L		 5782018-06-01 H.J. Lu <hongjiu.lu@intel.com>
579
580 * configure: Regenerated.
581
733bd0ab
JB		 5822018-06-01 Jan Beulich <jbeulich@suse.com>
583
584 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
585 * i386-tbl.h: Re-generate.
586
dfd27d41
JB		 5872018-06-01 Jan Beulich <jbeulich@suse.com>
588
589 * i386-opc.tbl (sldt, str): Add NoRex64.
590 * i386-tbl.h: Re-generate.
591
64795710
JB		 5922018-06-01 Jan Beulich <jbeulich@suse.com>
593
594 * i386-opc.tbl (invpcid): Add Oword.
595 * i386-tbl.h: Re-generate.
596
030157d8
AM		 5972018-06-01 Alan Modra <amodra@gmail.com>
598
599 * sysdep.h (_bfd_error_handler): Don't declare.
600 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
601 * rl78-decode.opc: Likewise.
602 * msp430-decode.c: Regenerate.
603 * rl78-decode.c: Regenerate.
604
a9660a6f
AP		 6052018-05-30 Amit Pawar <Amit.Pawar@amd.com>
606
607 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
608 * i386-init.h : Regenerated.
609
277eb7f6
AM		 6102018-05-25 Alan Modra <amodra@gmail.com>
611
612 * Makefile.in: Regenerate.
613 * po/POTFILES.in: Regenerate.
614
98553ad3
PB		 6152018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
616
617 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
618 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
619 (insert_bab, extract_bab, insert_btab, extract_btab,
620 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
621 (BAT, BBA VBA RBS XB6S): Delete macros.
622 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
623 (BB, BD, RBX, XC6): Update for new macros.
624 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
625 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
626 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
627 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
628
7b4ae824
JD		 6292018-05-18 John Darrington <john@darrington.wattle.id.au>
630
631 * Makefile.am: Add support for s12z architecture.
632 * configure.ac: Likewise.
633 * disassemble.c: Likewise.
634 * disassemble.h: Likewise.
635 * Makefile.in: Regenerate.
636 * configure: Regenerate.
637 * s12z-dis.c: New file.
638 * s12z.h: New file.
639
29e0f0a1
AM		 6402018-05-18 Alan Modra <amodra@gmail.com>
641
642 * nfp-dis.c: Don't #include libbfd.h.
643 (init_nfp3200_priv): Use bfd_get_section_contents.
644 (nit_nfp6000_mecsr_sec): Likewise.
645
809276d2
NC		 6462018-05-17 Nick Clifton <nickc@redhat.com>
647
648 * po/zh_CN.po: Updated simplified Chinese translation.
649
ff329288
TC		 6502018-05-16 Tamar Christina <tamar.christina@arm.com>
651
652 PR binutils/23109
653 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
654 * aarch64-dis-2.c: Regenerate.
655
f9830ec1
TC		 6562018-05-15 Tamar Christina <tamar.christina@arm.com>
657
658 PR binutils/21446
659 * aarch64-asm.c (opintl.h): Include.
660 (aarch64_ins_sysreg): Enforce read/write constraints.
661 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
662 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
663 (F_REG_READ, F_REG_WRITE): New.
664 * aarch64-opc.c (aarch64_print_operand): Generate notes for
665 AARCH64_OPND_SYSREG.
666 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
667 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
668 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
669 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
670 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
671 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
672 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
673 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
674 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
675 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
676 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
677 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
678 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
679 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
680 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
681 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
682 msr (F_SYS_WRITE), mrs (F_SYS_READ).
683
7d02540a
TC		 6842018-05-15 Tamar Christina <tamar.christina@arm.com>
685
686 PR binutils/21446
687 * aarch64-dis.c (no_notes: New.
688 (parse_aarch64_dis_option): Support notes.
689 (aarch64_decode_insn, print_operands): Likewise.
690 (print_aarch64_disassembler_options): Document notes.
691 * aarch64-opc.c (aarch64_print_operand): Support notes.
692
561a72d4
TC		 6932018-05-15 Tamar Christina <tamar.christina@arm.com>
694
695 PR binutils/21446
696 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
697 and take error struct.
698 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
699 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
700 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
701 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
702 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
703 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
704 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
705 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
706 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
707 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
708 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
709 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
710 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
711 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
712 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
713 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
714 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
715 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
716 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
717 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
718 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
719 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
720 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
721 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
722 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
723 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
724 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
725 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
726 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
727 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
728 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
729 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
730 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
731 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
732 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
733 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
734 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
735 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
736 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
737 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
738 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
739 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
740 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
741 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
742 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
743 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
744 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
745 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
746 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
747 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
748 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
749 (determine_disassembling_preference, aarch64_decode_insn,
750 print_insn_aarch64_word, print_insn_data): Take errors struct.
751 (print_insn_aarch64): Use errors.
752 * aarch64-asm-2.c: Regenerate.
753 * aarch64-dis-2.c: Regenerate.
754 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
755 boolean in aarch64_insert_operan.
756 (print_operand_extractor): Likewise.
757 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
758
1678bd35
FT		 7592018-05-15 Francois H. Theron <francois.theron@netronome.com>
760
761 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
762
06cfb1c8
L		 7632018-05-09 H.J. Lu <hongjiu.lu@intel.com>
764
765 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
766
84f9f8c3
AM		 7672018-05-09 Sebastian Rasmussen <sebras@gmail.com>
768
769 * cr16-opc.c (cr16_instruction): Comment typo fix.
770 * hppa-dis.c (print_insn_hppa): Likewise.
771
e6f372ba
JW		 7722018-05-08 Jim Wilson <jimw@sifive.com>
773
774 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
775 (match_c_slli64, match_srxi_as_c_srxi): New.
776 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
777 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
778 <c.slli, c.srli, c.srai>: Use match_s_slli.
779 <c.slli64, c.srli64, c.srai64>: New.
780
f413a913
AM		 7812018-05-08 Alan Modra <amodra@gmail.com>
782
783 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
784 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
785 partition opcode space for index lookup.
786
a87a6478
PB		 7872018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
788
789 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
790 <insn_length>: ...with this. Update usage.
791 Remove duplicate call to *info->memory_error_func.
792
c0a30a9f
L		 7932018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
794 H.J. Lu <hongjiu.lu@intel.com>
795
796 * i386-dis.c (Gva): New.
797 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
798 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
799 (prefix_table): New instructions (see prefix above).
800 (mod_table): New instructions (see prefix above).
801 (OP_G): Handle va_mode.
802 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
803 CPU_MOVDIR64B_FLAGS.
804 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
805 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
806 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
807 * i386-opc.tbl: Add movidir{i,64b}.
808 * i386-init.h: Regenerated.
809 * i386-tbl.h: Likewise.
810
75c0a438
L		 8112018-05-07 H.J. Lu <hongjiu.lu@intel.com>
812
813 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
814 AddrPrefixOpReg.
815 * i386-opc.h (AddrPrefixOp0): Renamed to ...
816 (AddrPrefixOpReg): This.
817 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
818 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
819
2ceb7719
PB		 8202018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
821
822 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
823 (vle_num_opcodes): Likewise.
824 (spe2_num_opcodes): Likewise.
825 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
826 initialization loop.
827 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
828 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
829 only once.
830
b3ac5c6c
TC		 8312018-05-01 Tamar Christina <tamar.christina@arm.com>
832
833 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
834
fe944acf
FT		 8352018-04-30 Francois H. Theron <francois.theron@netronome.com>
836
837 Makefile.am: Added nfp-dis.c.
838 configure.ac: Added bfd_nfp_arch.
839 disassemble.h: Added print_insn_nfp prototype.
840 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
841 nfp-dis.c: New, for NFP support.
842 po/POTFILES.in: Added nfp-dis.c to the list.
843 Makefile.in: Regenerate.
844 configure: Regenerate.
845
e2195274
JB		 8462018-04-26 Jan Beulich <jbeulich@suse.com>
847
848 * i386-opc.tbl: Fold various non-memory operand AVX512VL
849 templates into their base ones.
850 * i386-tlb.h: Re-generate.
851
59ef5df4
JB		 8522018-04-26 Jan Beulich <jbeulich@suse.com>
853
854 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
855 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
856 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
857 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
858 * i386-init.h: Re-generate.
859
6e041cf4
JB		 8602018-04-26 Jan Beulich <jbeulich@suse.com>
861
862 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
863 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
864 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
865 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
866 comment.
867 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
868 and CpuRegMask.
869 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
870 CpuRegMask: Delete.
871 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
872 cpuregzmm, and cpuregmask.
873 * i386-init.h: Re-generate.
874 * i386-tbl.h: Re-generate.
875
0e0eea78
JB		 8762018-04-26 Jan Beulich <jbeulich@suse.com>
877
878 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
879 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
880 * i386-init.h: Re-generate.
881
2f1bada2
JB		 8822018-04-26 Jan Beulich <jbeulich@suse.com>
883
884 * i386-gen.c (VexImmExt): Delete.
885 * i386-opc.h (VexImmExt, veximmext): Delete.
886 * i386-opc.tbl: Drop all VexImmExt uses.
887 * i386-tlb.h: Re-generate.
888
bacd1457
JB		 8892018-04-25 Jan Beulich <jbeulich@suse.com>
890
891 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
892 register-only forms.
893 * i386-tlb.h: Re-generate.
894
10bba94b
TC		 8952018-04-25 Tamar Christina <tamar.christina@arm.com>
896
897 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
898
c48935d7
IT		 8992018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
900
901 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
902 PREFIX_0F1C.
903 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
904 (cpu_flags): Add CpuCLDEMOTE.
905 * i386-init.h: Regenerate.
906 * i386-opc.h (enum): Add CpuCLDEMOTE,
907 (i386_cpu_flags): Add cpucldemote.
908 * i386-opc.tbl: Add cldemote.
909 * i386-tbl.h: Regenerate.
910
211dc24b
AM		 9112018-04-16 Alan Modra <amodra@gmail.com>
912
913 * Makefile.am: Remove sh5 and sh64 support.
914 * configure.ac: Likewise.
915 * disassemble.c: Likewise.
916 * disassemble.h: Likewise.
917 * sh-dis.c: Likewise.
918 * sh64-dis.c: Delete.
919 * sh64-opc.c: Delete.
920 * sh64-opc.h: Delete.
921 * Makefile.in: Regenerate.
922 * configure: Regenerate.
923 * po/POTFILES.in: Regenerate.
924
a9a4b302
AM		 9252018-04-16 Alan Modra <amodra@gmail.com>
926
927 * Makefile.am: Remove w65 support.
928 * configure.ac: Likewise.
929 * disassemble.c: Likewise.
930 * disassemble.h: Likewise.
931 * w65-dis.c: Delete.
932 * w65-opc.h: Delete.
933 * Makefile.in: Regenerate.
934 * configure: Regenerate.
935 * po/POTFILES.in: Regenerate.
936
04cb01fd
AM		 9372018-04-16 Alan Modra <amodra@gmail.com>
938
939 * configure.ac: Remove we32k support.
940 * configure: Regenerate.
941
c2bf1eec
AM		 9422018-04-16 Alan Modra <amodra@gmail.com>
943
944 * Makefile.am: Remove m88k support.
945 * configure.ac: Likewise.
946 * disassemble.c: Likewise.
947 * disassemble.h: Likewise.
948 * m88k-dis.c: Delete.
949 * Makefile.in: Regenerate.
950 * configure: Regenerate.
951 * po/POTFILES.in: Regenerate.
952
6793974d
AM		 9532018-04-16 Alan Modra <amodra@gmail.com>
954
955 * Makefile.am: Remove i370 support.
956 * configure.ac: Likewise.
957 * disassemble.c: Likewise.
958 * disassemble.h: Likewise.
959 * i370-dis.c: Delete.
960 * i370-opc.c: Delete.
961 * Makefile.in: Regenerate.
962 * configure: Regenerate.
963 * po/POTFILES.in: Regenerate.
964
e82aa794
AM		 9652018-04-16 Alan Modra <amodra@gmail.com>
966
967 * Makefile.am: Remove h8500 support.
968 * configure.ac: Likewise.
969 * disassemble.c: Likewise.
970 * disassemble.h: Likewise.
971 * h8500-dis.c: Delete.
972 * h8500-opc.h: Delete.
973 * Makefile.in: Regenerate.
974 * configure: Regenerate.
975 * po/POTFILES.in: Regenerate.
976
fceadf09
AM		 9772018-04-16 Alan Modra <amodra@gmail.com>
978
979 * configure.ac: Remove tahoe support.
980 * configure: Regenerate.
981
ae1d3843
L		 9822018-04-15 H.J. Lu <hongjiu.lu@intel.com>
983
984 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
985 umwait.
986 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
987 64-bit mode.
988 * i386-tbl.h: Regenerated.
989
de89d0a3
IT		 9902018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
991
992 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
993 PREFIX_MOD_1_0FAE_REG_6.
994 (va_mode): New.
995 (OP_E_register): Use va_mode.
996 * i386-dis-evex.h (prefix_table):
997 New instructions (see prefixes above).
998 * i386-gen.c (cpu_flag_init): Add WAITPKG.
999 (cpu_flags): Likewise.
1000 * i386-opc.h (enum): Likewise.
1001 (i386_cpu_flags): Likewise.
1002 * i386-opc.tbl: Add umonitor, umwait, tpause.
1003 * i386-init.h: Regenerate.
1004 * i386-tbl.h: Likewise.
1005
a8eb42a8
AM		 10062018-04-11 Alan Modra <amodra@gmail.com>
1007
1008 * opcodes/i860-dis.c: Delete.
1009 * opcodes/i960-dis.c: Delete.
1010 * Makefile.am: Remove i860 and i960 support.
1011 * configure.ac: Likewise.
1012 * disassemble.c: Likewise.
1013 * disassemble.h: Likewise.
1014 * Makefile.in: Regenerate.
1015 * configure: Regenerate.
1016 * po/POTFILES.in: Regenerate.
1017
caf0678c
L		 10182018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1019
1020 PR binutils/23025
1021 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1022 to 0.
1023 (print_insn): Clear vex instead of vex.evex.
1024
4fb0d2b9
NC		 10252018-04-04 Nick Clifton <nickc@redhat.com>
1026
1027 * po/es.po: Updated Spanish translation.
1028
c39e5b26
JB		 10292018-03-28 Jan Beulich <jbeulich@suse.com>
1030
1031 * i386-gen.c (opcode_modifiers): Delete VecESize.
1032 * i386-opc.h (VecESize): Delete.
1033 (struct i386_opcode_modifier): Delete vecesize.
1034 * i386-opc.tbl: Drop VecESize.
1035 * i386-tlb.h: Re-generate.
1036
8e6e0792
JB		 10372018-03-28 Jan Beulich <jbeulich@suse.com>
1038
1039 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1040 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1041 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1042 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1043 * i386-tlb.h: Re-generate.
1044
9f123b91
JB		 10452018-03-28 Jan Beulich <jbeulich@suse.com>
1046
1047 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1048 Fold AVX512 forms
1049 * i386-tlb.h: Re-generate.
1050
9646c87b
JB		 10512018-03-28 Jan Beulich <jbeulich@suse.com>
1052
1053 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1054 (vex_len_table): Drop Y for vcvt*2si.
1055 (putop): Replace plain 'Y' handling by abort().
1056
c8d59609
NC		 10572018-03-28 Nick Clifton <nickc@redhat.com>
1058
1059 PR 22988
1060 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1061 instructions with only a base address register.
1062 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1063 handle AARHC64_OPND_SVE_ADDR_R.
1064 (aarch64_print_operand): Likewise.
1065 * aarch64-asm-2.c: Regenerate.
1066 * aarch64_dis-2.c: Regenerate.
1067 * aarch64-opc-2.c: Regenerate.
1068
b8c169f3
JB		 10692018-03-22 Jan Beulich <jbeulich@suse.com>
1070
1071 * i386-opc.tbl: Drop VecESize from register only insn forms and
1072 memory forms not allowing broadcast.
1073 * i386-tlb.h: Re-generate.
1074
96bc132a
JB		 10752018-03-22 Jan Beulich <jbeulich@suse.com>
1076
1077 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1078 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1079 sha256*): Drop Disp<N>.
1080
9f79e886
JB		 10812018-03-22 Jan Beulich <jbeulich@suse.com>
1082
1083 * i386-dis.c (EbndS, bnd_swap_mode): New.
1084 (prefix_table): Use EbndS.
1085 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1086 * i386-opc.tbl (bndmov): Move misplaced Load.
1087 * i386-tlb.h: Re-generate.
1088
d6793fa1
JB		 10892018-03-22 Jan Beulich <jbeulich@suse.com>
1090
1091 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1092 templates allowing memory operands and folded ones for register
1093 only flavors.
1094 * i386-tlb.h: Re-generate.
1095
f7768225
JB		 10962018-03-22 Jan Beulich <jbeulich@suse.com>
1097
1098 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1099 256-bit templates. Drop redundant leftover Disp<N>.
1100 * i386-tlb.h: Re-generate.
1101
0e35537d
JW		 11022018-03-14 Kito Cheng <kito.cheng@gmail.com>
1103
1104 * riscv-opc.c (riscv_insn_types): New.
1105
b4a3689a
NC		 11062018-03-13 Nick Clifton <nickc@redhat.com>
1107
1108 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1109
d3d50934
L		 11102018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1111
1112 * i386-opc.tbl: Add Optimize to clr.
1113 * i386-tbl.h: Regenerated.
1114
bd5dea88
L		 11152018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1116
1117 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1118 * i386-opc.h (OldGcc): Removed.
1119 (i386_opcode_modifier): Remove oldgcc.
1120 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1121 instructions for old (<= 2.8.1) versions of gcc.
1122 * i386-tbl.h: Regenerated.
1123
e771e7c9
JB		 11242018-03-08 Jan Beulich <jbeulich@suse.com>
1125
1126 * i386-opc.h (EVEXDYN): New.
1127 * i386-opc.tbl: Fold various AVX512VL templates.
1128 * i386-tlb.h: Re-generate.
1129
ed438a93
JB		 11302018-03-08 Jan Beulich <jbeulich@suse.com>
1131
1132 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1133 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1134 vpexpandd, vpexpandq): Fold AFX512VF templates.
1135 * i386-tlb.h: Re-generate.
1136
454172a9
JB		 11372018-03-08 Jan Beulich <jbeulich@suse.com>
1138
1139 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1140 Fold 128- and 256-bit VEX-encoded templates.
1141 * i386-tlb.h: Re-generate.
1142
36824150
JB		 11432018-03-08 Jan Beulich <jbeulich@suse.com>
1144
1145 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1146 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1147 vpexpandd, vpexpandq): Fold AVX512F templates.
1148 * i386-tlb.h: Re-generate.
1149
e7f5c0a9
JB		 11502018-03-08 Jan Beulich <jbeulich@suse.com>
1151
1152 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1153 64-bit templates. Drop Disp<N>.
1154 * i386-tlb.h: Re-generate.
1155
25a4277f
JB		 11562018-03-08 Jan Beulich <jbeulich@suse.com>
1157
1158 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1159 and 256-bit templates.
1160 * i386-tlb.h: Re-generate.
1161
d2224064
JB		 11622018-03-08 Jan Beulich <jbeulich@suse.com>
1163
1164 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1165 * i386-tlb.h: Re-generate.
1166
1b193f0b
JB		 11672018-03-08 Jan Beulich <jbeulich@suse.com>
1168
1169 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1170 Drop NoAVX.
1171 * i386-tlb.h: Re-generate.
1172
f2f6a710
JB		 11732018-03-08 Jan Beulich <jbeulich@suse.com>
1174
1175 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1176 * i386-tlb.h: Re-generate.
1177
38e314eb
JB		 11782018-03-08 Jan Beulich <jbeulich@suse.com>
1179
1180 * i386-gen.c (opcode_modifiers): Delete FloatD.
1181 * i386-opc.h (FloatD): Delete.
1182 (struct i386_opcode_modifier): Delete floatd.
1183 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1184 FloatD by D.
1185 * i386-tlb.h: Re-generate.
1186
d53e6b98
JB		 11872018-03-08 Jan Beulich <jbeulich@suse.com>
1188
1189 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1190
2907c2f5
JB		 11912018-03-08 Jan Beulich <jbeulich@suse.com>
1192
1193 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1194 * i386-tlb.h: Re-generate.
1195
73053c1f
JB		 11962018-03-08 Jan Beulich <jbeulich@suse.com>
1197
1198 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1199 forms.
1200 * i386-tlb.h: Re-generate.
1201
52fe4420
AM		 12022018-03-07 Alan Modra <amodra@gmail.com>
1203
1204 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1205 bfd_arch_rs6000.
1206 * disassemble.h (print_insn_rs6000): Delete.
1207 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1208 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1209 (print_insn_rs6000): Delete.
1210
a6743a54
AM		 12112018-03-03 Alan Modra <amodra@gmail.com>
1212
1213 * sysdep.h (opcodes_error_handler): Define.
1214 (_bfd_error_handler): Declare.
1215 * Makefile.am: Remove stray #.
1216 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1217 EDIT" comment.
1218 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1219 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1220 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1221 opcodes_error_handler to print errors. Standardize error messages.
1222 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1223 and include opintl.h.
1224 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1225 * i386-gen.c: Standardize error messages.
1226 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1227 * Makefile.in: Regenerate.
1228 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1229 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1230 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1231 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1232 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1233 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1234 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1235 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1236 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1237 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1238 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1239 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1240 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1241
8305403a
L		 12422018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1243
1244 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1245 vpsub[bwdq] instructions.
1246 * i386-tbl.h: Regenerated.
1247
e184813f
AM		 12482018-03-01 Alan Modra <amodra@gmail.com>
1249
1250 * configure.ac (ALL_LINGUAS): Sort.
1251 * configure: Regenerate.
1252
5b616bef
TP		 12532018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1254
1255 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1256 macro by assignements.
1257
b6f8c7c4
L		 12582018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1259
1260 PR gas/22871
1261 * i386-gen.c (opcode_modifiers): Add Optimize.
1262 * i386-opc.h (Optimize): New enum.
1263 (i386_opcode_modifier): Add optimize.
1264 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1265 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1266 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1267 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1268 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1269 vpxord and vpxorq.
1270 * i386-tbl.h: Regenerated.
1271
e95b887f
AM		 12722018-02-26 Alan Modra <amodra@gmail.com>
1273
1274 * crx-dis.c (getregliststring): Allocate a large enough buffer
1275 to silence false positive gcc8 warning.
1276
0bccfb29
JW		 12772018-02-22 Shea Levy <shea@shealevy.com>
1278
1279 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1280
6b6b6807
L		 12812018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1282
1283 * i386-opc.tbl: Add {rex},
1284 * i386-tbl.h: Regenerated.
1285
75f31665
MR		 12862018-02-20 Maciej W. Rozycki <macro@mips.com>
1287
1288 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1289 (mips16_opcodes): Replace `M' with `m' for "restore".
1290
e207bc53
TP		 12912018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1292
1293 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1294
87993319
MR		 12952018-02-13 Maciej W. Rozycki <macro@mips.com>
1296
1297 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1298 variable to `function_index'.
1299
68d20676
NC		 13002018-02-13 Nick Clifton <nickc@redhat.com>
1301
1302 PR 22823
1303 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1304 about truncation of printing.
1305
d2159fdc
HW		 13062018-02-12 Henry Wong <henry@stuffedcow.net>
1307
1308 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1309
f174ef9f
NC		 13102018-02-05 Nick Clifton <nickc@redhat.com>
1311
1312 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1313
be3a8dca
IT		 13142018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1315
1316 * i386-dis.c (enum): Add pconfig.
1317 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1318 (cpu_flags): Add CpuPCONFIG.
1319 * i386-opc.h (enum): Add CpuPCONFIG.
1320 (i386_cpu_flags): Add cpupconfig.
1321 * i386-opc.tbl: Add PCONFIG instruction.
1322 * i386-init.h: Regenerate.
1323 * i386-tbl.h: Likewise.
1324
3233d7d0
IT		 13252018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1326
1327 * i386-dis.c (enum): Add PREFIX_0F09.
1328 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1329 (cpu_flags): Add CpuWBNOINVD.
1330 * i386-opc.h (enum): Add CpuWBNOINVD.
1331 (i386_cpu_flags): Add cpuwbnoinvd.
1332 * i386-opc.tbl: Add WBNOINVD instruction.
1333 * i386-init.h: Regenerate.
1334 * i386-tbl.h: Likewise.
1335
e925c834
JW		 13362018-01-17 Jim Wilson <jimw@sifive.com>
1337
1338 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1339
d777820b
IT		 13402018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1341
1342 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1343 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1344 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1345 (cpu_flags): Add CpuIBT, CpuSHSTK.
1346 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1347 (i386_cpu_flags): Add cpuibt, cpushstk.
1348 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1349 * i386-init.h: Regenerate.
1350 * i386-tbl.h: Likewise.
1351
f6efed01
NC		 13522018-01-16 Nick Clifton <nickc@redhat.com>
1353
1354 * po/pt_BR.po: Updated Brazilian Portugese translation.
1355 * po/de.po: Updated German translation.
1356
2721d702
JW		 13572018-01-15 Jim Wilson <jimw@sifive.com>
1358
1359 * riscv-opc.c (match_c_nop): New.
1360 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1361
616dcb87
NC		 13622018-01-15 Nick Clifton <nickc@redhat.com>
1363
1364 * po/uk.po: Updated Ukranian translation.
1365
3957a496
NC		 13662018-01-13 Nick Clifton <nickc@redhat.com>
1367
1368 * po/opcodes.pot: Regenerated.
1369
769c7ea5
NC		 13702018-01-13 Nick Clifton <nickc@redhat.com>
1371
1372 * configure: Regenerate.
1373
faf766e3
NC		 13742018-01-13 Nick Clifton <nickc@redhat.com>
1375
1376 2.30 branch created.
1377
888a89da
IT		 13782018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1379
1380 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1381 * i386-tbl.h: Regenerate.
1382
cbda583a
JB		 13832018-01-10 Jan Beulich <jbeulich@suse.com>
1384
1385 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1386 * i386-tbl.h: Re-generate.
1387
c9e92278
JB		 13882018-01-10 Jan Beulich <jbeulich@suse.com>
1389
1390 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1391 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1392 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1393 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1394 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1395 Disp8MemShift of AVX512VL forms.
1396 * i386-tbl.h: Re-generate.
1397
35fd2b2b
JW		 13982018-01-09 Jim Wilson <jimw@sifive.com>
1399
1400 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1401 then the hi_addr value is zero.
1402
91d8b670
JG		 14032018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1404
1405 * arm-dis.c (arm_opcodes): Add csdb.
1406 (thumb32_opcodes): Add csdb.
1407
be2e7d95
JG		 14082018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1409
1410 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1411 * aarch64-asm-2.c: Regenerate.
1412 * aarch64-dis-2.c: Regenerate.
1413 * aarch64-opc-2.c: Regenerate.
1414
704a705d
L		 14152018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1416
1417 PR gas/22681
1418 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1419 Remove AVX512 vmovd with 64-bit operands.
1420 * i386-tbl.h: Regenerated.
1421
35eeb78f
JW		 14222018-01-05 Jim Wilson <jimw@sifive.com>
1423
1424 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1425 jalr.
1426
219d1afa
AM		 14272018-01-03 Alan Modra <amodra@gmail.com>
1428
1429 Update year range in copyright notice of all files.
1430
1508bbf5
JB		 14312018-01-02 Jan Beulich <jbeulich@suse.com>
1432
1433 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1434 and OPERAND_TYPE_REGZMM entries.
1435
1e563868 1436For older changes see ChangeLog-2017
3499769a 1437\f
1e563868 1438Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1439
1440Copying and distribution of this file, with or without modification,
1441are permitted in any medium without royalty provided the copyright
1442notice and this notice are preserved.
1443
1444Local Variables:
1445mode: change-log
1446left-margin: 8
1447fill-column: 74
1448version-control: never
1449End:
GDB Binutils - Deliverables
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