[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2019-04-29  John Darrington  <john@darrington.wattle.id.au>

        * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.

2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
	    Faraz Shahbazker  <fshahbazker@wavecomp.com>

	* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.

2019-04-24  John Darrington  <john@darrington.wattle.id.au>

        * s12z-opc.h: Add extern "C" bracketing to help
	users who wish to use this interface in c++ code.

2019-04-24  John Darrington  <john@darrington.wattle.id.au>

	* s12z-opc.c (bm_decode): Handle bit map operations with the
	"reserved0" mode.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
	specifier.  Add entries for VLDR and VSTR of system registers.
	(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
	coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
	of %J and %K format specifier.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
	Add new entries for VSCCLRM instruction.
	(print_insn_coprocessor): Handle new %C format control code.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (enum isa): New enum.
	(struct sopcode32): New structure.
	(coprocessor_opcodes): change type of entries to struct sopcode32 and
	set isa field of all current entries to ANY.
	(print_insn_coprocessor): Change type of insn to struct sopcode32.
	Only match an entry if its isa field allows the current mode.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
	CLRM.
	(print_insn_thumb32): Add logic to print %n CLRM register list.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %P
	and %Q patterns.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
	(print_insn_thumb32): Edit the switch case for %Z.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (thumb32_opcodes): New instruction bfl.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
	Arm register with r13 and r15 unpredictable.
	(thumb32_opcodes): New instructions for bfx and bflx.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (thumb32_opcodes): New instructions for bf.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.

2019-04-15  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.

2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.

2019-04-12  John Darrington <john@darrington.wattle.id.au>

	s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
	"optr". ("operator" is a reserved word in c++).

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(verify_constraints): Likewise.
	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
	to accept Rt|SP as first operand.
	(AARCH64_OPERANDS): Add new Rt_SP.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.

2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.

2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Consolidate AVX512 BF16 entries.
	* i386-init.h: Regenerated.

2019-04-07  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
	op_separator to control printing of spaces, comma and parens
	rather than need_comma, need_paren and spaces vars.

2019-04-07  Alan Modra  <amodra@gmail.com>

	PR 24421
	* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
	(print_insn_neon, print_insn_arm): Likewise.

2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>

	* i386-dis-evex.h (evex_table): Updated to support BF16
	instructions.
	* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
	and EVEX_W_0F3872_P_3.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
	(cpu_flags): Add bitfield for CpuAVX512_BF16.
	* i386-opc.h (enum): Add CpuAVX512_BF16.
	(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
	* i386-opc.tbl: Add AVX512 BF16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2019-04-05  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
	(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
	to favour printing of "-" branch hint when using the "y" bit.
	Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.

2019-04-05  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
	opcode until first operand is output.

2019-04-04  Peter Bergner  <bergner@linux.ibm.com>

	PR gas/24349
	* ppc-opc.c (valid_bo_pre_v2): Add comments.
	(valid_bo_post_v2): Add support for 'at' branch hints.
	(insert_bo): Only error on branch on ctr.
	(get_bo_hint_mask): New function.
	(insert_boe): Add new 'branch_taken' formal argument.  Add support
	for inserting 'at' branch hints.
	(extract_boe): Add new 'branch_taken' formal argument.  Add support
	for extracting 'at' branch hints.
	(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
	(BOE): Delete operand.
	(BOM, BOP): New operands.
	(RM): Update value.
	(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
	(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
	bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
	(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
	bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
	<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
	bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
	bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
	bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
	bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
	bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
	bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
	bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
	beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
	bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
	buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
	bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
	bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
	bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
	bttarl+>: New extended mnemonics.

2019-03-28  Alan Modra  <amodra@gmail.com>

	PR 24390
	* ppc-opc.c (BTF): Define.
	(powerpc_opcodes): Use for mtfsb*.
	* ppc-dis.c (print_insn_powerpc): Print fields with both
	PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.

2019-03-25  Tamar Christina  <tamar.christina@arm.com>

	* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
	(mapping_symbol_for_insn): Implement new algorithm.
	(print_insn): Remove duplicate code.

2019-03-25  Tamar Christina  <tamar.christina@arm.com>

	* aarch64-dis.c (print_insn_aarch64):
	Implement override.

2019-03-25  Tamar Christina  <tamar.christina@arm.com>

	* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
	order.

2019-03-25  Tamar Christina  <tamar.christina@arm.com>

	* aarch64-dis.c (last_stop_offset): New.
	(print_insn_aarch64): Use stop_offset.

2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/24359
	* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
	CPU_ANY_AVX2_FLAGS.
	* i386-init.h: Regenerated.

2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/24348
	* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
	vmovdqu16, vmovdqu32 and vmovdqu64.
	* i386-tbl.h: Regenerated.

2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
	from vstrszb, vstrszh, and vstrszf.

2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-opc.txt: Add instruction descriptions.

2019-02-08  Jim Wilson  <jimw@sifive.com>

	* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
	<bne>: Likewise.

2019-02-07  Tamar Christina  <tamar.christina@arm.com>

	* arm-dis.c (arm_opcodes): Redefine hlt to armv1.

2019-02-07  Tamar Christina  <tamar.christina@arm.com>

	PR binutils/23212
	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
	* aarch64-opc.c (verify_elem_sd): New.
	(fields): Add FLD_sz entr.
	* aarch64-tbl.h (_SIMD_INSN): New.
	(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
	fmulx scalar and vector by element isns.

2019-02-07  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.

2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-mkopc.c (main): Accept arch13 as cpu string.
	* s390-opc.c: Add new instruction formats and instruction opcode
	masks.
	* s390-opc.txt: Add new arch13 instructions.

2019-01-25  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (QL_LDST_AT): Update macro.
	(aarch64_opcode): Change encoding for stg, stzg
	st2g and st2zg.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

2019-01-25  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-tbl.h (aarch64_opcode): Add new stzgm.

2019-01-25  Sudakshina Das  <sudi.das@arm.com>
	    Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
	* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
	* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
	* aarch64-dis.h (ext_addr_simple_2): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Remove
	case for ldstgv_indexed.
	(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
	* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
	(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

2019-01-23  Nick Clifton  <nickc@redhat.com>

	* po/pt_BR.po: Updated Brazilian Portuguese translation.

2019-01-21  Nick Clifton  <nickc@redhat.com>

	* po/de.po: Updated German translation.
	* po/uk.po: Updated Ukranian translation.

2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
	* mips-dis.c (mips_arch_choices): Fix typo in
	gs464, gs464e and gs264e descriptors.

2019-01-19  Nick Clifton  <nickc@redhat.com>

	* configure: Regenerate.
	* po/opcodes.pot: Regenerate.

2018-06-24  Nick Clifton  <nickc@redhat.com>

	2.32 branch created.

2019-01-09  John Darrington <john@darrington.wattle.id.au>

	* s12z-dis.c (print_insn_s12z):  Do not dereference an operand
	if it is null.
	-dis.c (opr_emit_disassembly): Do not omit an index if it is
	zero.

2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>

	* configure: Regenerate.

2019-01-07  Alan Modra  <amodra@gmail.com>

	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2019-01-03  John Darrington <john@darrington.wattle.id.au>

	* s12z-opc.c: New file.
	* s12z-opc.h: New file.
	* s12z-dis.c: Removed all code not directly related to display
	of instructions.  Used the interface provided by the new files
	instead.
	* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
	* Makefile.in: Regenerate.
	* configure.ac (bfd_s12z_arch): Correct the dependencies.
	* configure: Regenerate.

2019-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2018
\f
Copyright (C) 2019 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
4a90ce95 JD	1	2019-04-29 John Darrington <john@darrington.wattle.id.au>
	2
	3	* s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
	4
a45328b9 AB	5	2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
	6	Faraz Shahbazker <fshahbazker@wavecomp.com>
	7
	8	* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
	9
d10be0cb JD	10	2019-04-24 John Darrington <john@darrington.wattle.id.au>
	11
	12	* s12z-opc.h: Add extern "C" bracketing to help
	13	users who wish to use this interface in c++ code.
	14
a679f24e JD	15	2019-04-24 John Darrington <john@darrington.wattle.id.au>
	16
	17	* s12z-opc.c (bm_decode): Handle bit map operations with the
	18	"reserved0" mode.
	19
32c36c3c AV	20	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	21
	22	* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
	23	specifier. Add entries for VLDR and VSTR of system registers.
	24	(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
	25	coprocessor instructions on Armv8.1-M Mainline targets. Add handling
	26	of %J and %K format specifier.
	27
efd6b359 AV	28	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	29
	30	* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
	31	Add new entries for VSCCLRM instruction.
	32	(print_insn_coprocessor): Handle new %C format control code.
	33
6b0dd094 AV	34	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	35
	36	* arm-dis.c (enum isa): New enum.
	37	(struct sopcode32): New structure.
	38	(coprocessor_opcodes): change type of entries to struct sopcode32 and
	39	set isa field of all current entries to ANY.
	40	(print_insn_coprocessor): Change type of insn to struct sopcode32.
	41	Only match an entry if its isa field allows the current mode.
	42
4b5a202f AV	43	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	44
	45	* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
	46	CLRM.
	47	(print_insn_thumb32): Add logic to print %n CLRM register list.
	48
60f993ce AV	49	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	50
	51	* arm-dis.c (print_insn_thumb32): Updated to accept new %P
	52	and %Q patterns.
	53
f6b2b12d AV	54	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	55
	56	* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
	57	(print_insn_thumb32): Edit the switch case for %Z.
	58
1889da70 AV	59	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	60
	61	* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
	62
65d1bc05 AV	63	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	64
	65	* arm-dis.c (thumb32_opcodes): New instruction bfl.
	66
1caf72a5 AV	67	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	68
	69	* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
	70
f1c7f421 AV	71	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	72
	73	* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
	74	Arm register with r13 and r15 unpredictable.
	75	(thumb32_opcodes): New instructions for bfx and bflx.
	76
4389b29a AV	77	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	78
	79	* arm-dis.c (thumb32_opcodes): New instructions for bf.
	80
e5d6e09e AV	81	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	82
	83	* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
	84
e12437dc AV	85	2019-04-15 Sudakshina Das <sudi.das@arm.com>
	86
	87	* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
	88
031254f2 AV	89	2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
	90
	91	* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
	92
e5a557ac JD	93	2019-04-12 John Darrington <john@darrington.wattle.id.au>
	94
	95	s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
	96	"optr". ("operator" is a reserved word in c++).
	97
bd7ceb8d SD	98	2019-04-11 Sudakshina Das <sudi.das@arm.com>
	99
	100	* aarch64-opc.c (aarch64_print_operand): Add case for
	101	AARCH64_OPND_Rt_SP.
	102	(verify_constraints): Likewise.
	103	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
	104	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
	105	to accept Rt\|SP as first operand.
	106	(AARCH64_OPERANDS): Add new Rt_SP.
	107	* aarch64-asm-2.c: Regenerated.
	108	* aarch64-dis-2.c: Regenerated.
	109	* aarch64-opc-2.c: Regenerated.
	110
e54010f1 SD	111	2019-04-11 Sudakshina Das <sudi.das@arm.com>
	112
	113	* aarch64-asm-2.c: Regenerated.
	114	* aarch64-dis-2.c: Likewise.
	115	* aarch64-opc-2.c: Likewise.
	116	* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
	117
7e96e219 RS	118	2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
	119
	120	* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
	121
6f2791d5 L	122	2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
	123
	124	* i386-opc.tbl: Consolidate AVX512 BF16 entries.
	125	* i386-init.h: Regenerated.
	126
e392bad3 AM	127	2019-04-07 Alan Modra <amodra@gmail.com>
	128
	129	* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
	130	op_separator to control printing of spaces, comma and parens
	131	rather than need_comma, need_paren and spaces vars.
	132
dffaa15c AM	133	2019-04-07 Alan Modra <amodra@gmail.com>
	134
	135	PR 24421
	136	* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
	137	(print_insn_neon, print_insn_arm): Likewise.
	138
d6aab7a1 XG	139	2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
	140
	141	* i386-dis-evex.h (evex_table): Updated to support BF16
	142	instructions.
	143	* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
	144	and EVEX_W_0F3872_P_3.
	145	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
	146	(cpu_flags): Add bitfield for CpuAVX512_BF16.
	147	* i386-opc.h (enum): Add CpuAVX512_BF16.
	148	(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
	149	* i386-opc.tbl: Add AVX512 BF16 instructions.
	150	* i386-init.h: Regenerated.
	151	* i386-tbl.h: Likewise.
	152
66e85460 AM	153	2019-04-05 Alan Modra <amodra@gmail.com>
	154
	155	* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
	156	(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
	157	to favour printing of "-" branch hint when using the "y" bit.
	158	Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
	159
c2b1c275 AM	160	2019-04-05 Alan Modra <amodra@gmail.com>
	161
	162	* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
	163	opcode until first operand is output.
	164
aae9718e PB	165	2019-04-04 Peter Bergner <bergner@linux.ibm.com>
	166
	167	PR gas/24349
	168	* ppc-opc.c (valid_bo_pre_v2): Add comments.
	169	(valid_bo_post_v2): Add support for 'at' branch hints.
	170	(insert_bo): Only error on branch on ctr.
	171	(get_bo_hint_mask): New function.
	172	(insert_boe): Add new 'branch_taken' formal argument. Add support
	173	for inserting 'at' branch hints.
	174	(extract_boe): Add new 'branch_taken' formal argument. Add support
	175	for extracting 'at' branch hints.
	176	(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
	177	(BOE): Delete operand.
	178	(BOM, BOP): New operands.
	179	(RM): Update value.
	180	(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
	181	(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
	182	bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
	183	(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
	184	bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
	185	<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
	186	bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
	187	bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
	188	bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
	189	bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
	190	bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
	191	bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
	192	bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
	193	beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
	194	bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
	195	buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
	196	bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
	197	bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
	198	bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
	199	bttarl+>: New extended mnemonics.
	200
96a86c01 AM	201	2019-03-28 Alan Modra <amodra@gmail.com>
	202
	203	PR 24390
	204	* ppc-opc.c (BTF): Define.
	205	(powerpc_opcodes): Use for mtfsb*.
	206	* ppc-dis.c (print_insn_powerpc): Print fields with both
	207	PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
	208
796d6298 TC	209	2019-03-25 Tamar Christina <tamar.christina@arm.com>
	210
	211	* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
	212	(mapping_symbol_for_insn): Implement new algorithm.
	213	(print_insn): Remove duplicate code.
	214
60df3720 TC	215	2019-03-25 Tamar Christina <tamar.christina@arm.com>
	216
	217	* aarch64-dis.c (print_insn_aarch64):
	218	Implement override.
	219
51457761 TC	220	2019-03-25 Tamar Christina <tamar.christina@arm.com>
	221
	222	* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
	223	order.
	224
53b2f36b TC	225	2019-03-25 Tamar Christina <tamar.christina@arm.com>
	226
	227	* aarch64-dis.c (last_stop_offset): New.
	228	(print_insn_aarch64): Use stop_offset.
	229
89199bb5 L	230	2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
	231
	232	PR gas/24359
	233	* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
	234	CPU_ANY_AVX2_FLAGS.
	235	* i386-init.h: Regenerated.
	236
97ed31ae L	237	2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
	238
	239	PR gas/24348
	240	* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
	241	vmovdqu16, vmovdqu32 and vmovdqu64.
	242	* i386-tbl.h: Regenerated.
	243
0919bfe9 AK	244	2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
	245
	246	* s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
	247	from vstrszb, vstrszh, and vstrszf.
	248
	249	2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
	250
	251	* s390-opc.txt: Add instruction descriptions.
	252
21820ebe JW	253	2019-02-08 Jim Wilson <jimw@sifive.com>
	254
	255	* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
	256	<bne>: Likewise.
	257
f7dd2fb2 TC	258	2019-02-07 Tamar Christina <tamar.christina@arm.com>
	259
	260	* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
	261
6456d318 TC	262	2019-02-07 Tamar Christina <tamar.christina@arm.com>
	263
	264	PR binutils/23212
	265	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
	266	* aarch64-opc.c (verify_elem_sd): New.
	267	(fields): Add FLD_sz entr.
	268	* aarch64-tbl.h (_SIMD_INSN): New.
	269	(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
	270	fmulx scalar and vector by element isns.
	271
4a83b610 NC	272	2019-02-07 Nick Clifton <nickc@redhat.com>
	273
	274	* po/sv.po: Updated Swedish translation.
	275
fc60b8c8 AK	276	2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
	277
	278	* s390-mkopc.c (main): Accept arch13 as cpu string.
	279	* s390-opc.c: Add new instruction formats and instruction opcode
	280	masks.
	281	* s390-opc.txt: Add new arch13 instructions.
	282
e10620d3 TC	283	2019-01-25 Sudakshina Das <sudi.das@arm.com>
	284
	285	* aarch64-tbl.h (QL_LDST_AT): Update macro.
	286	(aarch64_opcode): Change encoding for stg, stzg
	287	st2g and st2zg.
	288	* aarch64-asm-2.c: Regenerated.
	289	* aarch64-dis-2.c: Regenerated.
	290	* aarch64-opc-2.c: Regenerated.
	291
20a4ca55 SD	292	2019-01-25 Sudakshina Das <sudi.das@arm.com>
	293
	294	* aarch64-asm-2.c: Regenerated.
	295	* aarch64-dis-2.c: Likewise.
	296	* aarch64-opc-2.c: Likewise.
	297	* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
	298
550fd7bf SD	299	2019-01-25 Sudakshina Das <sudi.das@arm.com>
	300	Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
	301
	302	* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
	303	* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
	304	* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
	305	* aarch64-dis.h (ext_addr_simple_2): Likewise.
	306	* aarch64-opc.c (operand_general_constraint_met_p): Remove
	307	case for ldstgv_indexed.
	308	(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
	309	* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
	310	(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
	311	* aarch64-asm-2.c: Regenerated.
	312	* aarch64-dis-2.c: Regenerated.
	313	* aarch64-opc-2.c: Regenerated.
	314
d9938630 NC	315	2019-01-23 Nick Clifton <nickc@redhat.com>
	316
	317	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	318
375cd423 NC	319	2019-01-21 Nick Clifton <nickc@redhat.com>
	320
	321	* po/de.po: Updated German translation.
	322	* po/uk.po: Updated Ukranian translation.
	323
57299f48 CX	324	2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
	325	* mips-dis.c (mips_arch_choices): Fix typo in
	326	gs464, gs464e and gs264e descriptors.
	327
f48dfe41 NC	328	2019-01-19 Nick Clifton <nickc@redhat.com>
	329
	330	* configure: Regenerate.
	331	* po/opcodes.pot: Regenerate.
	332
f974f26c NC	333	2018-06-24 Nick Clifton <nickc@redhat.com>
	334
	335	2.32 branch created.
	336
39f286cd JD	337	2019-01-09 John Darrington <john@darrington.wattle.id.au>
39f286cd JD	338
448b8ca8 JD	339	* s12z-dis.c (print_insn_s12z): Do not dereference an operand
	340	if it is null.
	341	-dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd JD	342	zero.
39f286cd JD	343
3107326d AP	344	2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
	345
	346	* configure: Regenerate.
	347
7e9ca91e AM	348	2019-01-07 Alan Modra <amodra@gmail.com>
	349
	350	* configure: Regenerate.
	351	* po/POTFILES.in: Regenerate.
	352
ef1ad42b JD	353	2019-01-03 John Darrington <john@darrington.wattle.id.au>
	354
	355	* s12z-opc.c: New file.
	356	* s12z-opc.h: New file.
	357	* s12z-dis.c: Removed all code not directly related to display
	358	of instructions. Used the interface provided by the new files
	359	instead.
	360	* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e	361	* Makefile.in: Regenerate.
ef1ad42b	362	* configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e	363	* configure: Regenerate.
ef1ad42b	364
82704155 AM	365	2019-01-01 Alan Modra <amodra@gmail.com>
	366
	367	Update year range in copyright notice of all files.
	368
d5c04e1b	369	For older changes see ChangeLog-2018
3499769a	370	\f
d5c04e1b	371	Copyright (C) 2019 Free Software Foundation, Inc.
3499769a AM	372
	373	Copying and distribution of this file, with or without modification,
	374	are permitted in any medium without royalty provided the copyright
	375	notice and this notice are preserved.
	376
	377	Local Variables:
	378	mode: change-log
	379	left-margin: 8
	380	fill-column: 74
	381	version-control: never
	382	End: