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MIPS16/opcodes: Correct 64-bit macros' ISA membership
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4ebce1a0
MR		 12016-12-20 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
4 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
5 INSN_MACRO entries.
6
c97dda72
MR		 72016-12-20 Maciej W. Rozycki <macro@imgtec.com>
8
9 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
10 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
11 opcode).
12
3e67a378
AW		 132016-12-20 Andrew Waterman <andrew@sifive.com>
14
15 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
16 "*.aqrl".
17
04386d9e
AW		 182016-12-20 Andrew Waterman <andrew@sifive.com>
19
20 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
21 INSN_ALIAS.
22
755c5297
AW		 232016-12-20 Andrew Waterman <andrew@sifive.com>
24
25 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
26 format.
27
2922d21d
AW		 282016-12-20 Andrew Waterman <andrew@sifive.com>
29
30 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
31 XLEN when none is provided.
32
1d65abb5
AW		 332016-12-20 Andrew Waterman <andrew@sifive.com>
34
35 * riscv-opc.c: Formatting fixes.
36
dd1d944e
AM		 372016-12-20 Alan Modra <amodra@gmail.com>
38
39 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
40 * Makefile.in: Regenerate.
41 * po/POTFILES.in: Regenerate.
42
91068ec6
MR		 432016-12-19 Maciej W. Rozycki <macro@imgtec.com>
44
45 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
46 Only examine ELF file structures here.
47
4df995c7
MR		 482016-12-19 Maciej W. Rozycki <macro@imgtec.com>
49
50 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
51 `bfd_mips_elf_get_abiflags' here.
52
db7b55fa
NC		 532016-12-16 Nick Clifton <nickc@redhat.com>
54
55 * arm-dis.c (print_insn_thumb32): Fix compile time warning
56 computing value_in_comment.
57
5e7fc731
MR		 582016-12-14 Maciej W. Rozycki <macro@imgtec.com>
59
60 * mips-dis.c (mips_convert_abiflags_ases): New function.
61 (set_default_mips_dis_options): Also infer ASE flags from ELF
62 file structures.
63
8184783a
MR		 642016-12-14 Maciej W. Rozycki <macro@imgtec.com>
65
66 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
67 header flag interpretation code.
68
353abf7c
MR		 692016-12-14 Maciej W. Rozycki <macro@imgtec.com>
70
71 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
72 `pinfo2' with SP-relative "sd" entries.
73
63e014fc
MR		 742016-12-14 Maciej W. Rozycki <macro@imgtec.com>
75
76 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
77 compact jumps.
78
a6a51754
RL		 792016-12-13 Renlin Li <renlin.li@arm.com>
80
81 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
82 qualifier.
83 (operand_general_constraint_met_p): Remove case for CP_REG.
84 (aarch64_print_operand): Print CRn, CRm operand using imm field.
85 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
86 (QL_SYSL): Likewise.
87 (aarch64_opcode_table): Change CRn, CRm operand class and type.
88 * aarch64-opc-2.c : Regenerate.
89 * aarch64-asm-2.c : Likewise.
90 * aarch64-dis-2.c : Likewise.
91
029e9d52
YQ		 922016-12-12 Yao Qi <yao.qi@linaro.org>
93
94 * rx-dis.c: Include <setjmp.h>
95 (struct private): New.
96 (rx_get_byte): Check return value of read_memory_func, and
97 call memory_error_func and OPCODES_SIGLONGJMP on error.
98 (print_insn_rx): Call OPCODES_SIGSETJMP.
99
3a0b8f7d
YQ		 1002016-12-12 Yao Qi <yao.qi@linaro.org>
101
102 * rl78-dis.c: Include <setjmp.h>.
103 (struct private): New.
104 (rl78_get_byte): Check return value of read_memory_func, and
105 call memory_error_func and OPCODES_SIGLONGJMP on error.
106 (print_insn_rl78_common): Call OPCODES_SIGJMP.
107
64c11183
MR		 1082016-12-09 Maciej W. Rozycki <macro@imgtec.com>
109
110 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
111
f17ecb4b
MR		 1122016-12-09 Maciej W. Rozycki <macro@imgtec.com>
113
114 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
115 than UINT.
116
55af4784
MR		 1172016-12-09 Maciej W. Rozycki <macro@imgtec.com>
118
119 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
120 to separate `extend' and its uninterpreted argument output.
121 Separate hexadecimal halves of undecoded extended instructions
122 output.
123
39f66f3a
MR		 1242016-12-08 Maciej W. Rozycki <macro@imgtec.com>
125
126 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
127 indentation space across.
128
860b03a8
MR		 1292016-12-08 Maciej W. Rozycki <macro@imgtec.com>
130
131 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
132 adjustment for PC-relative operations following MIPS16e compact
133 jumps or undefined RR/J(AL)R(C) encodings.
134
329d01f7
MR		 1352016-12-08 Maciej W. Rozycki <macro@imgtec.com>
136
137 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
138 variable to `reglane_index'.
139
3a2488dd
LM		 1402016-12-08 Luis Machado <lgustavo@codesourcery.com>
141
142 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
143
5f5c6e03
MR		 1442016-12-07 Maciej W. Rozycki <macro@imgtec.com>
145
146 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
147
343fa690
MR		 1482016-12-07 Maciej W. Rozycki <macro@imgtec.com>
149
150 * mips16-opc.c (mips16_opcodes): Update comment naming structure
151 members.
152
6725647c
MR		 1532016-12-07 Maciej W. Rozycki <macro@imgtec.com>
154
155 * mips-dis.c (print_mips_disassembler_options): Reformat output.
156
c28eeff2
SN		 1572016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
158
159 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
160 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
161
49e8a725
SN		 1622016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
163
164 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
165
a37a2806
NC		 1662016-12-01 Nick Clifton <nickc@redhat.com>
167
168 PR binutils/20893
169 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
170 opcode designator.
171
abe7c33b
CZ		 1722016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
173
174 * arc-opc.c (insert_ra_chk): New function.
175 (insert_rb_chk): Likewise.
176 (insert_rad): Update text error message.
177 (insert_rcd): Likewise.
178 (insert_rhv2): Likewise.
179 (insert_r0): Likewise.
180 (insert_r1): Likewise.
181 (insert_r2): Likewise.
182 (insert_r3): Likewise.
183 (insert_sp): Likewise.
184 (insert_gp): Likewise.
185 (insert_pcl): Likewise.
186 (insert_blink): Likewise.
187 (insert_ilink1): Likewise.
188 (insert_ilink2): Likewise.
189 (insert_ras): Likewise.
190 (insert_rbs): Likewise.
191 (insert_rcs): Likewise.
192 (insert_simm3s): Likewise.
193 (insert_rrange): Likewise.
194 (insert_fpel): Likewise.
195 (insert_blinkel): Likewise.
196 (insert_pcel): Likewise.
197 (insert_nps_3bit_dst): Likewise.
198 (insert_nps_3bit_dst_short): Likewise.
199 (insert_nps_3bit_src2_short): Likewise.
200 (insert_nps_bitop_size_2b): Likewise.
201 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
202 (RA_CHK): Define.
203 (RB): Adjust.
204 (RB_CHK): Define.
205 (RC): Adjust.
206 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
207 * arc-tbl.h (div, divu): All instructions are DIVREM class.
208 Change first insn argument to check for LP_COUNT usage.
209 (rem): Likewise.
210 (ld, ldd): All instructions are LOAD class. Change first insn
211 argument to check for LP_COUNT usage.
212 (st, std): All instructions are STORE class.
213 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
214 Change first insn argument to check for LP_COUNT usage.
215 (mov): All instructions are MOVE class. Change first insn
216 argument to check for LP_COUNT usage.
217
ee881e5d
CZ		 2182016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
219
220 * arc-dis.c (is_compatible_p): Remove function.
221 (skip_this_opcode): Don't add any decoding class to decode list.
222 Remove warning.
223 (find_format_from_table): Go through all opcodes, and warn if we
224 use a guessed mnemonic.
225
abfcb414
AP		 2262016-11-28 Ramiro Polla <ramiro@hex-rays.com>
227 Amit Pawar <amit.pawar@amd.com>
228
229 PR binutils/20637
230 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
231 instructions.
232
96fe4562
AM		 2332016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
234
235 * configure: Regenerate.
236
6884417a
JM		 2372016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
238
239 * sparc-opc.c (HWS_V8): Definition moved from
240 gas/config/tc-sparc.c.
241 (HWS_V9): Likewise.
242 (HWS_VA): Likewise.
243 (HWS_VB): Likewise.
244 (HWS_VC): Likewise.
245 (HWS_VD): Likewise.
246 (HWS_VE): Likewise.
247 (HWS_VV): Likewise.
248 (HWS_VM): Likewise.
249 (HWS2_VM): Likewise.
250 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
251 existing entries.
252
c4b943d7
CZ		 2532016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
254
255 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
256 instructions.
257
c2c4ff8d
SN		 2582016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
259
260 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
261 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
262 (aarch64_opcode_table): Add fcmla and fcadd.
263 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
264 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
265 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
266 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
267 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
268 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
269 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
270 (operand_general_constraint_met_p): Rotate and index range check.
271 (aarch64_print_operand): Handle rotate operand.
272 * aarch64-asm-2.c: Regenerate.
273 * aarch64-dis-2.c: Likewise.
274 * aarch64-opc-2.c: Likewise.
275
28617675
SN		 2762016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
277
278 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
279 * aarch64-asm-2.c: Regenerate.
280 * aarch64-dis-2.c: Regenerate.
281 * aarch64-opc-2.c: Regenerate.
282
ccfc90a3
SN		 2832016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
284
285 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
286 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
287 * aarch64-asm-2.c: Regenerate.
288 * aarch64-dis-2.c: Regenerate.
289 * aarch64-opc-2.c: Regenerate.
290
3f06e550
SN		 2912016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
292
293 * aarch64-tbl.h (QL_X1NIL): New.
294 (arch64_opcode_table): Add ldraa, ldrab.
295 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
296 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
297 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
298 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
299 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
300 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
301 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
302 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
303 (aarch64_print_operand): Likewise.
304 * aarch64-asm-2.c: Regenerate.
305 * aarch64-dis-2.c: Regenerate.
306 * aarch64-opc-2.c: Regenerate.
307
74f5402d
SN		 3082016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
309
310 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
311 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
312 * aarch64-asm-2.c: Regenerate.
313 * aarch64-dis-2.c: Regenerate.
314 * aarch64-opc-2.c: Regenerate.
315
c84364ec
SN		 3162016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
317
318 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
319 (AARCH64_OPERANDS): Add Rm_SP.
320 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
321 * aarch64-asm-2.c: Regenerate.
322 * aarch64-dis-2.c: Regenerate.
323 * aarch64-opc-2.c: Regenerate.
324
a2cfc830
SN		 3252016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
326
327 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
328 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
329 autdzb, xpaci, xpacd.
330 * aarch64-asm-2.c: Regenerate.
331 * aarch64-dis-2.c: Regenerate.
332 * aarch64-opc-2.c: Regenerate.
333
b0bfa7b5
SN		 3342016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
335
336 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
337 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
338 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
339 (aarch64_sys_reg_supported_p): Add feature test for new registers.
340
8787d804
SN		 3412016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
342
343 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
344 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
345 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
346 autibsp.
347 * aarch64-asm-2.c: Regenerate.
348 * aarch64-dis-2.c: Regenerate.
349
3d731f69
SN		 3502016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
351
352 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
353
60227d64
L		 3542016-11-09 H.J. Lu <hongjiu.lu@intel.com>
355
356 PR binutils/20799
357 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
358 * i386-dis.c (EdqwS): Removed.
359 (dqw_swap_mode): Likewise.
360 (intel_operand_size): Don't check dqw_swap_mode.
361 (OP_E_register): Likewise.
362 (OP_E_memory): Likewise.
363 (OP_G): Likewise.
364 (OP_EX): Likewise.
365 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
366 * i386-tbl.h: Regerated.
367
7efeed17
L		 3682016-11-09 H.J. Lu <hongjiu.lu@intel.com>
369
370 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 371 * i386-tbl.h: Regerated.
7efeed17 372
1f334aeb
L		 3732016-11-08 H.J. Lu <hongjiu.lu@intel.com>
374
375 PR binutils/20701
376 * i386-dis.c (THREE_BYTE_0F7A): Removed.
377 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
378 (three_byte_table): Remove THREE_BYTE_0F7A.
379
48c97fa1
L		 3802016-11-07 H.J. Lu <hongjiu.lu@intel.com>
381
382 PR binutils/20775
383 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
384 (FGRPd9_4): Replace 1 with 2.
385 (FGRPd9_5): Replace 2 with 3.
386 (FGRPd9_6): Replace 3 with 4.
387 (FGRPd9_7): Replace 4 with 5.
388 (FGRPda_5): Replace 5 with 6.
389 (FGRPdb_4): Replace 6 with 7.
390 (FGRPde_3): Replace 7 with 8.
391 (FGRPdf_4): Replace 8 with 9.
392 (fgrps): Add an entry for Bad_Opcode.
393
b437d035
AB		 3942016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
395
396 * arc-opc.c (arc_flag_operands): Add F_DI14.
397 (arc_flag_classes): Add C_DI14.
398 * arc-nps400-tbl.h: Add new exc instructions.
399
5a736821
GM		 4002016-11-03 Graham Markall <graham.markall@embecosm.com>
401
402 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
403 major opcode 0xa.
404 * arc-nps-400-tbl.h: Add dcmac instruction.
405 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
406 (insert_nps_rbdouble_64): Added.
407 (extract_nps_rbdouble_64): Added.
408 (insert_nps_proto_size): Added.
409 (extract_nps_proto_size): Added.
410
bdfe53e3
AB		 4112016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
412
413 * arc-dis.c (struct arc_operand_iterator): Remove all fields
414 relating to long instruction processing, add new limm field.
415 (OPCODE): Rename to...
416 (OPCODE_32BIT_INSN): ...this.
417 (OPCODE_AC): Delete.
418 (skip_this_opcode): Handle different instruction lengths, update
419 macro name.
420 (special_flag_p): Update parameter type.
421 (find_format_from_table): Update for more instruction lengths.
422 (find_format_long_instructions): Delete.
423 (find_format): Update for more instruction lengths.
424 (arc_insn_length): Likewise.
425 (extract_operand_value): Update for more instruction lengths.
426 (operand_iterator_next): Remove code relating to long
427 instructions.
428 (arc_opcode_to_insn_type): New function.
429 (print_insn_arc):Update for more instructions lengths.
430 * arc-ext.c (extInstruction_t): Change argument type.
431 * arc-ext.h (extInstruction_t): Change argument type.
432 * arc-fxi.h: Change type unsigned to unsigned long long
433 extensively throughout.
434 * arc-nps400-tbl.h: Add long instructions taken from
435 arc_long_opcodes table in arc-opc.c.
436 * arc-opc.c: Update parameter types on insert/extract handlers.
437 (arc_long_opcodes): Delete.
438 (arc_num_long_opcodes): Delete.
439 (arc_opcode_len): Update for more instruction lengths.
440
90f61cce
GM		 4412016-11-03 Graham Markall <graham.markall@embecosm.com>
442
443 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
444
06fe285f
GM		 4452016-11-03 Graham Markall <graham.markall@embecosm.com>
446
447 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
448 with arc_opcode_len.
449 (find_format_long_instructions): Likewise.
450 * arc-opc.c (arc_opcode_len): New function.
451
ecf64ec6
AB		 4522016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
453
454 * arc-nps400-tbl.h: Fix some instruction masks.
455
d039fef3
L		 4562016-11-03 H.J. Lu <hongjiu.lu@intel.com>
457
458 * i386-dis.c (REG_82): Removed.
459 (X86_64_82_REG_0): Likewise.
460 (X86_64_82_REG_1): Likewise.
461 (X86_64_82_REG_2): Likewise.
462 (X86_64_82_REG_3): Likewise.
463 (X86_64_82_REG_4): Likewise.
464 (X86_64_82_REG_5): Likewise.
465 (X86_64_82_REG_6): Likewise.
466 (X86_64_82_REG_7): Likewise.
467 (X86_64_82): New.
468 (dis386): Use X86_64_82 instead of REG_82.
469 (reg_table): Remove REG_82.
470 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
471 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
472 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
473 X86_64_82_REG_7.
474
8b89fe14
L		 4752016-11-03 H.J. Lu <hongjiu.lu@intel.com>
476
477 PR binutils/20754
478 * i386-dis.c (REG_82): New.
479 (X86_64_82_REG_0): Likewise.
480 (X86_64_82_REG_1): Likewise.
481 (X86_64_82_REG_2): Likewise.
482 (X86_64_82_REG_3): Likewise.
483 (X86_64_82_REG_4): Likewise.
484 (X86_64_82_REG_5): Likewise.
485 (X86_64_82_REG_6): Likewise.
486 (X86_64_82_REG_7): Likewise.
487 (dis386): Use REG_82.
488 (reg_table): Add REG_82.
489 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
490 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
491 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
492
7148c369
L		 4932016-11-03 H.J. Lu <hongjiu.lu@intel.com>
494
495 * i386-dis.c (REG_82): Renamed to ...
496 (REG_83): This.
497 (dis386): Updated.
498 (reg_table): Likewise.
499
47acf0bd
IT		 5002016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
501
502 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
503 * i386-dis-evex.h (evex_table): Updated.
504 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
505 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
506 (cpu_flags): Add CpuAVX512_4VNNIW.
507 * i386-opc.h (enum): (AVX512_4VNNIW): New.
508 (i386_cpu_flags): Add cpuavx512_4vnniw.
509 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
510 * i386-init.h: Regenerate.
511 * i386-tbl.h: Ditto.
512
920d2ddc
IT		 5132016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
514
515 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
516 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
517 * i386-dis-evex.h (evex_table): Updated.
518 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
519 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
520 (cpu_flags): Add CpuAVX512_4FMAPS.
521 (opcode_modifiers): Add ImplicitQuadGroup modifier.
522 * i386-opc.h (AVX512_4FMAP): New.
523 (i386_cpu_flags): Add cpuavx512_4fmaps.
524 (ImplicitQuadGroup): New.
525 (i386_opcode_modifier): Add implicitquadgroup.
526 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
527 * i386-init.h: Regenerate.
528 * i386-tbl.h: Ditto.
529
e23eba97
NC		 5302016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
531 Andrew Waterman <andrew@sifive.com>
532
533 Add support for RISC-V architecture.
534 * configure.ac: Add entry for bfd_riscv_arch.
535 * configure: Regenerate.
536 * disassemble.c (disassembler): Add support for riscv.
537 (disassembler_usage): Likewise.
538 * riscv-dis.c: New file.
539 * riscv-opc.c: New file.
540
b5cefcca
L		 5412016-10-21 H.J. Lu <hongjiu.lu@intel.com>
542
543 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
544 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
545 (rm_table): Update the RM_0FAE_REG_7 entry.
546 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
547 (cpu_flags): Remove CpuPCOMMIT.
548 * i386-opc.h (CpuPCOMMIT): Removed.
549 (i386_cpu_flags): Remove cpupcommit.
550 * i386-opc.tbl: Remove pcommit.
551 * i386-init.h: Regenerated.
552 * i386-tbl.h: Likewise.
553
9889cbb1
L		 5542016-10-20 H.J. Lu <hongjiu.lu@intel.com>
555
556 PR binutis/20705
557 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
558 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
559 32-bit mode. Don't check vex.register_specifier in 32-bit
560 mode.
561 (OP_VEX): Check for invalid mask registers.
562
28596323
L		 5632016-10-18 H.J. Lu <hongjiu.lu@intel.com>
564
565 PR binutis/20699
566 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
567 sizeflag.
568
da8d7d66
L		 5692016-10-18 H.J. Lu <hongjiu.lu@intel.com>
570
571 PR binutis/20704
572 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
573
eaf02703
MR		 5742016-10-18 Maciej W. Rozycki <macro@imgtec.com>
575
576 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
577 local variable to `index_regno'.
578
decf5bd1
CM		 5792016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
580
581 * arc-tbl.h: Removed any "inv.+" instructions from the table.
582
e5b06ef0
CZ		 5832016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
584
585 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
586 usage on ISA basis.
587
93562a34
JW		 5882016-10-11 Jiong Wang <jiong.wang@arm.com>
589
590 PR target/20666
591 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
592
362c0c4d
JW		 5932016-10-07 Jiong Wang <jiong.wang@arm.com>
594
595 PR target/20667
596 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
597 available.
598
1047201f
AM		 5992016-10-07 Alan Modra <amodra@gmail.com>
600
601 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
602
1a0670f3
AM		 6032016-10-06 Alan Modra <amodra@gmail.com>
604
605 * aarch64-opc.c: Spell fall through comments consistently.
606 * i386-dis.c: Likewise.
607 * aarch64-dis.c: Add missing fall through comments.
608 * aarch64-opc.c: Likewise.
609 * arc-dis.c: Likewise.
610 * arm-dis.c: Likewise.
611 * i386-dis.c: Likewise.
612 * m68k-dis.c: Likewise.
613 * mep-asm.c: Likewise.
614 * ns32k-dis.c: Likewise.
615 * sh-dis.c: Likewise.
616 * tic4x-dis.c: Likewise.
617 * tic6x-dis.c: Likewise.
618 * vax-dis.c: Likewise.
619
2b804145
AM		 6202016-10-06 Alan Modra <amodra@gmail.com>
621
622 * arc-ext.c (create_map): Add missing break.
623 * msp430-decode.opc (encode_as): Likewise.
624 * msp430-decode.c: Regenerate.
625
616ec358
AM		 6262016-10-06 Alan Modra <amodra@gmail.com>
627
628 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
629 * crx-dis.c (print_insn_crx): Likewise.
630
72da393d
L		 6312016-09-30 H.J. Lu <hongjiu.lu@intel.com>
632
633 PR binutils/20657
634 * i386-dis.c (putop): Don't assign alt twice.
635
744ce302
JW		 6362016-09-29 Jiong Wang <jiong.wang@arm.com>
637
638 PR target/20553
639 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
640
a5721ba2
AM		 6412016-09-29 Alan Modra <amodra@gmail.com>
642
643 * ppc-opc.c (L): Make compulsory.
644 (LOPT): New, optional form of L.
645 (HTM_R): Define as LOPT.
646 (L0, L1): Delete.
647 (L32OPT): New, optional for 32-bit L.
648 (L2OPT): New, 2-bit L for dcbf.
649 (SVC_LEC): Update.
650 (L2): Define.
651 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
652 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
653 <dcbf>: Use L2OPT.
654 <tlbiel, tlbie>: Use LOPT.
655 <wclr, wclrall>: Use L2.
656
c5da1932
VZ		 6572016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
658
659 * Makefile.in: Regenerate.
660 * configure: Likewise.
661
2b848ebd
CZ		 6622016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
663
664 * arc-ext-tbl.h (EXTINSN2OPF): Define.
665 (EXTINSN2OP): Use EXTINSN2OPF.
666 (bspeekm, bspop, modapp): New extension instructions.
667 * arc-opc.c (F_DNZ_ND): Define.
668 (F_DNZ_D): Likewise.
669 (F_SIZEB1): Changed.
670 (C_DNZ_D): Define.
671 (C_HARD): Changed.
672 * arc-tbl.h (dbnz): New instruction.
673 (prealloc): Allow it for ARC EM.
674 (xbfu): Likewise.
675
ad43e107
RS		 6762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
677
678 * aarch64-opc.c (print_immediate_offset_address): Print spaces
679 after commas in addresses.
680 (aarch64_print_operand): Likewise.
681
ab3b8fcf
RS		 6822016-09-21 Richard Sandiford <richard.sandiford@arm.com>
683
684 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
685 rather than "should be" or "expected to be" in error messages.
686
bb7eff52
RS		 6872016-09-21 Richard Sandiford <richard.sandiford@arm.com>
688
689 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
690 (print_mnemonic_name): ...here.
691 (print_comment): New function.
692 (print_aarch64_insn): Call it.
693 * aarch64-opc.c (aarch64_conds): Add SVE names.
694 (aarch64_print_operand): Print alternative condition names in
695 a comment.
696
c0890d26
RS		 6972016-09-21 Richard Sandiford <richard.sandiford@arm.com>
698
699 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
700 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
701 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
702 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
703 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
704 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
705 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
706 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
707 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
708 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
709 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
710 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
711 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
712 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
713 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
714 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
715 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
716 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
717 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
718 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
719 (OP_SVE_XWU, OP_SVE_XXU): New macros.
720 (aarch64_feature_sve): New variable.
721 (SVE): New macro.
722 (_SVE_INSN): Likewise.
723 (aarch64_opcode_table): Add SVE instructions.
724 * aarch64-opc.h (extract_fields): Declare.
725 * aarch64-opc-2.c: Regenerate.
726 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
727 * aarch64-asm-2.c: Regenerate.
728 * aarch64-dis.c (extract_fields): Make global.
729 (do_misc_decoding): Handle the new SVE aarch64_ops.
730 * aarch64-dis-2.c: Regenerate.
731
116b6019
RS		 7322016-09-21 Richard Sandiford <richard.sandiford@arm.com>
733
734 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
735 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
736 aarch64_field_kinds.
737 * aarch64-opc.c (fields): Add corresponding entries.
738 * aarch64-asm.c (aarch64_get_variant): New function.
739 (aarch64_encode_variant_using_iclass): Likewise.
740 (aarch64_opcode_encode): Call it.
741 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
742 (aarch64_opcode_decode): Call it.
743
047cd301
RS		 7442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
745
746 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
747 and FP register operands.
748 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
749 (FLD_SVE_Vn): New aarch64_field_kinds.
750 * aarch64-opc.c (fields): Add corresponding entries.
751 (aarch64_print_operand): Handle the new SVE core and FP register
752 operands.
753 * aarch64-opc-2.c: Regenerate.
754 * aarch64-asm-2.c: Likewise.
755 * aarch64-dis-2.c: Likewise.
756
165d4950
RS		 7572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
758
759 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
760 immediate operands.
761 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
762 * aarch64-opc.c (fields): Add corresponding entry.
763 (operand_general_constraint_met_p): Handle the new SVE FP immediate
764 operands.
765 (aarch64_print_operand): Likewise.
766 * aarch64-opc-2.c: Regenerate.
767 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
768 (ins_sve_float_zero_one): New inserters.
769 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
770 (aarch64_ins_sve_float_half_two): Likewise.
771 (aarch64_ins_sve_float_zero_one): Likewise.
772 * aarch64-asm-2.c: Regenerate.
773 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
774 (ext_sve_float_zero_one): New extractors.
775 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
776 (aarch64_ext_sve_float_half_two): Likewise.
777 (aarch64_ext_sve_float_zero_one): Likewise.
778 * aarch64-dis-2.c: Regenerate.
779
e950b345
RS		 7802016-09-21 Richard Sandiford <richard.sandiford@arm.com>
781
782 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
783 integer immediate operands.
784 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
785 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
786 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
787 * aarch64-opc.c (fields): Add corresponding entries.
788 (operand_general_constraint_met_p): Handle the new SVE integer
789 immediate operands.
790 (aarch64_print_operand): Likewise.
791 (aarch64_sve_dupm_mov_immediate_p): New function.
792 * aarch64-opc-2.c: Regenerate.
793 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
794 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
795 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
796 (aarch64_ins_limm): ...here.
797 (aarch64_ins_inv_limm): New function.
798 (aarch64_ins_sve_aimm): Likewise.
799 (aarch64_ins_sve_asimm): Likewise.
800 (aarch64_ins_sve_limm_mov): Likewise.
801 (aarch64_ins_sve_shlimm): Likewise.
802 (aarch64_ins_sve_shrimm): Likewise.
803 * aarch64-asm-2.c: Regenerate.
804 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
805 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
806 * aarch64-dis.c (decode_limm): New function, split out from...
807 (aarch64_ext_limm): ...here.
808 (aarch64_ext_inv_limm): New function.
809 (decode_sve_aimm): Likewise.
810 (aarch64_ext_sve_aimm): Likewise.
811 (aarch64_ext_sve_asimm): Likewise.
812 (aarch64_ext_sve_limm_mov): Likewise.
813 (aarch64_top_bit): Likewise.
814 (aarch64_ext_sve_shlimm): Likewise.
815 (aarch64_ext_sve_shrimm): Likewise.
816 * aarch64-dis-2.c: Regenerate.
817
98907a70
RS		 8182016-09-21 Richard Sandiford <richard.sandiford@arm.com>
819
820 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
821 operands.
822 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
823 the AARCH64_MOD_MUL_VL entry.
824 (value_aligned_p): Cope with non-power-of-two alignments.
825 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
826 (print_immediate_offset_address): Likewise.
827 (aarch64_print_operand): Likewise.
828 * aarch64-opc-2.c: Regenerate.
829 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
830 (ins_sve_addr_ri_s9xvl): New inserters.
831 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
832 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
833 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
834 * aarch64-asm-2.c: Regenerate.
835 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
836 (ext_sve_addr_ri_s9xvl): New extractors.
837 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
838 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
839 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
840 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
841 * aarch64-dis-2.c: Regenerate.
842
4df068de
RS		 8432016-09-21 Richard Sandiford <richard.sandiford@arm.com>
844
845 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
846 address operands.
847 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
848 (FLD_SVE_xs_22): New aarch64_field_kinds.
849 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
850 (get_operand_specific_data): New function.
851 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
852 FLD_SVE_xs_14 and FLD_SVE_xs_22.
853 (operand_general_constraint_met_p): Handle the new SVE address
854 operands.
855 (sve_reg): New array.
856 (get_addr_sve_reg_name): New function.
857 (aarch64_print_operand): Handle the new SVE address operands.
858 * aarch64-opc-2.c: Regenerate.
859 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
860 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
861 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
862 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
863 (aarch64_ins_sve_addr_rr_lsl): Likewise.
864 (aarch64_ins_sve_addr_rz_xtw): Likewise.
865 (aarch64_ins_sve_addr_zi_u5): Likewise.
866 (aarch64_ins_sve_addr_zz): Likewise.
867 (aarch64_ins_sve_addr_zz_lsl): Likewise.
868 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
869 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
870 * aarch64-asm-2.c: Regenerate.
871 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
872 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
873 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
874 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
875 (aarch64_ext_sve_addr_ri_u6): Likewise.
876 (aarch64_ext_sve_addr_rr_lsl): Likewise.
877 (aarch64_ext_sve_addr_rz_xtw): Likewise.
878 (aarch64_ext_sve_addr_zi_u5): Likewise.
879 (aarch64_ext_sve_addr_zz): Likewise.
880 (aarch64_ext_sve_addr_zz_lsl): Likewise.
881 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
882 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
883 * aarch64-dis-2.c: Regenerate.
884
2442d846
RS		 8852016-09-21 Richard Sandiford <richard.sandiford@arm.com>
886
887 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
888 AARCH64_OPND_SVE_PATTERN_SCALED.
889 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
890 * aarch64-opc.c (fields): Add a corresponding entry.
891 (set_multiplier_out_of_range_error): New function.
892 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
893 (operand_general_constraint_met_p): Handle
894 AARCH64_OPND_SVE_PATTERN_SCALED.
895 (print_register_offset_address): Use PRIi64 to print the
896 shift amount.
897 (aarch64_print_operand): Likewise. Handle
898 AARCH64_OPND_SVE_PATTERN_SCALED.
899 * aarch64-opc-2.c: Regenerate.
900 * aarch64-asm.h (ins_sve_scale): New inserter.
901 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
902 * aarch64-asm-2.c: Regenerate.
903 * aarch64-dis.h (ext_sve_scale): New inserter.
904 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
905 * aarch64-dis-2.c: Regenerate.
906
245d2e3f
RS		 9072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
908
909 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
910 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
911 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
912 (FLD_SVE_prfop): Likewise.
913 * aarch64-opc.c: Include libiberty.h.
914 (aarch64_sve_pattern_array): New variable.
915 (aarch64_sve_prfop_array): Likewise.
916 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
917 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
918 AARCH64_OPND_SVE_PRFOP.
919 * aarch64-asm-2.c: Regenerate.
920 * aarch64-dis-2.c: Likewise.
921 * aarch64-opc-2.c: Likewise.
922
d50c751e
RS		 9232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
924
925 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
926 AARCH64_OPND_QLF_P_[ZM].
927 (aarch64_print_operand): Print /z and /m where appropriate.
928
f11ad6bc
RS		 9292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
930
931 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
932 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
933 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
934 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
935 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
936 * aarch64-opc.c (fields): Add corresponding entries here.
937 (operand_general_constraint_met_p): Check that SVE register lists
938 have the correct length. Check the ranges of SVE index registers.
939 Check for cases where p8-p15 are used in 3-bit predicate fields.
940 (aarch64_print_operand): Handle the new SVE operands.
941 * aarch64-opc-2.c: Regenerate.
942 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
943 * aarch64-asm.c (aarch64_ins_sve_index): New function.
944 (aarch64_ins_sve_reglist): Likewise.
945 * aarch64-asm-2.c: Regenerate.
946 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
947 * aarch64-dis.c (aarch64_ext_sve_index): New function.
948 (aarch64_ext_sve_reglist): Likewise.
949 * aarch64-dis-2.c: Regenerate.
950
0c608d6b
RS		 9512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
952
953 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
954 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
955 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
956 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
957 tied operands.
958
01dbfe4c
RS		 9592016-09-21 Richard Sandiford <richard.sandiford@arm.com>
960
961 * aarch64-opc.c (get_offset_int_reg_name): New function.
962 (print_immediate_offset_address): Likewise.
963 (print_register_offset_address): Take the base and offset
964 registers as parameters.
965 (aarch64_print_operand): Update caller accordingly. Use
966 print_immediate_offset_address.
967
72e9f319
RS		 9682016-09-21 Richard Sandiford <richard.sandiford@arm.com>
969
970 * aarch64-opc.c (BANK): New macro.
971 (R32, R64): Take a register number as argument
972 (int_reg): Use BANK.
973
8a7f0c1b
RS		 9742016-09-21 Richard Sandiford <richard.sandiford@arm.com>
975
976 * aarch64-opc.c (print_register_list): Add a prefix parameter.
977 (aarch64_print_operand): Update accordingly.
978
aa2aa4c6
RS		 9792016-09-21 Richard Sandiford <richard.sandiford@arm.com>
980
981 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
982 for FPIMM.
983 * aarch64-asm.h (ins_fpimm): New inserter.
984 * aarch64-asm.c (aarch64_ins_fpimm): New function.
985 * aarch64-asm-2.c: Regenerate.
986 * aarch64-dis.h (ext_fpimm): New extractor.
987 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
988 (aarch64_ext_fpimm): New function.
989 * aarch64-dis-2.c: Regenerate.
990
b5464a68
RS		 9912016-09-21 Richard Sandiford <richard.sandiford@arm.com>
992
993 * aarch64-asm.c: Include libiberty.h.
994 (insert_fields): New function.
995 (aarch64_ins_imm): Use it.
996 * aarch64-dis.c (extract_fields): New function.
997 (aarch64_ext_imm): Use it.
998
42408347
RS		 9992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1000
1001 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1002 with an esize parameter.
1003 (operand_general_constraint_met_p): Update accordingly.
1004 Fix misindented code.
1005 * aarch64-asm.c (aarch64_ins_limm): Update call to
1006 aarch64_logical_immediate_p.
1007
4989adac
RS		 10082016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1009
1010 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1011
bd11d5d8
RS		 10122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1013
1014 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1015
f807f43d
CZ		 10162016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1017
1018 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1019
fd486b63
PB		 10202016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1021
1022 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1023 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1024 xor3>: Delete mnemonics.
1025 <cp_abort>: Rename mnemonic from ...
1026 <cpabort>: ...to this.
1027 <setb>: Change to a X form instruction.
1028 <sync>: Change to 1 operand form.
1029 <copy>: Delete mnemonic.
1030 <copy_first>: Rename mnemonic from ...
1031 <copy>: ...to this.
1032 <paste, paste.>: Delete mnemonics.
1033 <paste_last>: Rename mnemonic from ...
1034 <paste.>: ...to this.
1035
dce08442
AK		 10362016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1037
1038 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1039
952c3f51
AK		 10402016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1041
1042 * s390-mkopc.c (main): Support alternate arch strings.
1043
8b71537b
PS		 10442016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1045
1046 * s390-opc.txt: Fix kmctr instruction type.
1047
5b64d091
L		 10482016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1049
1050 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1051 * i386-init.h: Regenerated.
1052
7763838e
CM		 10532016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1054
1055 * opcodes/arc-dis.c (print_insn_arc): Changed.
1056
1b8b6532
JM		 10572016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1058
1059 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1060 camellia_fl.
1061
1a336194
TP		 10622016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1063
1064 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1065 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1066 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1067
6b40c462
L		 10682016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1069
1070 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1071 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1072 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1073 PREFIX_MOD_3_0FAE_REG_4.
1074 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1075 PREFIX_MOD_3_0FAE_REG_4.
1076 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1077 (cpu_flags): Add CpuPTWRITE.
1078 * i386-opc.h (CpuPTWRITE): New.
1079 (i386_cpu_flags): Add cpuptwrite.
1080 * i386-opc.tbl: Add ptwrite instruction.
1081 * i386-init.h: Regenerated.
1082 * i386-tbl.h: Likewise.
1083
ab548d2d
AK		 10842016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1085
1086 * arc-dis.h: Wrap around in extern "C".
1087
344bde0a
RS		 10882016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1089
1090 * aarch64-tbl.h (V8_2_INSN): New macro.
1091 (aarch64_opcode_table): Use it.
1092
5ce912d8
RS		 10932016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1094
1095 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1096 CORE_INSN, __FP_INSN and SIMD_INSN.
1097
9d30b0bd
RS		 10982016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1099
1100 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1101 (aarch64_opcode_table): Update uses accordingly.
1102
dfdaec14
AJ		 11032016-07-25 Andrew Jenner <andrew@codesourcery.com>
1104 Kwok Cheung Yeung <kcy@codesourcery.com>
1105
1106 opcodes/
1107 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1108 'e_cmplwi' to 'e_cmpli' instead.
1109 (OPVUPRT, OPVUPRT_MASK): Define.
1110 (powerpc_opcodes): Add E200Z4 insns.
1111 (vle_opcodes): Add context save/restore insns.
1112
7bd374a4
MR		 11132016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1114
1115 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1116 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1117 "j".
1118
db18dbab
GM		 11192016-07-27 Graham Markall <graham.markall@embecosm.com>
1120
1121 * arc-nps400-tbl.h: Change block comments to GNU format.
1122 * arc-dis.c: Add new globals addrtypenames,
1123 addrtypenames_max, and addtypeunknown.
1124 (get_addrtype): New function.
1125 (print_insn_arc): Print colons and address types when
1126 required.
1127 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1128 define insert and extract functions for all address types.
1129 (arc_operands): Add operands for colon and all address
1130 types.
1131 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1132 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1133 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1134 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1135 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1136 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1137
fecd57f9
L		 11382016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1139
1140 * configure: Regenerated.
1141
37fd5ef3
CZ		 11422016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1143
1144 * arc-dis.c (skipclass): New structure.
1145 (decodelist): New variable.
1146 (is_compatible_p): New function.
1147 (new_element): Likewise.
1148 (skip_class_p): Likewise.
1149 (find_format_from_table): Use skip_class_p function.
1150 (find_format): Decode first the extension instructions.
1151 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1152 e_flags.
1153 (parse_option): New function.
1154 (parse_disassembler_options): Likewise.
1155 (print_arc_disassembler_options): Likewise.
1156 (print_insn_arc): Use parse_disassembler_options function. Proper
1157 select ARCv2 cpu variant.
1158 * disassemble.c (disassembler_usage): Add ARC disassembler
1159 options.
1160
92281a5b
MR		 11612016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1162
1163 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1164 annotation from the "nal" entry and reorder it beyond "bltzal".
1165
6e7ced37
JM		 11662016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1167
1168 * sparc-opc.c (ldtxa): New macro.
1169 (sparc_opcodes): Use the macro defined above to add entries for
1170 the LDTXA instructions.
1171 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1172 instruction.
1173
2f831b9a 11742016-07-07 James Bowman <james.bowman@ftdichip.com>
1175
1176 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1177 and "jmpc".
1178
c07315e0
JB		 11792016-07-01 Jan Beulich <jbeulich@suse.com>
1180
1181 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1182 (movzb): Adjust to cover all permitted suffixes.
1183 (movzw): New.
1184 * i386-tbl.h: Re-generate.
1185
9243100a
JB		 11862016-07-01 Jan Beulich <jbeulich@suse.com>
1187
1188 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1189 (lgdt): Remove Tbyte from non-64-bit variant.
1190 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1191 xsaves64, xsavec64): Remove Disp16.
1192 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1193 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1194 64-bit variants.
1195 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1196 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1197 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1198 64-bit variants.
1199 * i386-tbl.h: Re-generate.
1200
8325cc63
JB		 12012016-07-01 Jan Beulich <jbeulich@suse.com>
1202
1203 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1204 * i386-tbl.h: Re-generate.
1205
838441e4
YQ		 12062016-06-30 Yao Qi <yao.qi@linaro.org>
1207
1208 * arm-dis.c (print_insn): Fix typo in comment.
1209
dab26bf4
RS		 12102016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1211
1212 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1213 range of ldst_elemlist operands.
1214 (print_register_list): Use PRIi64 to print the index.
1215 (aarch64_print_operand): Likewise.
1216
5703197e
TS		 12172016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1218
1219 * mcore-opc.h: Remove sentinal.
1220 * mcore-dis.c (print_insn_mcore): Adjust.
1221
ce440d63
GM		 12222016-06-23 Graham Markall <graham.markall@embecosm.com>
1223
1224 * arc-opc.c: Correct description of availability of NPS400
1225 features.
1226
6fd3a02d
PB		 12272016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1228
1229 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1230 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1231 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1232 xor3>: New mnemonics.
1233 <setb>: Change to a VX form instruction.
1234 (insert_sh6): Add support for rldixor.
1235 (extract_sh6): Likewise.
1236
6b477896
TS		 12372016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1238
1239 * arc-ext.h: Wrap in extern C.
1240
bdd582db
GM		 12412016-06-21 Graham Markall <graham.markall@embecosm.com>
1242
1243 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1244 Use same method for determining instruction length on ARC700 and
1245 NPS-400.
1246 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1247 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1248 with the NPS400 subclass.
1249 * arc-opc.c: Likewise.
1250
96074adc
JM		 12512016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1252
1253 * sparc-opc.c (rdasr): New macro.
1254 (wrasr): Likewise.
1255 (rdpr): Likewise.
1256 (wrpr): Likewise.
1257 (rdhpr): Likewise.
1258 (wrhpr): Likewise.
1259 (sparc_opcodes): Use the macros above to fix and expand the
1260 definition of read/write instructions from/to
1261 asr/privileged/hyperprivileged instructions.
1262 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1263 %hva_mask_nz. Prefer softint_set and softint_clear over
1264 set_softint and clear_softint.
1265 (print_insn_sparc): Support %ver in Rd.
1266
7a10c22f
JM		 12672016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1268
1269 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1270 architecture according to the hardware capabilities they require.
1271
4f26fb3a
JM		 12722016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1273
1274 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1275 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1276 bfd_mach_sparc_v9{c,d,e,v,m}.
1277 * sparc-opc.c (MASK_V9C): Define.
1278 (MASK_V9D): Likewise.
1279 (MASK_V9E): Likewise.
1280 (MASK_V9V): Likewise.
1281 (MASK_V9M): Likewise.
1282 (v6): Add MASK_V9{C,D,E,V,M}.
1283 (v6notlet): Likewise.
1284 (v7): Likewise.
1285 (v8): Likewise.
1286 (v9): Likewise.
1287 (v9andleon): Likewise.
1288 (v9a): Likewise.
1289 (v9b): Likewise.
1290 (v9c): Define.
1291 (v9d): Likewise.
1292 (v9e): Likewise.
1293 (v9v): Likewise.
1294 (v9m): Likewise.
1295 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1296
3ee6e4fb
NC		 12972016-06-15 Nick Clifton <nickc@redhat.com>
1298
1299 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1300 constants to match expected behaviour.
1301 (nds32_parse_opcode): Likewise. Also for whitespace.
1302
02f3be19
AB		 13032016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1304
1305 * arc-opc.c (extract_rhv1): Extract value from insn.
1306
6f9f37ed 13072016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1308
1309 * arc-nps400-tbl.h: Add ldbit instruction.
1310 * arc-opc.c: Add flag classes required for ldbit.
1311
6f9f37ed 13122016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1313
1314 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1315 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1316 support the above instructions.
1317
6f9f37ed 13182016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1319
1320 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1321 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1322 csma, cbba, zncv, and hofs.
1323 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1324 support the above instructions.
1325
13262016-06-06 Graham Markall <graham.markall@embecosm.com>
1327
1328 * arc-nps400-tbl.h: Add andab and orab instructions.
1329
13302016-06-06 Graham Markall <graham.markall@embecosm.com>
1331
1332 * arc-nps400-tbl.h: Add addl-like instructions.
1333
13342016-06-06 Graham Markall <graham.markall@embecosm.com>
1335
1336 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1337
13382016-06-06 Graham Markall <graham.markall@embecosm.com>
1339
1340 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1341 instructions.
1342
b2cc3f6f
AK		 13432016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1344
1345 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1346 variable.
1347 (init_disasm): Handle new command line option "insnlength".
1348 (print_s390_disassembler_options): Mention new option in help
1349 output.
1350 (print_insn_s390): Use the encoded insn length when dumping
1351 unknown instructions.
1352
1857fe72
DC		 13532016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1354
1355 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1356 to the address and set as symbol address for LDS/ STS immediate operands.
1357
14b57c7c
AM		 13582016-06-07 Alan Modra <amodra@gmail.com>
1359
1360 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1361 cpu for "vle" to e500.
1362 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1363 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1364 (PPCNONE): Delete, substitute throughout.
1365 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1366 except for major opcode 4 and 31.
1367 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1368
4d1464f2
MW		 13692016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1370
1371 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1372 ARM_EXT_RAS in relevant entries.
1373
026122a6
PB		 13742016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1375
1376 PR binutils/20196
1377 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1378 opcodes for E6500.
1379
07f5af7d
L		 13802016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1381
1382 PR binutis/18386
1383 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1384 (indir_v_mode): New.
1385 Add comments for '&'.
1386 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1387 (putop): Handle '&'.
1388 (intel_operand_size): Handle indir_v_mode.
1389 (OP_E_register): Likewise.
1390 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1391 64-bit indirect call/jmp for AMD64.
1392 * i386-tbl.h: Regenerated
1393
4eb6f892
AB		 13942016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1395
1396 * arc-dis.c (struct arc_operand_iterator): New structure.
1397 (find_format_from_table): All the old content from find_format,
1398 with some minor adjustments, and parameter renaming.
1399 (find_format_long_instructions): New function.
1400 (find_format): Rewritten.
1401 (arc_insn_length): Add LSB parameter.
1402 (extract_operand_value): New function.
1403 (operand_iterator_next): New function.
1404 (print_insn_arc): Use new functions to find opcode, and iterator
1405 over operands.
1406 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1407 (extract_nps_3bit_dst_short): New function.
1408 (insert_nps_3bit_src2_short): New function.
1409 (extract_nps_3bit_src2_short): New function.
1410 (insert_nps_bitop1_size): New function.
1411 (extract_nps_bitop1_size): New function.
1412 (insert_nps_bitop2_size): New function.
1413 (extract_nps_bitop2_size): New function.
1414 (insert_nps_bitop_mod4_msb): New function.
1415 (extract_nps_bitop_mod4_msb): New function.
1416 (insert_nps_bitop_mod4_lsb): New function.
1417 (extract_nps_bitop_mod4_lsb): New function.
1418 (insert_nps_bitop_dst_pos3_pos4): New function.
1419 (extract_nps_bitop_dst_pos3_pos4): New function.
1420 (insert_nps_bitop_ins_ext): New function.
1421 (extract_nps_bitop_ins_ext): New function.
1422 (arc_operands): Add new operands.
1423 (arc_long_opcodes): New global array.
1424 (arc_num_long_opcodes): New global.
1425 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1426
1fe0971e
TS		 14272016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1428
1429 * nds32-asm.h: Add extern "C".
1430 * sh-opc.h: Likewise.
1431
315f180f
GM		 14322016-06-01 Graham Markall <graham.markall@embecosm.com>
1433
1434 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1435 0,b,limm to the rflt instruction.
1436
a2b5fccc
TS		 14372016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1438
1439 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1440 constant.
1441
0cbd0046
L		 14422016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1443
1444 PR gas/20145
1445 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1446 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1447 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1448 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1449 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1450 * i386-init.h: Regenerated.
1451
1848e567
L		 14522016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1453
1454 PR gas/20145
1455 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1456 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1457 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1458 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1459 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1460 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1461 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1462 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1463 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1464 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1465 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1466 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1467 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1468 CpuRegMask for AVX512.
1469 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1470 and CpuRegMask.
1471 (set_bitfield_from_cpu_flag_init): New function.
1472 (set_bitfield): Remove const on f. Call
1473 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1474 * i386-opc.h (CpuRegMMX): New.
1475 (CpuRegXMM): Likewise.
1476 (CpuRegYMM): Likewise.
1477 (CpuRegZMM): Likewise.
1478 (CpuRegMask): Likewise.
1479 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1480 and cpuregmask.
1481 * i386-init.h: Regenerated.
1482 * i386-tbl.h: Likewise.
1483
e92bae62
L		 14842016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1485
1486 PR gas/20154
1487 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1488 (opcode_modifiers): Add AMD64 and Intel64.
1489 (main): Properly verify CpuMax.
1490 * i386-opc.h (CpuAMD64): Removed.
1491 (CpuIntel64): Likewise.
1492 (CpuMax): Set to CpuNo64.
1493 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1494 (AMD64): New.
1495 (Intel64): Likewise.
1496 (i386_opcode_modifier): Add amd64 and intel64.
1497 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1498 on call and jmp.
1499 * i386-init.h: Regenerated.
1500 * i386-tbl.h: Likewise.
1501
e89c5eaa
L		 15022016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1503
1504 PR gas/20154
1505 * i386-gen.c (main): Fail if CpuMax is incorrect.
1506 * i386-opc.h (CpuMax): Set to CpuIntel64.
1507 * i386-tbl.h: Regenerated.
1508
77d66e7b
NC		 15092016-05-27 Nick Clifton <nickc@redhat.com>
1510
1511 PR target/20150
1512 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1513 (msp430dis_opcode_unsigned): New function.
1514 (msp430dis_opcode_signed): New function.
1515 (msp430_singleoperand): Use the new opcode reading functions.
1516 Only disassenmble bytes if they were successfully read.
1517 (msp430_doubleoperand): Likewise.
1518 (msp430_branchinstr): Likewise.
1519 (msp430x_callx_instr): Likewise.
1520 (print_insn_msp430): Check that it is safe to read bytes before
1521 attempting disassembly. Use the new opcode reading functions.
1522
19dfcc89
PB		 15232016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1524
1525 * ppc-opc.c (CY): New define. Document it.
1526 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1527
f3ad7637
L		 15282016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1529
1530 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1531 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1532 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1533 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1534 CPU_ANY_AVX_FLAGS.
1535 * i386-init.h: Regenerated.
1536
f1360d58
L		 15372016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1538
1539 PR gas/20141
1540 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1541 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1542 * i386-init.h: Regenerated.
1543
293f5f65
L		 15442016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1545
1546 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1547 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1548 * i386-init.h: Regenerated.
1549
d9eca1df
CZ		 15502016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1551
1552 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1553 information.
1554 (print_insn_arc): Set insn_type information.
1555 * arc-opc.c (C_CC): Add F_CLASS_COND.
1556 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1557 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1558 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1559 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1560 (brne, brne_s, jeq_s, jne_s): Likewise.
1561
87789e08
CZ		 15622016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1563
1564 * arc-tbl.h (neg): New instruction variant.
1565
c810e0b8
CZ		 15662016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1567
1568 * arc-dis.c (find_format, find_format, get_auxreg)
1569 (print_insn_arc): Changed.
1570 * arc-ext.h (INSERT_XOP): Likewise.
1571
3d207518
TS		 15722016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1573
1574 * tic54x-dis.c (sprint_mmr): Adjust.
1575 * tic54x-opc.c: Likewise.
1576
514e58b7
AM		 15772016-05-19 Alan Modra <amodra@gmail.com>
1578
1579 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1580
e43de63c
AM		 15812016-05-19 Alan Modra <amodra@gmail.com>
1582
1583 * ppc-opc.c: Formatting.
1584 (NSISIGNOPT): Define.
1585 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1586
1401d2fe
MR		 15872016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1588
1589 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1590 replacing references to `micromips_ase' throughout.
1591 (_print_insn_mips): Don't use file-level microMIPS annotation to
1592 determine the disassembly mode with the symbol table.
1593
1178da44
PB		 15942016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1595
1596 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1597
8f4f9071
MF		 15982016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1599
1600 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1601 mips64r6.
1602 * mips-opc.c (D34): New macro.
1603 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1604
8bc52696
AF		 16052016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1606
1607 * i386-dis.c (prefix_table): Add RDPID instruction.
1608 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1609 (cpu_flags): Add RDPID bitfield.
1610 * i386-opc.h (enum): Add RDPID element.
1611 (i386_cpu_flags): Add RDPID field.
1612 * i386-opc.tbl: Add RDPID instruction.
1613 * i386-init.h: Regenerate.
1614 * i386-tbl.h: Regenerate.
1615
39d911fc
TP		 16162016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1617
1618 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1619 branch type of a symbol.
1620 (print_insn): Likewise.
1621
16a1fa25
TP		 16222016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1623
1624 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1625 Mainline Security Extensions instructions.
1626 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1627 Extensions instructions.
1628 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1629 instructions.
1630 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1631 special registers.
1632
d751b79e
JM		 16332016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1634
1635 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1636
945e0f82
CZ		 16372016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1638
1639 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1640 (arcExtMap_genOpcode): Likewise.
1641 * arc-opc.c (arg_32bit_rc): Define new variable.
1642 (arg_32bit_u6): Likewise.
1643 (arg_32bit_limm): Likewise.
1644
20f55f38
SN		 16452016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1646
1647 * aarch64-gen.c (VERIFIER): Define.
1648 * aarch64-opc.c (VERIFIER): Define.
1649 (verify_ldpsw): Use static linkage.
1650 * aarch64-opc.h (verify_ldpsw): Remove.
1651 * aarch64-tbl.h: Use VERIFIER for verifiers.
1652
4bd13cde
NC		 16532016-04-28 Nick Clifton <nickc@redhat.com>
1654
1655 PR target/19722
1656 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1657 * aarch64-opc.c (verify_ldpsw): New function.
1658 * aarch64-opc.h (verify_ldpsw): New prototype.
1659 * aarch64-tbl.h: Add initialiser for verifier field.
1660 (LDPSW): Set verifier to verify_ldpsw.
1661
c0f92bf9
L		 16622016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1663
1664 PR binutils/19983
1665 PR binutils/19984
1666 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1667 smaller than address size.
1668
e6c7cdec
TS		 16692016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1670
1671 * alpha-dis.c: Regenerate.
1672 * crx-dis.c: Likewise.
1673 * disassemble.c: Likewise.
1674 * epiphany-opc.c: Likewise.
1675 * fr30-opc.c: Likewise.
1676 * frv-opc.c: Likewise.
1677 * ip2k-opc.c: Likewise.
1678 * iq2000-opc.c: Likewise.
1679 * lm32-opc.c: Likewise.
1680 * lm32-opinst.c: Likewise.
1681 * m32c-opc.c: Likewise.
1682 * m32r-opc.c: Likewise.
1683 * m32r-opinst.c: Likewise.
1684 * mep-opc.c: Likewise.
1685 * mt-opc.c: Likewise.
1686 * or1k-opc.c: Likewise.
1687 * or1k-opinst.c: Likewise.
1688 * tic80-opc.c: Likewise.
1689 * xc16x-opc.c: Likewise.
1690 * xstormy16-opc.c: Likewise.
1691
537aefaf
AB		 16922016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1693
1694 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1695 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1696 calcsd, and calcxd instructions.
1697 * arc-opc.c (insert_nps_bitop_size): Delete.
1698 (extract_nps_bitop_size): Delete.
1699 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1700 (extract_nps_qcmp_m3): Define.
1701 (extract_nps_qcmp_m2): Define.
1702 (extract_nps_qcmp_m1): Define.
1703 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1704 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1705 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1706 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1707 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1708 NPS_QCMP_M3.
1709
c8f785f2
AB		 17102016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1711
1712 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1713
6fd8e7c2
L		 17142016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1715
1716 * Makefile.in: Regenerated with automake 1.11.6.
1717 * aclocal.m4: Likewise.
1718
4b0c052e
AB		 17192016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1720
1721 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1722 instructions.
1723 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1724 (extract_nps_cmem_uimm16): New function.
1725 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1726
cb040366
AB		 17272016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1728
1729 * arc-dis.c (arc_insn_length): New function.
1730 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1731 (find_format): Change insnLen parameter to unsigned.
1732
accc0180
NC		 17332016-04-13 Nick Clifton <nickc@redhat.com>
1734
1735 PR target/19937
1736 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1737 the LD.B and LD.BU instructions.
1738
f36e33da
CZ		 17392016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1740
1741 * arc-dis.c (find_format): Check for extension flags.
1742 (print_flags): New function.
1743 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1744 .extAuxRegister.
1745 * arc-ext.c (arcExtMap_coreRegName): Use
1746 LAST_EXTENSION_CORE_REGISTER.
1747 (arcExtMap_coreReadWrite): Likewise.
1748 (dump_ARC_extmap): Update printing.
1749 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1750 (arc_aux_regs): Add cpu field.
1751 * arc-regs.h: Add cpu field, lower case name aux registers.
1752
1c2e355e
CZ		 17532016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1754
1755 * arc-tbl.h: Add rtsc, sleep with no arguments.
1756
b99747ae
CZ		 17572016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1758
1759 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1760 Initialize.
1761 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1762 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1763 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1764 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1765 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1766 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1767 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1768 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1769 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1770 (arc_opcode arc_opcodes): Null terminate the array.
1771 (arc_num_opcodes): Remove.
1772 * arc-ext.h (INSERT_XOP): Define.
1773 (extInstruction_t): Likewise.
1774 (arcExtMap_instName): Delete.
1775 (arcExtMap_insn): New function.
1776 (arcExtMap_genOpcode): Likewise.
1777 * arc-ext.c (ExtInstruction): Remove.
1778 (create_map): Zero initialize instruction fields.
1779 (arcExtMap_instName): Remove.
1780 (arcExtMap_insn): New function.
1781 (dump_ARC_extmap): More info while debuging.
1782 (arcExtMap_genOpcode): New function.
1783 * arc-dis.c (find_format): New function.
1784 (print_insn_arc): Use find_format.
1785 (arc_get_disassembler): Enable dump_ARC_extmap only when
1786 debugging.
1787
92708cec
MR		 17882016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1789
1790 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1791 instruction bits out.
1792
a42a4f84
AB		 17932016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1794
1795 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1796 * arc-opc.c (arc_flag_operands): Add new flags.
1797 (arc_flag_classes): Add new classes.
1798
1328504b
AB		 17992016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1800
1801 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1802
820f03ff
AB		 18032016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1804
1805 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1806 encode1, rflt, crc16, and crc32 instructions.
1807 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1808 (arc_flag_classes): Add C_NPS_R.
1809 (insert_nps_bitop_size_2b): New function.
1810 (extract_nps_bitop_size_2b): Likewise.
1811 (insert_nps_bitop_uimm8): Likewise.
1812 (extract_nps_bitop_uimm8): Likewise.
1813 (arc_operands): Add new operand entries.
1814
8ddf6b2a
CZ		 18152016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1816
b99747ae
CZ		 1817 * arc-regs.h: Add a new subclass field. Add double assist
1818 accumulator register values.
1819 * arc-tbl.h: Use DPA subclass to mark the double assist
1820 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1821 * arc-opc.c (RSP): Define instead of SP.
1822 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1823
589a7d88
JW		 18242016-04-05 Jiong Wang <jiong.wang@arm.com>
1825
1826 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1827
0a191de9 18282016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1829
1830 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1831 NPS_R_SRC1.
1832
0a106562
AB		 18332016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1834
1835 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1836 issues. No functional changes.
1837
bd05ac5f
CZ		 18382016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1839
b99747ae
CZ		 1840 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1841 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1842 (RTT): Remove duplicate.
1843 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1844 (PCT_CONFIG*): Remove.
1845 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1846
9885948f
CZ		 18472016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1848
b99747ae 1849 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1850
f2dd8838
CZ		 18512016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1852
b99747ae
CZ		 1853 * arc-tbl.h (invld07): Remove.
1854 * arc-ext-tbl.h: New file.
1855 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1856 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1857
0d2f91fe
JK		 18582016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1859
1860 Fix -Wstack-usage warnings.
1861 * aarch64-dis.c (print_operands): Substitute size.
1862 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1863
a6b71f42
JM		 18642016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1865
1866 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1867 to get a proper diagnostic when an invalid ASR register is used.
1868
9780e045
NC		 18692016-03-22 Nick Clifton <nickc@redhat.com>
1870
1871 * configure: Regenerate.
1872
e23e8ebe
AB		 18732016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1874
1875 * arc-nps400-tbl.h: New file.
1876 * arc-opc.c: Add top level comment.
1877 (insert_nps_3bit_dst): New function.
1878 (extract_nps_3bit_dst): New function.
1879 (insert_nps_3bit_src2): New function.
1880 (extract_nps_3bit_src2): New function.
1881 (insert_nps_bitop_size): New function.
1882 (extract_nps_bitop_size): New function.
1883 (arc_flag_operands): Add nps400 entries.
1884 (arc_flag_classes): Add nps400 entries.
1885 (arc_operands): Add nps400 entries.
1886 (arc_opcodes): Add nps400 include.
1887
1ae8ab47
AB		 18882016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1889
1890 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1891 the new class enum values.
1892
8699fc3e
AB		 18932016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1894
1895 * arc-dis.c (print_insn_arc): Handle nps400.
1896
24740d83
AB		 18972016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1898
1899 * arc-opc.c (BASE): Delete.
1900
8678914f
NC		 19012016-03-18 Nick Clifton <nickc@redhat.com>
1902
1903 PR target/19721
1904 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1905 of MOV insn that aliases an ORR insn.
1906
cc933301
JW		 19072016-03-16 Jiong Wang <jiong.wang@arm.com>
1908
1909 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1910
f86f5863
TS		 19112016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1912
1913 * mcore-opc.h: Add const qualifiers.
1914 * microblaze-opc.h (struct op_code_struct): Likewise.
1915 * sh-opc.h: Likewise.
1916 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1917 (tic4x_print_op): Likewise.
1918
62de1c63
AM		 19192016-03-02 Alan Modra <amodra@gmail.com>
1920
d11698cd 1921 * or1k-desc.h: Regenerate.
62de1c63 1922 * fr30-ibld.c: Regenerate.
c697cf0b 1923 * rl78-decode.c: Regenerate.
62de1c63 1924
020efce5
NC		 19252016-03-01 Nick Clifton <nickc@redhat.com>
1926
1927 PR target/19747
1928 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1929
b0c11777
RL		 19302016-02-24 Renlin Li <renlin.li@arm.com>
1931
1932 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1933 (print_insn_coprocessor): Support fp16 instructions.
1934
3e309328
RL		 19352016-02-24 Renlin Li <renlin.li@arm.com>
1936
1937 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1938 vminnm, vrint(mpna).
1939
8afc7bea
RL		 19402016-02-24 Renlin Li <renlin.li@arm.com>
1941
1942 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1943 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1944
4fd7268a
L		 19452016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1946
1947 * i386-dis.c (print_insn): Parenthesize expression to prevent
1948 truncated addresses.
1949 (OP_J): Likewise.
1950
4670103e
CZ		 19512016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1952 Janek van Oirschot <jvanoirs@synopsys.com>
1953
b99747ae
CZ		 1954 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1955 variable.
4670103e 1956
c1d9289f
NC		 19572016-02-04 Nick Clifton <nickc@redhat.com>
1958
1959 PR target/19561
1960 * msp430-dis.c (print_insn_msp430): Add a special case for
1961 decoding an RRC instruction with the ZC bit set in the extension
1962 word.
1963
a143b004
AB		 19642016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1965
1966 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1967 * epiphany-ibld.c: Regenerate.
1968 * fr30-ibld.c: Regenerate.
1969 * frv-ibld.c: Regenerate.
1970 * ip2k-ibld.c: Regenerate.
1971 * iq2000-ibld.c: Regenerate.
1972 * lm32-ibld.c: Regenerate.
1973 * m32c-ibld.c: Regenerate.
1974 * m32r-ibld.c: Regenerate.
1975 * mep-ibld.c: Regenerate.
1976 * mt-ibld.c: Regenerate.
1977 * or1k-ibld.c: Regenerate.
1978 * xc16x-ibld.c: Regenerate.
1979 * xstormy16-ibld.c: Regenerate.
1980
b89807c6
AB		 19812016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1982
1983 * epiphany-dis.c: Regenerated from latest cpu files.
1984
d8c823c8
MM		 19852016-02-01 Michael McConville <mmcco@mykolab.com>
1986
1987 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1988 test bit.
1989
5bc5ae88
RL		 19902016-01-25 Renlin Li <renlin.li@arm.com>
1991
1992 * arm-dis.c (mapping_symbol_for_insn): New function.
1993 (find_ifthen_state): Call mapping_symbol_for_insn().
1994
0bff6e2d
MW		 19952016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1996
1997 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1998 of MSR UAO immediate operand.
1999
100b4f2e
MR		 20002016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2001
2002 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2003 instruction support.
2004
5c14705f
AM		 20052016-01-17 Alan Modra <amodra@gmail.com>
2006
2007 * configure: Regenerate.
2008
4d82fe66
NC		 20092016-01-14 Nick Clifton <nickc@redhat.com>
2010
2011 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2012 instructions that can support stack pointer operations.
2013 * rl78-decode.c: Regenerate.
2014 * rl78-dis.c: Fix display of stack pointer in MOVW based
2015 instructions.
2016
651657fa
MW		 20172016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2018
2019 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2020 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2021 erxtatus_el1 and erxaddr_el1.
2022
105bde57
MW		 20232016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2024
2025 * arm-dis.c (arm_opcodes): Add "esb".
2026 (thumb_opcodes): Likewise.
2027
afa8d405
PB		 20282016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2029
2030 * ppc-opc.c <xscmpnedp>: Delete.
2031 <xvcmpnedp>: Likewise.
2032 <xvcmpnedp.>: Likewise.
2033 <xvcmpnesp>: Likewise.
2034 <xvcmpnesp.>: Likewise.
2035
83c3256e
AS		 20362016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2037
2038 PR gas/13050
2039 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2040 addition to ISA_A.
2041
6f2750fe
AM		 20422016-01-01 Alan Modra <amodra@gmail.com>
2043
2044 Update year range in copyright notice of all files.
2045
3499769a
AM		 2046For older changes see ChangeLog-2015
2047\f
2048Copyright (C) 2016 Free Software Foundation, Inc.
2049
2050Copying and distribution of this file, with or without modification,
2051are permitted in any medium without royalty provided the copyright
2052notice and this notice are preserved.
2053
2054Local Variables:
2055mode: change-log
2056left-margin: 8
2057fill-column: 74
2058version-control: never
2059End:
GDB Binutils - Deliverables
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