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nds32: Rename __BIT() to N32_BIT().
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4ec521f2
KLC		 12017-09-09 Kamil Rytarowski <n54@gmx.com>
2
3 * nds32-asm.c: Rename __BIT() to N32_BIT().
4 * nds32-asm.h: Likewise.
5 * nds32-dis.c: Likewise.
6
4e9ac44a
L		 72017-09-09 H.J. Lu <hongjiu.lu@intel.com>
8
9 * i386-dis.c (last_active_prefix): Removed.
10 (ckprefix): Don't set last_active_prefix.
11 (NOTRACK_Fixup): Don't check last_active_prefix.
12
b55f3386
NC		 132017-08-31 Nick Clifton <nickc@redhat.com>
14
15 * po/fr.po: Updated French translation.
16
59e8523b
JB		 172017-08-31 James Bowman <james.bowman@ftdichip.com>
18
19 * ft32-dis.c (print_insn_ft32): Correct display of non-address
20 fields.
21
74081948
AF		 222017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
23 Edmar Wienskoski <edmar.wienskoski@nxp.com>
24
25 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
26 PPC_OPCODE_EFS2 flag to "e200z4" entry.
27 New entries efs2 and spe2.
28 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
29 (SPE2_OPCD_SEGS): New macro.
30 (spe2_opcd_indices): New.
31 (disassemble_init_powerpc): Handle SPE2 opcodes.
32 (lookup_spe2): New function.
33 (print_insn_powerpc): call lookup_spe2.
34 * ppc-opc.c (insert_evuimm1_ex0): New function.
35 (extract_evuimm1_ex0): Likewise.
36 (insert_evuimm_lt8): Likewise.
37 (extract_evuimm_lt8): Likewise.
38 (insert_off_spe2): Likewise.
39 (extract_off_spe2): Likewise.
40 (insert_Ddd): Likewise.
41 (extract_Ddd): Likewise.
42 (DD): New operand.
43 (EVUIMM_LT8): Likewise.
44 (EVUIMM_LT16): Adjust.
45 (MMMM): New operand.
46 (EVUIMM_1): Likewise.
47 (EVUIMM_1_EX0): Likewise.
48 (EVUIMM_2): Adjust.
49 (NNN): New operand.
50 (VX_OFF_SPE2): Likewise.
51 (BBB): Likewise.
52 (DDD): Likewise.
53 (VX_MASK_DDD): New mask.
54 (HH): New operand.
55 (VX_RA_CONST): New macro.
56 (VX_RA_CONST_MASK): Likewise.
57 (VX_RB_CONST): Likewise.
58 (VX_RB_CONST_MASK): Likewise.
59 (VX_OFF_SPE2_MASK): Likewise.
60 (VX_SPE_CRFD): Likewise.
61 (VX_SPE_CRFD_MASK VX): Likewise.
62 (VX_SPE2_CLR): Likewise.
63 (VX_SPE2_CLR_MASK): Likewise.
64 (VX_SPE2_SPLATB): Likewise.
65 (VX_SPE2_SPLATB_MASK): Likewise.
66 (VX_SPE2_OCTET): Likewise.
67 (VX_SPE2_OCTET_MASK): Likewise.
68 (VX_SPE2_DDHH): Likewise.
69 (VX_SPE2_DDHH_MASK): Likewise.
70 (VX_SPE2_HH): Likewise.
71 (VX_SPE2_HH_MASK): Likewise.
72 (VX_SPE2_EVMAR): Likewise.
73 (VX_SPE2_EVMAR_MASK): Likewise.
74 (PPCSPE2): Likewise.
75 (PPCEFS2): Likewise.
76 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
77 (powerpc_macros): Map old SPE instructions have new names
78 with the same opcodes. Add SPE2 instructions which just are
79 mapped to SPE2.
80 (spe2_opcodes): Add SPE2 opcodes.
81
b80c7270
AM		 822017-08-23 Alan Modra <amodra@gmail.com>
83
84 * ppc-opc.c: Formatting and comment fixes. Move insert and
85 extract functions earlier, deleting forward declarations.
86 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
87 RA_MASK.
88
67d888f5
PD		 892017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
90
91 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
92
e3c2f928
AF		 932017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
94 Edmar Wienskoski <edmar.wienskoski@nxp.com>
95
96 * ppc-opc.c (insert_evuimm2_ex0): New function.
97 (extract_evuimm2_ex0): Likewise.
98 (insert_evuimm4_ex0): Likewise.
99 (extract_evuimm4_ex0): Likewise.
100 (insert_evuimm8_ex0): Likewise.
101 (extract_evuimm8_ex0): Likewise.
102 (insert_evuimm_lt16): Likewise.
103 (extract_evuimm_lt16): Likewise.
104 (insert_rD_rS_even): Likewise.
105 (extract_rD_rS_even): Likewise.
106 (insert_off_lsp): Likewise.
107 (extract_off_lsp): Likewise.
108 (RD_EVEN): New operand.
109 (RS_EVEN): Likewise.
110 (RSQ): Adjust.
111 (EVUIMM_LT16): New operand.
112 (HTM_SI): Adjust.
113 (EVUIMM_2_EX0): New operand.
114 (EVUIMM_4): Adjust.
115 (EVUIMM_4_EX0): New operand.
116 (EVUIMM_8): Adjust.
117 (EVUIMM_8_EX0): New operand.
118 (WS): Adjust.
119 (VX_OFF): New operand.
120 (VX_LSP): New macro.
121 (VX_LSP_MASK): Likewise.
122 (VX_LSP_OFF_MASK): Likewise.
123 (PPC_OPCODE_LSP): Likewise.
124 (vle_opcodes): Add LSP opcodes.
125 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
126
cc4a945a
JW		 1272017-08-09 Jiong Wang <jiong.wang@arm.com>
128
129 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
130 register operands in CRC instructions.
131 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
132 comments.
133
b28b8b5e
L		 1342017-08-07 H.J. Lu <hongjiu.lu@intel.com>
135
136 * disassemble.c (disassembler): Mark big and mach with
137 ATTRIBUTE_UNUSED.
138
e347efc3
MR		 1392017-08-07 Maciej W. Rozycki <macro@imgtec.com>
140
141 * disassemble.c (disassembler): Remove arch/mach/endian
142 assertions.
143
7cbc739c
NC		 1442017-07-25 Nick Clifton <nickc@redhat.com>
145
146 PR 21739
147 * arc-opc.c (insert_rhv2): Use lower case first letter in error
148 message.
149 (insert_r0): Likewise.
150 (insert_r1): Likewise.
151 (insert_r2): Likewise.
152 (insert_r3): Likewise.
153 (insert_sp): Likewise.
154 (insert_gp): Likewise.
155 (insert_pcl): Likewise.
156 (insert_blink): Likewise.
157 (insert_ilink1): Likewise.
158 (insert_ilink2): Likewise.
159 (insert_ras): Likewise.
160 (insert_rbs): Likewise.
161 (insert_rcs): Likewise.
162 (insert_simm3s): Likewise.
163 (insert_rrange): Likewise.
164 (insert_r13el): Likewise.
165 (insert_fpel): Likewise.
166 (insert_blinkel): Likewise.
167 (insert_pclel): Likewise.
168 (insert_nps_bitop_size_2b): Likewise.
169 (insert_nps_imm_offset): Likewise.
170 (insert_nps_imm_entry): Likewise.
171 (insert_nps_size_16bit): Likewise.
172 (insert_nps_##NAME##_pos): Likewise.
173 (insert_nps_##NAME): Likewise.
174 (insert_nps_bitop_ins_ext): Likewise.
175 (insert_nps_##NAME): Likewise.
176 (insert_nps_min_hofs): Likewise.
177 (insert_nps_##NAME): Likewise.
178 (insert_nps_rbdouble_64): Likewise.
179 (insert_nps_misc_imm_offset): Likewise.
180 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
181 option description.
182
7684e580
JW		 1832017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
184 Jiong Wang <jiong.wang@arm.com>
185
186 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
187 correct the print.
188 * aarch64-dis-2.c: Regenerated.
189
47826cdb
AK		 1902017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
191
192 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
193 table.
194
2d2dbad0
NC		 1952017-07-20 Nick Clifton <nickc@redhat.com>
196
197 * po/de.po: Updated German translation.
198
70b448ba 1992017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
200
201 * arc-regs.h (sec_stat): New aux register.
202 (aux_kernel_sp): Likewise.
203 (aux_sec_u_sp): Likewise.
204 (aux_sec_k_sp): Likewise.
205 (sec_vecbase_build): Likewise.
206 (nsc_table_top): Likewise.
207 (nsc_table_base): Likewise.
208 (ersec_stat): Likewise.
209 (aux_sec_except): Likewise.
210
7179e0e6
CZ		 2112017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
212
213 * arc-opc.c (extract_uimm12_20): New function.
214 (UIMM12_20): New operand.
215 (SIMM3_5_S): Adjust.
216 * arc-tbl.h (sjli): Add new instruction.
217
684d5a10
JEM		 2182017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
219 John Eric Martin <John.Martin@emmicro-us.com>
220
221 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
222 (UIMM3_23): Adjust accordingly.
223 * arc-regs.h: Add/correct jli_base register.
224 * arc-tbl.h (jli_s): Likewise.
225
de194d85
YC		 2262017-07-18 Nick Clifton <nickc@redhat.com>
227
228 PR 21775
229 * aarch64-opc.c: Fix spelling typos.
230 * i386-dis.c: Likewise.
231
0f6329bd
RB		 2322017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
233
234 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
235 max_addr_offset and octets variables to size_t.
236
429d795d
AM		 2372017-07-12 Alan Modra <amodra@gmail.com>
238
239 * po/da.po: Update from translationproject.org/latest/opcodes/.
240 * po/de.po: Likewise.
241 * po/es.po: Likewise.
242 * po/fi.po: Likewise.
243 * po/fr.po: Likewise.
244 * po/id.po: Likewise.
245 * po/it.po: Likewise.
246 * po/nl.po: Likewise.
247 * po/pt_BR.po: Likewise.
248 * po/ro.po: Likewise.
249 * po/sv.po: Likewise.
250 * po/tr.po: Likewise.
251 * po/uk.po: Likewise.
252 * po/vi.po: Likewise.
253 * po/zh_CN.po: Likewise.
254
4162bb66
AM		 2552017-07-11 Yao Qi <yao.qi@linaro.org>
256 Alan Modra <amodra@gmail.com>
257
258 * cgen.sh: Mark generated files read-only.
259 * epiphany-asm.c: Regenerate.
260 * epiphany-desc.c: Regenerate.
261 * epiphany-desc.h: Regenerate.
262 * epiphany-dis.c: Regenerate.
263 * epiphany-ibld.c: Regenerate.
264 * epiphany-opc.c: Regenerate.
265 * epiphany-opc.h: Regenerate.
266 * fr30-asm.c: Regenerate.
267 * fr30-desc.c: Regenerate.
268 * fr30-desc.h: Regenerate.
269 * fr30-dis.c: Regenerate.
270 * fr30-ibld.c: Regenerate.
271 * fr30-opc.c: Regenerate.
272 * fr30-opc.h: Regenerate.
273 * frv-asm.c: Regenerate.
274 * frv-desc.c: Regenerate.
275 * frv-desc.h: Regenerate.
276 * frv-dis.c: Regenerate.
277 * frv-ibld.c: Regenerate.
278 * frv-opc.c: Regenerate.
279 * frv-opc.h: Regenerate.
280 * ip2k-asm.c: Regenerate.
281 * ip2k-desc.c: Regenerate.
282 * ip2k-desc.h: Regenerate.
283 * ip2k-dis.c: Regenerate.
284 * ip2k-ibld.c: Regenerate.
285 * ip2k-opc.c: Regenerate.
286 * ip2k-opc.h: Regenerate.
287 * iq2000-asm.c: Regenerate.
288 * iq2000-desc.c: Regenerate.
289 * iq2000-desc.h: Regenerate.
290 * iq2000-dis.c: Regenerate.
291 * iq2000-ibld.c: Regenerate.
292 * iq2000-opc.c: Regenerate.
293 * iq2000-opc.h: Regenerate.
294 * lm32-asm.c: Regenerate.
295 * lm32-desc.c: Regenerate.
296 * lm32-desc.h: Regenerate.
297 * lm32-dis.c: Regenerate.
298 * lm32-ibld.c: Regenerate.
299 * lm32-opc.c: Regenerate.
300 * lm32-opc.h: Regenerate.
301 * lm32-opinst.c: Regenerate.
302 * m32c-asm.c: Regenerate.
303 * m32c-desc.c: Regenerate.
304 * m32c-desc.h: Regenerate.
305 * m32c-dis.c: Regenerate.
306 * m32c-ibld.c: Regenerate.
307 * m32c-opc.c: Regenerate.
308 * m32c-opc.h: Regenerate.
309 * m32r-asm.c: Regenerate.
310 * m32r-desc.c: Regenerate.
311 * m32r-desc.h: Regenerate.
312 * m32r-dis.c: Regenerate.
313 * m32r-ibld.c: Regenerate.
314 * m32r-opc.c: Regenerate.
315 * m32r-opc.h: Regenerate.
316 * m32r-opinst.c: Regenerate.
317 * mep-asm.c: Regenerate.
318 * mep-desc.c: Regenerate.
319 * mep-desc.h: Regenerate.
320 * mep-dis.c: Regenerate.
321 * mep-ibld.c: Regenerate.
322 * mep-opc.c: Regenerate.
323 * mep-opc.h: Regenerate.
324 * mt-asm.c: Regenerate.
325 * mt-desc.c: Regenerate.
326 * mt-desc.h: Regenerate.
327 * mt-dis.c: Regenerate.
328 * mt-ibld.c: Regenerate.
329 * mt-opc.c: Regenerate.
330 * mt-opc.h: Regenerate.
331 * or1k-asm.c: Regenerate.
332 * or1k-desc.c: Regenerate.
333 * or1k-desc.h: Regenerate.
334 * or1k-dis.c: Regenerate.
335 * or1k-ibld.c: Regenerate.
336 * or1k-opc.c: Regenerate.
337 * or1k-opc.h: Regenerate.
338 * or1k-opinst.c: Regenerate.
339 * xc16x-asm.c: Regenerate.
340 * xc16x-desc.c: Regenerate.
341 * xc16x-desc.h: Regenerate.
342 * xc16x-dis.c: Regenerate.
343 * xc16x-ibld.c: Regenerate.
344 * xc16x-opc.c: Regenerate.
345 * xc16x-opc.h: Regenerate.
346 * xstormy16-asm.c: Regenerate.
347 * xstormy16-desc.c: Regenerate.
348 * xstormy16-desc.h: Regenerate.
349 * xstormy16-dis.c: Regenerate.
350 * xstormy16-ibld.c: Regenerate.
351 * xstormy16-opc.c: Regenerate.
352 * xstormy16-opc.h: Regenerate.
353
7639175c
AM		 3542017-07-07 Alan Modra <amodra@gmail.com>
355
356 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
357 * m32c-dis.c: Regenerate.
358 * mep-dis.c: Regenerate.
359
e4bdd679
BP		 3602017-07-05 Borislav Petkov <bp@suse.de>
361
362 * i386-dis.c: Enable ModRM.reg /6 aliases.
363
60c96dbf
RR		 3642017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
365
366 * opcodes/arm-dis.c: Support MVFR2 in disassembly
367 with vmrs and vmsr.
368
0d702cfe
TG		 3692017-07-04 Tristan Gingold <gingold@adacore.com>
370
371 * configure: Regenerate.
372
15e6ed8c
TG		 3732017-07-03 Tristan Gingold <gingold@adacore.com>
374
375 * po/opcodes.pot: Regenerate.
376
b1d3c886
MR		 3772017-06-30 Maciej W. Rozycki <macro@imgtec.com>
378
379 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
380 entries to the MSA ASE instruction block.
381
909b4e3d
MR		 3822017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
383 Maciej W. Rozycki <macro@imgtec.com>
384
385 * micromips-opc.c (XPA, XPAVZ): New macros.
386 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
387 "mthgc0".
388
f5b2fd52
MR		 3892017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
390 Maciej W. Rozycki <macro@imgtec.com>
391
392 * micromips-opc.c (I36): New macro.
393 (micromips_opcodes): Add "eretnc".
394
9785fc2a
MR		 3952017-06-30 Maciej W. Rozycki <macro@imgtec.com>
396 Andrew Bennett <andrew.bennett@imgtec.com>
397
398 * mips-dis.c (mips_calculate_combination_ases): Handle the
399 ASE_XPA_VIRT flag.
400 (parse_mips_ase_option): New function.
401 (parse_mips_dis_option): Factor out ASE option handling to the
402 new function. Call `mips_calculate_combination_ases'.
403 * mips-opc.c (XPAVZ): New macro.
404 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
405 "mfhgc0", "mthc0" and "mthgc0".
406
60804c53
MR		 4072017-06-29 Maciej W. Rozycki <macro@imgtec.com>
408
409 * mips-dis.c (mips_calculate_combination_ases): New function.
410 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
411 calculation to the new function.
412 (set_default_mips_dis_options): Call the new function.
413
2e74f9dd
AK		 4142017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
415
416 * arc-dis.c (parse_disassembler_options): Use
417 FOR_EACH_DISASSEMBLER_OPTION.
418
e1e94c49
AK		 4192017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
420
421 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
422 disassembler option strings.
423 (parse_cpu_option): Likewise.
424
65a55fbb
TC		 4252017-06-28 Tamar Christina <tamar.christina@arm.com>
426
427 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
428 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
429 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
430 (aarch64_feature_dotprod, DOT_INSN): New.
431 (udot, sdot): New.
432 * aarch64-dis-2.c: Regenerated.
433
c604a79a
JW		 4342017-06-28 Jiong Wang <jiong.wang@arm.com>
435
436 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
437
38bf472a
MR		 4382017-06-28 Maciej W. Rozycki <macro@imgtec.com>
439 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 440 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 441
442 * mips-formats.h (INT_BIAS): New macro.
443 (INT_ADJ): Redefine in INT_BIAS terms.
444 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
445 (mips_print_save_restore): New function.
446 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
447 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
448 call.
449 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
450 (print_mips16_insn_arg): Call `mips_print_save_restore' for
451 OP_SAVE_RESTORE_LIST handling, factored out from here.
452 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
453 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
454 (mips_builtin_opcodes): Add "restore" and "save" entries.
455 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
456 (IAMR2): New macro.
457 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
458
9bdfdbf9
AW		 4592017-06-23 Andrew Waterman <andrew@sifive.com>
460
461 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
462 alias; do not mark SLTI instruction as an alias.
463
2234eee6
L		 4642017-06-21 H.J. Lu <hongjiu.lu@intel.com>
465
466 * i386-dis.c (RM_0FAE_REG_5): Removed.
467 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
468 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
469 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
470 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
471 PREFIX_MOD_3_0F01_REG_5_RM_0.
472 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
473 PREFIX_MOD_3_0FAE_REG_5.
474 (mod_table): Update MOD_0FAE_REG_5.
475 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
476 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
477 * i386-tbl.h: Regenerated.
478
c2f76402
L		 4792017-06-21 H.J. Lu <hongjiu.lu@intel.com>
480
481 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
482 * i386-opc.tbl: Likewise.
483 * i386-tbl.h: Regenerated.
484
9fef80d6
L		 4852017-06-21 H.J. Lu <hongjiu.lu@intel.com>
486
487 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
488 and "jmp{&|}".
489 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
490 prefix.
491
0f6d864d
NC		 4922017-06-19 Nick Clifton <nickc@redhat.com>
493
494 PR binutils/21614
495 * score-dis.c (score_opcodes): Add sentinel.
496
e197589b
AM		 4972017-06-16 Alan Modra <amodra@gmail.com>
498
499 * rx-decode.c: Regenerate.
500
0d96e4df
L		 5012017-06-15 H.J. Lu <hongjiu.lu@intel.com>
502
503 PR binutils/21594
504 * i386-dis.c (OP_E_register): Check valid bnd register.
505 (OP_G): Likewise.
506
cd3ea7c6
NC		 5072017-06-15 Nick Clifton <nickc@redhat.com>
508
509 PR binutils/21595
510 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
511 range value.
512
63323b5b
NC		 5132017-06-15 Nick Clifton <nickc@redhat.com>
514
515 PR binutils/21588
516 * rl78-decode.opc (OP_BUF_LEN): Define.
517 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
518 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
519 array.
520 * rl78-decode.c: Regenerate.
521
08c7881b
NC		 5222017-06-15 Nick Clifton <nickc@redhat.com>
523
524 PR binutils/21586
525 * bfin-dis.c (gregs): Clip index to prevent overflow.
526 (regs): Likewise.
527 (regs_lo): Likewise.
528 (regs_hi): Likewise.
529
e64519d1
NC		 5302017-06-14 Nick Clifton <nickc@redhat.com>
531
532 PR binutils/21576
533 * score7-dis.c (score_opcodes): Add sentinel.
534
6394c606
YQ		 5352017-06-14 Yao Qi <yao.qi@linaro.org>
536
537 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
538 * arm-dis.c: Likewise.
539 * ia64-dis.c: Likewise.
540 * mips-dis.c: Likewise.
541 * spu-dis.c: Likewise.
542 * disassemble.h (print_insn_aarch64): New declaration, moved from
543 include/dis-asm.h.
544 (print_insn_big_arm, print_insn_big_mips): Likewise.
545 (print_insn_i386, print_insn_ia64): Likewise.
546 (print_insn_little_arm, print_insn_little_mips): Likewise.
547
db5fa770
NC		 5482017-06-14 Nick Clifton <nickc@redhat.com>
549
550 PR binutils/21587
551 * rx-decode.opc: Include libiberty.h
552 (GET_SCALE): New macro - validates access to SCALE array.
553 (GET_PSCALE): New macro - validates access to PSCALE array.
554 (DIs, SIs, S2Is, rx_disp): Use new macros.
555 * rx-decode.c: Regenerate.
556
05c966f3
AV		 5572017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
558
559 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
560
10045478
AK		 5612017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
562
563 * arc-dis.c (enforced_isa_mask): Declare.
564 (cpu_types): Likewise.
565 (parse_cpu_option): New function.
566 (parse_disassembler_options): Use it.
567 (print_insn_arc): Use enforced_isa_mask.
568 (print_arc_disassembler_options): Document new options.
569
88c1242d
YQ		 5702017-05-24 Yao Qi <yao.qi@linaro.org>
571
572 * alpha-dis.c: Include disassemble.h, don't include
573 dis-asm.h.
574 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
575 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
576 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
577 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
578 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
579 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
580 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
581 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
582 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
583 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
584 * moxie-dis.c, msp430-dis.c, mt-dis.c:
585 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
586 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
587 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
588 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
589 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
590 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
591 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
592 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
593 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
594 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
595 * z80-dis.c, z8k-dis.c: Likewise.
596 * disassemble.h: New file.
597
ab20fa4a
YQ		 5982017-05-24 Yao Qi <yao.qi@linaro.org>
599
600 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
601 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
602
003ca0fd
YQ		 6032017-05-24 Yao Qi <yao.qi@linaro.org>
604
605 * disassemble.c (disassembler): Add arguments a, big and mach.
606 Use them.
607
04ef582a
L		 6082017-05-22 H.J. Lu <hongjiu.lu@intel.com>
609
610 * i386-dis.c (NOTRACK_Fixup): New.
611 (NOTRACK): Likewise.
612 (NOTRACK_PREFIX): Likewise.
613 (last_active_prefix): Likewise.
614 (reg_table): Use NOTRACK on indirect call and jmp.
615 (ckprefix): Set last_active_prefix.
616 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
617 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
618 * i386-opc.h (NoTrackPrefixOk): New.
619 (i386_opcode_modifier): Add notrackprefixok.
620 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
621 Add notrack.
622 * i386-tbl.h: Regenerated.
623
64517994
JM		 6242017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
625
626 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
627 (X_IMM2): Define.
628 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
629 bfd_mach_sparc_v9m8.
630 (print_insn_sparc): Handle new operand types.
631 * sparc-opc.c (MASK_M8): Define.
632 (v6): Add MASK_M8.
633 (v6notlet): Likewise.
634 (v7): Likewise.
635 (v8): Likewise.
636 (v9): Likewise.
637 (v9a): Likewise.
638 (v9b): Likewise.
639 (v9c): Likewise.
640 (v9d): Likewise.
641 (v9e): Likewise.
642 (v9v): Likewise.
643 (v9m): Likewise.
644 (v9andleon): Likewise.
645 (m8): Define.
646 (HWS_VM8): Define.
647 (HWS2_VM8): Likewise.
648 (sparc_opcode_archs): Add entry for "m8".
649 (sparc_opcodes): Add OSA2017 and M8 instructions
650 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
651 fpx{ll,ra,rl}64x,
652 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
653 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
654 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
655 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
656 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
657 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
658 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
659 ASI_CORE_SELECT_COMMIT_NHT.
660
535b785f
AM		 6612017-05-18 Alan Modra <amodra@gmail.com>
662
663 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
664 * aarch64-dis.c: Likewise.
665 * aarch64-gen.c: Likewise.
666 * aarch64-opc.c: Likewise.
667
25499ac7
MR		 6682017-05-15 Maciej W. Rozycki <macro@imgtec.com>
669 Matthew Fortune <matthew.fortune@imgtec.com>
670
671 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
672 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
673 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
674 (print_insn_arg) <OP_REG28>: Add handler.
675 (validate_insn_args) <OP_REG28>: Handle.
676 (print_mips16_insn_arg): Handle MIPS16 instructions that require
677 32-bit encoding and 9-bit immediates.
678 (print_insn_mips16): Handle MIPS16 instructions that require
679 32-bit encoding and MFC0/MTC0 operand decoding.
680 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
681 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
682 (RD_C0, WR_C0, E2, E2MT): New macros.
683 (mips16_opcodes): Add entries for MIPS16e2 instructions:
684 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
685 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
686 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
687 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
688 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
689 instructions, "swl", "swr", "sync" and its "sync_acquire",
690 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
691 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
692 regular/extended entries for original MIPS16 ISA revision
693 instructions whose extended forms are subdecoded in the MIPS16e2
694 ISA revision: "li", "sll" and "srl".
695
fdfb4752
MR		 6962017-05-15 Maciej W. Rozycki <macro@imgtec.com>
697
698 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
699 reference in CP0 move operand decoding.
700
a4f89915
MR		 7012017-05-12 Maciej W. Rozycki <macro@imgtec.com>
702
703 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
704 type to hexadecimal.
705 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
706
99e2d67a
MR		 7072017-05-11 Maciej W. Rozycki <macro@imgtec.com>
708
709 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
710 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
711 "sync_rmb" and "sync_wmb" as aliases.
712 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
713 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
714
53a346d8
CZ		 7152017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
716
717 * arc-dis.c (parse_option): Update quarkse_em option..
718 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
719 QUARKSE1.
720 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
721
f91d48de
KC		 7222017-05-03 Kito Cheng <kito.cheng@gmail.com>
723
724 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
725
43e379d7
MC		 7262017-05-01 Michael Clark <michaeljclark@mac.com>
727
728 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
729 register.
730
a4ddc54e
MR		 7312017-05-02 Maciej W. Rozycki <macro@imgtec.com>
732
733 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
734 and branches and not synthetic data instructions.
735
fe50e98c
BE		 7362017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
737
738 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
739
126124cc
CZ		 7402017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
741
742 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
743 * arc-opc.c (insert_r13el): New function.
744 (R13_EL): Define.
745 * arc-tbl.h: Add new enter/leave variants.
746
be6a24d8
CZ		 7472017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
748
749 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
750
0348fd79
MR		 7512017-04-25 Maciej W. Rozycki <macro@imgtec.com>
752
753 * mips-dis.c (print_mips_disassembler_options): Add
754 `no-aliases'.
755
6e3d1f07
MR		 7562017-04-25 Maciej W. Rozycki <macro@imgtec.com>
757
758 * mips16-opc.c (AL): New macro.
759 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
760 of "ld" and "lw" as aliases.
761
957f6b39
TC		 7622017-04-24 Tamar Christina <tamar.christina@arm.com>
763
764 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
765 arguments.
766
a8cc8a54
AM		 7672017-04-22 Alexander Fedotov <alfedotov@gmail.com>
768 Alan Modra <amodra@gmail.com>
769
770 * ppc-opc.c (ELEV): Define.
771 (vle_opcodes): Add se_rfgi and e_sc.
772 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
773 for E200Z4.
774
3ab87b68
JM		 7752017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
776
777 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
778
792f174f
NC		 7792017-04-21 Nick Clifton <nickc@redhat.com>
780
781 PR binutils/21380
782 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
783 LD3R and LD4R.
784
42742084
AM		 7852017-04-13 Alan Modra <amodra@gmail.com>
786
787 * epiphany-desc.c: Regenerate.
788 * fr30-desc.c: Regenerate.
789 * frv-desc.c: Regenerate.
790 * ip2k-desc.c: Regenerate.
791 * iq2000-desc.c: Regenerate.
792 * lm32-desc.c: Regenerate.
793 * m32c-desc.c: Regenerate.
794 * m32r-desc.c: Regenerate.
795 * mep-desc.c: Regenerate.
796 * mt-desc.c: Regenerate.
797 * or1k-desc.c: Regenerate.
798 * xc16x-desc.c: Regenerate.
799 * xstormy16-desc.c: Regenerate.
800
9a85b496
AM		 8012017-04-11 Alan Modra <amodra@gmail.com>
802
ef85eab0 803 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 804 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
805 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 806 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
807 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 808 (PPCVSX2): Define as PPC_OPCODE_POWER8.
809 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 810 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 811 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 812
62adc510
AM		 8132017-04-10 Alan Modra <amodra@gmail.com>
814
815 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
816 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
817 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
818 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
819
aa808707
PC		 8202017-04-09 Pip Cet <pipcet@gmail.com>
821
822 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
823 appropriate floating-point precision directly.
824
ac8f0f72
AM		 8252017-04-07 Alan Modra <amodra@gmail.com>
826
827 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
828 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
829 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
830 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
831 vector instructions with E6500 not PPCVEC2.
832
62ecb94c
PC		 8332017-04-06 Pip Cet <pipcet@gmail.com>
834
835 * Makefile.am: Add wasm32-dis.c.
836 * configure.ac: Add wasm32-dis.c to wasm32 target.
837 * disassemble.c: Add wasm32 disassembler code.
838 * wasm32-dis.c: New file.
839 * Makefile.in: Regenerate.
840 * configure: Regenerate.
841 * po/POTFILES.in: Regenerate.
842 * po/opcodes.pot: Regenerate.
843
f995bbe8
PA		 8442017-04-05 Pedro Alves <palves@redhat.com>
845
846 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
847 * arm-dis.c (parse_arm_disassembler_options): Constify.
848 * ppc-dis.c (powerpc_init_dialect): Constify local.
849 * vax-dis.c (parse_disassembler_options): Constify.
850
b5292032
PD		 8512017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
852
853 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
854 RISCV_GP_SYMBOL.
855
f96bd6c2
PC		 8562017-03-30 Pip Cet <pipcet@gmail.com>
857
858 * configure.ac: Add (empty) bfd_wasm32_arch target.
859 * configure: Regenerate
860 * po/opcodes.pot: Regenerate.
861
f7c514a3
JM		 8622017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
863
864 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
865 OSA2015.
866 * opcodes/sparc-opc.c (asi_table): New ASIs.
867
52be03fd
AM		 8682017-03-29 Alan Modra <amodra@gmail.com>
869
870 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
871 "raw" option.
872 (lookup_powerpc): Don't special case -1 dialect. Handle
873 PPC_OPCODE_RAW.
874 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
875 lookup_powerpc call, pass it on second.
876
9b753937
AM		 8772017-03-27 Alan Modra <amodra@gmail.com>
878
879 PR 21303
880 * ppc-dis.c (struct ppc_mopt): Comment.
881 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
882
c0c31e91
RZ		 8832017-03-27 Rinat Zelig <rinat@mellanox.com>
884
885 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
886 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
887 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
888 (insert_nps_misc_imm_offset): New function.
889 (extract_nps_misc imm_offset): New function.
890 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
891 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
892
2253c8f0
AK		 8932017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
894
895 * s390-mkopc.c (main): Remove vx2 check.
896 * s390-opc.txt: Remove vx2 instruction flags.
897
645d3342
RZ		 8982017-03-21 Rinat Zelig <rinat@mellanox.com>
899
900 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
901 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
902 (insert_nps_imm_offset): New function.
903 (extract_nps_imm_offset): New function.
904 (insert_nps_imm_entry): New function.
905 (extract_nps_imm_entry): New function.
906
4b94dd2d
AM		 9072017-03-17 Alan Modra <amodra@gmail.com>
908
909 PR 21248
910 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
911 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
912 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
913
b416fe87
KC		 9142017-03-14 Kito Cheng <kito.cheng@gmail.com>
915
916 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
917 <c.andi>: Likewise.
918 <c.addiw> Likewise.
919
03b039a5
KC		 9202017-03-14 Kito Cheng <kito.cheng@gmail.com>
921
922 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
923
2c232b83
AW		 9242017-03-13 Andrew Waterman <andrew@sifive.com>
925
926 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
927 <srl> Likewise.
928 <srai> Likewise.
929 <sra> Likewise.
930
86fa6981
L		 9312017-03-09 H.J. Lu <hongjiu.lu@intel.com>
932
933 * i386-gen.c (opcode_modifiers): Replace S with Load.
934 * i386-opc.h (S): Removed.
935 (Load): New.
936 (i386_opcode_modifier): Replace s with load.
937 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
938 and {evex}. Replace S with Load.
939 * i386-tbl.h: Regenerated.
940
c1fe188b
L		 9412017-03-09 H.J. Lu <hongjiu.lu@intel.com>
942
943 * i386-opc.tbl: Use CpuCET on rdsspq.
944 * i386-tbl.h: Regenerated.
945
4b8b687e
PB		 9462017-03-08 Peter Bergner <bergner@vnet.ibm.com>
947
948 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
949 <vsx>: Do not use PPC_OPCODE_VSX3;
950
1437d063
PB		 9512017-03-08 Peter Bergner <bergner@vnet.ibm.com>
952
953 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
954
603555e5
L		 9552017-03-06 H.J. Lu <hongjiu.lu@intel.com>
956
957 * i386-dis.c (REG_0F1E_MOD_3): New enum.
958 (MOD_0F1E_PREFIX_1): Likewise.
959 (MOD_0F38F5_PREFIX_2): Likewise.
960 (MOD_0F38F6_PREFIX_0): Likewise.
961 (RM_0F1E_MOD_3_REG_7): Likewise.
962 (PREFIX_MOD_0_0F01_REG_5): Likewise.
963 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
964 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
965 (PREFIX_0F1E): Likewise.
966 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
967 (PREFIX_0F38F5): Likewise.
968 (dis386_twobyte): Use PREFIX_0F1E.
969 (reg_table): Add REG_0F1E_MOD_3.
970 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
971 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
972 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
973 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
974 (three_byte_table): Use PREFIX_0F38F5.
975 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
976 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
977 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
978 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
979 PREFIX_MOD_3_0F01_REG_5_RM_2.
980 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
981 (cpu_flags): Add CpuCET.
982 * i386-opc.h (CpuCET): New enum.
983 (CpuUnused): Commented out.
984 (i386_cpu_flags): Add cpucet.
985 * i386-opc.tbl: Add Intel CET instructions.
986 * i386-init.h: Regenerated.
987 * i386-tbl.h: Likewise.
988
73f07bff
AM		 9892017-03-06 Alan Modra <amodra@gmail.com>
990
991 PR 21124
992 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
993 (extract_raq, extract_ras, extract_rbx): New functions.
994 (powerpc_operands): Use opposite corresponding insert function.
995 (Q_MASK): Define.
996 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
997 register restriction.
998
65b48a81
PB		 9992017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1000
1001 * disassemble.c Include "safe-ctype.h".
1002 (disassemble_init_for_target): Handle s390 init.
1003 (remove_whitespace_and_extra_commas): New function.
1004 (disassembler_options_cmp): Likewise.
1005 * arm-dis.c: Include "libiberty.h".
1006 (NUM_ELEM): Delete.
1007 (regnames): Use long disassembler style names.
1008 Add force-thumb and no-force-thumb options.
1009 (NUM_ARM_REGNAMES): Rename from this...
1010 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1011 (get_arm_regname_num_options): Delete.
1012 (set_arm_regname_option): Likewise.
1013 (get_arm_regnames): Likewise.
1014 (parse_disassembler_options): Likewise.
1015 (parse_arm_disassembler_option): Rename from this...
1016 (parse_arm_disassembler_options): ...to this. Make static.
1017 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1018 (print_insn): Use parse_arm_disassembler_options.
1019 (disassembler_options_arm): New function.
1020 (print_arm_disassembler_options): Handle updated regnames.
1021 * ppc-dis.c: Include "libiberty.h".
1022 (ppc_opts): Add "32" and "64" entries.
1023 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1024 (powerpc_init_dialect): Add break to switch statement.
1025 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1026 (disassembler_options_powerpc): New function.
1027 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1028 Remove printing of "32" and "64".
1029 * s390-dis.c: Include "libiberty.h".
1030 (init_flag): Remove unneeded variable.
1031 (struct s390_options_t): New structure type.
1032 (options): New structure.
1033 (init_disasm): Rename from this...
1034 (disassemble_init_s390): ...to this. Add initializations for
1035 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1036 (print_insn_s390): Delete call to init_disasm.
1037 (disassembler_options_s390): New function.
1038 (print_s390_disassembler_options): Print using information from
1039 struct 'options'.
1040 * po/opcodes.pot: Regenerate.
1041
15c7c1d8
JB		 10422017-02-28 Jan Beulich <jbeulich@suse.com>
1043
1044 * i386-dis.c (PCMPESTR_Fixup): New.
1045 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1046 (prefix_table): Use PCMPESTR_Fixup.
1047 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1048 PCMPESTR_Fixup.
1049 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1050 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1051 Split 64-bit and non-64-bit variants.
1052 * opcodes/i386-tbl.h: Re-generate.
1053
582e12bf
RS		 10542017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1055
1056 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1057 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1058 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1059 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1060 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1061 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1062 (OP_SVE_V_HSD): New macros.
1063 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1064 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1065 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1066 (aarch64_opcode_table): Add new SVE instructions.
1067 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1068 for rotation operands. Add new SVE operands.
1069 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1070 (ins_sve_quad_index): Likewise.
1071 (ins_imm_rotate): Split into...
1072 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1073 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1074 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1075 functions.
1076 (aarch64_ins_sve_addr_ri_s4): New function.
1077 (aarch64_ins_sve_quad_index): Likewise.
1078 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1079 * aarch64-asm-2.c: Regenerate.
1080 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1081 (ext_sve_quad_index): Likewise.
1082 (ext_imm_rotate): Split into...
1083 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1084 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1085 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1086 functions.
1087 (aarch64_ext_sve_addr_ri_s4): New function.
1088 (aarch64_ext_sve_quad_index): Likewise.
1089 (aarch64_ext_sve_index): Allow quad indices.
1090 (do_misc_decoding): Likewise.
1091 * aarch64-dis-2.c: Regenerate.
1092 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1093 aarch64_field_kinds.
1094 (OPD_F_OD_MASK): Widen by one bit.
1095 (OPD_F_NO_ZR): Bump accordingly.
1096 (get_operand_field_width): New function.
1097 * aarch64-opc.c (fields): Add new SVE fields.
1098 (operand_general_constraint_met_p): Handle new SVE operands.
1099 (aarch64_print_operand): Likewise.
1100 * aarch64-opc-2.c: Regenerate.
1101
f482d304
RS		 11022017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1103
1104 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1105 (aarch64_feature_compnum): ...this.
1106 (SIMD_V8_3): Replace with...
1107 (COMPNUM): ...this.
1108 (CNUM_INSN): New macro.
1109 (aarch64_opcode_table): Use it for the complex number instructions.
1110
7db2c588
JB		 11112017-02-24 Jan Beulich <jbeulich@suse.com>
1112
1113 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1114
1e9d41d4
SL		 11152017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1116
1117 Add support for associating SPARC ASIs with an architecture level.
1118 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1119 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1120 decoding of SPARC ASIs.
1121
53c4d625
JB		 11222017-02-23 Jan Beulich <jbeulich@suse.com>
1123
1124 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1125 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1126
11648de5
JB		 11272017-02-21 Jan Beulich <jbeulich@suse.com>
1128
1129 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1130 1 (instead of to itself). Correct typo.
1131
f98d33be
AW		 11322017-02-14 Andrew Waterman <andrew@sifive.com>
1133
1134 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1135 pseudoinstructions.
1136
773fb663
RS		 11372017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1138
1139 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1140 (aarch64_sys_reg_supported_p): Handle them.
1141
cc07cda6
CZ		 11422017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1143
1144 * arc-opc.c (UIMM6_20R): Define.
1145 (SIMM12_20): Use above.
1146 (SIMM12_20R): Define.
1147 (SIMM3_5_S): Use above.
1148 (UIMM7_A32_11R_S): Define.
1149 (UIMM7_9_S): Use above.
1150 (UIMM3_13R_S): Define.
1151 (SIMM11_A32_7_S): Use above.
1152 (SIMM9_8R): Define.
1153 (UIMM10_A32_8_S): Use above.
1154 (UIMM8_8R_S): Define.
1155 (W6): Use above.
1156 (arc_relax_opcodes): Use all above defines.
1157
66a5a740
VG		 11582017-02-15 Vineet Gupta <vgupta@synopsys.com>
1159
1160 * arc-regs.h: Distinguish some of the registers different on
1161 ARC700 and HS38 cpus.
1162
7e0de605
AM		 11632017-02-14 Alan Modra <amodra@gmail.com>
1164
1165 PR 21118
1166 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1167 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1168
54064fdb
AM		 11692017-02-11 Stafford Horne <shorne@gmail.com>
1170 Alan Modra <amodra@gmail.com>
1171
1172 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1173 Use insn_bytes_value and insn_int_value directly instead. Don't
1174 free allocated memory until function exit.
1175
dce75bf9
NP		 11762017-02-10 Nicholas Piggin <npiggin@gmail.com>
1177
1178 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1179
1b7e3d2f
NC		 11802017-02-03 Nick Clifton <nickc@redhat.com>
1181
1182 PR 21096
1183 * aarch64-opc.c (print_register_list): Ensure that the register
1184 list index will fir into the tb buffer.
1185 (print_register_offset_address): Likewise.
1186 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1187
8ec5cf65
AD		 11882017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1189
1190 PR 21056
1191 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1192 instructions when the previous fetch packet ends with a 32-bit
1193 instruction.
1194
a1aa5e81
DD		 11952017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1196
1197 * pru-opc.c: Remove vague reference to a future GDB port.
1198
add3afb2
NC		 11992017-01-20 Nick Clifton <nickc@redhat.com>
1200
1201 * po/ga.po: Updated Irish translation.
1202
c13a63b0
SN		 12032017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1204
1205 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1206
9608051a
YQ		 12072017-01-13 Yao Qi <yao.qi@linaro.org>
1208
1209 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1210 if FETCH_DATA returns 0.
1211 (m68k_scan_mask): Likewise.
1212 (print_insn_m68k): Update code to handle -1 return value.
1213
f622ea96
YQ		 12142017-01-13 Yao Qi <yao.qi@linaro.org>
1215
1216 * m68k-dis.c (enum print_insn_arg_error): New.
1217 (NEXTBYTE): Replace -3 with
1218 PRINT_INSN_ARG_MEMORY_ERROR.
1219 (NEXTULONG): Likewise.
1220 (NEXTSINGLE): Likewise.
1221 (NEXTDOUBLE): Likewise.
1222 (NEXTDOUBLE): Likewise.
1223 (NEXTPACKED): Likewise.
1224 (FETCH_ARG): Likewise.
1225 (FETCH_DATA): Update comments.
1226 (print_insn_arg): Update comments. Replace magic numbers with
1227 enum.
1228 (match_insn_m68k): Likewise.
1229
620214f7
IT		 12302017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1231
1232 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1233 * i386-dis-evex.h (evex_table): Updated.
1234 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1235 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1236 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1237 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1238 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1239 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1240 * i386-init.h: Regenerate.
1241 * i386-tbl.h: Ditto.
1242
d95014a2
YQ		 12432017-01-12 Yao Qi <yao.qi@linaro.org>
1244
1245 * msp430-dis.c (msp430_singleoperand): Return -1 if
1246 msp430dis_opcode_signed returns false.
1247 (msp430_doubleoperand): Likewise.
1248 (msp430_branchinstr): Return -1 if
1249 msp430dis_opcode_unsigned returns false.
1250 (msp430x_calla_instr): Likewise.
1251 (print_insn_msp430): Likewise.
1252
0ae60c3e
NC		 12532017-01-05 Nick Clifton <nickc@redhat.com>
1254
1255 PR 20946
1256 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1257 could not be matched.
1258 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1259 NULL.
1260
d74d4880
SN		 12612017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1262
1263 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1264 (aarch64_opcode_table): Use RCPC_INSN.
1265
cc917fd9
KC		 12662017-01-03 Kito Cheng <kito.cheng@gmail.com>
1267
1268 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1269 extension.
1270 * riscv-opcodes/all-opcodes: Likewise.
1271
b52d3cfc
DP		 12722017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1273
1274 * riscv-dis.c (print_insn_args): Add fall through comment.
1275
f90c58d5
NC		 12762017-01-03 Nick Clifton <nickc@redhat.com>
1277
1278 * po/sr.po: New Serbian translation.
1279 * configure.ac (ALL_LINGUAS): Add sr.
1280 * configure: Regenerate.
1281
f47b0d4a
AM		 12822017-01-02 Alan Modra <amodra@gmail.com>
1283
1284 * epiphany-desc.h: Regenerate.
1285 * epiphany-opc.h: Regenerate.
1286 * fr30-desc.h: Regenerate.
1287 * fr30-opc.h: Regenerate.
1288 * frv-desc.h: Regenerate.
1289 * frv-opc.h: Regenerate.
1290 * ip2k-desc.h: Regenerate.
1291 * ip2k-opc.h: Regenerate.
1292 * iq2000-desc.h: Regenerate.
1293 * iq2000-opc.h: Regenerate.
1294 * lm32-desc.h: Regenerate.
1295 * lm32-opc.h: Regenerate.
1296 * m32c-desc.h: Regenerate.
1297 * m32c-opc.h: Regenerate.
1298 * m32r-desc.h: Regenerate.
1299 * m32r-opc.h: Regenerate.
1300 * mep-desc.h: Regenerate.
1301 * mep-opc.h: Regenerate.
1302 * mt-desc.h: Regenerate.
1303 * mt-opc.h: Regenerate.
1304 * or1k-desc.h: Regenerate.
1305 * or1k-opc.h: Regenerate.
1306 * xc16x-desc.h: Regenerate.
1307 * xc16x-opc.h: Regenerate.
1308 * xstormy16-desc.h: Regenerate.
1309 * xstormy16-opc.h: Regenerate.
1310
2571583a
AM		 13112017-01-02 Alan Modra <amodra@gmail.com>
1312
1313 Update year range in copyright notice of all files.
1314
5c1ad6b5 1315For older changes see ChangeLog-2016
3499769a 1316\f
5c1ad6b5 1317Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1318
1319Copying and distribution of this file, with or without modification,
1320are permitted in any medium without royalty provided the copyright
1321notice and this notice are preserved.
1322
1323Local Variables:
1324mode: change-log
1325left-margin: 8
1326fill-column: 74
1327version-control: never
1328End:
GDB Binutils - Deliverables
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