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Update version number on development (aka HEAD) branch.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
719d8288
NC		 12018-06-24 Nick Clifton <nickc@redhat.com>
2
3 2.31 branch created.
4
514cd3a0
TC		 52018-06-19 Tamar Christina <tamar.christina@arm.com>
6
7 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
8 * aarch64-asm-2.c: Regenerate.
9 * aarch64-dis-2.c: Likewise.
10
385e4d0f
MR		 112018-06-21 Maciej W. Rozycki <macro@mips.com>
12
13 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
14 `-M ginv' option description.
15
160d1b3d
SH		 162018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
17
18 PR gas/23305
19 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
20 la and lla.
21
d0ac1c44
SM		 222018-06-19 Simon Marchi <simon.marchi@ericsson.com>
23
24 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
25 * configure.ac: Remove AC_PREREQ.
26 * Makefile.in: Re-generate.
27 * aclocal.m4: Re-generate.
28 * configure: Re-generate.
29
6f20c942
FS		 302018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
31
32 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
33 mips64r6 descriptors.
34 (parse_mips_ase_option): Handle -Mginv option.
35 (print_mips_disassembler_options): Document -Mginv.
36 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
37 (GINV): New macro.
38 (mips_opcodes): Define ginvi and ginvt.
39
730c3174
SE		 402018-06-13 Scott Egerton <scott.egerton@imgtec.com>
41 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
42
43 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
44 * mips-opc.c (CRC, CRC64): New macros.
45 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
46 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
47 crc32cd for CRC64.
48
cb366992
EB		 492018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
50
51 PR 20319
52 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
53 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
54
ce72cd46
AM		 552018-06-06 Alan Modra <amodra@gmail.com>
56
57 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
58 setjmp. Move init for some other vars later too.
59
4b8e28c7
MF		 602018-06-04 Max Filippov <jcmvbkbc@gmail.com>
61
62 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
63 (dis_private): Add new fields for property section tracking.
64 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
65 (xtensa_instruction_fits): New functions.
66 (fetch_data): Bump minimal fetch size to 4.
67 (print_insn_xtensa): Make struct dis_private static.
68 Load and prepare property table on section change.
69 Don't disassemble literals. Don't disassemble instructions that
70 cross property table boundaries.
71
55e99962
L		 722018-06-01 H.J. Lu <hongjiu.lu@intel.com>
73
74 * configure: Regenerated.
75
733bd0ab
JB		 762018-06-01 Jan Beulich <jbeulich@suse.com>
77
78 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
79 * i386-tbl.h: Re-generate.
80
dfd27d41
JB		 812018-06-01 Jan Beulich <jbeulich@suse.com>
82
83 * i386-opc.tbl (sldt, str): Add NoRex64.
84 * i386-tbl.h: Re-generate.
85
64795710
JB		 862018-06-01 Jan Beulich <jbeulich@suse.com>
87
88 * i386-opc.tbl (invpcid): Add Oword.
89 * i386-tbl.h: Re-generate.
90
030157d8
AM		 912018-06-01 Alan Modra <amodra@gmail.com>
92
93 * sysdep.h (_bfd_error_handler): Don't declare.
94 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
95 * rl78-decode.opc: Likewise.
96 * msp430-decode.c: Regenerate.
97 * rl78-decode.c: Regenerate.
98
a9660a6f
AP		 992018-05-30 Amit Pawar <Amit.Pawar@amd.com>
100
101 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
102 * i386-init.h : Regenerated.
103
277eb7f6
AM		 1042018-05-25 Alan Modra <amodra@gmail.com>
105
106 * Makefile.in: Regenerate.
107 * po/POTFILES.in: Regenerate.
108
98553ad3
PB		 1092018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
110
111 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
112 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
113 (insert_bab, extract_bab, insert_btab, extract_btab,
114 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
115 (BAT, BBA VBA RBS XB6S): Delete macros.
116 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
117 (BB, BD, RBX, XC6): Update for new macros.
118 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
119 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
120 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
121 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
122
7b4ae824
JD		 1232018-05-18 John Darrington <john@darrington.wattle.id.au>
124
125 * Makefile.am: Add support for s12z architecture.
126 * configure.ac: Likewise.
127 * disassemble.c: Likewise.
128 * disassemble.h: Likewise.
129 * Makefile.in: Regenerate.
130 * configure: Regenerate.
131 * s12z-dis.c: New file.
132 * s12z.h: New file.
133
29e0f0a1
AM		 1342018-05-18 Alan Modra <amodra@gmail.com>
135
136 * nfp-dis.c: Don't #include libbfd.h.
137 (init_nfp3200_priv): Use bfd_get_section_contents.
138 (nit_nfp6000_mecsr_sec): Likewise.
139
809276d2
NC		 1402018-05-17 Nick Clifton <nickc@redhat.com>
141
142 * po/zh_CN.po: Updated simplified Chinese translation.
143
ff329288
TC		 1442018-05-16 Tamar Christina <tamar.christina@arm.com>
145
146 PR binutils/23109
147 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
148 * aarch64-dis-2.c: Regenerate.
149
f9830ec1
TC		 1502018-05-15 Tamar Christina <tamar.christina@arm.com>
151
152 PR binutils/21446
153 * aarch64-asm.c (opintl.h): Include.
154 (aarch64_ins_sysreg): Enforce read/write constraints.
155 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
156 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
157 (F_REG_READ, F_REG_WRITE): New.
158 * aarch64-opc.c (aarch64_print_operand): Generate notes for
159 AARCH64_OPND_SYSREG.
160 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
161 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
162 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
163 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
164 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
165 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
166 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
167 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
168 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
169 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
170 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
171 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
172 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
173 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
174 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
175 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
176 msr (F_SYS_WRITE), mrs (F_SYS_READ).
177
7d02540a
TC		 1782018-05-15 Tamar Christina <tamar.christina@arm.com>
179
180 PR binutils/21446
181 * aarch64-dis.c (no_notes: New.
182 (parse_aarch64_dis_option): Support notes.
183 (aarch64_decode_insn, print_operands): Likewise.
184 (print_aarch64_disassembler_options): Document notes.
185 * aarch64-opc.c (aarch64_print_operand): Support notes.
186
561a72d4
TC		 1872018-05-15 Tamar Christina <tamar.christina@arm.com>
188
189 PR binutils/21446
190 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
191 and take error struct.
192 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
193 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
194 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
195 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
196 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
197 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
198 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
199 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
200 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
201 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
202 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
203 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
204 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
205 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
206 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
207 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
208 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
209 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
210 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
211 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
212 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
213 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
214 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
215 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
216 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
217 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
218 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
219 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
220 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
221 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
222 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
223 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
224 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
225 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
226 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
227 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
228 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
229 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
230 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
231 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
232 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
233 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
234 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
235 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
236 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
237 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
238 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
239 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
240 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
241 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
242 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
243 (determine_disassembling_preference, aarch64_decode_insn,
244 print_insn_aarch64_word, print_insn_data): Take errors struct.
245 (print_insn_aarch64): Use errors.
246 * aarch64-asm-2.c: Regenerate.
247 * aarch64-dis-2.c: Regenerate.
248 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
249 boolean in aarch64_insert_operan.
250 (print_operand_extractor): Likewise.
251 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
252
1678bd35
FT		 2532018-05-15 Francois H. Theron <francois.theron@netronome.com>
254
255 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
256
06cfb1c8
L		 2572018-05-09 H.J. Lu <hongjiu.lu@intel.com>
258
259 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
260
84f9f8c3
AM		 2612018-05-09 Sebastian Rasmussen <sebras@gmail.com>
262
263 * cr16-opc.c (cr16_instruction): Comment typo fix.
264 * hppa-dis.c (print_insn_hppa): Likewise.
265
e6f372ba
JW		 2662018-05-08 Jim Wilson <jimw@sifive.com>
267
268 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
269 (match_c_slli64, match_srxi_as_c_srxi): New.
270 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
271 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
272 <c.slli, c.srli, c.srai>: Use match_s_slli.
273 <c.slli64, c.srli64, c.srai64>: New.
274
f413a913
AM		 2752018-05-08 Alan Modra <amodra@gmail.com>
276
277 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
278 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
279 partition opcode space for index lookup.
280
a87a6478
PB		 2812018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
282
283 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
284 <insn_length>: ...with this. Update usage.
285 Remove duplicate call to *info->memory_error_func.
286
c0a30a9f
L		 2872018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
288 H.J. Lu <hongjiu.lu@intel.com>
289
290 * i386-dis.c (Gva): New.
291 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
292 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
293 (prefix_table): New instructions (see prefix above).
294 (mod_table): New instructions (see prefix above).
295 (OP_G): Handle va_mode.
296 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
297 CPU_MOVDIR64B_FLAGS.
298 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
299 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
300 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
301 * i386-opc.tbl: Add movidir{i,64b}.
302 * i386-init.h: Regenerated.
303 * i386-tbl.h: Likewise.
304
75c0a438
L		 3052018-05-07 H.J. Lu <hongjiu.lu@intel.com>
306
307 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
308 AddrPrefixOpReg.
309 * i386-opc.h (AddrPrefixOp0): Renamed to ...
310 (AddrPrefixOpReg): This.
311 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
312 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
313
2ceb7719
PB		 3142018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
315
316 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
317 (vle_num_opcodes): Likewise.
318 (spe2_num_opcodes): Likewise.
319 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
320 initialization loop.
321 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
322 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
323 only once.
324
b3ac5c6c
TC		 3252018-05-01 Tamar Christina <tamar.christina@arm.com>
326
327 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
328
fe944acf
FT		 3292018-04-30 Francois H. Theron <francois.theron@netronome.com>
330
331 Makefile.am: Added nfp-dis.c.
332 configure.ac: Added bfd_nfp_arch.
333 disassemble.h: Added print_insn_nfp prototype.
334 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
335 nfp-dis.c: New, for NFP support.
336 po/POTFILES.in: Added nfp-dis.c to the list.
337 Makefile.in: Regenerate.
338 configure: Regenerate.
339
e2195274
JB		 3402018-04-26 Jan Beulich <jbeulich@suse.com>
341
342 * i386-opc.tbl: Fold various non-memory operand AVX512VL
343 templates into their base ones.
344 * i386-tlb.h: Re-generate.
345
59ef5df4
JB		 3462018-04-26 Jan Beulich <jbeulich@suse.com>
347
348 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
349 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
350 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
351 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
352 * i386-init.h: Re-generate.
353
6e041cf4
JB		 3542018-04-26 Jan Beulich <jbeulich@suse.com>
355
356 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
357 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
358 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
359 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
360 comment.
361 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
362 and CpuRegMask.
363 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
364 CpuRegMask: Delete.
365 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
366 cpuregzmm, and cpuregmask.
367 * i386-init.h: Re-generate.
368 * i386-tbl.h: Re-generate.
369
0e0eea78
JB		 3702018-04-26 Jan Beulich <jbeulich@suse.com>
371
372 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
373 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
374 * i386-init.h: Re-generate.
375
2f1bada2
JB		 3762018-04-26 Jan Beulich <jbeulich@suse.com>
377
378 * i386-gen.c (VexImmExt): Delete.
379 * i386-opc.h (VexImmExt, veximmext): Delete.
380 * i386-opc.tbl: Drop all VexImmExt uses.
381 * i386-tlb.h: Re-generate.
382
bacd1457
JB		 3832018-04-25 Jan Beulich <jbeulich@suse.com>
384
385 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
386 register-only forms.
387 * i386-tlb.h: Re-generate.
388
10bba94b
TC		 3892018-04-25 Tamar Christina <tamar.christina@arm.com>
390
391 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
392
c48935d7
IT		 3932018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
394
395 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
396 PREFIX_0F1C.
397 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
398 (cpu_flags): Add CpuCLDEMOTE.
399 * i386-init.h: Regenerate.
400 * i386-opc.h (enum): Add CpuCLDEMOTE,
401 (i386_cpu_flags): Add cpucldemote.
402 * i386-opc.tbl: Add cldemote.
403 * i386-tbl.h: Regenerate.
404
211dc24b
AM		 4052018-04-16 Alan Modra <amodra@gmail.com>
406
407 * Makefile.am: Remove sh5 and sh64 support.
408 * configure.ac: Likewise.
409 * disassemble.c: Likewise.
410 * disassemble.h: Likewise.
411 * sh-dis.c: Likewise.
412 * sh64-dis.c: Delete.
413 * sh64-opc.c: Delete.
414 * sh64-opc.h: Delete.
415 * Makefile.in: Regenerate.
416 * configure: Regenerate.
417 * po/POTFILES.in: Regenerate.
418
a9a4b302
AM		 4192018-04-16 Alan Modra <amodra@gmail.com>
420
421 * Makefile.am: Remove w65 support.
422 * configure.ac: Likewise.
423 * disassemble.c: Likewise.
424 * disassemble.h: Likewise.
425 * w65-dis.c: Delete.
426 * w65-opc.h: Delete.
427 * Makefile.in: Regenerate.
428 * configure: Regenerate.
429 * po/POTFILES.in: Regenerate.
430
04cb01fd
AM		 4312018-04-16 Alan Modra <amodra@gmail.com>
432
433 * configure.ac: Remove we32k support.
434 * configure: Regenerate.
435
c2bf1eec
AM		 4362018-04-16 Alan Modra <amodra@gmail.com>
437
438 * Makefile.am: Remove m88k support.
439 * configure.ac: Likewise.
440 * disassemble.c: Likewise.
441 * disassemble.h: Likewise.
442 * m88k-dis.c: Delete.
443 * Makefile.in: Regenerate.
444 * configure: Regenerate.
445 * po/POTFILES.in: Regenerate.
446
6793974d
AM		 4472018-04-16 Alan Modra <amodra@gmail.com>
448
449 * Makefile.am: Remove i370 support.
450 * configure.ac: Likewise.
451 * disassemble.c: Likewise.
452 * disassemble.h: Likewise.
453 * i370-dis.c: Delete.
454 * i370-opc.c: Delete.
455 * Makefile.in: Regenerate.
456 * configure: Regenerate.
457 * po/POTFILES.in: Regenerate.
458
e82aa794
AM		 4592018-04-16 Alan Modra <amodra@gmail.com>
460
461 * Makefile.am: Remove h8500 support.
462 * configure.ac: Likewise.
463 * disassemble.c: Likewise.
464 * disassemble.h: Likewise.
465 * h8500-dis.c: Delete.
466 * h8500-opc.h: Delete.
467 * Makefile.in: Regenerate.
468 * configure: Regenerate.
469 * po/POTFILES.in: Regenerate.
470
fceadf09
AM		 4712018-04-16 Alan Modra <amodra@gmail.com>
472
473 * configure.ac: Remove tahoe support.
474 * configure: Regenerate.
475
ae1d3843
L		 4762018-04-15 H.J. Lu <hongjiu.lu@intel.com>
477
478 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
479 umwait.
480 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
481 64-bit mode.
482 * i386-tbl.h: Regenerated.
483
de89d0a3
IT		 4842018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
485
486 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
487 PREFIX_MOD_1_0FAE_REG_6.
488 (va_mode): New.
489 (OP_E_register): Use va_mode.
490 * i386-dis-evex.h (prefix_table):
491 New instructions (see prefixes above).
492 * i386-gen.c (cpu_flag_init): Add WAITPKG.
493 (cpu_flags): Likewise.
494 * i386-opc.h (enum): Likewise.
495 (i386_cpu_flags): Likewise.
496 * i386-opc.tbl: Add umonitor, umwait, tpause.
497 * i386-init.h: Regenerate.
498 * i386-tbl.h: Likewise.
499
a8eb42a8
AM		 5002018-04-11 Alan Modra <amodra@gmail.com>
501
502 * opcodes/i860-dis.c: Delete.
503 * opcodes/i960-dis.c: Delete.
504 * Makefile.am: Remove i860 and i960 support.
505 * configure.ac: Likewise.
506 * disassemble.c: Likewise.
507 * disassemble.h: Likewise.
508 * Makefile.in: Regenerate.
509 * configure: Regenerate.
510 * po/POTFILES.in: Regenerate.
511
caf0678c
L		 5122018-04-04 H.J. Lu <hongjiu.lu@intel.com>
513
514 PR binutils/23025
515 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
516 to 0.
517 (print_insn): Clear vex instead of vex.evex.
518
4fb0d2b9
NC		 5192018-04-04 Nick Clifton <nickc@redhat.com>
520
521 * po/es.po: Updated Spanish translation.
522
c39e5b26
JB		 5232018-03-28 Jan Beulich <jbeulich@suse.com>
524
525 * i386-gen.c (opcode_modifiers): Delete VecESize.
526 * i386-opc.h (VecESize): Delete.
527 (struct i386_opcode_modifier): Delete vecesize.
528 * i386-opc.tbl: Drop VecESize.
529 * i386-tlb.h: Re-generate.
530
8e6e0792
JB		 5312018-03-28 Jan Beulich <jbeulich@suse.com>
532
533 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
534 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
535 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
536 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
537 * i386-tlb.h: Re-generate.
538
9f123b91
JB		 5392018-03-28 Jan Beulich <jbeulich@suse.com>
540
541 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
542 Fold AVX512 forms
543 * i386-tlb.h: Re-generate.
544
9646c87b
JB		 5452018-03-28 Jan Beulich <jbeulich@suse.com>
546
547 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
548 (vex_len_table): Drop Y for vcvt*2si.
549 (putop): Replace plain 'Y' handling by abort().
550
c8d59609
NC		 5512018-03-28 Nick Clifton <nickc@redhat.com>
552
553 PR 22988
554 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
555 instructions with only a base address register.
556 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
557 handle AARHC64_OPND_SVE_ADDR_R.
558 (aarch64_print_operand): Likewise.
559 * aarch64-asm-2.c: Regenerate.
560 * aarch64_dis-2.c: Regenerate.
561 * aarch64-opc-2.c: Regenerate.
562
b8c169f3
JB		 5632018-03-22 Jan Beulich <jbeulich@suse.com>
564
565 * i386-opc.tbl: Drop VecESize from register only insn forms and
566 memory forms not allowing broadcast.
567 * i386-tlb.h: Re-generate.
568
96bc132a
JB		 5692018-03-22 Jan Beulich <jbeulich@suse.com>
570
571 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
572 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
573 sha256*): Drop Disp<N>.
574
9f79e886
JB		 5752018-03-22 Jan Beulich <jbeulich@suse.com>
576
577 * i386-dis.c (EbndS, bnd_swap_mode): New.
578 (prefix_table): Use EbndS.
579 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
580 * i386-opc.tbl (bndmov): Move misplaced Load.
581 * i386-tlb.h: Re-generate.
582
d6793fa1
JB		 5832018-03-22 Jan Beulich <jbeulich@suse.com>
584
585 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
586 templates allowing memory operands and folded ones for register
587 only flavors.
588 * i386-tlb.h: Re-generate.
589
f7768225
JB		 5902018-03-22 Jan Beulich <jbeulich@suse.com>
591
592 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
593 256-bit templates. Drop redundant leftover Disp<N>.
594 * i386-tlb.h: Re-generate.
595
0e35537d
JW		 5962018-03-14 Kito Cheng <kito.cheng@gmail.com>
597
598 * riscv-opc.c (riscv_insn_types): New.
599
b4a3689a
NC		 6002018-03-13 Nick Clifton <nickc@redhat.com>
601
602 * po/pt_BR.po: Updated Brazilian Portuguese translation.
603
d3d50934
L		 6042018-03-08 H.J. Lu <hongjiu.lu@intel.com>
605
606 * i386-opc.tbl: Add Optimize to clr.
607 * i386-tbl.h: Regenerated.
608
bd5dea88
L		 6092018-03-08 H.J. Lu <hongjiu.lu@intel.com>
610
611 * i386-gen.c (opcode_modifiers): Remove OldGcc.
612 * i386-opc.h (OldGcc): Removed.
613 (i386_opcode_modifier): Remove oldgcc.
614 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
615 instructions for old (<= 2.8.1) versions of gcc.
616 * i386-tbl.h: Regenerated.
617
e771e7c9
JB		 6182018-03-08 Jan Beulich <jbeulich@suse.com>
619
620 * i386-opc.h (EVEXDYN): New.
621 * i386-opc.tbl: Fold various AVX512VL templates.
622 * i386-tlb.h: Re-generate.
623
ed438a93
JB		 6242018-03-08 Jan Beulich <jbeulich@suse.com>
625
626 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
627 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
628 vpexpandd, vpexpandq): Fold AFX512VF templates.
629 * i386-tlb.h: Re-generate.
630
454172a9
JB		 6312018-03-08 Jan Beulich <jbeulich@suse.com>
632
633 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
634 Fold 128- and 256-bit VEX-encoded templates.
635 * i386-tlb.h: Re-generate.
636
36824150
JB		 6372018-03-08 Jan Beulich <jbeulich@suse.com>
638
639 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
640 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
641 vpexpandd, vpexpandq): Fold AVX512F templates.
642 * i386-tlb.h: Re-generate.
643
e7f5c0a9
JB		 6442018-03-08 Jan Beulich <jbeulich@suse.com>
645
646 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
647 64-bit templates. Drop Disp<N>.
648 * i386-tlb.h: Re-generate.
649
25a4277f
JB		 6502018-03-08 Jan Beulich <jbeulich@suse.com>
651
652 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
653 and 256-bit templates.
654 * i386-tlb.h: Re-generate.
655
d2224064
JB		 6562018-03-08 Jan Beulich <jbeulich@suse.com>
657
658 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
659 * i386-tlb.h: Re-generate.
660
1b193f0b
JB		 6612018-03-08 Jan Beulich <jbeulich@suse.com>
662
663 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
664 Drop NoAVX.
665 * i386-tlb.h: Re-generate.
666
f2f6a710
JB		 6672018-03-08 Jan Beulich <jbeulich@suse.com>
668
669 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
670 * i386-tlb.h: Re-generate.
671
38e314eb
JB		 6722018-03-08 Jan Beulich <jbeulich@suse.com>
673
674 * i386-gen.c (opcode_modifiers): Delete FloatD.
675 * i386-opc.h (FloatD): Delete.
676 (struct i386_opcode_modifier): Delete floatd.
677 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
678 FloatD by D.
679 * i386-tlb.h: Re-generate.
680
d53e6b98
JB		 6812018-03-08 Jan Beulich <jbeulich@suse.com>
682
683 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
684
2907c2f5
JB		 6852018-03-08 Jan Beulich <jbeulich@suse.com>
686
687 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
688 * i386-tlb.h: Re-generate.
689
73053c1f
JB		 6902018-03-08 Jan Beulich <jbeulich@suse.com>
691
692 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
693 forms.
694 * i386-tlb.h: Re-generate.
695
52fe4420
AM		 6962018-03-07 Alan Modra <amodra@gmail.com>
697
698 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
699 bfd_arch_rs6000.
700 * disassemble.h (print_insn_rs6000): Delete.
701 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
702 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
703 (print_insn_rs6000): Delete.
704
a6743a54
AM		 7052018-03-03 Alan Modra <amodra@gmail.com>
706
707 * sysdep.h (opcodes_error_handler): Define.
708 (_bfd_error_handler): Declare.
709 * Makefile.am: Remove stray #.
710 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
711 EDIT" comment.
712 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
713 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
714 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
715 opcodes_error_handler to print errors. Standardize error messages.
716 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
717 and include opintl.h.
718 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
719 * i386-gen.c: Standardize error messages.
720 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
721 * Makefile.in: Regenerate.
722 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
723 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
724 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
725 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
726 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
727 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
728 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
729 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
730 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
731 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
732 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
733 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
734 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
735
8305403a
L		 7362018-03-01 H.J. Lu <hongjiu.lu@intel.com>
737
738 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
739 vpsub[bwdq] instructions.
740 * i386-tbl.h: Regenerated.
741
e184813f
AM		 7422018-03-01 Alan Modra <amodra@gmail.com>
743
744 * configure.ac (ALL_LINGUAS): Sort.
745 * configure: Regenerate.
746
5b616bef
TP		 7472018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
748
749 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
750 macro by assignements.
751
b6f8c7c4
L		 7522018-02-27 H.J. Lu <hongjiu.lu@intel.com>
753
754 PR gas/22871
755 * i386-gen.c (opcode_modifiers): Add Optimize.
756 * i386-opc.h (Optimize): New enum.
757 (i386_opcode_modifier): Add optimize.
758 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
759 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
760 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
761 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
762 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
763 vpxord and vpxorq.
764 * i386-tbl.h: Regenerated.
765
e95b887f
AM		 7662018-02-26 Alan Modra <amodra@gmail.com>
767
768 * crx-dis.c (getregliststring): Allocate a large enough buffer
769 to silence false positive gcc8 warning.
770
0bccfb29
JW		 7712018-02-22 Shea Levy <shea@shealevy.com>
772
773 * disassemble.c (ARCH_riscv): Define if ARCH_all.
774
6b6b6807
L		 7752018-02-22 H.J. Lu <hongjiu.lu@intel.com>
776
777 * i386-opc.tbl: Add {rex},
778 * i386-tbl.h: Regenerated.
779
75f31665
MR		 7802018-02-20 Maciej W. Rozycki <macro@mips.com>
781
782 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
783 (mips16_opcodes): Replace `M' with `m' for "restore".
784
e207bc53
TP		 7852018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
786
787 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
788
87993319
MR		 7892018-02-13 Maciej W. Rozycki <macro@mips.com>
790
791 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
792 variable to `function_index'.
793
68d20676
NC		 7942018-02-13 Nick Clifton <nickc@redhat.com>
795
796 PR 22823
797 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
798 about truncation of printing.
799
d2159fdc
HW		 8002018-02-12 Henry Wong <henry@stuffedcow.net>
801
802 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
803
f174ef9f
NC		 8042018-02-05 Nick Clifton <nickc@redhat.com>
805
806 * po/pt_BR.po: Updated Brazilian Portuguese translation.
807
be3a8dca
IT		 8082018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
809
810 * i386-dis.c (enum): Add pconfig.
811 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
812 (cpu_flags): Add CpuPCONFIG.
813 * i386-opc.h (enum): Add CpuPCONFIG.
814 (i386_cpu_flags): Add cpupconfig.
815 * i386-opc.tbl: Add PCONFIG instruction.
816 * i386-init.h: Regenerate.
817 * i386-tbl.h: Likewise.
818
3233d7d0
IT		 8192018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
820
821 * i386-dis.c (enum): Add PREFIX_0F09.
822 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
823 (cpu_flags): Add CpuWBNOINVD.
824 * i386-opc.h (enum): Add CpuWBNOINVD.
825 (i386_cpu_flags): Add cpuwbnoinvd.
826 * i386-opc.tbl: Add WBNOINVD instruction.
827 * i386-init.h: Regenerate.
828 * i386-tbl.h: Likewise.
829
e925c834
JW		 8302018-01-17 Jim Wilson <jimw@sifive.com>
831
832 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
833
d777820b
IT		 8342018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
835
836 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
837 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
838 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
839 (cpu_flags): Add CpuIBT, CpuSHSTK.
840 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
841 (i386_cpu_flags): Add cpuibt, cpushstk.
842 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
843 * i386-init.h: Regenerate.
844 * i386-tbl.h: Likewise.
845
f6efed01
NC		 8462018-01-16 Nick Clifton <nickc@redhat.com>
847
848 * po/pt_BR.po: Updated Brazilian Portugese translation.
849 * po/de.po: Updated German translation.
850
2721d702
JW		 8512018-01-15 Jim Wilson <jimw@sifive.com>
852
853 * riscv-opc.c (match_c_nop): New.
854 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
855
616dcb87
NC		 8562018-01-15 Nick Clifton <nickc@redhat.com>
857
858 * po/uk.po: Updated Ukranian translation.
859
3957a496
NC		 8602018-01-13 Nick Clifton <nickc@redhat.com>
861
862 * po/opcodes.pot: Regenerated.
863
769c7ea5
NC		 8642018-01-13 Nick Clifton <nickc@redhat.com>
865
866 * configure: Regenerate.
867
faf766e3
NC		 8682018-01-13 Nick Clifton <nickc@redhat.com>
869
870 2.30 branch created.
871
888a89da
IT		 8722018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
873
874 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
875 * i386-tbl.h: Regenerate.
876
cbda583a
JB		 8772018-01-10 Jan Beulich <jbeulich@suse.com>
878
879 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
880 * i386-tbl.h: Re-generate.
881
c9e92278
JB		 8822018-01-10 Jan Beulich <jbeulich@suse.com>
883
884 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
885 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
886 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
887 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
888 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
889 Disp8MemShift of AVX512VL forms.
890 * i386-tbl.h: Re-generate.
891
35fd2b2b
JW		 8922018-01-09 Jim Wilson <jimw@sifive.com>
893
894 * riscv-dis.c (maybe_print_address): If base_reg is zero,
895 then the hi_addr value is zero.
896
91d8b670
JG		 8972018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
898
899 * arm-dis.c (arm_opcodes): Add csdb.
900 (thumb32_opcodes): Add csdb.
901
be2e7d95
JG		 9022018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
903
904 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
905 * aarch64-asm-2.c: Regenerate.
906 * aarch64-dis-2.c: Regenerate.
907 * aarch64-opc-2.c: Regenerate.
908
704a705d
L		 9092018-01-08 H.J. Lu <hongjiu.lu@intel.com>
910
911 PR gas/22681
912 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
913 Remove AVX512 vmovd with 64-bit operands.
914 * i386-tbl.h: Regenerated.
915
35eeb78f
JW		 9162018-01-05 Jim Wilson <jimw@sifive.com>
917
918 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
919 jalr.
920
219d1afa
AM		 9212018-01-03 Alan Modra <amodra@gmail.com>
922
923 Update year range in copyright notice of all files.
924
1508bbf5
JB		 9252018-01-02 Jan Beulich <jbeulich@suse.com>
926
927 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
928 and OPERAND_TYPE_REGZMM entries.
929
1e563868 930For older changes see ChangeLog-2017
3499769a 931\f
1e563868 932Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 933
934Copying and distribution of this file, with or without modification,
935are permitted in any medium without royalty provided the copyright
936notice and this notice are preserved.
937
938Local Variables:
939mode: change-log
940left-margin: 8
941fill-column: 74
942version-control: never
943End:
GDB Binutils - Deliverables
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