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Fix computation of got relocations for .got sections greater than
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4b8c8c02
RE		 12012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2
3 * arm-dis.c: Changed ldra and strl-form mnemonics
4 to lda and stl-form.
5
83ea18d0
MR		 62012-09-18 Chao-ying Fu <fu@mips.com>
7
8 * micromips-opc.c (micromips_opcodes): Correct the encoding of
9 the "swxc1" instruction.
10
062f38fa
RE		 112012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
12
13 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
14 the parameter 'inst'.
15 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
16 (convert_mov_to_movewide): Change to assert (0) when
17 aarch64_wide_constant_p returns FALSE.
18
b132a67d
DE		 192012-09-14 David Edelsohn <dje.gcc@gmail.com>
20
21 * configure: Regenerate.
22
1f9b75dd
AG		 232012-09-14 Anthony Green <green@moxielogic.com>
24
25 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
26 the address after the branch instruction.
27
e202fa84
AG		 282012-09-13 Anthony Green <green@moxielogic.com>
29
30 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
31
00716ab1
AM		 322012-09-10 Matthias Klose <doko@ubuntu.com>
33
34 * config.in: Disable sanity check for kfreebsd.
35
6d2920c8
L		 362012-09-10 H.J. Lu <hongjiu.lu@intel.com>
37
38 * configure: Regenerated.
39
b3e14eda
L		 402012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
41
42 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
43 * ia64-gen.c: Promote completer index type to longlong.
44 (irf_operand): Add new register recognition.
45 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
46 (lookup_specifier): Add new resource recognition.
47 (insert_bit_table_ent): Relax abort condition according to the
48 changed completer index type.
49 (print_dis_table): Fix printf format for completer index.
50 * ia64-ic.tbl: Add a new instruction class.
51 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
52 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
53 * ia64-opc.h: Define short names for new operand types.
54 * ia64-raw.tbl: Add new RAW resource for DAHR register.
55 * ia64-waw.tbl: Add new WAW resource for DAHR register.
56 * ia64-asmtab.c: Regenerate.
57
382c72e9
PB		 582012-08-29 Peter Bergner <bergner@vnet.ibm.com>
59
60 * ppc-opc.c (VXASHB_MASK): New define.
61 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
62
fb048c26
PB		 632012-08-28 Peter Bergner <bergner@vnet.ibm.com>
64
65 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
66 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
67 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
68 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
69 vupklsh>: Use VXVA_MASK.
70 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
71 <mfvscr>: Use VXVAVB_MASK.
72 <mtvscr>: Use VXVDVA_MASK.
73 <vspltb>: Use VXUIMM4_MASK.
74 <vsplth>: Use VXUIMM3_MASK.
75 <vspltw>: Use VXUIMM2_MASK.
76
3c9017d2
MGD		 772012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
78
79 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
80
48adcd8e
MGD		 812012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
82
83 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
84
4f51b4bd
MGD		 852012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
86
87 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
88
91ff7894
MGD		 892012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
90
91 * arm-dis.c (neon_opcodes): Add support for AES instructions.
92
c70a8987
MGD		 932012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
94
95 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
96 conversions.
97
30bdf752
MGD		 982012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
99
100 * arm-dis.c (coprocessor_opcodes): Add VRINT.
101 (neon_opcodes): Likewise.
102
7e8e6784
MGD		 1032012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
104
105 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
106 variants.
107 (neon_opcodes): Likewise.
108
73924fbc
MGD		 1092012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
110
111 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
112 (neon_opcodes): Likewise.
113
33399f07
MGD		 1142012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
115
116 * arm-dis.c (coprocessor_opcodes): Add VSEL.
117 (print_insn_coprocessor): Add new %<>c bitfield format
118 specifier.
119
9eb6c0f1
MGD		 1202012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
121
122 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
123 (thumb32_opcodes): Likewise.
124 (print_arm_insn): Add support for %<>T formatter.
125
8884b720
MGD		 1262012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
127
128 * arm-dis.c (arm_opcodes): Add HLT.
129 (thumb_opcodes): Likewise.
130
b79f7053
MGD		 1312012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
132
133 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
134
53c4b28b
MGD		 1352012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
136
137 * arm-dis.c (arm_opcodes): Add SEVL.
138 (thumb_opcodes): Likewise.
139 (thumb32_opcodes): Likewise.
140
e797f7e0
MGD		 1412012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
142
143 * arm-dis.c (data_barrier_option): New function.
144 (print_insn_arm): Use data_barrier_option.
145 (print_insn_thumb32): Use data_barrier_option.
146
e2efe87d
MGD		 1472012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
148
149 * arm-dis.c (COND_UNCOND): New constant.
150 (print_insn_coprocessor): Add support for %u format specifier.
151 (print_insn_neon): Likewise.
152
2c63854f
DM		 1532012-08-21 David S. Miller <davem@davemloft.net>
154
155 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
156 F3F4 macro.
157
e67ed0e8
AM		 1582012-08-20 Edmar Wienskoski <edmar@freescale.com>
159
160 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
161 vabsduh, vabsduw, mviwsplt.
162
7b458c12
L		 1632012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
164
165 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
166 CPU_BTVER2_FLAGS.
167
e67ed0e8 168 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 169
170 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
171 * i386-init.h: Regenerated.
172 * i386-tbl.h: Likewise.
173
eb80cb87
NC		 1742012-08-17 Nick Clifton <nickc@redhat.com>
175
176 * po/uk.po: New Ukranian translation.
177 * configure.in (ALL_LINGUAS): Add uk.
178 * configure: Regenerate.
179
8baf7b78
PB		 1802012-08-16 Peter Bergner <bergner@vnet.ibm.com>
181
182 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
183 RBX for the third operand.
184 <"lswi">: Use RAX for second and NBI for the third operand.
185
3d557b4c
DD		 1862012-08-15 DJ Delorie <dj@redhat.com>
187
188 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
189 operands, so that data addresses can be corrected when not
190 ES-overridden.
191 * rl78-decode.c: Regenerate.
192 * rl78-dis.c (print_insn_rl78): Make order of modifiers
193 irrelevent. When the 'e' specifier is used on an operand and no
194 ES prefix is provided, adjust address to make it absolute.
195
588925d0
PB		 1962012-08-15 Peter Bergner <bergner@vnet.ibm.com>
197
198 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
199
9f6a6cc0
PB		 2002012-08-15 Peter Bergner <bergner@vnet.ibm.com>
201
202 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
203
fc8c4fd1
MR		 2042012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
205
206 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
207 macros, use local variables for info struct member accesses,
208 update the type of the variable used to hold the instruction
209 word.
210 (print_insn_mips, print_mips16_insn_arg): Likewise.
211 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
212 local variables for info struct member accesses.
213 (print_insn_micromips): Add GET_OP_S local macro.
214 (_print_insn_mips): Update the type of the variable used to hold
215 the instruction word.
216
a06ea964 2172012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 218 Laurent Desnogues <laurent.desnogues@arm.com>
219 Jim MacArthur <jim.macarthur@arm.com>
220 Marcus Shawcroft <marcus.shawcroft@arm.com>
221 Nigel Stephens <nigel.stephens@arm.com>
222 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
223 Richard Earnshaw <rearnsha@arm.com>
224 Sofiane Naci <sofiane.naci@arm.com>
225 Tejas Belagod <tejas.belagod@arm.com>
226 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 227
228 * Makefile.am: Add AArch64.
229 * Makefile.in: Regenerate.
230 * aarch64-asm.c: New file.
231 * aarch64-asm.h: New file.
232 * aarch64-dis.c: New file.
233 * aarch64-dis.h: New file.
234 * aarch64-gen.c: New file.
235 * aarch64-opc.c: New file.
236 * aarch64-opc.h: New file.
237 * aarch64-tbl.h: New file.
238 * configure.in: Add AArch64.
239 * configure: Regenerate.
240 * disassemble.c: Add AArch64.
241 * aarch64-asm-2.c: New file (automatically generated).
242 * aarch64-dis-2.c: New file (automatically generated).
243 * aarch64-opc-2.c: New file (automatically generated).
244 * po/POTFILES.in: Regenerate.
245
35d0a169
MR		 2462012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
247
248 * micromips-opc.c (micromips_opcodes): Update comment.
249 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
250 instructions for IOCT as appropriate.
251 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
252 opcode_is_member.
253 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
254 the result of a check for the -Wno-missing-field-initializers
255 GCC option.
256 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
257 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
258 compilation.
259 (mips16-opc.lo): Likewise.
260 (micromips-opc.lo): Likewise.
261 * aclocal.m4: Regenerate.
262 * configure: Regenerate.
263 * Makefile.in: Regenerate.
264
5c5acbbd
L		 2652012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
266
267 PR gas/14423
268 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
269 * i386-init.h: Regenerated.
270
3c892704
NC		 2712012-08-09 Nick Clifton <nickc@redhat.com>
272
273 * po/vi.po: Updated Vietnamese translation.
274
d7189fa5
RM		 2752012-08-07 Roland McGrath <mcgrathr@google.com>
276
277 * i386-dis.c (reg_table): Fill out REG_0F0D table with
278 AMD-reserved cases as "prefetch".
279 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
280 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
281 (reg_table): Use those under REG_0F18.
282 (mod_table): Add those cases as "nop/reserved".
283
4c692bc7
JB		 2842012-08-07 Jan Beulich <jbeulich@suse.com>
285
286 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
287
de882298
RM		 2882012-08-06 Roland McGrath <mcgrathr@google.com>
289
290 * i386-dis.c (print_insn): Print spaces between multiple excess
291 prefixes. Return actual number of excess prefixes consumed,
292 not always one.
293
294 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
295
7bb15c6f
RM		 2962012-08-06 Roland McGrath <mcgrathr@google.com>
297 Victor Khimenko <khim@google.com>
298 H.J. Lu <hongjiu.lu@intel.com>
299
300 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
301 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
302 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
303 (OP_E_register): Likewise.
304 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
305
3843081d
JBG		 3062012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
307
308 * configure.in: Formatting.
309 * configure: Regenerate.
310
48891606
AM		 3112012-08-01 Alan Modra <amodra@gmail.com>
312
313 * h8300-dis.c: Fix printf arg warnings.
314 * i960-dis.c: Likewise.
315 * mips-dis.c: Likewise.
316 * pdp11-dis.c: Likewise.
317 * sh-dis.c: Likewise.
318 * v850-dis.c: Likewise.
319 * configure.in: Formatting.
320 * configure: Regenerate.
321 * rl78-decode.c: Regenerate.
322 * po/POTFILES.in: Regenerate.
323
03f66e8a 3242012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 325 Catherine Moore <clm@codesourcery.com>
326 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 327
328 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
329 (DSP_VOLA): Likewise.
330 (D32, D33): Likewise.
331 (micromips_opcodes): Add DSP ASE instructions.
48891606 332 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 333 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
334
94948e64
JB		 3352012-07-31 Jan Beulich <jbeulich@suse.com>
336
337 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
338 instruction group. Mark as requiring AVX2.
339 * i386-tbl.h: Re-generate.
340
a6dc81d2
NC		 3412012-07-30 Nick Clifton <nickc@redhat.com>
342
343 * po/opcodes.pot: Updated template.
344 * po/es.po: Updated Spanish translation.
345 * po/fi.po: Updated Finnish translation.
346
c4dd807e
MF		 3472012-07-27 Mike Frysinger <vapier@gentoo.org>
348
349 * configure.in (BFD_VERSION): Run bfd/configure --version and
350 parse the output of that.
351 * configure: Regenerate.
352
03edbe3b
JL		 3532012-07-25 James Lemke <jwlemke@codesourcery.com>
354
355 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
356
63d08c68
NC		 3572012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
358 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 359
360 PR binutils/13135
361 * arm-dis.c: Add necessary casts for printing integer values.
362 Use %s when printing string values.
363 * hppa-dis.c: Likewise.
364 * m68k-dis.c: Likewise.
365 * microblaze-dis.c: Likewise.
366 * mips-dis.c: Likewise.
367 * sparc-dis.c: Likewise.
368
ff688e1f
L		 3692012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
370
371 PR binutils/14355
372 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
373 (VEX_LEN_0FXOP_08_CD): Likewise.
374 (VEX_LEN_0FXOP_08_CE): Likewise.
375 (VEX_LEN_0FXOP_08_CF): Likewise.
376 (VEX_LEN_0FXOP_08_EC): Likewise.
377 (VEX_LEN_0FXOP_08_ED): Likewise.
378 (VEX_LEN_0FXOP_08_EE): Likewise.
379 (VEX_LEN_0FXOP_08_EF): Likewise.
380 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
381 vpcomub, vpcomuw, vpcomud, vpcomuq.
382 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
383 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
384 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
385 VEX_LEN_0FXOP_08_EF.
386
e2e1fcde
L		 3872012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
388
389 * i386-dis.c (PREFIX_0F38F6): New.
390 (prefix_table): Add adcx, adox instructions.
391 (three_byte_table): Use PREFIX_0F38F6.
392 (mod_table): Add rdseed instruction.
393 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
394 (cpu_flags): Likewise.
395 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
396 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
397 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
398 prefetchw.
399 * i386-tbl.h: Regenerate.
400 * i386-init.h: Likewise.
401
8b99bf0b
TS		 4022012-07-05 Thomas Schwinge <thomas@codesourcery.com>
403
f4263ca2 404 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 405
416cf80a
SK		 4062012-07-05 Sean Keys <skeys@ipdatasys.com>
407
408 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 409 always be false due to overlapping operand masks.
410 * xgate-opc.c: Corrected 'com' opcode entry and
411 fixed spacing.
416cf80a 412
9fa0f14a
RM		 4132012-07-02 Roland McGrath <mcgrathr@google.com>
414
415 * i386-opc.tbl: Add RepPrefixOk to nop.
416 * i386-tbl.h: Regenerate.
417
4c6a93d3
NC		 4182012-06-28 Nick Clifton <nickc@redhat.com>
419
420 * po/vi.po: Updated Vietnamese translation.
421
29c048b6
RM		 4222012-06-22 Roland McGrath <mcgrathr@google.com>
423
fe13e45b
RM		 424 * i386-opc.tbl: Add RepPrefixOk to ret.
425 * i386-tbl.h: Regenerate.
426
29c048b6
RM		 427 * i386-opc.h (RepPrefixOk): New enum constant.
428 (i386_opcode_modifier): New bitfield 'repprefixok'.
429 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
430 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
431 instructions that have IsString.
432 * i386-tbl.h: Regenerate.
433
c7a8dbf9
AS		 4342012-06-11 Andreas Schwab <schwab@linux-m68k.org>
435
436 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
437 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
438 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
439 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
440 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
441 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
442 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
443 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
444 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
445
94caa966
AM		 4462012-05-19 Alan Modra <amodra@gmail.com>
447
448 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
449 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
450
5eb3690e
AM		 4512012-05-18 Alan Modra <amodra@gmail.com>
452
71fe7bab
AM		 453 * ia64-opc.c: Remove #include "ansidecl.h".
454 * z8kgen.c: Include sysdep.h first.
455
5eb3690e
AM		 456 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
457 * bfin-dis.c: Likewise.
458 * i860-dis.c: Likewise.
459 * ia64-dis.c: Likewise.
460 * ia64-gen.c: Likewise.
461 * m68hc11-dis.c: Likewise.
462 * mmix-dis.c: Likewise.
463 * msp430-dis.c: Likewise.
464 * or32-dis.c: Likewise.
465 * rl78-dis.c: Likewise.
466 * rx-dis.c: Likewise.
467 * tic4x-dis.c: Likewise.
468 * tilegx-opc.c: Likewise.
469 * tilepro-opc.c: Likewise.
470 * rx-decode.c: Regenerate.
471
a4ebc835
AM		 4722012-05-17 James Lemke <jwlemke@codesourcery.com>
473
474 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
475
98c76446
AM		 4762012-05-17 James Lemke <jwlemke@codesourcery.com>
477
478 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
479
df7b86aa
NC		 4802012-05-17 Daniel Richard G. <skunk@iskunk.org>
481 Nick Clifton <nickc@redhat.com>
482
483 PR 14072
484 * configure.in: Add check that sysdep.h has been included before
485 any system header files.
486 * configure: Regenerate.
487 * config.in: Regenerate.
488 * sysdep.h: Generate an error if included before config.h.
489 * alpha-opc.c: Include sysdep.h before any other header file.
490 * alpha-dis.c: Likewise.
491 * avr-dis.c: Likewise.
492 * cgen-opc.c: Likewise.
493 * cr16-dis.c: Likewise.
494 * cris-dis.c: Likewise.
495 * crx-dis.c: Likewise.
496 * d10v-dis.c: Likewise.
497 * d10v-opc.c: Likewise.
498 * d30v-dis.c: Likewise.
499 * d30v-opc.c: Likewise.
500 * h8500-dis.c: Likewise.
501 * i370-dis.c: Likewise.
502 * i370-opc.c: Likewise.
503 * m10200-dis.c: Likewise.
504 * m10300-dis.c: Likewise.
505 * micromips-opc.c: Likewise.
506 * mips-opc.c: Likewise.
507 * mips61-opc.c: Likewise.
508 * moxie-dis.c: Likewise.
509 * or32-opc.c: Likewise.
510 * pj-dis.c: Likewise.
511 * ppc-dis.c: Likewise.
512 * ppc-opc.c: Likewise.
513 * s390-dis.c: Likewise.
514 * sh-dis.c: Likewise.
515 * sh64-dis.c: Likewise.
516 * sparc-dis.c: Likewise.
517 * sparc-opc.c: Likewise.
518 * spu-dis.c: Likewise.
519 * tic30-dis.c: Likewise.
520 * tic54x-dis.c: Likewise.
521 * tic80-dis.c: Likewise.
522 * tic80-opc.c: Likewise.
523 * tilegx-dis.c: Likewise.
524 * tilepro-dis.c: Likewise.
525 * v850-dis.c: Likewise.
526 * v850-opc.c: Likewise.
527 * vax-dis.c: Likewise.
528 * w65-dis.c: Likewise.
529 * xgate-dis.c: Likewise.
530 * xtensa-dis.c: Likewise.
531 * rl78-decode.opc: Likewise.
532 * rl78-decode.c: Regenerate.
533 * rx-decode.opc: Likewise.
534 * rx-decode.c: Regenerate.
535
e1dad58d
AM		 5362012-05-17 Alan Modra <amodra@gmail.com>
537
538 * ppc_dis.c: Don't include elf/ppc.h.
539
101af531
NC		 5402012-05-16 Meador Inge <meadori@codesourcery.com>
541
542 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
543 to PUSH/POP {reg}.
544
6927f982
NC		 5452012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
546 Stephane Carrez <stcarrez@nerim.fr>
547
548 * configure.in: Add S12X and XGATE co-processor support to m68hc11
549 target.
550 * disassemble.c: Likewise.
551 * configure: Regenerate.
552 * m68hc11-dis.c: Make objdump output more consistent, use hex
553 instead of decimal and use 0x prefix for hex.
554 * m68hc11-opc.c: Add S12X and XGATE opcodes.
555
b9c361e0
JL		 5562012-05-14 James Lemke <jwlemke@codesourcery.com>
557
558 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
559 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
560 (vle_opcd_indices): New array.
561 (lookup_vle): New function.
562 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
563 (print_insn_powerpc): Likewise.
564 * ppc-opc.c: Likewise.
565
5662012-05-14 Catherine Moore <clm@codesourcery.com>
567 Maciej W. Rozycki <macro@codesourcery.com>
568 Rhonda Wittels <rhonda@codesourcery.com>
569 Nathan Froyd <froydnj@codesourcery.com>
570
571 * ppc-opc.c (insert_arx, extract_arx): New functions.
572 (insert_ary, extract_ary): New functions.
573 (insert_li20, extract_li20): New functions.
574 (insert_rx, extract_rx): New functions.
575 (insert_ry, extract_ry): New functions.
576 (insert_sci8, extract_sci8): New functions.
577 (insert_sci8n, extract_sci8n): New functions.
578 (insert_sd4h, extract_sd4h): New functions.
579 (insert_sd4w, extract_sd4w): New functions.
580 (insert_vlesi, extract_vlesi): New functions.
581 (insert_vlensi, extract_vlensi): New functions.
582 (insert_vleui, extract_vleui): New functions.
583 (insert_vleil, extract_vleil): New functions.
584 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
585 (BI16, BI32, BO32, B8): New.
586 (B15, B24, CRD32, CRS): New.
587 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
588 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
589 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
590 (SH6_MASK): Use PPC_OPSHIFT_INV.
591 (SI8, UI5, OIMM5, UI7, BO16): New.
592 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
593 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
594 (ALLOW8_SPRG): New.
595 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
596 (OPVUP, OPVUP_MASK OPVUP): New
597 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
598 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
599 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
600 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
601 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
602 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
603 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
604 (SE_IM5, SE_IM5_MASK): New.
605 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
606 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
607 (BO32DNZ, BO32DZ): New.
608 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
609 (PPCVLE): New.
610 (powerpc_opcodes): Add new VLE instructions. Update existing
611 instruction to include PPCVLE if supported.
612 * ppc-dis.c (ppc_opts): Add vle entry.
613 (get_powerpc_dialect): New function.
614 (powerpc_init_dialect): VLE support.
615 (print_insn_big_powerpc): Call get_powerpc_dialect.
616 (print_insn_little_powerpc): Likewise.
617 (operand_value_powerpc): Handle negative shift counts.
618 (print_insn_powerpc): Handle 2-byte instruction lengths.
619
208a4923
NC		 6202012-05-11 Daniel Richard G. <skunk@iskunk.org>
621
622 PR binutils/14028
623 * configure.in: Invoke ACX_HEADER_STRING.
624 * configure: Regenerate.
625 * config.in: Regenerate.
626 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
627 string.h and strings.h.
628
6750a3a7
NC		 6292012-05-11 Nick Clifton <nickc@redhat.com>
630
631 PR binutils/14006
632 * arm-dis.c (print_insn): Fix detection of instruction mode in
633 files containing multiple executable sections.
634
f6c1a2d5
NC		 6352012-05-03 Sean Keys <skeys@ipdatasys.com>
636
637 * Makefile.in, configure: regenerate
638 * disassemble.c (disassembler): Recognize ARCH_XGATE.
639 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
640 New functions.
641 * configure.in: Recognize xgate.
642 * xgate-dis.c, xgate-opc.c: New files for support of xgate
643 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
644 and opcode generation for xgate.
645
78e98aab
DD		 6462012-04-30 DJ Delorie <dj@redhat.com>
647
648 * rx-decode.opc (MOV): Do not sign-extend immediates which are
649 already the maximum bit size.
650 * rx-decode.c: Regenerate.
651
ec668d69
DM		 6522012-04-27 David S. Miller <davem@davemloft.net>
653
2e52845b
DM		 654 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
655 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
656
58004e23
DM		 657 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
658 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
659
698544e1
DM		 660 * sparc-opc.c (CBCOND): New define.
661 (CBCOND_XCC): Likewise.
662 (cbcond): New helper macro.
663 (sparc_opcodes): Add compare-and-branch instructions.
664
6cda1326
DM		 665 * sparc-dis.c (print_insn_sparc): Handle ')'.
666 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
667
ec668d69
DM		 668 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
669 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
670
2615994e
DM		 6712012-04-12 David S. Miller <davem@davemloft.net>
672
673 * sparc-dis.c (X_DISP10): Define.
674 (print_insn_sparc): Handle '='.
675
5de10af0
MF		 6762012-04-01 Mike Frysinger <vapier@gentoo.org>
677
678 * bfin-dis.c (fmtconst): Replace decimal handling with a single
679 sprintf call and the '*' field width.
680
55a36193
MK		 6812012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
682
683 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
684
d6688282
AM		 6852012-03-16 Alan Modra <amodra@gmail.com>
686
687 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
688 (powerpc_opcd_indices): Bump array size.
689 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
690 corresponding to unused opcodes to following entry.
691 (lookup_powerpc): New function, extracted and optimised from..
692 (print_insn_powerpc): ..here.
693
b240011a
AM		 6942012-03-15 Alan Modra <amodra@gmail.com>
695 James Lemke <jwlemke@codesourcery.com>
696
697 * disassemble.c (disassemble_init_for_target): Handle ppc init.
698 * ppc-dis.c (private): New var.
699 (powerpc_init_dialect): Don't return calloc failure, instead use
700 private.
701 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
702 (powerpc_opcd_indices): New array.
703 (disassemble_init_powerpc): New function.
704 (print_insn_big_powerpc): Don't init dialect here.
705 (print_insn_little_powerpc): Likewise.
706 (print_insn_powerpc): Start search using powerpc_opcd_indices.
707
aea77599
AM		 7082012-03-10 Edmar Wienskoski <edmar@freescale.com>
709
710 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
711 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
712 (PPCVEC2, PPCTMR, E6500): New short names.
713 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
714 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
715 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
716 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
717 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
718 optional operands on sync instruction for E6500 target.
719
5333187a
AK		 7202012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
721
722 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
723
a597d2d3
AM		 7242012-02-27 Alan Modra <amodra@gmail.com>
725
726 * mt-dis.c: Regenerate.
727
3f26eb3a
AM		 7282012-02-27 Alan Modra <amodra@gmail.com>
729
730 * v850-opc.c (extract_v8): Rearrange to make it obvious this
731 is the inverse of corresponding insert function.
732 (extract_d22, extract_u9, extract_r4): Likewise.
733 (extract_d9): Correct sign extension.
734 (extract_d16_15): Don't assume "long" is 32 bits, and don't
735 rely on implementation defined behaviour for shift right of
736 signed types.
737 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
738 (extract_d23): Likewise, and correct mask.
739
1f42f8b3
AM		 7402012-02-27 Alan Modra <amodra@gmail.com>
741
742 * crx-dis.c (print_arg): Mask constant to 32 bits.
743 * crx-opc.c (cst4_map): Use int array.
744
cdb06235
AM		 7452012-02-27 Alan Modra <amodra@gmail.com>
746
747 * arc-dis.c (BITS): Don't use shifts to mask off bits.
748 (FIELDD): Sign extend with xor,sub.
749
6f7be959
WL		 7502012-02-25 Walter Lee <walt@tilera.com>
751
752 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
753 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
754 TILEPRO_OPC_LW_TLS_SN.
755
82c2def5
L		 7562012-02-21 H.J. Lu <hongjiu.lu@intel.com>
757
758 * i386-opc.h (HLEPrefixNone): New.
759 (HLEPrefixLock): Likewise.
760 (HLEPrefixAny): Likewise.
761 (HLEPrefixRelease): Likewise.
762
42164a71
L		 7632012-02-08 H.J. Lu <hongjiu.lu@intel.com>
764
765 * i386-dis.c (HLE_Fixup1): New.
766 (HLE_Fixup2): Likewise.
767 (HLE_Fixup3): Likewise.
768 (Ebh1): Likewise.
769 (Evh1): Likewise.
770 (Ebh2): Likewise.
771 (Evh2): Likewise.
772 (Ebh3): Likewise.
773 (Evh3): Likewise.
774 (MOD_C6_REG_7): Likewise.
775 (MOD_C7_REG_7): Likewise.
776 (RM_C6_REG_7): Likewise.
777 (RM_C7_REG_7): Likewise.
778 (XACQUIRE_PREFIX): Likewise.
779 (XRELEASE_PREFIX): Likewise.
780 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
781 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
782 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
783 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
784 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
785 MOD_C6_REG_7 and MOD_C7_REG_7.
786 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
787 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
788 xtest.
789 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
790 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
791
792 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
793 CPU_RTM_FLAGS.
794 (cpu_flags): Add CpuHLE and CpuRTM.
795 (opcode_modifiers): Add HLEPrefixOk.
796
797 * i386-opc.h (CpuHLE): New.
798 (CpuRTM): Likewise.
799 (HLEPrefixOk): Likewise.
800 (i386_cpu_flags): Add cpuhle and cpurtm.
801 (i386_opcode_modifier): Add hleprefixok.
802
803 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
804 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
805 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
806 operand. Add xacquire, xrelease, xabort, xbegin, xend and
807 xtest.
808 * i386-init.h: Regenerated.
809 * i386-tbl.h: Likewise.
810
21abe33a
DD		 8112012-01-24 DJ Delorie <dj@redhat.com>
812
813 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
814 * rl78-decode.c: Regenerate.
815
e20cc039
AM		 8162012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
817
818 PR binutils/10173
819 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
820
e143d25c
AS		 8212012-01-17 Andreas Schwab <schwab@linux-m68k.org>
822
823 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
824 register and move them after pmove with PSR/PCSR register.
825
8729a6f6
L		 8262012-01-13 H.J. Lu <hongjiu.lu@intel.com>
827
828 * i386-dis.c (mod_table): Add vmfunc.
829
830 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
831 (cpu_flags): CpuVMFUNC.
832
833 * i386-opc.h (CpuVMFUNC): New.
834 (i386_cpu_flags): Add cpuvmfunc.
835
836 * i386-opc.tbl: Add vmfunc.
837 * i386-init.h: Regenerated.
838 * i386-tbl.h: Likewise.
5011093d 839
23e1d329 840For older changes see ChangeLog-2011
252b5132
RH		 841\f
842Local Variables:
2f6d2f85
NC		 843mode: change-log
844left-margin: 8
845fill-column: 74
252b5132
RH		 846version-control: never
847End:
GDB Binutils - Deliverables
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