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Regenerate frv-dis.c in order to fix a compile time warning.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5a84f3e0
NC		 12005-02-11 Nick Clifton <nickc@redhat.com>
2
3 * frv-dis.c: Regenerate.
4
0a40490e
JB		 52005-02-07 Jim Blandy <jimb@redhat.com>
6
7 * Makefile.am (CGEN): Load guile.scm before calling the main
8 application script.
9 * Makefile.in: Regenerated.
10 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
11 Simply pass the cgen-opc.scm path to ${cgen} as its first
12 argument; ${cgen} itself now contains the '-s', or whatever is
13 appropriate for the Scheme being used.
14
c46f8c51
AC		 152005-01-31 Andrew Cagney <cagney@gnu.org>
16
17 * configure: Regenerate to track ../gettext.m4.
18
60b9a617
JB		 192005-01-31 Jan Beulich <jbeulich@novell.com>
20
21 * ia64-gen.c (NELEMS): Define.
22 (shrink): Generate alias with missing second predicate register when
23 opcode has two outputs and these are both predicates.
24 * ia64-opc-i.c (FULL17): Define.
25 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
26 here to generate output template.
27 (TBITCM, TNATCM): Undefine after use.
28 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
29 first input. Add ld16 aliases without ar.csd as second output. Add
30 st16 aliases without ar.csd as second input. Add cmpxchg aliases
31 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
32 ar.ccv as third/fourth inputs. Consolidate through...
33 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
34 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
35 * ia64-asmtab.c: Regenerate.
36
a53bf506
AC		 372005-01-27 Andrew Cagney <cagney@gnu.org>
38
39 * configure: Regenerate to track ../gettext.m4 change.
40
90219bd0
AO		 412005-01-25 Alexandre Oliva <aoliva@redhat.com>
42
43 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
44 * frv-asm.c: Rebuilt.
45 * frv-desc.c: Rebuilt.
46 * frv-desc.h: Rebuilt.
47 * frv-dis.c: Rebuilt.
48 * frv-ibld.c: Rebuilt.
49 * frv-opc.c: Rebuilt.
50 * frv-opc.h: Rebuilt.
51
45181ed1
AC		 522005-01-24 Andrew Cagney <cagney@gnu.org>
53
54 * configure: Regenerate, ../gettext.m4 was updated.
55
9e836e3d
FF		 562005-01-21 Fred Fish <fnf@specifixinc.com>
57
58 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
59 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
60 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
61 * mips-dis.c: Ditto.
62
5e8cb021
AM		 632005-01-20 Alan Modra <amodra@bigpond.net.au>
64
65 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
66
986e18a5
FF		 672005-01-19 Fred Fish <fnf@specifixinc.com>
68
69 * mips-dis.c (no_aliases): New disassembly option flag.
70 (set_default_mips_dis_options): Init no_aliases to zero.
71 (parse_mips_dis_option): Handle no-aliases option.
72 (print_insn_mips): Ignore table entries that are aliases
73 if no_aliases is set.
74 (print_insn_mips16): Ditto.
75 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
76 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
77 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
78 * mips16-opc.c (mips16_opcodes): Ditto.
79
e38bc3b5
NC		 802005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
81
82 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
83 (inheritance diagram): Add missing edge.
84 (arch_sh1_up): Rename arch_sh_up to match external name to make life
85 easier for the testsuite.
86 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
87 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
88 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
89 arch_sh2a_or_sh4_up child.
90 (sh_table): Do renaming as above.
91 Correct comment for ldc.l for gas testsuite to read.
92 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
93 Correct comments for movy.w and movy.l for gas testsuite to read.
94 Correct comments for fmov.d and fmov.s for gas testsuite to read.
95
9df48ba9
L		 962005-01-12 H.J. Lu <hongjiu.lu@intel.com>
97
98 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
99
2033b4b9
L		 1002005-01-12 H.J. Lu <hongjiu.lu@intel.com>
101
102 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
103
0bcb06d2
AS		 1042005-01-10 Andreas Schwab <schwab@suse.de>
105
106 * disassemble.c (disassemble_init_for_target) <case
107 bfd_arch_ia64>: Set skip_zeroes to 16.
108 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
109
47add74d
TL		 1102004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
111
112 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
113
246f4c05
SS		 1142004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
115
116 * avr-dis.c: Prettyprint. Added printing of symbol names in all
117 memory references. Convert avr_operand() to C90 formatting.
118
0e1200e5
TL		 1192004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
120
121 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
122
89a649f7
TL		 1232004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
124
125 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
126 (no_op_insn): Initialize array with instructions that have no
127 operands.
128 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
129
6255809c
RE		 1302004-11-29 Richard Earnshaw <rearnsha@arm.com>
131
132 * arm-dis.c: Correct top-level comment.
133
2fbad815
RE		 1342004-11-27 Richard Earnshaw <rearnsha@arm.com>
135
136 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
137 architecuture defining the insn.
138 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 139 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
140 field.
2fbad815
RE		 141 Also include opcode/arm.h.
142 * Makefile.am (arm-dis.lo): Update dependency list.
143 * Makefile.in: Regenerate.
144
d81acc42
NC		 1452004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
146
147 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
148 reflect the change to the short immediate syntax.
149
ca4f2377
AM		 1502004-11-19 Alan Modra <amodra@bigpond.net.au>
151
5da8bf1b
AM		 152 * or32-opc.c (debug): Warning fix.
153 * po/POTFILES.in: Regenerate.
154
ca4f2377
AM		 155 * maxq-dis.c: Formatting.
156 (print_insn): Warning fix.
157
b7693d02
DJ		 1582004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
159
160 * arm-dis.c (WORD_ADDRESS): Define.
161 (print_insn): Use it. Correct big-endian end-of-section handling.
162
300dac7e
NC		 1632004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
164 Vineet Sharma <vineets@noida.hcltech.com>
165
166 * maxq-dis.c: New file.
167 * disassemble.c (ARCH_maxq): Define.
168 (disassembler): Add 'print_insn_maxq_little' for handling maxq
169 instructions..
170 * configure.in: Add case for bfd_maxq_arch.
171 * configure: Regenerate.
172 * Makefile.am: Add support for maxq-dis.c
173 * Makefile.in: Regenerate.
174 * aclocal.m4: Regenerate.
175
42048ee7
TL		 1762004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
177
178 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
179 mode.
180 * crx-dis.c: Likewise.
181
bd21e58e
HPN		 1822004-11-04 Hans-Peter Nilsson <hp@axis.com>
183
184 Generally, handle CRISv32.
185 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
186 (struct cris_disasm_data): New type.
187 (format_reg, format_hex, cris_constraint, print_flags)
188 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
189 callers changed.
190 (format_sup_reg, print_insn_crisv32_with_register_prefix)
191 (print_insn_crisv32_without_register_prefix)
192 (print_insn_crisv10_v32_with_register_prefix)
193 (print_insn_crisv10_v32_without_register_prefix)
194 (cris_parse_disassembler_options): New functions.
195 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
196 parameter. All callers changed.
197 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
198 failure.
199 (cris_constraint) <case 'Y', 'U'>: New cases.
200 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
201 for constraint 'n'.
202 (print_with_operands) <case 'Y'>: New case.
203 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
204 <case 'N', 'Y', 'Q'>: New cases.
205 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
206 (print_insn_cris_with_register_prefix)
207 (print_insn_cris_without_register_prefix): Call
208 cris_parse_disassembler_options.
209 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
210 for CRISv32 and the size of immediate operands. New v32-only
211 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
212 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
213 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
214 Change brp to be v3..v10.
215 (cris_support_regs): New vector.
216 (cris_opcodes): Update head comment. New format characters '[',
217 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
218 Add new opcodes for v32 and adjust existing opcodes to accommodate
219 differences to earlier variants.
220 (cris_cond15s): New vector.
221
9306ca4a
JB		 2222004-11-04 Jan Beulich <jbeulich@novell.com>
223
224 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
225 (indirEb): Remove.
226 (Mp): Use f_mode rather than none at all.
227 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
228 replaces what previously was x_mode; x_mode now means 128-bit SSE
229 operands.
230 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
231 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
232 pinsrw's second operand is Edqw.
233 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
234 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
235 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
236 mode when an operand size override is present or always suffixing.
237 More instructions will need to be added to this group.
238 (putop): Handle new macro chars 'C' (short/long suffix selector),
239 'I' (Intel mode override for following macro char), and 'J' (for
240 adding the 'l' prefix to far branches in AT&T mode). When an
241 alternative was specified in the template, honor macro character when
242 specified for Intel mode.
243 (OP_E): Handle new *_mode values. Correct pointer specifications for
244 memory operands. Consolidate output of index register.
245 (OP_G): Handle new *_mode values.
246 (OP_I): Handle const_1_mode.
247 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
248 respective opcode prefix bits have been consumed.
249 (OP_EM, OP_EX): Provide some default handling for generating pointer
250 specifications.
251
f39c96a9
TL		 2522004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
253
254 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
255 COP_INST macro.
256
812337be
TL		 2572004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
258
259 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
260 (getregliststring): Support HI/LO and user registers.
261 * crx-opc.c (crx_instruction): Update data structure according to the
262 rearrangement done in CRX opcode header file.
263 (crx_regtab): Likewise.
264 (crx_optab): Likewise.
265 (crx_instruction): Reorder load/stor instructions, remove unsupported
266 formats.
267 support new Co-Processor instruction 'cpi'.
268
4030fa5a
NC		 2692004-10-27 Nick Clifton <nickc@redhat.com>
270
271 * opcodes/iq2000-asm.c: Regenerate.
272 * opcodes/iq2000-desc.c: Regenerate.
273 * opcodes/iq2000-desc.h: Regenerate.
274 * opcodes/iq2000-dis.c: Regenerate.
275 * opcodes/iq2000-ibld.c: Regenerate.
276 * opcodes/iq2000-opc.c: Regenerate.
277 * opcodes/iq2000-opc.h: Regenerate.
278
fc3d45e8
TL		 2792004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
280
281 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
282 us4, us5 (respectively).
283 Remove unsupported 'popa' instruction.
284 Reverse operands order in store co-processor instructions.
285
3c55da70
AM		 2862004-10-15 Alan Modra <amodra@bigpond.net.au>
287
288 * Makefile.am: Run "make dep-am"
289 * Makefile.in: Regenerate.
290
7fa3d080
BW		 2912004-10-12 Bob Wilson <bob.wilson@acm.org>
292
293 * xtensa-dis.c: Use ISO C90 formatting.
294
e612bb4d
AM		 2952004-10-09 Alan Modra <amodra@bigpond.net.au>
296
297 * ppc-opc.c: Revert 2004-09-09 change.
298
43cd72b9
BW		 2992004-10-07 Bob Wilson <bob.wilson@acm.org>
300
301 * xtensa-dis.c (state_names): Delete.
302 (fetch_data): Use xtensa_isa_maxlength.
303 (print_xtensa_operand): Replace operand parameter with opcode/operand
304 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
305 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
306 instruction bundles. Use xmalloc instead of malloc.
307
bbac1f2a
NC		 3082004-10-07 David Gibson <david@gibson.dropbear.id.au>
309
310 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
311 initializers.
312
48c9f030
NC		 3132004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
314
315 * crx-opc.c (crx_instruction): Support Co-processor insns.
316 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
317 (getregliststring): Change function to use the above enum.
318 (print_arg): Handle CO-Processor insns.
319 (crx_cinvs): Add 'b' option to invalidate the branch-target
320 cache.
321
12c64a4e
AH		 3222004-10-06 Aldy Hernandez <aldyh@redhat.com>
323
324 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
325 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
326 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
327 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
328 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
329
14127cc4
NC		 3302004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
331
332 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
333 rather than add it.
334
0dd132b6
NC		 3352004-09-30 Paul Brook <paul@codesourcery.com>
336
337 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
338 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
339
3f85e526
L		 3402004-09-17 H.J. Lu <hongjiu.lu@intel.com>
341
342 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
343 (CONFIG_STATUS_DEPENDENCIES): New.
344 (Makefile): Removed.
345 (config.status): Likewise.
346 * Makefile.in: Regenerated.
347
8ae85421
AM		 3482004-09-17 Alan Modra <amodra@bigpond.net.au>
349
350 * Makefile.am: Run "make dep-am".
351 * Makefile.in: Regenerate.
352 * aclocal.m4: Regenerate.
353 * configure: Regenerate.
354 * po/POTFILES.in: Regenerate.
355 * po/opcodes.pot: Regenerate.
356
24443139
AS		 3572004-09-11 Andreas Schwab <schwab@suse.de>
358
359 * configure: Rebuild.
360
2a309db0
AM		 3612004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
362
363 * ppc-opc.c (L): Make this field not optional.
364
42851540
NC		 3652004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
366
367 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
368 Fix parameter to 'm[t|f]csr' insns.
369
979273e3
NN		 3702004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
371
372 * configure.in: Autoupdate to autoconf 2.59.
373 * aclocal.m4: Rebuild with aclocal 1.4p6.
374 * configure: Rebuild with autoconf 2.59.
375 * Makefile.in: Rebuild with automake 1.4p6 (picking up
376 bfd changes for autoconf 2.59 on the way).
377 * config.in: Rebuild with autoheader 2.59.
378
ac28a1cb
RS		 3792004-08-27 Richard Sandiford <rsandifo@redhat.com>
380
381 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
382
30d1c836
ML		 3832004-07-30 Michal Ludvig <mludvig@suse.cz>
384
385 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
386 (GRPPADLCK2): New define.
387 (twobyte_has_modrm): True for 0xA6.
388 (grps): GRPPADLCK2 for opcode 0xA6.
389
0b0ac059
AO		 3902004-07-29 Alexandre Oliva <aoliva@redhat.com>
391
392 Introduce SH2a support.
393 * sh-opc.h (arch_sh2a_base): Renumber.
394 (arch_sh2a_nofpu_base): Remove.
395 (arch_sh_base_mask): Adjust.
396 (arch_opann_mask): New.
397 (arch_sh2a, arch_sh2a_nofpu): Adjust.
398 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
399 (sh_table): Adjust whitespace.
400 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
401 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
402 instruction list throughout.
403 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
404 of arch_sh2a in instruction list throughout.
405 (arch_sh2e_up): Accomodate above changes.
406 (arch_sh2_up): Ditto.
407 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
408 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
409 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
410 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
411 * sh-opc.h (arch_sh2a_nofpu): New.
412 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
413 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
414 instruction.
415 2004-01-20 DJ Delorie <dj@redhat.com>
416 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
417 2003-12-29 DJ Delorie <dj@redhat.com>
418 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
419 sh_opcode_info, sh_table): Add sh2a support.
420 (arch_op32): New, to tag 32-bit opcodes.
421 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
422 2003-12-02 Michael Snyder <msnyder@redhat.com>
423 * sh-opc.h (arch_sh2a): Add.
424 * sh-dis.c (arch_sh2a): Handle.
425 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
426
670ec21d
NC		 4272004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
428
429 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
430
ed049af3
NC		 4312004-07-22 Nick Clifton <nickc@redhat.com>
432
433 PR/280
434 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
435 insns - this is done by objdump itself.
436 * h8500-dis.c (print_insn_h8500): Likewise.
437
20f0a1fc
NC		 4382004-07-21 Jan Beulich <jbeulich@novell.com>
439
440 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
441 regardless of address size prefix in effect.
442 (ptr_reg): Size or address registers does not depend on rex64, but
443 on the presence of an address size override.
444 (OP_MMX): Use rex.x only for xmm registers.
445 (OP_EM): Use rex.z only for xmm registers.
446
6f14957b
MR		 4472004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
448
449 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
450 move/branch operations to the bottom so that VR5400 multimedia
451 instructions take precedence in disassembly.
452
1586d91e
MR		 4532004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
454
455 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
456 ISA-specific "break" encoding.
457
982de27a
NC		 4582004-07-13 Elvis Chiang <elvisfb@gmail.com>
459
460 * arm-opc.h: Fix typo in comment.
461
4300ab10
AS		 4622004-07-11 Andreas Schwab <schwab@suse.de>
463
464 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
465
8577e690
AS		 4662004-07-09 Andreas Schwab <schwab@suse.de>
467
468 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
469
1fe1f39c
NC		 4702004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
471
472 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
473 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
474 (crx-dis.lo): New target.
475 (crx-opc.lo): Likewise.
476 * Makefile.in: Regenerate.
477 * configure.in: Handle bfd_crx_arch.
478 * configure: Regenerate.
479 * crx-dis.c: New file.
480 * crx-opc.c: New file.
481 * disassemble.c (ARCH_crx): Define.
482 (disassembler): Handle ARCH_crx.
483
7a33b495
JW		 4842004-06-29 James E Wilson <wilson@specifixinc.com>
485
486 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
487 * ia64-asmtab.c: Regnerate.
488
98e69875
AM		 4892004-06-28 Alan Modra <amodra@bigpond.net.au>
490
491 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
492 (extract_fxm): Don't test dialect.
493 (XFXFXM_MASK): Include the power4 bit.
494 (XFXM): Add p4 param.
495 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
496
a53b85e2
AO		 4972004-06-27 Alexandre Oliva <aoliva@redhat.com>
498
499 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
500 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
501
d0618d1c
AM		 5022004-06-26 Alan Modra <amodra@bigpond.net.au>
503
504 * ppc-opc.c (BH, XLBH_MASK): Define.
505 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
506
1d9f512f
AM		 5072004-06-24 Alan Modra <amodra@bigpond.net.au>
508
509 * i386-dis.c (x_mode): Comment.
510 (two_source_ops): File scope.
511 (float_mem): Correct fisttpll and fistpll.
512 (float_mem_mode): New table.
513 (dofloat): Use it.
514 (OP_E): Correct intel mode PTR output.
515 (ptr_reg): Use open_char and close_char.
516 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
517 operands. Set two_source_ops.
518
52886d70
AM		 5192004-06-15 Alan Modra <amodra@bigpond.net.au>
520
521 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
522 instead of _raw_size.
523
bad9ceea
JJ		 5242004-06-08 Jakub Jelinek <jakub@redhat.com>
525
526 * ia64-gen.c (in_iclass): Handle more postinc st
527 and ld variants.
528 * ia64-asmtab.c: Rebuilt.
529
0451f5df
MS		 5302004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
531
532 * s390-opc.txt: Correct architecture mask for some opcodes.
533 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
534 in the esa mode as well.
535
f6f9408f
JR		 5362004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
537
538 * sh-dis.c (target_arch): Make unsigned.
539 (print_insn_sh): Replace (most of) switch with a call to
540 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
541 * sh-opc.h: Redefine architecture flags values.
542 Add sh3-nommu architecture.
543 Reorganise <arch>_up macros so they make more visual sense.
544 (SH_MERGE_ARCH_SET): Define new macro.
545 (SH_VALID_BASE_ARCH_SET): Likewise.
546 (SH_VALID_MMU_ARCH_SET): Likewise.
547 (SH_VALID_CO_ARCH_SET): Likewise.
548 (SH_VALID_ARCH_SET): Likewise.
549 (SH_MERGE_ARCH_SET_VALID): Likewise.
550 (SH_ARCH_SET_HAS_FPU): Likewise.
551 (SH_ARCH_SET_HAS_DSP): Likewise.
552 (SH_ARCH_UNKNOWN_ARCH): Likewise.
553 (sh_get_arch_from_bfd_mach): Add prototype.
554 (sh_get_arch_up_from_bfd_mach): Likewise.
555 (sh_get_bfd_mach_from_arch_set): Likewise.
556 (sh_merge_bfd_arc): Likewise.
557
be8c092b
NC		 5582004-05-24 Peter Barada <peter@the-baradas.com>
559
560 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
561 into new match_insn_m68k function. Loop over canidate
562 matches and select first that completely matches.
563 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
564 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
565 to verify addressing for MAC/EMAC.
566 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
567 reigster halves since 'fpu' and 'spl' look misleading.
568 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
569 * m68k-opc.c: Rearragne mac/emac cases to use longest for
570 first, tighten up match masks.
571 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
572 'size' from special case code in print_insn_m68k to
573 determine decode size of insns.
574
a30e9cc4
AM		 5752004-05-19 Alan Modra <amodra@bigpond.net.au>
576
577 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
578 well as when -mpower4.
579
9598fbe5
NC		 5802004-05-13 Nick Clifton <nickc@redhat.com>
581
582 * po/fr.po: Updated French translation.
583
6b6e92f4
NC		 5842004-05-05 Peter Barada <peter@the-baradas.com>
585
586 * m68k-dis.c(print_insn_m68k): Add new chips, use core
587 variants in arch_mask. Only set m68881/68851 for 68k chips.
588 * m68k-op.c: Switch from ColdFire chips to core variants.
589
a404d431
AM		 5902004-05-05 Alan Modra <amodra@bigpond.net.au>
591
a30e9cc4 592 PR 147.
a404d431
AM		 593 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
594
f3806e43
BE		 5952004-04-29 Ben Elliston <bje@au.ibm.com>
596
520ceea4
BE		 597 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
598 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 599
1f1799d5
KK		 6002004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
601
602 * sh-dis.c (print_insn_sh): Print the value in constant pool
603 as a symbol if it looks like a symbol.
604
fd99574b
NC		 6052004-04-22 Peter Barada <peter@the-baradas.com>
606
607 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
608 appropriate ColdFire architectures.
609 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
610 mask addressing.
611 Add EMAC instructions, fix MAC instructions. Remove
612 macmw/macml/msacmw/msacml instructions since mask addressing now
613 supported.
614
b4781d44
JJ		 6152004-04-20 Jakub Jelinek <jakub@redhat.com>
616
617 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
618 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
619 suffix. Use fmov*x macros, create all 3 fpsize variants in one
620 macro. Adjust all users.
621
91809fda
NC		 6222004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
623
624 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
625 separately.
626
f4453dfa
NC		 6272004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
628
629 * m32r-asm.c: Regenerate.
630
9b0de91a
SS		 6312004-03-29 Stan Shebs <shebs@apple.com>
632
633 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
634 used.
635
e20c0b3d
AM		 6362004-03-19 Alan Modra <amodra@bigpond.net.au>
637
638 * aclocal.m4: Regenerate.
639 * config.in: Regenerate.
640 * configure: Regenerate.
641 * po/POTFILES.in: Regenerate.
642 * po/opcodes.pot: Regenerate.
643
fdd12ef3
AM		 6442004-03-16 Alan Modra <amodra@bigpond.net.au>
645
646 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
647 PPC_OPERANDS_GPR_0.
648 * ppc-opc.c (RA0): Define.
649 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
650 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 651 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 652
2dc111b3 6532004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 654
655 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 656
7bfeee7b
AM		 6572004-03-15 Alan Modra <amodra@bigpond.net.au>
658
659 * sparc-dis.c (print_insn_sparc): Update getword prototype.
660
7ffdda93
ML		 6612004-03-12 Michal Ludvig <mludvig@suse.cz>
662
663 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 664 (grps): Delete GRPPLOCK entry.
7ffdda93 665
cc0ec051
AM		 6662004-03-12 Alan Modra <amodra@bigpond.net.au>
667
668 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
669 (M, Mp): Use OP_M.
670 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
671 (GRPPADLCK): Define.
672 (dis386): Use NOP_Fixup on "nop".
673 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
674 (twobyte_has_modrm): Set for 0xa7.
675 (padlock_table): Delete. Move to..
676 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
677 and clflush.
678 (print_insn): Revert PADLOCK_SPECIAL code.
679 (OP_E): Delete sfence, lfence, mfence checks.
680
4fd61dcb
JJ		 6812004-03-12 Jakub Jelinek <jakub@redhat.com>
682
683 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
684 (INVLPG_Fixup): New function.
685 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
686
0f10071e
ML		 6872004-03-12 Michal Ludvig <mludvig@suse.cz>
688
689 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
690 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
691 (padlock_table): New struct with PadLock instructions.
692 (print_insn): Handle PADLOCK_SPECIAL.
693
c02908d2
AM		 6942004-03-12 Alan Modra <amodra@bigpond.net.au>
695
696 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
697 (OP_E): Twiddle clflush to sfence here.
698
d5bb7600
NC		 6992004-03-08 Nick Clifton <nickc@redhat.com>
700
701 * po/de.po: Updated German translation.
702
ae51a426
JR		 7032003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
704
705 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
706 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
707 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
708 accordingly.
709
676a64f4
RS		 7102004-03-01 Richard Sandiford <rsandifo@redhat.com>
711
712 * frv-asm.c: Regenerate.
713 * frv-desc.c: Regenerate.
714 * frv-desc.h: Regenerate.
715 * frv-dis.c: Regenerate.
716 * frv-ibld.c: Regenerate.
717 * frv-opc.c: Regenerate.
718 * frv-opc.h: Regenerate.
719
c7a48b9a
RS		 7202004-03-01 Richard Sandiford <rsandifo@redhat.com>
721
722 * frv-desc.c, frv-opc.c: Regenerate.
723
8ae0baa2
RS		 7242004-03-01 Richard Sandiford <rsandifo@redhat.com>
725
726 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
727
ce11586c
JR		 7282004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
729
730 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
731 Also correct mistake in the comment.
732
6a5709a5
JR		 7332004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
734
735 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
736 ensure that double registers have even numbers.
737 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
738 that reserved instruction 0xfffd does not decode the same
739 as 0xfdfd (ftrv).
740 * sh-opc.h: Add REG_N_D nibble type and use it whereever
741 REG_N refers to a double register.
742 Add REG_N_B01 nibble type and use it instead of REG_NM
743 in ftrv.
744 Adjust the bit patterns in a few comments.
745
e5d2b64f 7462004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 747
748 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 749
1f04b05f
AH		 7502004-02-20 Aldy Hernandez <aldyh@redhat.com>
751
752 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
753
2f3b8700
AH		 7542004-02-20 Aldy Hernandez <aldyh@redhat.com>
755
756 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
757
f0b26da6 7582004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 759
760 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
761 mtivor32, mtivor33, mtivor34.
f0b26da6 762
23d59c56 7632004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 764
765 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 766
34920d91
NC		 7672004-02-10 Petko Manolov <petkan@nucleusys.com>
768
769 * arm-opc.h Maverick accumulator register opcode fixes.
770
44d86481
BE		 7712004-02-13 Ben Elliston <bje@wasabisystems.com>
772
773 * m32r-dis.c: Regenerate.
774
17707c23
MS		 7752004-01-27 Michael Snyder <msnyder@redhat.com>
776
777 * sh-opc.h (sh_table): "fsrra", not "fssra".
778
fe3a9bc4
NC		 7792004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
780
781 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
782 contraints.
783
ff24f124
JJ		 7842004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
785
786 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
787
a02a862a
AM		 7882004-01-19 Alan Modra <amodra@bigpond.net.au>
789
790 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
791 1. Don't print scale factor on AT&T mode when index missing.
792
d164ea7f
AO		 7932004-01-16 Alexandre Oliva <aoliva@redhat.com>
794
795 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
796 when loaded into XR registers.
797
cb10e79a
RS		 7982004-01-14 Richard Sandiford <rsandifo@redhat.com>
799
800 * frv-desc.h: Regenerate.
801 * frv-desc.c: Regenerate.
802 * frv-opc.c: Regenerate.
803
f532f3fa
MS		 8042004-01-13 Michael Snyder <msnyder@redhat.com>
805
806 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
807
e45d0630
PB		 8082004-01-09 Paul Brook <paul@codesourcery.com>
809
810 * arm-opc.h (arm_opcodes): Move generic mcrr after known
811 specific opcodes.
812
3ba7a1aa
DJ		 8132004-01-07 Daniel Jacobowitz <drow@mvista.com>
814
815 * Makefile.am (libopcodes_la_DEPENDENCIES)
816 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
817 comment about the problem.
818 * Makefile.in: Regenerate.
819
ba2d3f07
AO		 8202004-01-06 Alexandre Oliva <aoliva@redhat.com>
821
822 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
823 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
824 cut&paste errors in shifting/truncating numerical operands.
825 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
826 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
827 (parse_uslo16): Likewise.
828 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
829 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
830 (parse_s12): Likewise.
831 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
832 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
833 (parse_uslo16): Likewise.
834 (parse_uhi16): Parse gothi and gotfuncdeschi.
835 (parse_d12): Parse got12 and gotfuncdesc12.
836 (parse_s12): Likewise.
837
3ab48931
NC		 8382004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
839
840 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
841 instruction which looks similar to an 'rla' instruction.
a0bd404e 842
c9e214e5 843For older changes see ChangeLog-0203
252b5132
RH		 844\f
845Local Variables:
2f6d2f85
NC		 846mode: change-log
847left-margin: 8
848fill-column: 74
252b5132
RH		 849version-control: never
850End:
GDB Binutils - Deliverables
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