projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
include/opcode/
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5c324c16
RS		 12013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
4 MDMX-like instructions.
5 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
6 printing "Q" operands for INSN_5400 instructions.
7
23e69e47
RS		 82013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
9
10 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
11 "+S" for "cins".
12 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
13 Combine cases.
14
27c5c572
RS		 152013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
16
17 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
18 "jalx".
19 * mips16-opc.c (mips16_opcodes): Likewise.
20 * micromips-opc.c (micromips_opcodes): Likewise.
21 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
22 (print_insn_mips16): Handle "+i".
23 (print_insn_micromips): Likewise. Conditionally preserve the
24 ISA bit for "a" but not for "+i".
25
e76ff5ab
RS		 262013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
27
28 * micromips-opc.c (WR_mhi): Rename to..
29 (WR_mh): ...this.
30 (micromips_opcodes): Update "movep" entry accordingly. Replace
31 "mh,mi" with "mh".
32 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
33 (micromips_to_32_reg_h_map1): ...this.
34 (micromips_to_32_reg_i_map): Rename to...
35 (micromips_to_32_reg_h_map2): ...this.
36 (print_micromips_insn): Remove "mi" case. Print both registers
37 in the pair for "mh".
38
fa7616a4
RS		 392013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
40
41 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
42 * micromips-opc.c (micromips_opcodes): Likewise.
43 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
44 and "+T" handling. Check for a "0" suffix when deciding whether to
45 use coprocessor 0 names. In that case, also check for ",H" selectors.
46
fb798c50
AK		 472013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
48
49 * s390-opc.c (J12_12, J24_24): New macros.
50 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
51 (MASK_MII_UPI): Rename to MASK_MII_UPP.
52 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
53
58ae08f2
AM		 542013-07-04 Alan Modra <amodra@gmail.com>
55
56 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
57
b5e04c2b
NC		 582013-06-26 Nick Clifton <nickc@redhat.com>
59
60 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
61 field when checking for type 2 nop.
62 * rx-decode.c: Regenerate.
63
833794fc
MR		 642013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
65
66 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
67 and "movep" macros.
68
1bbce132
MR		 692013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
70
71 * mips-dis.c (is_mips16_plt_tail): New function.
72 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
73 word.
74 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
75
34c911a4
NC		 762013-06-21 DJ Delorie <dj@redhat.com>
77
78 * msp430-decode.opc: New.
79 * msp430-decode.c: New/generated.
80 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
81 (MAINTAINER_CLEANFILES): Likewise.
82 Add rule to build msp430-decode.c frommsp430decode.opc
83 using the opc2c program.
84 * Makefile.in: Regenerate.
85 * configure.in: Add msp430-decode.lo to msp430 architecture files.
86 * configure: Regenerate.
87
b9eead84
YZ		 882013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
89
90 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
91 (SYMTAB_AVAILABLE): Removed.
92 (#include "elf/aarch64.h): Ditto.
93
7f3c4072
CM		 942013-06-17 Catherine Moore <clm@codesourcery.com>
95 Maciej W. Rozycki <macro@codesourcery.com>
96 Chao-Ying Fu <fu@mips.com>
97
98 * micromips-opc.c (EVA): Define.
99 (TLBINV): Define.
100 (micromips_opcodes): Add EVA opcodes.
101 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
102 (print_insn_args): Handle EVA offsets.
103 (print_insn_micromips): Likewise.
104 * mips-opc.c (EVA): Define.
105 (TLBINV): Define.
106 (mips_builtin_opcodes): Add EVA opcodes.
107
de40ceb6
AM		 1082013-06-17 Alan Modra <amodra@gmail.com>
109
110 * Makefile.am (mips-opc.lo): Add rules to create automatic
111 dependency files. Pass archdefs.
112 (micromips-opc.lo, mips16-opc.lo): Likewise.
113 * Makefile.in: Regenerate.
114
3531d549
DD		 1152013-06-14 DJ Delorie <dj@redhat.com>
116
117 * rx-decode.opc (rx_decode_opcode): Bit operations on
118 registers are 32-bit operations, not 8-bit operations.
119 * rx-decode.c: Regenerate.
120
ba92f7fb
CF		 1212013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
122
123 * micromips-opc.c (IVIRT): New define.
124 (IVIRT64): New define.
125 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
126 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
127
128 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
129 dmtgc0 to print cp0 names.
130
9daf7bab
SL		 1312013-06-09 Sandra Loosemore <sandra@codesourcery.com>
132
133 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
134 argument.
135
d301a56b
RS		 1362013-06-08 Catherine Moore <clm@codesourcery.com>
137 Richard Sandiford <rdsandiford@googlemail.com>
138
139 * micromips-opc.c (D32, D33, MC): Update definitions.
140 (micromips_opcodes): Initialize ase field.
141 * mips-dis.c (mips_arch_choice): Add ase field.
142 (mips_arch_choices): Initialize ase field.
143 (set_default_mips_dis_options): Declare and setup mips_ase.
144 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
145 MT32, MC): Update definitions.
146 (mips_builtin_opcodes): Initialize ase field.
147
a3dcb6c5
RS		 1482013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
149
150 * s390-opc.txt (flogr): Require a register pair destination.
151
6cf1d90c
AK		 1522013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
153
154 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
155 instruction format.
156
c77c0862
RS		 1572013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
158
159 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
160
c0637f3a
PB		 1612013-05-20 Peter Bergner <bergner@vnet.ibm.com>
162
163 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
164 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
165 XLS_MASK, PPCVSX2): New defines.
166 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
167 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
168 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
169 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
170 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
171 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
172 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
173 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
174 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
175 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
176 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
177 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
178 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
179 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
180 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
181 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
182 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
183 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
184 <lxvx, stxvx>: New extended mnemonics.
185
4934fdaf
AM		 1862013-05-17 Alan Modra <amodra@gmail.com>
187
188 * ia64-raw.tbl: Replace non-ASCII char.
189 * ia64-waw.tbl: Likewise.
190 * ia64-asmtab.c: Regenerate.
191
6091d651
SE		 1922013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
193
194 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
195 * i386-init.h: Regenerated.
196
d2865ed3
YZ		 1972013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
198
199 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
200 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
201 check from [0, 255] to [-128, 255].
202
b015e599
AP		 2032013-05-09 Andrew Pinski <apinski@cavium.com>
204
205 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
206 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
207 (parse_mips_dis_option): Handle the virt option.
208 (print_insn_args): Handle "+J".
209 (print_mips_disassembler_options): Print out message about virt64.
210 * mips-opc.c (IVIRT): New define.
211 (IVIRT64): New define.
212 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
213 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
214 Move rfe to the bottom as it conflicts with tlbgp.
215
9f0682fe
AM		 2162013-05-09 Alan Modra <amodra@gmail.com>
217
218 * ppc-opc.c (extract_vlesi): Properly sign extend.
219 (extract_vlensi): Likewise. Comment reason for setting invalid.
220
13761a11
NC		 2212013-05-02 Nick Clifton <nickc@redhat.com>
222
223 * msp430-dis.c: Add support for MSP430X instructions.
224
e3031850
SL		 2252013-04-24 Sandra Loosemore <sandra@codesourcery.com>
226
227 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
228 to "eccinj".
229
17310e56
NC		 2302013-04-17 Wei-chen Wang <cole945@gmail.com>
231
232 PR binutils/15369
233 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
234 of CGEN_CPU_ENDIAN.
235 (hash_insns_list): Likewise.
236
731df338
JK		 2372013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
238
239 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
240 warning workaround.
241
5f77db52
JB		 2422013-04-08 Jan Beulich <jbeulich@suse.com>
243
244 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
245 * i386-tbl.h: Re-generate.
246
0afd1215
DM		 2472013-04-06 David S. Miller <davem@davemloft.net>
248
249 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
250 of an opcode, prefer the one with F_PREFERRED set.
251 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
252 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
253 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
254 mark existing mnenomics as aliases. Add "cc" suffix to edge
255 instructions generating condition codes, mark existing mnenomics
256 as aliases. Add "fp" prefix to VIS compare instructions, mark
257 existing mnenomics as aliases.
258
41702d50
NC		 2592013-04-03 Nick Clifton <nickc@redhat.com>
260
261 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
262 destination address by subtracting the operand from the current
263 address.
264 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
265 a positive value in the insn.
266 (extract_u16_loop): Do not negate the returned value.
267 (D16_LOOP): Add V850_INVERSE_PCREL flag.
268
269 (ceilf.sw): Remove duplicate entry.
270 (cvtf.hs): New entry.
271 (cvtf.sh): Likewise.
272 (fmaf.s): Likewise.
273 (fmsf.s): Likewise.
274 (fnmaf.s): Likewise.
275 (fnmsf.s): Likewise.
276 (maddf.s): Restrict to E3V5 architectures.
277 (msubf.s): Likewise.
278 (nmaddf.s): Likewise.
279 (nmsubf.s): Likewise.
280
55cf16e1
L		 2812013-03-27 H.J. Lu <hongjiu.lu@intel.com>
282
283 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
284 check address mode.
285 (print_insn): Pass sizeflag to get_sib.
286
51dcdd4d
NC		 2872013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
288
289 PR binutils/15068
290 * tic6x-dis.c: Add support for displaying 16-bit insns.
291
795b8e6b
NC		 2922013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
293
294 PR gas/15095
295 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
296 individual msb and lsb halves in src1 & src2 fields. Discard the
297 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
298 follow what Ti SDK does in that case as any value in the src1
299 field yields the same output with SDK disassembler.
300
314d60dd
ME		 3012013-03-12 Michael Eager <eager@eagercon.com>
302
795b8e6b 303 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 304
dad60f8e
SL		 3052013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
306
307 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
308
f5cb796a
SL		 3092013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
310
311 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
312
21fde85c
SL		 3132013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
314
315 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
316
dd5181d5
KT		 3172013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
318
319 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
320 (thumb32_opcodes): Likewise.
321 (print_insn_thumb32): Handle 'S' control char.
322
87a8d6cb
NC		 3232013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
324
325 * lm32-desc.c: Regenerate.
326
99dce992
L		 3272013-03-01 H.J. Lu <hongjiu.lu@intel.com>
328
329 * i386-reg.tbl (riz): Add RegRex64.
330 * i386-tbl.h: Regenerated.
331
e60bb1dd
YZ		 3322013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
333
334 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
335 (aarch64_feature_crc): New static.
336 (CRC): New macro.
337 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
338 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
339 * aarch64-asm-2.c: Re-generate.
340 * aarch64-dis-2.c: Ditto.
341 * aarch64-opc-2.c: Ditto.
342
c7570fcd
AM		 3432013-02-27 Alan Modra <amodra@gmail.com>
344
345 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
346 * rl78-decode.c: Regenerate.
347
151fa98f
NC		 3482013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
349
350 * rl78-decode.opc: Fix encoding of DIVWU insn.
351 * rl78-decode.c: Regenerate.
352
5c111e37
L		 3532013-02-19 H.J. Lu <hongjiu.lu@intel.com>
354
355 PR gas/15159
356 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
357
358 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
359 (cpu_flags): Add CpuSMAP.
360
361 * i386-opc.h (CpuSMAP): New.
362 (i386_cpu_flags): Add cpusmap.
363
364 * i386-opc.tbl: Add clac and stac.
365
366 * i386-init.h: Regenerated.
367 * i386-tbl.h: Likewise.
368
9d1df426
NC		 3692013-02-15 Markos Chandras <markos.chandras@imgtec.com>
370
371 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
372 which also makes the disassembler output be in little
373 endian like it should be.
374
a1ccaec9
YZ		 3752013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
376
377 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
378 fields to NULL.
379 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
380
ef068ef4 3812013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 382
383 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
384 section disassembled.
385
6fe6ded9
RE		 3862013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
387
388 * arm-dis.c: Update strht pattern.
389
0aa27725
RS		 3902013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
391
392 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
393 single-float. Disable ll, lld, sc and scd for EE. Disable the
394 trunc.w.s macro for EE.
395
36591ba1
SL		 3962013-02-06 Sandra Loosemore <sandra@codesourcery.com>
397 Andrew Jenner <andrew@codesourcery.com>
398
399 Based on patches from Altera Corporation.
400
401 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
402 nios2-opc.c.
403 * Makefile.in: Regenerated.
404 * configure.in: Add case for bfd_nios2_arch.
405 * configure: Regenerated.
406 * disassemble.c (ARCH_nios2): Define.
407 (disassembler): Add case for bfd_arch_nios2.
408 * nios2-dis.c: New file.
409 * nios2-opc.c: New file.
410
545093a4
AM		 4112013-02-04 Alan Modra <amodra@gmail.com>
412
413 * po/POTFILES.in: Regenerate.
414 * rl78-decode.c: Regenerate.
415 * rx-decode.c: Regenerate.
416
e30181a5
YZ		 4172013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
418
419 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
420 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
421 * aarch64-asm.c (convert_xtl_to_shll): New function.
422 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
423 calling convert_xtl_to_shll.
424 * aarch64-dis.c (convert_shll_to_xtl): New function.
425 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
426 calling convert_shll_to_xtl.
427 * aarch64-gen.c: Update copyright year.
428 * aarch64-asm-2.c: Re-generate.
429 * aarch64-dis-2.c: Re-generate.
430 * aarch64-opc-2.c: Re-generate.
431
78c8d46c
NC		 4322013-01-24 Nick Clifton <nickc@redhat.com>
433
434 * v850-dis.c: Add support for e3v5 architecture.
435 * v850-opc.c: Likewise.
436
f5555712
YZ		 4372013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
438
439 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
440 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
441 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 442 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 443 alignment check; change to call set_sft_amount_out_of_range_error
444 instead of set_imm_out_of_range_error.
445 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
446 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
447 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
448 SIMD_IMM_SFT.
449
2f81ff92
L		 4502013-01-16 H.J. Lu <hongjiu.lu@intel.com>
451
452 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
453
454 * i386-init.h: Regenerated.
455 * i386-tbl.h: Likewise.
456
dd42f060
NC		 4572013-01-15 Nick Clifton <nickc@redhat.com>
458
459 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
460 values.
461 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
462
a4533ed8
NC		 4632013-01-14 Will Newton <will.newton@imgtec.com>
464
465 * metag-dis.c (REG_WIDTH): Increase to 64.
466
5817ffd1
PB		 4672013-01-10 Peter Bergner <bergner@vnet.ibm.com>
468
469 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
470 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
471 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
472 (SH6): Update.
473 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
474 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
475 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
476 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
477
a3c62988
NC		 4782013-01-10 Will Newton <will.newton@imgtec.com>
479
480 * Makefile.am: Add Meta.
481 * configure.in: Add Meta.
482 * disassemble.c: Add Meta support.
483 * metag-dis.c: New file.
484 * Makefile.in: Regenerate.
485 * configure: Regenerate.
486
73335eae
NC		 4872013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
488
489 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
490 (match_opcode): Rename to cr16_match_opcode.
491
e407c74b
NC		 4922013-01-04 Juergen Urban <JuergenUrban@gmx.de>
493
494 * mips-dis.c: Add names for CP0 registers of r5900.
495 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
496 instructions sq and lq.
497 Add support for MIPS r5900 CPU.
498 Add support for 128 bit MMI (Multimedia Instructions).
499 Add support for EE instructions (Emotion Engine).
500 Disable unsupported floating point instructions (64 bit and
501 undefined compare operations).
502 Enable instructions of MIPS ISA IV which are supported by r5900.
503 Disable 64 bit co processor instructions.
504 Disable 64 bit multiplication and division instructions.
505 Disable instructions for co-processor 2 and 3, because these are
506 not supported (preparation for later VU0 support (Vector Unit)).
507 Disable cvt.w.s because this behaves like trunc.w.s and the
508 correct execution can't be ensured on r5900.
509 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
510 will confuse less developers and compilers.
511
a32c3ff8
NC		 5122013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
513
fb098a1e
YZ		 514 * aarch64-opc.c (aarch64_print_operand): Change to print
515 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
516 in comment.
517 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
518 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
519 OP_MOV_IMM_WIDE.
520
5212013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
522
523 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
524 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 525
62658407
L		 5262013-01-02 H.J. Lu <hongjiu.lu@intel.com>
527
528 * i386-gen.c (process_copyright): Update copyright year to 2013.
529
bab4becb 5302013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 531
bab4becb
NC		 532 * cr16-dis.c (match_opcode,make_instruction): Remove static
533 declaration.
534 (dwordU,wordU): Moved typedefs to opcode/cr16.h
535 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 536
bab4becb 537For older changes see ChangeLog-2012
252b5132 538\f
bab4becb 539Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 540
541Copying and distribution of this file, with or without modification,
542are permitted in any medium without royalty provided the copyright
543notice and this notice are preserved.
544
252b5132 545Local Variables:
2f6d2f85
NC		 546mode: change-log
547left-margin: 8
548fill-column: 74
252b5132
RH		 549version-control: never
550End:
GDB Binutils - Deliverables
This page took 0.634177 seconds and 4 git commands to generate.