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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5d4c71e1
BS		 12010-10-07 Bernd Schmidt <bernds@codesourcery.com>
2
3 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
4 in SPKERNEL instructions.
5
9ce00134
L		 62010-10-02 H.J. Lu <hongjiu.lu@intel.com>
7
8 PR binutils/12076
9 * i386-dis.c (RMAL): Remove duplicate.
10
e7390eec
PM		 112010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
12
13 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
14 to parse all 6 parameters.
15
d2ae9c84
PM		 162010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
17
18 * s390-mkopc.c (main): Change description array size to 80.
19 Add maximum length of 79 to description parsing.
20
3cac54d2
RW		 212010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
22
23 * configure: Regenerate.
24
d9aee5d7
AK		 252010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
26
27 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
28 (main): Recognize the new CPU string.
29 * s390-opc.c: Add new instruction formats and masks.
30 * s390-opc.txt: Add new z196 instructions.
31
02cbf767
AK		 322010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
33
34 * s390-dis.c (print_insn_s390): Pick instruction with most
35 specific mask.
36 * s390-opc.c: Add unused bits to the insn mask.
37 * s390-opc.txt: Reorder some instructions to prefer more recent
38 versions.
39
6844b2c2
MGD		 402010-09-27 Tejas Belagod <tejas.belagod@arm.com>
41
42 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
43 correction to unaligned PCs while printing comment.
44
90ec0d68
MGD		 452010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
46
47 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
48 (thumb32_opcodes): Likewise.
49 (banked_regname): New function.
50 (print_insn_arm): Add Virtualization Extensions support.
51 (print_insn_thumb32): Likewise.
52
eea54501
MGD		 532010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
54
55 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
56 ARM state.
57
f4c65163
MGD		 582010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
59
60 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
61 (thumb32_opcodes): Likewise.
62
60e5ef9f
MGD		 632010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
64
65 * arm-dis.c (arm_opcodes): Add support for pldw.
66 (thumb32_opcodes): Likewise.
67
7a360e83
MF		 682010-09-22 Robin Getz <robin.getz@analog.com>
69
70 * bfin-dis.c (fmtconst): Cast address to 32bits.
71
35fc57f3
MF		 722010-09-22 Mike Frysinger <vapier@gentoo.org>
73
74 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
75
219b747a
MF		 762010-09-22 Robin Getz <robin.getz@analog.com>
77
78 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
79 Reject P6/P7 to TESTSET.
80 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
81 SP onto the stack.
82 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
83 P/D fields match all the time.
84 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
85 are 0 for accumulator compares.
86 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
87 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
88 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
89 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
90 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
91 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
92 insns.
93 (decode_dagMODim_0): Verify br field for IREG ops.
94 (decode_LDST_0): Reject preg load into same preg.
95 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
96 (print_insn_bfin): Likewise.
97
775f1cf0
MF		 982010-09-22 Mike Frysinger <vapier@gentoo.org>
99
100 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
101
0b7691fd
MF		 1022010-09-22 Robin Getz <robin.getz@analog.com>
103
104 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
105
b2459327
MF		 1062010-09-22 Mike Frysinger <vapier@gentoo.org>
107
108 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
109
50e2162a
MF		 1102010-09-22 Robin Getz <robin.getz@analog.com>
111
112 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
113 register values greater than 8.
114 (IS_RESERVEDREG, allreg, mostreg): New helpers.
115 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
116 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
117 (decode_CC2dreg_0): Check valid CC register number.
118
a01eda85
MF		 1192010-09-22 Robin Getz <robin.getz@analog.com>
120
121 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
122
22215ae0
MF		 1232010-09-22 Robin Getz <robin.getz@analog.com>
124
125 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
126 (reg_names): Likewise.
127 (decode_statbits): Likewise; while reformatting to make manageable.
128
73a63ccf
MF		 1292010-09-22 Mike Frysinger <vapier@gentoo.org>
130
131 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
132 (decode_pseudoOChar_0): New function.
133 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
134
59a82d23
MF		 1352010-09-22 Robin Getz <robin.getz@analog.com>
136
137 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
138 LSHIFT instead of SHIFT.
139
528c6277
MF		 1402010-09-22 Mike Frysinger <vapier@gentoo.org>
141
142 * bfin-dis.c (constant_formats): Constify the whole structure.
143 (fmtconst): Add const to return value.
144 (reg_names): Mark const.
145 (decode_multfunc): Mark s0/s1 as const.
146 (decode_macfunc): Mark a/sop as const.
147
db472d6f
MGD		 1482010-09-17 Tejas Belagod <tejas.belagod@arm.com>
149
150 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
151
f6690563
MR		 1522010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
153
154 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
155 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
156
8901a3cd
PM		 1572010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
158
159 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
160 dlx_insn_type array.
161
d9e3625e
L		 1622010-08-31 H.J. Lu <hongjiu.lu@intel.com>
163
164 PR binutils/11960
165 * i386-dis.c (sIv): New.
166 (dis386): Replace Iq with sIv on "pushT".
167 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
168 (x86_64_table): Replace {T|}/{P|} with P.
169 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
170 (OP_sI): Update v_mode. Remove w_mode.
171
f383de66
NF		 1722010-08-27 Nathan Froyd <froydnj@codesourcery.com>
173
174 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
175 on E500 and E500MC.
176
1ab03f4b
L		 1772010-08-17 H.J. Lu <hongjiu.lu@intel.com>
178
179 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
180 prefetchw.
181
22109423
L		 1822010-08-06 Quentin Neill <quentin.neill@amd.com>
183
184 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
185 to processor flags for PENTIUMPRO processors and later.
186 * i386-opc.h (enum): Add CpuNop.
187 (i386_cpu_flags): Add cpunop bit.
188 * i386-opc.tbl: Change nop cpu_flags.
189 * i386-init.h: Regenerated.
190 * i386-tbl.h: Likewise.
191
b49dfb4a
L		 1922010-08-06 Quentin Neill <quentin.neill@amd.com>
193
194 * i386-opc.h (enum): Fix typos in comments.
195
6ca4eb77
AM		 1962010-08-06 Alan Modra <amodra@gmail.com>
197
198 * disassemble.c: Formatting.
199 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
200
92d4d42e
L		 2012010-08-05 H.J. Lu <hongjiu.lu@intel.com>
202
203 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
204 * i386-tbl.h: Regenerated.
205
b414985b
L		 2062010-08-05 H.J. Lu <hongjiu.lu@intel.com>
207
208 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
209
210 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
211 * i386-tbl.h: Regenerated.
212
f9c7014e
DD		 2132010-07-29 DJ Delorie <dj@redhat.com>
214
215 * rx-decode.opc (SRR): New.
216 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
217 r0,r0) and NOP3 (max r0,r0) special cases.
218 * rx-decode.c: Regenerate.
6ca4eb77 219
592a252b
L		 2202010-07-28 H.J. Lu <hongjiu.lu@intel.com>
221
222 * i386-dis.c: Add 0F to VEX opcode enums.
223
3cf79a01
DD		 2242010-07-27 DJ Delorie <dj@redhat.com>
225
226 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
227 (rx_decode_opcode): Likewise.
228 * rx-decode.c: Regenerate.
229
1cd986c5
NC		 2302010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
231 Ina Pandit <ina.pandit@kpitcummins.com>
232
233 * v850-dis.c (v850_sreg_names): Updated structure for system
234 registers.
235 (float_cc_names): new structure for condition codes.
236 (print_value): Update the function that prints value.
237 (get_operand_value): New function to get the operand value.
238 (disassemble): Updated to handle the disassembly of instructions.
239 (print_insn_v850): Updated function to print instruction for different
240 families.
241 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
242 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
243 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
244 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
245 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
246 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
247 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
248 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
249 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
250 (v850_operands): Update with the relocation name. Also update
251 the instructions with specific set of processors.
252
52e7f43d
RE		 2532010-07-08 Tejas Belagod <tejas.belagod@arm.com>
254
255 * arm-dis.c (print_insn_arm): Add cases for printing more
256 symbolic operands.
257 (print_insn_thumb32): Likewise.
258
c680e7f6
MR		 2592010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
260
261 * mips-dis.c (print_insn_mips): Correct branch instruction type
262 determination.
263
9a2c7088
MR		 2642010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
265
266 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
267 type and delay slot determination.
268 (print_insn_mips16): Extend branch instruction type and delay
269 slot determination to cover all instructions.
270 * mips16-opc.c (BR): Remove macro.
271 (UBR, CBR): New macros.
272 (mips16_opcodes): Update branch annotation for "b", "beqz",
273 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
274 and "jrc".
275
d7d9a9f8
L		 2762010-07-05 H.J. Lu <hongjiu.lu@intel.com>
277
278 AVX Programming Reference (June, 2010)
279 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
280 * i386-opc.tbl: Likewise.
281 * i386-tbl.h: Regenerated.
282
77321f53
L		 2832010-07-05 H.J. Lu <hongjiu.lu@intel.com>
284
285 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
286
7102e95e
AS		 2872010-07-03 Andreas Schwab <schwab@linux-m68k.org>
288
289 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
290 ppc_cpu_t before inverting.
3a5530ea
AS		 291 (ppc_parse_cpu): Likewise.
292 (print_insn_powerpc): Likewise.
7102e95e 293
bdc70b4a
AM		 2942010-07-03 Alan Modra <amodra@gmail.com>
295
296 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
297 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
298 (PPC64, MFDEC2): Update.
299 (NON32, NO371): Define.
300 (powerpc_opcode): Update to not use old opcode flags, and avoid
301 -m601 duplicates.
302
21375995
DD		 3032010-07-03 DJ Delorie <dj@delorie.com>
304
305 * m32c-ibld.c: Regenerate.
306
81a0b7e2
AM		 3072010-07-03 Alan Modra <amodra@gmail.com>
308
309 * ppc-opc.c (PWR2COM): Define.
310 (PPCPWR2): Add PPC_OPCODE_COMMON.
311 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
312 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
313 "rac" from -mcom.
314
c7b8aa3a
L		 3152010-07-01 H.J. Lu <hongjiu.lu@intel.com>
316
317 AVX Programming Reference (June, 2010)
318 * i386-dis.c (PREFIX_0FAE_REG_0): New.
319 (PREFIX_0FAE_REG_1): Likewise.
320 (PREFIX_0FAE_REG_2): Likewise.
321 (PREFIX_0FAE_REG_3): Likewise.
322 (PREFIX_VEX_3813): Likewise.
323 (PREFIX_VEX_3A1D): Likewise.
324 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
325 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
326 PREFIX_VEX_3A1D.
327 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
328 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
329 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
330
331 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
332 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
333 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
334
335 * i386-opc.h (CpuXsaveopt): New.
77321f53 336 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 337 (CpuRdRnd): Likewise.
338 (CpuF16C): Likewise.
339 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
340 cpuf16c.
341
342 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
343 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 344 * i386-init.h: Regenerated.
345 * i386-tbl.h: Likewise.
c7b8aa3a 346
09a8ad8d
AM		 3472010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
348
349 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
350 and mtocrf on EFS.
351
360cfc9c
AM		 3522010-06-29 Alan Modra <amodra@gmail.com>
353
354 * maxq-dis.c: Delete file.
355 * Makefile.am: Remove references to maxq.
356 * configure.in: Likewise.
357 * disassemble.c: Likewise.
358 * Makefile.in: Regenerate.
359 * configure: Regenerate.
360 * po/POTFILES.in: Regenerate.
361
dc898d5e
AM		 3622010-06-29 Alan Modra <amodra@gmail.com>
363
364 * mep-dis.c: Regenerate.
365
8e560766
MGD		 3662010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
367
368 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
369
c7e2358a
AM		 3702010-06-27 Alan Modra <amodra@gmail.com>
371
372 * arc-dis.c (arc_sprintf): Delete set but unused variables.
373 (decodeInstr): Likewise.
374 * dlx-dis.c (print_insn_dlx): Likewise.
375 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
376 * maxq-dis.c (check_move, print_insn): Likewise.
377 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
378 * msp430-dis.c (msp430_branchinstr): Likewise.
379 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
380 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
381 * sparc-dis.c (print_insn_sparc): Likewise.
382 * fr30-asm.c: Regenerate.
383 * frv-asm.c: Regenerate.
384 * ip2k-asm.c: Regenerate.
385 * iq2000-asm.c: Regenerate.
386 * lm32-asm.c: Regenerate.
387 * m32c-asm.c: Regenerate.
388 * m32r-asm.c: Regenerate.
389 * mep-asm.c: Regenerate.
390 * mt-asm.c: Regenerate.
391 * openrisc-asm.c: Regenerate.
392 * xc16x-asm.c: Regenerate.
393 * xstormy16-asm.c: Regenerate.
394
6ffe3d99
NC		 3952010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
396
397 PR gas/11673
398 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
399
09ec0d17
NC		 4002010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
401
402 PR binutils/11676
403 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
404
e01d869a
AM		 4052010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
406
407 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
408 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
409 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
410 touch floating point regs and are enabled by COM, PPC or PPCCOM.
411 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
412 Treat lwsync as msync on e500.
413
1f4e4950
MGD		 4142010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
415
416 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
417
9d82ec38
MGD		 4182010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
419
e01d869a 420 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 421 constants is the same on 32-bit and 64-bit hosts.
422
c3a6ea62 4232010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 424
425 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
426 .short directives so that they can be reassembled.
427
9db8dccb
CM		 4282010-05-26 Catherine Moore <clm@codesourcery.com>
429 David Ung <davidu@mips.com>
430
431 * mips-opc.c: Change membership to I1 for instructions ssnop and
432 ehb.
433
dfc8cf43
L		 4342010-05-26 H.J. Lu <hongjiu.lu@intel.com>
435
436 * i386-dis.c (sib): New.
437 (get_sib): Likewise.
438 (print_insn): Call get_sib.
439 OP_E_memory): Use sib.
440
f79e2745
CM		 4412010-05-26 Catherine Moore <clm@codesoourcery.com>
442
443 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
444 * mips-opc.c (I16): Remove.
445 (mips_builtin_op): Reclassify jalx.
446
51b5d4a8
AM		 4472010-05-19 Alan Modra <amodra@gmail.com>
448
449 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
450 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
451
85d4ac0b
AM		 4522010-05-13 Alan Modra <amodra@gmail.com>
453
454 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
455
4547cb56
NC		 4562010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
457
458 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
459 format.
460 (print_insn_thumb16): Add support for new %W format.
461
6540b386
TG		 4622010-05-07 Tristan Gingold <gingold@adacore.com>
463
464 * Makefile.in: Regenerate with automake 1.11.1.
465 * aclocal.m4: Ditto.
466
3e01a7fd
NC		 4672010-05-05 Nick Clifton <nickc@redhat.com>
468
469 * po/es.po: Updated Spanish translation.
470
9c9c98a5
NC		 4712010-04-22 Nick Clifton <nickc@redhat.com>
472
473 * po/opcodes.pot: Updated by the Translation project.
474 * po/vi.po: Updated Vietnamese translation.
475
f07af43e
L		 4762010-04-16 H.J. Lu <hongjiu.lu@intel.com>
477
478 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
479 bits in opcode.
480
3d540e93
NC		 4812010-04-09 Nick Clifton <nickc@redhat.com>
482
483 * i386-dis.c (print_insn): Remove unused variable op.
484 (OP_sI): Remove unused variable mask.
485
397841b5
AM		 4862010-04-07 Alan Modra <amodra@gmail.com>
487
488 * configure: Regenerate.
489
cee62821
PB		 4902010-04-06 Peter Bergner <bergner@vnet.ibm.com>
491
492 * ppc-opc.c (RBOPT): New define.
493 ("dccci"): Enable for PPCA2. Make operands optional.
494 ("iccci"): Likewise. Do not deprecate for PPC476.
495
accf4463
NC		 4962010-04-02 Masaki Muranaka <monaka@monami-software.com>
497
498 * cr16-opc.c (cr16_instruction): Fix typo in comment.
499
40b36596
JM		 5002010-03-25 Joseph Myers <joseph@codesourcery.com>
501
502 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
503 * Makefile.in: Regenerate.
504 * configure.in (bfd_tic6x_arch): New.
505 * configure: Regenerate.
506 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
507 (disassembler): Handle TI C6X.
508 * tic6x-dis.c: New.
509
1985c81c
MF		 5102010-03-24 Mike Frysinger <vapier@gentoo.org>
511
512 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
513
f66187fd
JM		 5142010-03-23 Joseph Myers <joseph@codesourcery.com>
515
516 * dis-buf.c (buffer_read_memory): Give error for reading just
517 before the start of memory.
518
ce7d077e
SP		 5192010-03-22 Sebastian Pop <sebastian.pop@amd.com>
520 Quentin Neill <quentin.neill@amd.com>
521
522 * i386-dis.c (OP_LWP_I): Removed.
523 (reg_table): Do not use OP_LWP_I, use Iq.
524 (OP_LWPCB_E): Remove use of names16.
525 (OP_LWP_E): Same.
526 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
527 should not set the Vex.length bit.
528 * i386-tbl.h: Regenerated.
529
63d0fa4e
AM		 5302010-02-25 Edmar Wienskoski <edmar@freescale.com>
531
532 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
533
c060226a
NC		 5342010-02-24 Nick Clifton <nickc@redhat.com>
535
536 PR binutils/6773
537 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
538 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
539 (thumb32_opcodes): Likewise.
540
ab7875de
NC		 5412010-02-15 Nick Clifton <nickc@redhat.com>
542
543 * po/vi.po: Updated Vietnamese translation.
544
fee1d3e8
DE		 5452010-02-12 Doug Evans <dje@sebabeach.org>
546
547 * lm32-opinst.c: Regenerate.
548
37ec9240
DE		 5492010-02-11 Doug Evans <dje@sebabeach.org>
550
9468ae89
DE		 551 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
552 (print_address): Delete CGEN_PRINT_ADDRESS.
553 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
554 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
555 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
556 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
557
37ec9240
DE		 558 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
559 * frv-desc.c, * frv-desc.h, * frv-opc.c,
560 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
561 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
562 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
563 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
564 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
565 * mep-desc.c, * mep-desc.h, * mep-opc.c,
566 * mt-desc.c, * mt-desc.h, * mt-opc.c,
567 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
568 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
569 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
570
c75ef631
L		 5712010-02-11 H.J. Lu <hongjiu.lu@intel.com>
572
573 * i386-dis.c: Update copyright.
574 * i386-gen.c: Likewise.
575 * i386-opc.h: Likewise.
576 * i386-opc.tbl: Likewise.
577
a683cc34
SP		 5782010-02-10 Quentin Neill <quentin.neill@amd.com>
579 Sebastian Pop <sebastian.pop@amd.com>
580
581 * i386-dis.c (OP_EX_VexImmW): Reintroduced
582 function to handle 5th imm8 operand.
583 (PREFIX_VEX_3A48): Added.
584 (PREFIX_VEX_3A49): Added.
585 (VEX_W_3A48_P_2): Added.
586 (VEX_W_3A49_P_2): Added.
587 (prefix table): Added entries for PREFIX_VEX_3A48
588 and PREFIX_VEX_3A49.
589 (vex table): Added entries for VEX_W_3A48_P_2 and
590 and VEX_W_3A49_P_2.
591 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
592 for Vec_Imm4 operands.
593 * i386-opc.h (enum): Added Vec_Imm4.
594 (i386_operand_type): Added vec_imm4.
595 * i386-opc.tbl: Add entries for vpermilp[ds].
596 * i386-init.h: Regenerated.
597 * i386-tbl.h: Regenerated.
598
cdc51b07
RS		 5992010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
600
601 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
602 and "pwr7". Move "a2" into alphabetical order.
603
ce3d2015
AM		 6042010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
605
606 * ppc-dis.c (ppc_opts): Add titan entry.
607 * ppc-opc.c (TITAN, MULHW): Define.
608 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
609
68339fdf
SP		 6102010-02-03 Quentin Neill <quentin.neill@amd.com>
611
612 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
613 to CPU_BDVER1_FLAGS
614 * i386-init.h: Regenerated.
615
f3d55a94
AG		 6162010-02-03 Anthony Green <green@moxielogic.com>
617
618 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
619 0x0f, and make 0x00 an illegal instruction.
620
b0e28b39
DJ		 6212010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
622
623 * opcodes/arm-dis.c (struct arm_private_data): New.
624 (print_insn_coprocessor, print_insn_arm): Update to use struct
625 arm_private_data.
626 (is_mapping_symbol, get_map_sym_type): New functions.
627 (get_sym_code_type): Check the symbol's section. Do not check
628 mapping symbols.
629 (print_insn): Default to disassembling ARM mode code. Check
630 for mapping symbols separately from other symbols. Use
631 struct arm_private_data.
632
1c480963
L		 6332010-01-28 H.J. Lu <hongjiu.lu@intel.com>
634
635 * i386-dis.c (EXVexWdqScalar): New.
636 (vex_scalar_w_dq_mode): Likewise.
637 (prefix_table): Update entries for PREFIX_VEX_3899,
638 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
639 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
640 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
641 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
642 (intel_operand_size): Handle vex_scalar_w_dq_mode.
643 (OP_EX): Likewise.
644
539f890d
L		 6452010-01-27 H.J. Lu <hongjiu.lu@intel.com>
646
647 * i386-dis.c (XMScalar): New.
648 (EXdScalar): Likewise.
649 (EXqScalar): Likewise.
650 (EXqScalarS): Likewise.
651 (VexScalar): Likewise.
652 (EXdVexScalarS): Likewise.
653 (EXqVexScalarS): Likewise.
654 (XMVexScalar): Likewise.
655 (scalar_mode): Likewise.
656 (d_scalar_mode): Likewise.
657 (d_scalar_swap_mode): Likewise.
658 (q_scalar_mode): Likewise.
659 (q_scalar_swap_mode): Likewise.
660 (vex_scalar_mode): Likewise.
661 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
662 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
663 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
664 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
665 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
666 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
667 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
668 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
669 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
670 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
671 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
672 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
673 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
674 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
675 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
676 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
677 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
678 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
679 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
680 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
681 q_scalar_mode, q_scalar_swap_mode.
682 (OP_XMM): Handle scalar_mode.
683 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
684 and q_scalar_swap_mode.
685 (OP_VEX): Handle vex_scalar_mode.
686
208b4d78
L		 6872010-01-24 H.J. Lu <hongjiu.lu@intel.com>
688
689 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
690
448b213a
L		 6912010-01-24 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
694
47cf8fa0
L		 6952010-01-24 H.J. Lu <hongjiu.lu@intel.com>
696
697 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
698
592d1631
L		 6992010-01-24 H.J. Lu <hongjiu.lu@intel.com>
700
701 * i386-dis.c (Bad_Opcode): New.
702 (bad_opcode): Likewise.
703 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
704 (dis386_twobyte): Likewise.
705 (reg_table): Likewise.
706 (prefix_table): Likewise.
707 (x86_64_table): Likewise.
708 (vex_len_table): Likewise.
709 (vex_w_table): Likewise.
710 (mod_table): Likewise.
711 (rm_table): Likewise.
712 (float_reg): Likewise.
713 (reg_table): Remove trailing "(bad)" entries.
714 (prefix_table): Likewise.
715 (x86_64_table): Likewise.
716 (vex_len_table): Likewise.
717 (vex_w_table): Likewise.
718 (mod_table): Likewise.
719 (rm_table): Likewise.
720 (get_valid_dis386): Handle bytemode 0.
721
712366da
L		 7222010-01-23 H.J. Lu <hongjiu.lu@intel.com>
723
724 * i386-opc.h (VEXScalar): New.
725
726 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
727 instructions.
728 * i386-tbl.h: Regenerated.
729
706e8205 7302010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 731
732 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
733
734 * i386-opc.tbl: Add xsave64 and xrstor64.
735 * i386-tbl.h: Regenerated.
736
99ea83aa
NC		 7372010-01-20 Nick Clifton <nickc@redhat.com>
738
739 PR 11170
740 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
741 based post-indexed addressing.
742
a6461c02
SP		 7432010-01-15 Sebastian Pop <sebastian.pop@amd.com>
744
745 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
746 * i386-tbl.h: Regenerated.
747
a2a7d12c
L		 7482010-01-14 H.J. Lu <hongjiu.lu@intel.com>
749
750 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
751 comments.
752
b9733481
L		 7532010-01-14 H.J. Lu <hongjiu.lu@intel.com>
754
755 * i386-dis.c (names_mm): New.
756 (intel_names_mm): Likewise.
757 (att_names_mm): Likewise.
758 (names_xmm): Likewise.
759 (intel_names_xmm): Likewise.
760 (att_names_xmm): Likewise.
761 (names_ymm): Likewise.
762 (intel_names_ymm): Likewise.
763 (att_names_ymm): Likewise.
764 (print_insn): Set names_mm, names_xmm and names_ymm.
765 (OP_MMX): Use names_mm, names_xmm and names_ymm.
766 (OP_XMM): Likewise.
767 (OP_EM): Likewise.
768 (OP_EMC): Likewise.
769 (OP_MXC): Likewise.
770 (OP_EX): Likewise.
771 (XMM_Fixup): Likewise.
772 (OP_VEX): Likewise.
773 (OP_EX_VexReg): Likewise.
774 (OP_Vex_2src): Likewise.
775 (OP_Vex_2src_1): Likewise.
776 (OP_Vex_2src_2): Likewise.
777 (OP_REG_VexI4): Likewise.
778
5e6718e4
L		 7792010-01-13 H.J. Lu <hongjiu.lu@intel.com>
780
781 * i386-dis.c (print_insn): Update comments.
782
d869730d
L		 7832010-01-12 H.J. Lu <hongjiu.lu@intel.com>
784
785 * i386-dis.c (rex_original): Removed.
786 (ckprefix): Remove rex_original.
787 (print_insn): Update comments.
788
3725885a
RW		 7892010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
790
791 * Makefile.in: Regenerate.
792 * configure: Regenerate.
793
b7cd1872
DE		 7942010-01-07 Doug Evans <dje@sebabeach.org>
795
796 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
797 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
798 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
799 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
800 * xstormy16-ibld.c: Regenerate.
801
69dd9865
SP		 8022010-01-06 Quentin Neill <quentin.neill@amd.com>
803
804 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
805 * i386-init.h: Regenerated.
806
e3e535bc
NC		 8072010-01-06 Daniel Gutson <dgutson@codesourcery.com>
808
809 * arm-dis.c (print_insn): Fixed search for next symbol and data
810 dumping condition, and the initial mapping symbol state.
811
fe8afbc4
DE		 8122010-01-05 Doug Evans <dje@sebabeach.org>
813
814 * cgen-ibld.in: #include "cgen/basic-modes.h".
815 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
816 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
817 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
818 * xstormy16-ibld.c: Regenerate.
819
2edcd244
NC		 8202010-01-04 Nick Clifton <nickc@redhat.com>
821
822 PR 11123
823 * arm-dis.c (print_insn_coprocessor): Initialise value.
824
0dc93057
AM		 8252010-01-04 Edmar Wienskoski <edmar@freescale.com>
826
827 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
828
05994f45
DE		 8292010-01-02 Doug Evans <dje@sebabeach.org>
830
831 * cgen-asm.in: Update copyright year.
832 * cgen-dis.in: Update copyright year.
833 * cgen-ibld.in: Update copyright year.
834 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
835 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
836 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
837 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
838 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
839 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
840 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
841 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
842 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
843 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
844 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
845 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
846 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
847 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
848 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
849 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
850 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
851 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
852 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
853 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
854 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 855
43ecc30f 856For older changes see ChangeLog-2009
252b5132
RH		 857\f
858Local Variables:
2f6d2f85
NC		 859mode: change-log
860left-margin: 8
861fill-column: 74
252b5132
RH		 862version-control: never
863End:
GDB Binutils - Deliverables
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