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x86: ignore high register select bit(s) in 32- and 16-bit modes
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5f847646
JB		 12017-11-16 Jan Beulich <jbeulich@suse.com>
2
3 (get_valid_dis386): Never flag bad opcode when
4 vex.register_specifier is beyond 7. Always store all four
5 bits of it. Move 16-/32-bit override in EVEX handling after
6 all to be overridden bits have been set.
7 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
8 Use rex to determine GPR register set.
9 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
10 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
11
390a6789
JB		 122017-11-15 Jan Beulich <jbeulich@suse.com>
13
14 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
15 determine GPR register set.
16
3a2430e0
JB		 172017-11-15 Jan Beulich <jbeulich@suse.com>
18
19 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
20 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
21 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
22 pass.
23 (OP_REG_VexI4): Drop low 4 bits check.
24
0645f0a2
JB		 252017-11-15 Jan Beulich <jbeulich@suse.com>
26
27 * i386-reg.tbl (axl): Remove Acc and Byte.
28 * i386-tbl.h: Re-generate.
29
be92cb14
JB		 302017-11-14 Jan Beulich <jbeulich@suse.com>
31
32 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
33 (vex_len_table): Use VPCOM.
34
2645e1d0
JB		 352017-11-14 Jan Beulich <jbeulich@suse.com>
36
37 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
38 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
39 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
40 vpcmpw): Move up.
41 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
42 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
43 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
44 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
45 vpcmpnltuw): New.
46 * i386-tbl.h: Re-generate.
47
df145ef6
JB		 482017-11-14 Jan Beulich <jbeulich@suse.com>
49
50 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
51 smov, ssca, stos, ssto, xlat): Drop Disp*.
52 * i386-tbl.h: Re-generate.
53
897e603c
JB		 542017-11-13 Jan Beulich <jbeulich@suse.com>
55
56 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
57 xsaveopt64): Add No_qSuf.
58 * i386-tbl.h: Re-generate.
59
793a1948
TC		 602017-11-09 Tamar Christina <tamar.christina@arm.com>
61
62 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
63 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
64 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
65 sder32_el2, vncr_el2.
66 (aarch64_sys_reg_supported_p): Likewise.
67 (aarch64_pstatefields): Add dit register.
68 (aarch64_pstatefield_supported_p): Likewise.
69 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
70 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
71 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
72 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
73 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
74 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
75 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
76
1a7ed57c
TC		 772017-11-09 Tamar Christina <tamar.christina@arm.com>
78
79 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
80 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
81 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
82 (QL_STLW, QL_STLX): New.
83
f42f1a1d
TC		 842017-11-09 Tamar Christina <tamar.christina@arm.com>
85
86 * aarch64-asm.h (ins_addr_offset): New.
87 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
88 (aarch64_ins_addr_offset): New.
89 * aarch64-asm-2.c: Regenerate.
90 * aarch64-dis.h (ext_addr_offset): New.
91 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
92 (aarch64_ext_addr_offset): New.
93 * aarch64-dis-2.c: Regenerate.
94 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
95 FLD_imm4_2 and FLD_SM3_imm2.
96 * aarch64-opc.c (fields): Add FLD_imm6_2,
97 FLD_imm4_2 and FLD_SM3_imm2.
98 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
99 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
100 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
101 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
102 * aarch64-tbl.h
103 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
104
b6b9ca0c
TC		 1052017-11-09 Tamar Christina <tamar.christina@arm.com>
106
107 * aarch64-tbl.h
108 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
109 (aarch64_feature_sm4, aarch64_feature_sha3): New.
110 (aarch64_feature_fp_16_v8_2): New.
111 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
112 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
113 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
114
c0e7cef7
NC		 1152017-11-08 Tamar Christina <tamar.christina@arm.com>
116
117 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
118 (aarch64_feature_sha2, aarch64_feature_aes): New.
119 (SHA2, AES): New.
120 (AES_INSN, SHA2_INSN): New.
121 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
122 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
123 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
124 Change to SHA2_INS.
125
dec41383
JW		 1262017-11-08 Jiong Wang <jiong.wang@arm.com>
127 Tamar Christina <tamar.christina@arm.com>
128
129 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
130 FP16 instructions, including vfmal.f16 and vfmsl.f16.
131
52eab766
AB		 1322017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
133
134 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
135
6003e27e
AM		 1362017-11-07 Alan Modra <amodra@gmail.com>
137
138 * opintl.h: Formatting, comment fixes.
139 (gettext, ngettext): Redefine when ENABLE_NLS.
140 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
141 (_): Define using gettext.
142 (textdomain, bindtextdomain): Use safer "do nothing".
143
fdddd290 1442017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
145
146 * arc-dis.c (print_hex): New variable.
147 (parse_option): Check for hex option.
148 (print_insn_arc): Use hexadecimal representation for short
149 immediate values when requested.
150 (print_arc_disassembler_options): Add hex option to the list.
151
3334eba7 1522017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
153
154 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
155 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
156 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
157 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
158 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
159 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
160 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
161 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
162 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
163 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
164 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
165 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
166 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
167 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
168 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
169 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
170 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
171 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
172 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
173 Changed opcodes.
174 (prealloc, prefetch*): Place them before ld instruction.
175 * arc-opc.c (skip_this_opcode): Add ARITH class.
176
e5d70d6b
AM		 1772017-10-25 Alan Modra <amodra@gmail.com>
178
179 PR 22348
180 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
181 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
182 (imm4flag, size_changed): Likewise.
183 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
184 (words, allWords, processing_argument_number): Likewise.
185 (cst4flag, size_changed): Likewise.
186 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
187 (crx_cst4_maps): Rename from cst4_maps.
188 (crx_no_op_insn): Rename from no_op_insn.
189
63a25ea0
AW		 1902017-10-24 Andrew Waterman <andrew@sifive.com>
191
192 * riscv-opc.c (match_c_addi16sp) : New function.
193 (match_c_addi4spn): New function.
194 (match_c_lui): Don't allow 0-immediate encodings.
195 (riscv_opcodes) <addi>: Use the above functions.
196 <add>: Likewise.
197 <c.addi4spn>: Likewise.
198 <c.addi16sp>: Likewise.
199
fe4e2a3c
IT		 2002017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
201
202 * i386-init.h: Regenerate
203 * i386-tbl.h: Likewise
204
2739ef6d
IT		 2052017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
206
207 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
208 (enum): Add EVEX_W_0F3854_P_2.
209 * i386-dis-evex.h (evex_table): Updated.
210 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
211 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
212 (cpu_flags): Add CpuAVX512_BITALG.
213 * i386-opc.h (enum): Add CpuAVX512_BITALG.
214 (i386_cpu_flags): Add cpuavx512_bitalg..
215 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
216 * i386-init.h: Regenerate.
217 * i386-tbl.h: Likewise.
218
2192017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
220
221 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
222 * i386-dis-evex.h (evex_table): Updated.
223 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
224 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
225 (cpu_flags): Add CpuAVX512_VNNI.
226 * i386-opc.h (enum): Add CpuAVX512_VNNI.
227 (i386_cpu_flags): Add cpuavx512_vnni.
228 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
229 * i386-init.h: Regenerate.
230 * i386-tbl.h: Likewise.
231
2322017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
233
234 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
235 (enum): Remove VEX_LEN_0F3A44_P_2.
236 (vex_len_table): Ditto.
237 (enum): Remove VEX_W_0F3A44_P_2.
238 (vew_w_table): Ditto.
239 (prefix_table): Adjust instructions (see prefixes above).
240 * i386-dis-evex.h (evex_table):
241 Add new instructions (see prefixes above).
242 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
243 (bitfield_cpu_flags): Ditto.
244 * i386-opc.h (enum): Ditto.
245 (i386_cpu_flags): Ditto.
246 (CpuUnused): Comment out to avoid zero-width field problem.
247 * i386-opc.tbl (vpclmulqdq): New instruction.
248 * i386-init.h: Regenerate.
249 * i386-tbl.h: Ditto.
250
2512017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
252
253 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
254 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
255 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
256 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
257 (vex_len_table): Ditto.
258 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
259 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
260 (vew_w_table): Ditto.
261 (prefix_table): Adjust instructions (see prefixes above).
262 * i386-dis-evex.h (evex_table):
263 Add new instructions (see prefixes above).
264 * i386-gen.c (cpu_flag_init): Add VAES.
265 (bitfield_cpu_flags): Ditto.
266 * i386-opc.h (enum): Ditto.
267 (i386_cpu_flags): Ditto.
268 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
269 * i386-init.h: Regenerate.
270 * i386-tbl.h: Ditto.
271
2722017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
273
274 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
275 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
276 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
277 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
278 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
279 (prefix_table): Updated (see prefixes above).
280 (three_byte_table): Likewise.
281 (vex_w_table): Likewise.
282 * i386-dis-evex.h: Likewise.
283 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
284 (cpu_flags): Add CpuGFNI.
285 * i386-opc.h (enum): Add CpuGFNI.
286 (i386_cpu_flags): Add cpugfni.
287 * i386-opc.tbl: Add Intel GFNI instructions.
288 * i386-init.h: Regenerate.
289 * i386-tbl.h: Likewise.
290
2912017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
292
293 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
294 Define EXbScalar and EXwScalar for OP_EX.
295 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
296 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
297 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
298 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
299 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
300 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
301 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
302 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
303 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
304 (OP_E_memory): Likewise.
305 * i386-dis-evex.h: Updated.
306 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
307 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
308 (cpu_flags): Add CpuAVX512_VBMI2.
309 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
310 (i386_cpu_flags): Add cpuavx512_vbmi2.
311 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
312 * i386-init.h: Regenerate.
313 * i386-tbl.h: Likewise.
314
2a6969e1
EB		 3152017-10-18 Eric Botcazou <ebotcazou@adacore.com>
316
317 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
318
3b4b0a62
JB		 3192017-10-12 James Bowman <james.bowman@ftdichip.com>
320
321 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
322 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
323 K15. Add jmpix pattern.
324
8e464506
AK		 3252017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
326
327 * s390-opc.txt (prno, tpei, irbm): New instructions added.
328
ee6767da
AK		 3292017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
330
331 * s390-opc.c (INSTR_SI_RD): New macro.
332 (INSTR_S_RD): Adjust example instruction.
333 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
334 SI_RD.
335
d2e6c9a3
AF		 3362017-10-01 Alexander Fedotov <alfedotov@gmail.com>
337
338 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
339 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
340 VLE multimple load/store instructions. Old e_ldm* variants are
341 kept as aliases.
342 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
343
8e43602e
NC		 3442017-09-27 Nick Clifton <nickc@redhat.com>
345
346 PR 22179
347 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
348 names for the fmv.x.s and fmv.s.x instructions respectively.
349
58a0b827
NC		 3502017-09-26 do <do@nerilex.org>
351
352 PR 22123
353 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
354 be used on CPUs that have emacs support.
355
57a024f4
SDJ		 3562017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
357
358 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
359
4ec521f2
KLC		 3602017-09-09 Kamil Rytarowski <n54@gmx.com>
361
362 * nds32-asm.c: Rename __BIT() to N32_BIT().
363 * nds32-asm.h: Likewise.
364 * nds32-dis.c: Likewise.
365
4e9ac44a
L		 3662017-09-09 H.J. Lu <hongjiu.lu@intel.com>
367
368 * i386-dis.c (last_active_prefix): Removed.
369 (ckprefix): Don't set last_active_prefix.
370 (NOTRACK_Fixup): Don't check last_active_prefix.
371
b55f3386
NC		 3722017-08-31 Nick Clifton <nickc@redhat.com>
373
374 * po/fr.po: Updated French translation.
375
59e8523b
JB		 3762017-08-31 James Bowman <james.bowman@ftdichip.com>
377
378 * ft32-dis.c (print_insn_ft32): Correct display of non-address
379 fields.
380
74081948
AF		 3812017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
382 Edmar Wienskoski <edmar.wienskoski@nxp.com>
383
384 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
385 PPC_OPCODE_EFS2 flag to "e200z4" entry.
386 New entries efs2 and spe2.
387 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
388 (SPE2_OPCD_SEGS): New macro.
389 (spe2_opcd_indices): New.
390 (disassemble_init_powerpc): Handle SPE2 opcodes.
391 (lookup_spe2): New function.
392 (print_insn_powerpc): call lookup_spe2.
393 * ppc-opc.c (insert_evuimm1_ex0): New function.
394 (extract_evuimm1_ex0): Likewise.
395 (insert_evuimm_lt8): Likewise.
396 (extract_evuimm_lt8): Likewise.
397 (insert_off_spe2): Likewise.
398 (extract_off_spe2): Likewise.
399 (insert_Ddd): Likewise.
400 (extract_Ddd): Likewise.
401 (DD): New operand.
402 (EVUIMM_LT8): Likewise.
403 (EVUIMM_LT16): Adjust.
404 (MMMM): New operand.
405 (EVUIMM_1): Likewise.
406 (EVUIMM_1_EX0): Likewise.
407 (EVUIMM_2): Adjust.
408 (NNN): New operand.
409 (VX_OFF_SPE2): Likewise.
410 (BBB): Likewise.
411 (DDD): Likewise.
412 (VX_MASK_DDD): New mask.
413 (HH): New operand.
414 (VX_RA_CONST): New macro.
415 (VX_RA_CONST_MASK): Likewise.
416 (VX_RB_CONST): Likewise.
417 (VX_RB_CONST_MASK): Likewise.
418 (VX_OFF_SPE2_MASK): Likewise.
419 (VX_SPE_CRFD): Likewise.
420 (VX_SPE_CRFD_MASK VX): Likewise.
421 (VX_SPE2_CLR): Likewise.
422 (VX_SPE2_CLR_MASK): Likewise.
423 (VX_SPE2_SPLATB): Likewise.
424 (VX_SPE2_SPLATB_MASK): Likewise.
425 (VX_SPE2_OCTET): Likewise.
426 (VX_SPE2_OCTET_MASK): Likewise.
427 (VX_SPE2_DDHH): Likewise.
428 (VX_SPE2_DDHH_MASK): Likewise.
429 (VX_SPE2_HH): Likewise.
430 (VX_SPE2_HH_MASK): Likewise.
431 (VX_SPE2_EVMAR): Likewise.
432 (VX_SPE2_EVMAR_MASK): Likewise.
433 (PPCSPE2): Likewise.
434 (PPCEFS2): Likewise.
435 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
436 (powerpc_macros): Map old SPE instructions have new names
437 with the same opcodes. Add SPE2 instructions which just are
438 mapped to SPE2.
439 (spe2_opcodes): Add SPE2 opcodes.
440
b80c7270
AM		 4412017-08-23 Alan Modra <amodra@gmail.com>
442
443 * ppc-opc.c: Formatting and comment fixes. Move insert and
444 extract functions earlier, deleting forward declarations.
445 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
446 RA_MASK.
447
67d888f5
PD		 4482017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
449
450 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
451
e3c2f928
AF		 4522017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
453 Edmar Wienskoski <edmar.wienskoski@nxp.com>
454
455 * ppc-opc.c (insert_evuimm2_ex0): New function.
456 (extract_evuimm2_ex0): Likewise.
457 (insert_evuimm4_ex0): Likewise.
458 (extract_evuimm4_ex0): Likewise.
459 (insert_evuimm8_ex0): Likewise.
460 (extract_evuimm8_ex0): Likewise.
461 (insert_evuimm_lt16): Likewise.
462 (extract_evuimm_lt16): Likewise.
463 (insert_rD_rS_even): Likewise.
464 (extract_rD_rS_even): Likewise.
465 (insert_off_lsp): Likewise.
466 (extract_off_lsp): Likewise.
467 (RD_EVEN): New operand.
468 (RS_EVEN): Likewise.
469 (RSQ): Adjust.
470 (EVUIMM_LT16): New operand.
471 (HTM_SI): Adjust.
472 (EVUIMM_2_EX0): New operand.
473 (EVUIMM_4): Adjust.
474 (EVUIMM_4_EX0): New operand.
475 (EVUIMM_8): Adjust.
476 (EVUIMM_8_EX0): New operand.
477 (WS): Adjust.
478 (VX_OFF): New operand.
479 (VX_LSP): New macro.
480 (VX_LSP_MASK): Likewise.
481 (VX_LSP_OFF_MASK): Likewise.
482 (PPC_OPCODE_LSP): Likewise.
483 (vle_opcodes): Add LSP opcodes.
484 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
485
cc4a945a
JW		 4862017-08-09 Jiong Wang <jiong.wang@arm.com>
487
488 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
489 register operands in CRC instructions.
490 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
491 comments.
492
b28b8b5e
L		 4932017-08-07 H.J. Lu <hongjiu.lu@intel.com>
494
495 * disassemble.c (disassembler): Mark big and mach with
496 ATTRIBUTE_UNUSED.
497
e347efc3
MR		 4982017-08-07 Maciej W. Rozycki <macro@imgtec.com>
499
500 * disassemble.c (disassembler): Remove arch/mach/endian
501 assertions.
502
7cbc739c
NC		 5032017-07-25 Nick Clifton <nickc@redhat.com>
504
505 PR 21739
506 * arc-opc.c (insert_rhv2): Use lower case first letter in error
507 message.
508 (insert_r0): Likewise.
509 (insert_r1): Likewise.
510 (insert_r2): Likewise.
511 (insert_r3): Likewise.
512 (insert_sp): Likewise.
513 (insert_gp): Likewise.
514 (insert_pcl): Likewise.
515 (insert_blink): Likewise.
516 (insert_ilink1): Likewise.
517 (insert_ilink2): Likewise.
518 (insert_ras): Likewise.
519 (insert_rbs): Likewise.
520 (insert_rcs): Likewise.
521 (insert_simm3s): Likewise.
522 (insert_rrange): Likewise.
523 (insert_r13el): Likewise.
524 (insert_fpel): Likewise.
525 (insert_blinkel): Likewise.
526 (insert_pclel): Likewise.
527 (insert_nps_bitop_size_2b): Likewise.
528 (insert_nps_imm_offset): Likewise.
529 (insert_nps_imm_entry): Likewise.
530 (insert_nps_size_16bit): Likewise.
531 (insert_nps_##NAME##_pos): Likewise.
532 (insert_nps_##NAME): Likewise.
533 (insert_nps_bitop_ins_ext): Likewise.
534 (insert_nps_##NAME): Likewise.
535 (insert_nps_min_hofs): Likewise.
536 (insert_nps_##NAME): Likewise.
537 (insert_nps_rbdouble_64): Likewise.
538 (insert_nps_misc_imm_offset): Likewise.
539 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
540 option description.
541
7684e580
JW		 5422017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
543 Jiong Wang <jiong.wang@arm.com>
544
545 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
546 correct the print.
547 * aarch64-dis-2.c: Regenerated.
548
47826cdb
AK		 5492017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
550
551 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
552 table.
553
2d2dbad0
NC		 5542017-07-20 Nick Clifton <nickc@redhat.com>
555
556 * po/de.po: Updated German translation.
557
70b448ba 5582017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
559
560 * arc-regs.h (sec_stat): New aux register.
561 (aux_kernel_sp): Likewise.
562 (aux_sec_u_sp): Likewise.
563 (aux_sec_k_sp): Likewise.
564 (sec_vecbase_build): Likewise.
565 (nsc_table_top): Likewise.
566 (nsc_table_base): Likewise.
567 (ersec_stat): Likewise.
568 (aux_sec_except): Likewise.
569
7179e0e6
CZ		 5702017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
571
572 * arc-opc.c (extract_uimm12_20): New function.
573 (UIMM12_20): New operand.
574 (SIMM3_5_S): Adjust.
575 * arc-tbl.h (sjli): Add new instruction.
576
684d5a10
JEM		 5772017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
578 John Eric Martin <John.Martin@emmicro-us.com>
579
580 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
581 (UIMM3_23): Adjust accordingly.
582 * arc-regs.h: Add/correct jli_base register.
583 * arc-tbl.h (jli_s): Likewise.
584
de194d85
YC		 5852017-07-18 Nick Clifton <nickc@redhat.com>
586
587 PR 21775
588 * aarch64-opc.c: Fix spelling typos.
589 * i386-dis.c: Likewise.
590
0f6329bd
RB		 5912017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
592
593 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
594 max_addr_offset and octets variables to size_t.
595
429d795d
AM		 5962017-07-12 Alan Modra <amodra@gmail.com>
597
598 * po/da.po: Update from translationproject.org/latest/opcodes/.
599 * po/de.po: Likewise.
600 * po/es.po: Likewise.
601 * po/fi.po: Likewise.
602 * po/fr.po: Likewise.
603 * po/id.po: Likewise.
604 * po/it.po: Likewise.
605 * po/nl.po: Likewise.
606 * po/pt_BR.po: Likewise.
607 * po/ro.po: Likewise.
608 * po/sv.po: Likewise.
609 * po/tr.po: Likewise.
610 * po/uk.po: Likewise.
611 * po/vi.po: Likewise.
612 * po/zh_CN.po: Likewise.
613
4162bb66
AM		 6142017-07-11 Yao Qi <yao.qi@linaro.org>
615 Alan Modra <amodra@gmail.com>
616
617 * cgen.sh: Mark generated files read-only.
618 * epiphany-asm.c: Regenerate.
619 * epiphany-desc.c: Regenerate.
620 * epiphany-desc.h: Regenerate.
621 * epiphany-dis.c: Regenerate.
622 * epiphany-ibld.c: Regenerate.
623 * epiphany-opc.c: Regenerate.
624 * epiphany-opc.h: Regenerate.
625 * fr30-asm.c: Regenerate.
626 * fr30-desc.c: Regenerate.
627 * fr30-desc.h: Regenerate.
628 * fr30-dis.c: Regenerate.
629 * fr30-ibld.c: Regenerate.
630 * fr30-opc.c: Regenerate.
631 * fr30-opc.h: Regenerate.
632 * frv-asm.c: Regenerate.
633 * frv-desc.c: Regenerate.
634 * frv-desc.h: Regenerate.
635 * frv-dis.c: Regenerate.
636 * frv-ibld.c: Regenerate.
637 * frv-opc.c: Regenerate.
638 * frv-opc.h: Regenerate.
639 * ip2k-asm.c: Regenerate.
640 * ip2k-desc.c: Regenerate.
641 * ip2k-desc.h: Regenerate.
642 * ip2k-dis.c: Regenerate.
643 * ip2k-ibld.c: Regenerate.
644 * ip2k-opc.c: Regenerate.
645 * ip2k-opc.h: Regenerate.
646 * iq2000-asm.c: Regenerate.
647 * iq2000-desc.c: Regenerate.
648 * iq2000-desc.h: Regenerate.
649 * iq2000-dis.c: Regenerate.
650 * iq2000-ibld.c: Regenerate.
651 * iq2000-opc.c: Regenerate.
652 * iq2000-opc.h: Regenerate.
653 * lm32-asm.c: Regenerate.
654 * lm32-desc.c: Regenerate.
655 * lm32-desc.h: Regenerate.
656 * lm32-dis.c: Regenerate.
657 * lm32-ibld.c: Regenerate.
658 * lm32-opc.c: Regenerate.
659 * lm32-opc.h: Regenerate.
660 * lm32-opinst.c: Regenerate.
661 * m32c-asm.c: Regenerate.
662 * m32c-desc.c: Regenerate.
663 * m32c-desc.h: Regenerate.
664 * m32c-dis.c: Regenerate.
665 * m32c-ibld.c: Regenerate.
666 * m32c-opc.c: Regenerate.
667 * m32c-opc.h: Regenerate.
668 * m32r-asm.c: Regenerate.
669 * m32r-desc.c: Regenerate.
670 * m32r-desc.h: Regenerate.
671 * m32r-dis.c: Regenerate.
672 * m32r-ibld.c: Regenerate.
673 * m32r-opc.c: Regenerate.
674 * m32r-opc.h: Regenerate.
675 * m32r-opinst.c: Regenerate.
676 * mep-asm.c: Regenerate.
677 * mep-desc.c: Regenerate.
678 * mep-desc.h: Regenerate.
679 * mep-dis.c: Regenerate.
680 * mep-ibld.c: Regenerate.
681 * mep-opc.c: Regenerate.
682 * mep-opc.h: Regenerate.
683 * mt-asm.c: Regenerate.
684 * mt-desc.c: Regenerate.
685 * mt-desc.h: Regenerate.
686 * mt-dis.c: Regenerate.
687 * mt-ibld.c: Regenerate.
688 * mt-opc.c: Regenerate.
689 * mt-opc.h: Regenerate.
690 * or1k-asm.c: Regenerate.
691 * or1k-desc.c: Regenerate.
692 * or1k-desc.h: Regenerate.
693 * or1k-dis.c: Regenerate.
694 * or1k-ibld.c: Regenerate.
695 * or1k-opc.c: Regenerate.
696 * or1k-opc.h: Regenerate.
697 * or1k-opinst.c: Regenerate.
698 * xc16x-asm.c: Regenerate.
699 * xc16x-desc.c: Regenerate.
700 * xc16x-desc.h: Regenerate.
701 * xc16x-dis.c: Regenerate.
702 * xc16x-ibld.c: Regenerate.
703 * xc16x-opc.c: Regenerate.
704 * xc16x-opc.h: Regenerate.
705 * xstormy16-asm.c: Regenerate.
706 * xstormy16-desc.c: Regenerate.
707 * xstormy16-desc.h: Regenerate.
708 * xstormy16-dis.c: Regenerate.
709 * xstormy16-ibld.c: Regenerate.
710 * xstormy16-opc.c: Regenerate.
711 * xstormy16-opc.h: Regenerate.
712
7639175c
AM		 7132017-07-07 Alan Modra <amodra@gmail.com>
714
715 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
716 * m32c-dis.c: Regenerate.
717 * mep-dis.c: Regenerate.
718
e4bdd679
BP		 7192017-07-05 Borislav Petkov <bp@suse.de>
720
721 * i386-dis.c: Enable ModRM.reg /6 aliases.
722
60c96dbf
RR		 7232017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
724
725 * opcodes/arm-dis.c: Support MVFR2 in disassembly
726 with vmrs and vmsr.
727
0d702cfe
TG		 7282017-07-04 Tristan Gingold <gingold@adacore.com>
729
730 * configure: Regenerate.
731
15e6ed8c
TG		 7322017-07-03 Tristan Gingold <gingold@adacore.com>
733
734 * po/opcodes.pot: Regenerate.
735
b1d3c886
MR		 7362017-06-30 Maciej W. Rozycki <macro@imgtec.com>
737
738 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
739 entries to the MSA ASE instruction block.
740
909b4e3d
MR		 7412017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
742 Maciej W. Rozycki <macro@imgtec.com>
743
744 * micromips-opc.c (XPA, XPAVZ): New macros.
745 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
746 "mthgc0".
747
f5b2fd52
MR		 7482017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
749 Maciej W. Rozycki <macro@imgtec.com>
750
751 * micromips-opc.c (I36): New macro.
752 (micromips_opcodes): Add "eretnc".
753
9785fc2a
MR		 7542017-06-30 Maciej W. Rozycki <macro@imgtec.com>
755 Andrew Bennett <andrew.bennett@imgtec.com>
756
757 * mips-dis.c (mips_calculate_combination_ases): Handle the
758 ASE_XPA_VIRT flag.
759 (parse_mips_ase_option): New function.
760 (parse_mips_dis_option): Factor out ASE option handling to the
761 new function. Call `mips_calculate_combination_ases'.
762 * mips-opc.c (XPAVZ): New macro.
763 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
764 "mfhgc0", "mthc0" and "mthgc0".
765
60804c53
MR		 7662017-06-29 Maciej W. Rozycki <macro@imgtec.com>
767
768 * mips-dis.c (mips_calculate_combination_ases): New function.
769 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
770 calculation to the new function.
771 (set_default_mips_dis_options): Call the new function.
772
2e74f9dd
AK		 7732017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
774
775 * arc-dis.c (parse_disassembler_options): Use
776 FOR_EACH_DISASSEMBLER_OPTION.
777
e1e94c49
AK		 7782017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
779
780 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
781 disassembler option strings.
782 (parse_cpu_option): Likewise.
783
65a55fbb
TC		 7842017-06-28 Tamar Christina <tamar.christina@arm.com>
785
786 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
787 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
788 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
789 (aarch64_feature_dotprod, DOT_INSN): New.
790 (udot, sdot): New.
791 * aarch64-dis-2.c: Regenerated.
792
c604a79a
JW		 7932017-06-28 Jiong Wang <jiong.wang@arm.com>
794
795 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
796
38bf472a
MR		 7972017-06-28 Maciej W. Rozycki <macro@imgtec.com>
798 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 799 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 800
801 * mips-formats.h (INT_BIAS): New macro.
802 (INT_ADJ): Redefine in INT_BIAS terms.
803 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
804 (mips_print_save_restore): New function.
805 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
806 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
807 call.
808 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
809 (print_mips16_insn_arg): Call `mips_print_save_restore' for
810 OP_SAVE_RESTORE_LIST handling, factored out from here.
811 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
812 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
813 (mips_builtin_opcodes): Add "restore" and "save" entries.
814 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
815 (IAMR2): New macro.
816 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
817
9bdfdbf9
AW		 8182017-06-23 Andrew Waterman <andrew@sifive.com>
819
820 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
821 alias; do not mark SLTI instruction as an alias.
822
2234eee6
L		 8232017-06-21 H.J. Lu <hongjiu.lu@intel.com>
824
825 * i386-dis.c (RM_0FAE_REG_5): Removed.
826 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
827 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
828 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
829 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
830 PREFIX_MOD_3_0F01_REG_5_RM_0.
831 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
832 PREFIX_MOD_3_0FAE_REG_5.
833 (mod_table): Update MOD_0FAE_REG_5.
834 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
835 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
836 * i386-tbl.h: Regenerated.
837
c2f76402
L		 8382017-06-21 H.J. Lu <hongjiu.lu@intel.com>
839
840 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
841 * i386-opc.tbl: Likewise.
842 * i386-tbl.h: Regenerated.
843
9fef80d6
L		 8442017-06-21 H.J. Lu <hongjiu.lu@intel.com>
845
846 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
847 and "jmp{&|}".
848 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
849 prefix.
850
0f6d864d
NC		 8512017-06-19 Nick Clifton <nickc@redhat.com>
852
853 PR binutils/21614
854 * score-dis.c (score_opcodes): Add sentinel.
855
e197589b
AM		 8562017-06-16 Alan Modra <amodra@gmail.com>
857
858 * rx-decode.c: Regenerate.
859
0d96e4df
L		 8602017-06-15 H.J. Lu <hongjiu.lu@intel.com>
861
862 PR binutils/21594
863 * i386-dis.c (OP_E_register): Check valid bnd register.
864 (OP_G): Likewise.
865
cd3ea7c6
NC		 8662017-06-15 Nick Clifton <nickc@redhat.com>
867
868 PR binutils/21595
869 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
870 range value.
871
63323b5b
NC		 8722017-06-15 Nick Clifton <nickc@redhat.com>
873
874 PR binutils/21588
875 * rl78-decode.opc (OP_BUF_LEN): Define.
876 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
877 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
878 array.
879 * rl78-decode.c: Regenerate.
880
08c7881b
NC		 8812017-06-15 Nick Clifton <nickc@redhat.com>
882
883 PR binutils/21586
884 * bfin-dis.c (gregs): Clip index to prevent overflow.
885 (regs): Likewise.
886 (regs_lo): Likewise.
887 (regs_hi): Likewise.
888
e64519d1
NC		 8892017-06-14 Nick Clifton <nickc@redhat.com>
890
891 PR binutils/21576
892 * score7-dis.c (score_opcodes): Add sentinel.
893
6394c606
YQ		 8942017-06-14 Yao Qi <yao.qi@linaro.org>
895
896 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
897 * arm-dis.c: Likewise.
898 * ia64-dis.c: Likewise.
899 * mips-dis.c: Likewise.
900 * spu-dis.c: Likewise.
901 * disassemble.h (print_insn_aarch64): New declaration, moved from
902 include/dis-asm.h.
903 (print_insn_big_arm, print_insn_big_mips): Likewise.
904 (print_insn_i386, print_insn_ia64): Likewise.
905 (print_insn_little_arm, print_insn_little_mips): Likewise.
906
db5fa770
NC		 9072017-06-14 Nick Clifton <nickc@redhat.com>
908
909 PR binutils/21587
910 * rx-decode.opc: Include libiberty.h
911 (GET_SCALE): New macro - validates access to SCALE array.
912 (GET_PSCALE): New macro - validates access to PSCALE array.
913 (DIs, SIs, S2Is, rx_disp): Use new macros.
914 * rx-decode.c: Regenerate.
915
05c966f3
AV		 9162017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
917
918 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
919
10045478
AK		 9202017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
921
922 * arc-dis.c (enforced_isa_mask): Declare.
923 (cpu_types): Likewise.
924 (parse_cpu_option): New function.
925 (parse_disassembler_options): Use it.
926 (print_insn_arc): Use enforced_isa_mask.
927 (print_arc_disassembler_options): Document new options.
928
88c1242d
YQ		 9292017-05-24 Yao Qi <yao.qi@linaro.org>
930
931 * alpha-dis.c: Include disassemble.h, don't include
932 dis-asm.h.
933 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
934 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
935 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
936 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
937 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
938 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
939 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
940 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
941 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
942 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
943 * moxie-dis.c, msp430-dis.c, mt-dis.c:
944 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
945 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
946 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
947 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
948 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
949 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
950 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
951 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
952 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
953 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
954 * z80-dis.c, z8k-dis.c: Likewise.
955 * disassemble.h: New file.
956
ab20fa4a
YQ		 9572017-05-24 Yao Qi <yao.qi@linaro.org>
958
959 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
960 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
961
003ca0fd
YQ		 9622017-05-24 Yao Qi <yao.qi@linaro.org>
963
964 * disassemble.c (disassembler): Add arguments a, big and mach.
965 Use them.
966
04ef582a
L		 9672017-05-22 H.J. Lu <hongjiu.lu@intel.com>
968
969 * i386-dis.c (NOTRACK_Fixup): New.
970 (NOTRACK): Likewise.
971 (NOTRACK_PREFIX): Likewise.
972 (last_active_prefix): Likewise.
973 (reg_table): Use NOTRACK on indirect call and jmp.
974 (ckprefix): Set last_active_prefix.
975 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
976 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
977 * i386-opc.h (NoTrackPrefixOk): New.
978 (i386_opcode_modifier): Add notrackprefixok.
979 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
980 Add notrack.
981 * i386-tbl.h: Regenerated.
982
64517994
JM		 9832017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
984
985 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
986 (X_IMM2): Define.
987 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
988 bfd_mach_sparc_v9m8.
989 (print_insn_sparc): Handle new operand types.
990 * sparc-opc.c (MASK_M8): Define.
991 (v6): Add MASK_M8.
992 (v6notlet): Likewise.
993 (v7): Likewise.
994 (v8): Likewise.
995 (v9): Likewise.
996 (v9a): Likewise.
997 (v9b): Likewise.
998 (v9c): Likewise.
999 (v9d): Likewise.
1000 (v9e): Likewise.
1001 (v9v): Likewise.
1002 (v9m): Likewise.
1003 (v9andleon): Likewise.
1004 (m8): Define.
1005 (HWS_VM8): Define.
1006 (HWS2_VM8): Likewise.
1007 (sparc_opcode_archs): Add entry for "m8".
1008 (sparc_opcodes): Add OSA2017 and M8 instructions
1009 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1010 fpx{ll,ra,rl}64x,
1011 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1012 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1013 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1014 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1015 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1016 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1017 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1018 ASI_CORE_SELECT_COMMIT_NHT.
1019
535b785f
AM		 10202017-05-18 Alan Modra <amodra@gmail.com>
1021
1022 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1023 * aarch64-dis.c: Likewise.
1024 * aarch64-gen.c: Likewise.
1025 * aarch64-opc.c: Likewise.
1026
25499ac7
MR		 10272017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1028 Matthew Fortune <matthew.fortune@imgtec.com>
1029
1030 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1031 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1032 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1033 (print_insn_arg) <OP_REG28>: Add handler.
1034 (validate_insn_args) <OP_REG28>: Handle.
1035 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1036 32-bit encoding and 9-bit immediates.
1037 (print_insn_mips16): Handle MIPS16 instructions that require
1038 32-bit encoding and MFC0/MTC0 operand decoding.
1039 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1040 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1041 (RD_C0, WR_C0, E2, E2MT): New macros.
1042 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1043 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1044 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1045 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1046 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1047 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1048 instructions, "swl", "swr", "sync" and its "sync_acquire",
1049 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1050 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1051 regular/extended entries for original MIPS16 ISA revision
1052 instructions whose extended forms are subdecoded in the MIPS16e2
1053 ISA revision: "li", "sll" and "srl".
1054
fdfb4752
MR		 10552017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1056
1057 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1058 reference in CP0 move operand decoding.
1059
a4f89915
MR		 10602017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1061
1062 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1063 type to hexadecimal.
1064 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1065
99e2d67a
MR		 10662017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1067
1068 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1069 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1070 "sync_rmb" and "sync_wmb" as aliases.
1071 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1072 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1073
53a346d8
CZ		 10742017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1075
1076 * arc-dis.c (parse_option): Update quarkse_em option..
1077 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1078 QUARKSE1.
1079 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1080
f91d48de
KC		 10812017-05-03 Kito Cheng <kito.cheng@gmail.com>
1082
1083 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1084
43e379d7
MC		 10852017-05-01 Michael Clark <michaeljclark@mac.com>
1086
1087 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1088 register.
1089
a4ddc54e
MR		 10902017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1091
1092 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1093 and branches and not synthetic data instructions.
1094
fe50e98c
BE		 10952017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1096
1097 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1098
126124cc
CZ		 10992017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1100
1101 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1102 * arc-opc.c (insert_r13el): New function.
1103 (R13_EL): Define.
1104 * arc-tbl.h: Add new enter/leave variants.
1105
be6a24d8
CZ		 11062017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1107
1108 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1109
0348fd79
MR		 11102017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1111
1112 * mips-dis.c (print_mips_disassembler_options): Add
1113 `no-aliases'.
1114
6e3d1f07
MR		 11152017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1116
1117 * mips16-opc.c (AL): New macro.
1118 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1119 of "ld" and "lw" as aliases.
1120
957f6b39
TC		 11212017-04-24 Tamar Christina <tamar.christina@arm.com>
1122
1123 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1124 arguments.
1125
a8cc8a54
AM		 11262017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1127 Alan Modra <amodra@gmail.com>
1128
1129 * ppc-opc.c (ELEV): Define.
1130 (vle_opcodes): Add se_rfgi and e_sc.
1131 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1132 for E200Z4.
1133
3ab87b68
JM		 11342017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1135
1136 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1137
792f174f
NC		 11382017-04-21 Nick Clifton <nickc@redhat.com>
1139
1140 PR binutils/21380
1141 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1142 LD3R and LD4R.
1143
42742084
AM		 11442017-04-13 Alan Modra <amodra@gmail.com>
1145
1146 * epiphany-desc.c: Regenerate.
1147 * fr30-desc.c: Regenerate.
1148 * frv-desc.c: Regenerate.
1149 * ip2k-desc.c: Regenerate.
1150 * iq2000-desc.c: Regenerate.
1151 * lm32-desc.c: Regenerate.
1152 * m32c-desc.c: Regenerate.
1153 * m32r-desc.c: Regenerate.
1154 * mep-desc.c: Regenerate.
1155 * mt-desc.c: Regenerate.
1156 * or1k-desc.c: Regenerate.
1157 * xc16x-desc.c: Regenerate.
1158 * xstormy16-desc.c: Regenerate.
1159
9a85b496
AM		 11602017-04-11 Alan Modra <amodra@gmail.com>
1161
ef85eab0 1162 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 1163 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1164 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 1165 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1166 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 1167 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1168 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 1169 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 1170 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 1171
62adc510
AM		 11722017-04-10 Alan Modra <amodra@gmail.com>
1173
1174 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1175 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1176 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1177 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1178
aa808707
PC		 11792017-04-09 Pip Cet <pipcet@gmail.com>
1180
1181 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1182 appropriate floating-point precision directly.
1183
ac8f0f72
AM		 11842017-04-07 Alan Modra <amodra@gmail.com>
1185
1186 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1187 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1188 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1189 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1190 vector instructions with E6500 not PPCVEC2.
1191
62ecb94c
PC		 11922017-04-06 Pip Cet <pipcet@gmail.com>
1193
1194 * Makefile.am: Add wasm32-dis.c.
1195 * configure.ac: Add wasm32-dis.c to wasm32 target.
1196 * disassemble.c: Add wasm32 disassembler code.
1197 * wasm32-dis.c: New file.
1198 * Makefile.in: Regenerate.
1199 * configure: Regenerate.
1200 * po/POTFILES.in: Regenerate.
1201 * po/opcodes.pot: Regenerate.
1202
f995bbe8
PA		 12032017-04-05 Pedro Alves <palves@redhat.com>
1204
1205 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1206 * arm-dis.c (parse_arm_disassembler_options): Constify.
1207 * ppc-dis.c (powerpc_init_dialect): Constify local.
1208 * vax-dis.c (parse_disassembler_options): Constify.
1209
b5292032
PD		 12102017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1211
1212 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1213 RISCV_GP_SYMBOL.
1214
f96bd6c2
PC		 12152017-03-30 Pip Cet <pipcet@gmail.com>
1216
1217 * configure.ac: Add (empty) bfd_wasm32_arch target.
1218 * configure: Regenerate
1219 * po/opcodes.pot: Regenerate.
1220
f7c514a3
JM		 12212017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1222
1223 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1224 OSA2015.
1225 * opcodes/sparc-opc.c (asi_table): New ASIs.
1226
52be03fd
AM		 12272017-03-29 Alan Modra <amodra@gmail.com>
1228
1229 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1230 "raw" option.
1231 (lookup_powerpc): Don't special case -1 dialect. Handle
1232 PPC_OPCODE_RAW.
1233 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1234 lookup_powerpc call, pass it on second.
1235
9b753937
AM		 12362017-03-27 Alan Modra <amodra@gmail.com>
1237
1238 PR 21303
1239 * ppc-dis.c (struct ppc_mopt): Comment.
1240 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1241
c0c31e91
RZ		 12422017-03-27 Rinat Zelig <rinat@mellanox.com>
1243
1244 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1245 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1246 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1247 (insert_nps_misc_imm_offset): New function.
1248 (extract_nps_misc imm_offset): New function.
1249 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1250 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1251
2253c8f0
AK		 12522017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1253
1254 * s390-mkopc.c (main): Remove vx2 check.
1255 * s390-opc.txt: Remove vx2 instruction flags.
1256
645d3342
RZ		 12572017-03-21 Rinat Zelig <rinat@mellanox.com>
1258
1259 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1260 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1261 (insert_nps_imm_offset): New function.
1262 (extract_nps_imm_offset): New function.
1263 (insert_nps_imm_entry): New function.
1264 (extract_nps_imm_entry): New function.
1265
4b94dd2d
AM		 12662017-03-17 Alan Modra <amodra@gmail.com>
1267
1268 PR 21248
1269 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1270 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1271 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1272
b416fe87
KC		 12732017-03-14 Kito Cheng <kito.cheng@gmail.com>
1274
1275 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1276 <c.andi>: Likewise.
1277 <c.addiw> Likewise.
1278
03b039a5
KC		 12792017-03-14 Kito Cheng <kito.cheng@gmail.com>
1280
1281 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1282
2c232b83
AW		 12832017-03-13 Andrew Waterman <andrew@sifive.com>
1284
1285 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1286 <srl> Likewise.
1287 <srai> Likewise.
1288 <sra> Likewise.
1289
86fa6981
L		 12902017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1291
1292 * i386-gen.c (opcode_modifiers): Replace S with Load.
1293 * i386-opc.h (S): Removed.
1294 (Load): New.
1295 (i386_opcode_modifier): Replace s with load.
1296 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1297 and {evex}. Replace S with Load.
1298 * i386-tbl.h: Regenerated.
1299
c1fe188b
L		 13002017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1301
1302 * i386-opc.tbl: Use CpuCET on rdsspq.
1303 * i386-tbl.h: Regenerated.
1304
4b8b687e
PB		 13052017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1306
1307 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1308 <vsx>: Do not use PPC_OPCODE_VSX3;
1309
1437d063
PB		 13102017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1311
1312 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1313
603555e5
L		 13142017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1315
1316 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1317 (MOD_0F1E_PREFIX_1): Likewise.
1318 (MOD_0F38F5_PREFIX_2): Likewise.
1319 (MOD_0F38F6_PREFIX_0): Likewise.
1320 (RM_0F1E_MOD_3_REG_7): Likewise.
1321 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1322 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1323 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1324 (PREFIX_0F1E): Likewise.
1325 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1326 (PREFIX_0F38F5): Likewise.
1327 (dis386_twobyte): Use PREFIX_0F1E.
1328 (reg_table): Add REG_0F1E_MOD_3.
1329 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1330 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1331 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1332 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1333 (three_byte_table): Use PREFIX_0F38F5.
1334 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1335 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1336 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1337 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1338 PREFIX_MOD_3_0F01_REG_5_RM_2.
1339 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1340 (cpu_flags): Add CpuCET.
1341 * i386-opc.h (CpuCET): New enum.
1342 (CpuUnused): Commented out.
1343 (i386_cpu_flags): Add cpucet.
1344 * i386-opc.tbl: Add Intel CET instructions.
1345 * i386-init.h: Regenerated.
1346 * i386-tbl.h: Likewise.
1347
73f07bff
AM		 13482017-03-06 Alan Modra <amodra@gmail.com>
1349
1350 PR 21124
1351 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1352 (extract_raq, extract_ras, extract_rbx): New functions.
1353 (powerpc_operands): Use opposite corresponding insert function.
1354 (Q_MASK): Define.
1355 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1356 register restriction.
1357
65b48a81
PB		 13582017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1359
1360 * disassemble.c Include "safe-ctype.h".
1361 (disassemble_init_for_target): Handle s390 init.
1362 (remove_whitespace_and_extra_commas): New function.
1363 (disassembler_options_cmp): Likewise.
1364 * arm-dis.c: Include "libiberty.h".
1365 (NUM_ELEM): Delete.
1366 (regnames): Use long disassembler style names.
1367 Add force-thumb and no-force-thumb options.
1368 (NUM_ARM_REGNAMES): Rename from this...
1369 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1370 (get_arm_regname_num_options): Delete.
1371 (set_arm_regname_option): Likewise.
1372 (get_arm_regnames): Likewise.
1373 (parse_disassembler_options): Likewise.
1374 (parse_arm_disassembler_option): Rename from this...
1375 (parse_arm_disassembler_options): ...to this. Make static.
1376 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1377 (print_insn): Use parse_arm_disassembler_options.
1378 (disassembler_options_arm): New function.
1379 (print_arm_disassembler_options): Handle updated regnames.
1380 * ppc-dis.c: Include "libiberty.h".
1381 (ppc_opts): Add "32" and "64" entries.
1382 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1383 (powerpc_init_dialect): Add break to switch statement.
1384 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1385 (disassembler_options_powerpc): New function.
1386 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1387 Remove printing of "32" and "64".
1388 * s390-dis.c: Include "libiberty.h".
1389 (init_flag): Remove unneeded variable.
1390 (struct s390_options_t): New structure type.
1391 (options): New structure.
1392 (init_disasm): Rename from this...
1393 (disassemble_init_s390): ...to this. Add initializations for
1394 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1395 (print_insn_s390): Delete call to init_disasm.
1396 (disassembler_options_s390): New function.
1397 (print_s390_disassembler_options): Print using information from
1398 struct 'options'.
1399 * po/opcodes.pot: Regenerate.
1400
15c7c1d8
JB		 14012017-02-28 Jan Beulich <jbeulich@suse.com>
1402
1403 * i386-dis.c (PCMPESTR_Fixup): New.
1404 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1405 (prefix_table): Use PCMPESTR_Fixup.
1406 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1407 PCMPESTR_Fixup.
1408 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1409 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1410 Split 64-bit and non-64-bit variants.
1411 * opcodes/i386-tbl.h: Re-generate.
1412
582e12bf
RS		 14132017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1414
1415 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1416 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1417 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1418 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1419 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1420 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1421 (OP_SVE_V_HSD): New macros.
1422 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1423 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1424 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1425 (aarch64_opcode_table): Add new SVE instructions.
1426 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1427 for rotation operands. Add new SVE operands.
1428 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1429 (ins_sve_quad_index): Likewise.
1430 (ins_imm_rotate): Split into...
1431 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1432 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1433 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1434 functions.
1435 (aarch64_ins_sve_addr_ri_s4): New function.
1436 (aarch64_ins_sve_quad_index): Likewise.
1437 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1438 * aarch64-asm-2.c: Regenerate.
1439 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1440 (ext_sve_quad_index): Likewise.
1441 (ext_imm_rotate): Split into...
1442 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1443 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1444 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1445 functions.
1446 (aarch64_ext_sve_addr_ri_s4): New function.
1447 (aarch64_ext_sve_quad_index): Likewise.
1448 (aarch64_ext_sve_index): Allow quad indices.
1449 (do_misc_decoding): Likewise.
1450 * aarch64-dis-2.c: Regenerate.
1451 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1452 aarch64_field_kinds.
1453 (OPD_F_OD_MASK): Widen by one bit.
1454 (OPD_F_NO_ZR): Bump accordingly.
1455 (get_operand_field_width): New function.
1456 * aarch64-opc.c (fields): Add new SVE fields.
1457 (operand_general_constraint_met_p): Handle new SVE operands.
1458 (aarch64_print_operand): Likewise.
1459 * aarch64-opc-2.c: Regenerate.
1460
f482d304
RS		 14612017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1462
1463 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1464 (aarch64_feature_compnum): ...this.
1465 (SIMD_V8_3): Replace with...
1466 (COMPNUM): ...this.
1467 (CNUM_INSN): New macro.
1468 (aarch64_opcode_table): Use it for the complex number instructions.
1469
7db2c588
JB		 14702017-02-24 Jan Beulich <jbeulich@suse.com>
1471
1472 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1473
1e9d41d4
SL		 14742017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1475
1476 Add support for associating SPARC ASIs with an architecture level.
1477 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1478 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1479 decoding of SPARC ASIs.
1480
53c4d625
JB		 14812017-02-23 Jan Beulich <jbeulich@suse.com>
1482
1483 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1484 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1485
11648de5
JB		 14862017-02-21 Jan Beulich <jbeulich@suse.com>
1487
1488 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1489 1 (instead of to itself). Correct typo.
1490
f98d33be
AW		 14912017-02-14 Andrew Waterman <andrew@sifive.com>
1492
1493 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1494 pseudoinstructions.
1495
773fb663
RS		 14962017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1497
1498 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1499 (aarch64_sys_reg_supported_p): Handle them.
1500
cc07cda6
CZ		 15012017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1502
1503 * arc-opc.c (UIMM6_20R): Define.
1504 (SIMM12_20): Use above.
1505 (SIMM12_20R): Define.
1506 (SIMM3_5_S): Use above.
1507 (UIMM7_A32_11R_S): Define.
1508 (UIMM7_9_S): Use above.
1509 (UIMM3_13R_S): Define.
1510 (SIMM11_A32_7_S): Use above.
1511 (SIMM9_8R): Define.
1512 (UIMM10_A32_8_S): Use above.
1513 (UIMM8_8R_S): Define.
1514 (W6): Use above.
1515 (arc_relax_opcodes): Use all above defines.
1516
66a5a740
VG		 15172017-02-15 Vineet Gupta <vgupta@synopsys.com>
1518
1519 * arc-regs.h: Distinguish some of the registers different on
1520 ARC700 and HS38 cpus.
1521
7e0de605
AM		 15222017-02-14 Alan Modra <amodra@gmail.com>
1523
1524 PR 21118
1525 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1526 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1527
54064fdb
AM		 15282017-02-11 Stafford Horne <shorne@gmail.com>
1529 Alan Modra <amodra@gmail.com>
1530
1531 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1532 Use insn_bytes_value and insn_int_value directly instead. Don't
1533 free allocated memory until function exit.
1534
dce75bf9
NP		 15352017-02-10 Nicholas Piggin <npiggin@gmail.com>
1536
1537 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1538
1b7e3d2f
NC		 15392017-02-03 Nick Clifton <nickc@redhat.com>
1540
1541 PR 21096
1542 * aarch64-opc.c (print_register_list): Ensure that the register
1543 list index will fir into the tb buffer.
1544 (print_register_offset_address): Likewise.
1545 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1546
8ec5cf65
AD		 15472017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1548
1549 PR 21056
1550 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1551 instructions when the previous fetch packet ends with a 32-bit
1552 instruction.
1553
a1aa5e81
DD		 15542017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1555
1556 * pru-opc.c: Remove vague reference to a future GDB port.
1557
add3afb2
NC		 15582017-01-20 Nick Clifton <nickc@redhat.com>
1559
1560 * po/ga.po: Updated Irish translation.
1561
c13a63b0
SN		 15622017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1563
1564 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1565
9608051a
YQ		 15662017-01-13 Yao Qi <yao.qi@linaro.org>
1567
1568 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1569 if FETCH_DATA returns 0.
1570 (m68k_scan_mask): Likewise.
1571 (print_insn_m68k): Update code to handle -1 return value.
1572
f622ea96
YQ		 15732017-01-13 Yao Qi <yao.qi@linaro.org>
1574
1575 * m68k-dis.c (enum print_insn_arg_error): New.
1576 (NEXTBYTE): Replace -3 with
1577 PRINT_INSN_ARG_MEMORY_ERROR.
1578 (NEXTULONG): Likewise.
1579 (NEXTSINGLE): Likewise.
1580 (NEXTDOUBLE): Likewise.
1581 (NEXTDOUBLE): Likewise.
1582 (NEXTPACKED): Likewise.
1583 (FETCH_ARG): Likewise.
1584 (FETCH_DATA): Update comments.
1585 (print_insn_arg): Update comments. Replace magic numbers with
1586 enum.
1587 (match_insn_m68k): Likewise.
1588
620214f7
IT		 15892017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1590
1591 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1592 * i386-dis-evex.h (evex_table): Updated.
1593 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1594 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1595 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1596 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1597 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1598 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1599 * i386-init.h: Regenerate.
1600 * i386-tbl.h: Ditto.
1601
d95014a2
YQ		 16022017-01-12 Yao Qi <yao.qi@linaro.org>
1603
1604 * msp430-dis.c (msp430_singleoperand): Return -1 if
1605 msp430dis_opcode_signed returns false.
1606 (msp430_doubleoperand): Likewise.
1607 (msp430_branchinstr): Return -1 if
1608 msp430dis_opcode_unsigned returns false.
1609 (msp430x_calla_instr): Likewise.
1610 (print_insn_msp430): Likewise.
1611
0ae60c3e
NC		 16122017-01-05 Nick Clifton <nickc@redhat.com>
1613
1614 PR 20946
1615 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1616 could not be matched.
1617 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1618 NULL.
1619
d74d4880
SN		 16202017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1621
1622 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1623 (aarch64_opcode_table): Use RCPC_INSN.
1624
cc917fd9
KC		 16252017-01-03 Kito Cheng <kito.cheng@gmail.com>
1626
1627 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1628 extension.
1629 * riscv-opcodes/all-opcodes: Likewise.
1630
b52d3cfc
DP		 16312017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1632
1633 * riscv-dis.c (print_insn_args): Add fall through comment.
1634
f90c58d5
NC		 16352017-01-03 Nick Clifton <nickc@redhat.com>
1636
1637 * po/sr.po: New Serbian translation.
1638 * configure.ac (ALL_LINGUAS): Add sr.
1639 * configure: Regenerate.
1640
f47b0d4a
AM		 16412017-01-02 Alan Modra <amodra@gmail.com>
1642
1643 * epiphany-desc.h: Regenerate.
1644 * epiphany-opc.h: Regenerate.
1645 * fr30-desc.h: Regenerate.
1646 * fr30-opc.h: Regenerate.
1647 * frv-desc.h: Regenerate.
1648 * frv-opc.h: Regenerate.
1649 * ip2k-desc.h: Regenerate.
1650 * ip2k-opc.h: Regenerate.
1651 * iq2000-desc.h: Regenerate.
1652 * iq2000-opc.h: Regenerate.
1653 * lm32-desc.h: Regenerate.
1654 * lm32-opc.h: Regenerate.
1655 * m32c-desc.h: Regenerate.
1656 * m32c-opc.h: Regenerate.
1657 * m32r-desc.h: Regenerate.
1658 * m32r-opc.h: Regenerate.
1659 * mep-desc.h: Regenerate.
1660 * mep-opc.h: Regenerate.
1661 * mt-desc.h: Regenerate.
1662 * mt-opc.h: Regenerate.
1663 * or1k-desc.h: Regenerate.
1664 * or1k-opc.h: Regenerate.
1665 * xc16x-desc.h: Regenerate.
1666 * xc16x-opc.h: Regenerate.
1667 * xstormy16-desc.h: Regenerate.
1668 * xstormy16-opc.h: Regenerate.
1669
2571583a
AM		 16702017-01-02 Alan Modra <amodra@gmail.com>
1671
1672 Update year range in copyright notice of all files.
1673
5c1ad6b5 1674For older changes see ChangeLog-2016
3499769a 1675\f
5c1ad6b5 1676Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1677
1678Copying and distribution of this file, with or without modification,
1679are permitted in any medium without royalty provided the copyright
1680notice and this notice are preserved.
1681
1682Local Variables:
1683mode: change-log
1684left-margin: 8
1685fill-column: 74
1686version-control: never
1687End:
GDB Binutils - Deliverables
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