[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

2013-02-27  Alan Modra  <amodra@gmail.com>

	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	* rl78-decode.c: Regenerate.

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
e60bb1dd YZ	1	2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
	2
	3	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	4	(aarch64_feature_crc): New static.
	5	(CRC): New macro.
	6	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	7	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	8	* aarch64-asm-2.c: Re-generate.
	9	* aarch64-dis-2.c: Ditto.
	10	* aarch64-opc-2.c: Ditto.
	11
c7570fcd AM	12	2013-02-27 Alan Modra <amodra@gmail.com>
	13
	14	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	15	* rl78-decode.c: Regenerate.
	16
151fa98f NC	17	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	18
	19	* rl78-decode.opc: Fix encoding of DIVWU insn.
	20	* rl78-decode.c: Regenerate.
	21
5c111e37 L	22	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	23
	24	PR gas/15159
	25	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	26
	27	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	28	(cpu_flags): Add CpuSMAP.
	29
	30	* i386-opc.h (CpuSMAP): New.
	31	(i386_cpu_flags): Add cpusmap.
	32
	33	* i386-opc.tbl: Add clac and stac.
	34
	35	* i386-init.h: Regenerated.
	36	* i386-tbl.h: Likewise.
	37
9d1df426 NC	38	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	39
	40	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	41	which also makes the disassembler output be in little
	42	endian like it should be.
	43
a1ccaec9 YZ	44	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	45
	46	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	47	fields to NULL.
	48	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	49
ef068ef4	50	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	51
	52	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	53	section disassembled.
	54
6fe6ded9 RE	55	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	56
	57	* arm-dis.c: Update strht pattern.
	58
0aa27725 RS	59	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	60
	61	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	62	single-float. Disable ll, lld, sc and scd for EE. Disable the
	63	trunc.w.s macro for EE.
	64
36591ba1 SL	65	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	66	Andrew Jenner <andrew@codesourcery.com>
	67
	68	Based on patches from Altera Corporation.
	69
	70	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	71	nios2-opc.c.
	72	* Makefile.in: Regenerated.
	73	* configure.in: Add case for bfd_nios2_arch.
	74	* configure: Regenerated.
	75	* disassemble.c (ARCH_nios2): Define.
	76	(disassembler): Add case for bfd_arch_nios2.
	77	* nios2-dis.c: New file.
	78	* nios2-opc.c: New file.
	79
545093a4 AM	80	2013-02-04 Alan Modra <amodra@gmail.com>
	81
	82	* po/POTFILES.in: Regenerate.
	83	* rl78-decode.c: Regenerate.
	84	* rx-decode.c: Regenerate.
	85
e30181a5 YZ	86	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	87
	88	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	89	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	90	* aarch64-asm.c (convert_xtl_to_shll): New function.
	91	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	92	calling convert_xtl_to_shll.
	93	* aarch64-dis.c (convert_shll_to_xtl): New function.
	94	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	95	calling convert_shll_to_xtl.
	96	* aarch64-gen.c: Update copyright year.
	97	* aarch64-asm-2.c: Re-generate.
	98	* aarch64-dis-2.c: Re-generate.
	99	* aarch64-opc-2.c: Re-generate.
	100
78c8d46c NC	101	2013-01-24 Nick Clifton <nickc@redhat.com>
	102
	103	* v850-dis.c: Add support for e3v5 architecture.
	104	* v850-opc.c: Likewise.
	105
f5555712 YZ	106	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	107
	108	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	109	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	110	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	111	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	112	alignment check; change to call set_sft_amount_out_of_range_error
	113	instead of set_imm_out_of_range_error.
	114	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	115	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	116	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	117	SIMD_IMM_SFT.
	118
2f81ff92 L	119	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	120
	121	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	122
	123	* i386-init.h: Regenerated.
	124	* i386-tbl.h: Likewise.
	125
dd42f060 NC	126	2013-01-15 Nick Clifton <nickc@redhat.com>
	127
	128	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	129	values.
	130	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	131
a4533ed8 NC	132	2013-01-14 Will Newton <will.newton@imgtec.com>
	133
	134	* metag-dis.c (REG_WIDTH): Increase to 64.
	135
5817ffd1 PB	136	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	137
	138	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	139	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	140	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	141	(SH6): Update.
	142	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	143	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	144	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	145	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	146
a3c62988 NC	147	2013-01-10 Will Newton <will.newton@imgtec.com>
	148
	149	* Makefile.am: Add Meta.
	150	* configure.in: Add Meta.
	151	* disassemble.c: Add Meta support.
	152	* metag-dis.c: New file.
	153	* Makefile.in: Regenerate.
	154	* configure: Regenerate.
	155
73335eae NC	156	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	157
	158	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	159	(match_opcode): Rename to cr16_match_opcode.
	160
e407c74b NC	161	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	162
	163	* mips-dis.c: Add names for CP0 registers of r5900.
	164	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	165	instructions sq and lq.
	166	Add support for MIPS r5900 CPU.
	167	Add support for 128 bit MMI (Multimedia Instructions).
	168	Add support for EE instructions (Emotion Engine).
	169	Disable unsupported floating point instructions (64 bit and
	170	undefined compare operations).
	171	Enable instructions of MIPS ISA IV which are supported by r5900.
	172	Disable 64 bit co processor instructions.
	173	Disable 64 bit multiplication and division instructions.
	174	Disable instructions for co-processor 2 and 3, because these are
	175	not supported (preparation for later VU0 support (Vector Unit)).
	176	Disable cvt.w.s because this behaves like trunc.w.s and the
	177	correct execution can't be ensured on r5900.
	178	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	179	will confuse less developers and compilers.
	180
a32c3ff8 NC	181	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	182
fb098a1e YZ	183	* aarch64-opc.c (aarch64_print_operand): Change to print
	184	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	185	in comment.
	186	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	187	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	188	OP_MOV_IMM_WIDE.
	189
	190	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	191
	192	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	193	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	194
62658407 L	195	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	196
	197	* i386-gen.c (process_copyright): Update copyright year to 2013.
	198
bab4becb	199	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	200
bab4becb NC	201	* cr16-dis.c (match_opcode,make_instruction): Remove static
	202	declaration.
	203	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	204	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	205
bab4becb	206	For older changes see ChangeLog-2012
252b5132	207	\f
bab4becb	208	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	209
	210	Copying and distribution of this file, with or without modification,
	211	are permitted in any medium without royalty provided the copyright
	212	notice and this notice are preserved.
	213
252b5132	214	Local Variables:
2f6d2f85 NC	215	mode: change-log
	216	left-margin: 8
	217	fill-column: 74
252b5132 RH	218	version-control: never
252b5132 RH	219	End: