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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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0f35dbc4
RS		 12013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
4 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
5 and OPTIONAL_MAPPED_REG.
6 * mips-opc.c (decode_mips_operand): Likewise.
7 * mips16-opc.c (decode_mips16_operand): Likewise.
8 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
9
79ceb7cb
L		 102013-08-19 H.J. Lu <hongjiu.lu@intel.com>
11
12 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
13 (PREFIX_EVEX_0F3A3F): Likewise.
14 * i386-dis-evex.h (evex_table): Updated.
15
ee5734f0
RS		 162013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
17
18 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
19 VCLIPW.
20
d6787ef9
EB		 212013-08-05 Eric Botcazou <ebotcazou@adacore.com>
22 Konrad Eisele <konrad@gaisler.com>
23
24 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
25 bfd_mach_sparc.
26 * sparc-opc.c (MASK_LEON): Define.
27 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
28 (letandleon): New macro.
29 (v9andleon): Likewise.
30 (sparc_opc): Add leon.
31 (umac): Enable for letandleon.
32 (smac): Likewise.
33 (casa): Enable for v9andleon.
34 (cas): Likewise.
35 (casl): Likewise.
36
14daeee3
RS		 372013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
38 Richard Sandiford <rdsandiford@googlemail.com>
39
40 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
41 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
42 (print_vu0_channel): New function.
43 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
44 (print_insn_args): Handle '#'.
45 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
46 * mips-opc.c (mips_vu0_channel_mask): New constant.
47 (decode_mips_operand): Handle new VU0 operand types.
48 (VU0, VU0CH): New macros.
49 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
50 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
51 Use "+6" rather than "G" for QMFC2 and QMTC2.
52
3ccad066
RS		 532013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
54
55 * mips-formats.h (PCREL): Reorder parameters and update the definition
56 to match new mips_pcrel_operand layout.
57 (JUMP, JALX, BRANCH): Update accordingly.
58 * mips16-opc.c (decode_mips16_operand): Likewise.
59
df34fbcc
RS		 602013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
61
62 * micromips-opc.c (WR_s): Delete.
63
fc76e730
RS		 642013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
65
66 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
67 New macros.
68 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
69 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
70 (mips_builtin_opcodes): Use the new position-based read-write flags
71 instead of field-based ones. Use UDI for "udi..." instructions.
72 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
73 New macros.
74 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
75 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
76 (WR_SP, RD_16): New macros.
77 (RD_SP): Redefine as an INSN2_* flag.
78 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
79 (mips16_opcodes): Use the new position-based read-write flags
80 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
81 pinfo2 field.
82 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
83 New macros.
84 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
85 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
86 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
87 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
88 (micromips_opcodes): Use the new position-based read-write flags
89 instead of field-based ones.
90 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
91 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
92 of field-based flags.
93
26545944
RS		 942013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
95
96 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
97 (WR_SP): Replace with...
98 (MOD_SP): ...this.
99 (mips16_opcodes): Update accordingly.
100 * mips-dis.c (print_insn_mips16): Likewise.
101
a8d92fc6
RS		 1022013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
103
104 * mips16-opc.c (mips16_opcodes): Reformat.
105
6a819047
RS		 1062013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
107
108 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
109 for operands that are hard-coded to $0.
110 * micromips-opc.c (micromips_opcodes): Likewise.
111
344c74a6
RS		 1122013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
113
114 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
115 for the single-operand forms of JALR and JALR.HB.
116 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
117 and JALRS.HB.
118
41989114
RS		 1192013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
120
121 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
122 instructions. Fix them to use WR_MACC instead of WR_CC and
123 add missing RD_MACCs.
124
6d075bce
RS		 1252013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
126
127 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
128
4f6ffcd3
PB		 1292013-07-29 Peter Bergner <bergner@vnet.ibm.com>
130
131 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
132
43234a1e
L		 1332013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
134 Alexander Ivchenko <alexander.ivchenko@intel.com>
135 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
136 Sergey Lega <sergey.s.lega@intel.com>
137 Anna Tikhonova <anna.tikhonova@intel.com>
138 Ilya Tocar <ilya.tocar@intel.com>
139 Andrey Turetskiy <andrey.turetskiy@intel.com>
140 Ilya Verbin <ilya.verbin@intel.com>
141 Kirill Yukhin <kirill.yukhin@intel.com>
142 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
143
144 * i386-dis-evex.h: New.
145 * i386-dis.c (OP_Rounding): New.
146 (VPCMP_Fixup): New.
147 (OP_Mask): New.
148 (Rdq): New.
149 (XMxmmq): New.
150 (EXdScalarS): New.
151 (EXymm): New.
152 (EXEvexHalfBcstXmmq): New.
153 (EXxmm_mdq): New.
154 (EXEvexXGscat): New.
155 (EXEvexXNoBcst): New.
156 (VPCMP): New.
157 (EXxEVexR): New.
158 (EXxEVexS): New.
159 (XMask): New.
160 (MaskG): New.
161 (MaskE): New.
162 (MaskR): New.
163 (MaskVex): New.
164 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
165 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
166 evex_rounding_mode, evex_sae_mode, mask_mode.
167 (USE_EVEX_TABLE): New.
168 (EVEX_TABLE): New.
169 (EVEX enum): New.
170 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
171 REG_EVEX_0F38C7.
172 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
173 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
174 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
175 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
176 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
177 MOD_EVEX_0F38C7_REG_6.
178 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
179 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
180 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
181 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
182 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
183 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
184 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
185 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
186 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
187 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
188 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
189 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
190 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
191 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
192 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
193 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
194 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
195 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
196 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
197 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
198 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
199 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
200 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
201 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
202 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
203 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
204 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
205 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
206 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
207 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
208 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
209 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
210 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
211 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
212 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
213 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
214 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
215 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
216 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
217 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
218 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
219 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
220 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
221 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
222 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
223 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
224 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
225 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
226 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
227 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
228 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
229 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
230 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
231 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
232 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
233 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
234 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
235 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
236 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
237 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
238 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
239 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
240 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
241 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
242 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
243 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
244 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
245 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
246 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
247 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
248 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
249 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
250 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
251 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
252 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
253 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
254 PREFIX_EVEX_0F3A55.
255 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
256 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
257 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
258 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
259 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
260 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
261 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
262 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
263 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
264 VEX_W_0F3A32_P_2_LEN_0.
265 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
266 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
267 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
268 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
269 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
270 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
271 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
272 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
273 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
274 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
275 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
276 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
277 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
278 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
279 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
280 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
281 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
282 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
283 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
284 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
285 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
286 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
287 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
288 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
289 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
290 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
291 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
292 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
293 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
294 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
295 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
296 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
297 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
298 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
299 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
300 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
301 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
302 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
303 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
304 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
305 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
306 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
307 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
308 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
309 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
310 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
311 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
312 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
313 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
314 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
315 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
316 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
317 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
318 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
319 (struct vex): Add fields evex, r, v, mask_register_specifier,
320 zeroing, ll, b.
321 (intel_names_xmm): Add upper 16 registers.
322 (att_names_xmm): Ditto.
323 (intel_names_ymm): Ditto.
324 (att_names_ymm): Ditto.
325 (names_zmm): New.
326 (intel_names_zmm): Ditto.
327 (att_names_zmm): Ditto.
328 (names_mask): Ditto.
329 (intel_names_mask): Ditto.
330 (att_names_mask): Ditto.
331 (names_rounding): Ditto.
332 (names_broadcast): Ditto.
333 (x86_64_table): Add escape to evex-table.
334 (reg_table): Include reg_table evex-entries from
335 i386-dis-evex.h. Fix prefetchwt1 instruction.
336 (prefix_table): Add entries for new instructions.
337 (vex_table): Ditto.
338 (vex_len_table): Ditto.
339 (vex_w_table): Ditto.
340 (mod_table): Ditto.
341 (get_valid_dis386): Properly handle new instructions.
342 (print_insn): Handle zmm and mask registers, print mask operand.
343 (intel_operand_size): Support EVEX, new modes and sizes.
344 (OP_E_register): Handle new modes.
345 (OP_E_memory): Ditto.
346 (OP_G): Ditto.
347 (OP_XMM): Ditto.
348 (OP_EX): Ditto.
349 (OP_VEX): Ditto.
350 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
351 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
352 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
353 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
354 CpuAVX512PF and CpuVREX.
355 (operand_type_init): Add OPERAND_TYPE_REGZMM,
356 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
357 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
358 StaticRounding, SAE, Disp8MemShift, NoDefMask.
359 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
360 * i386-init.h: Regenerate.
361 * i386-opc.h (CpuAVX512F): New.
362 (CpuAVX512CD): New.
363 (CpuAVX512ER): New.
364 (CpuAVX512PF): New.
365 (CpuVREX): New.
366 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
367 cpuavx512pf and cpuvrex fields.
368 (VecSIB): Add VecSIB512.
369 (EVex): New.
370 (Masking): New.
371 (VecESize): New.
372 (Broadcast): New.
373 (StaticRounding): New.
374 (SAE): New.
375 (Disp8MemShift): New.
376 (NoDefMask): New.
377 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
378 staticrounding, sae, disp8memshift and nodefmask.
379 (RegZMM): New.
380 (Zmmword): Ditto.
381 (Vec_Disp8): Ditto.
382 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
383 fields.
384 (RegVRex): New.
385 * i386-opc.tbl: Add AVX512 instructions.
386 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
387 registers, mask registers.
388 * i386-tbl.h: Regenerate.
389
1d2db237
RS		 3902013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
391
392 PR gas/15220
393 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
394 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
395
a0046408
L		 3962013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
397
398 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
399 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
400 PREFIX_0F3ACC.
401 (prefix_table): Updated.
402 (three_byte_table): Likewise.
403 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
404 (cpu_flags): Add CpuSHA.
405 (i386_cpu_flags): Add cpusha.
406 * i386-init.h: Regenerate.
407 * i386-opc.h (CpuSHA): New.
408 (CpuUnused): Restored.
409 (i386_cpu_flags): Add cpusha.
410 * i386-opc.tbl: Add SHA instructions.
411 * i386-tbl.h: Regenerate.
412
7e8b059b
L		 4132013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
414 Kirill Yukhin <kirill.yukhin@intel.com>
415 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
416
417 * i386-dis.c (BND_Fixup): New.
418 (Ebnd): New.
419 (Ev_bnd): New.
420 (Gbnd): New.
421 (BND): New.
422 (v_bnd_mode): New.
423 (bnd_mode): New.
c623f86c
L		 424 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
425 MOD_0F1B_PREFIX_1.
426 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 427 (dis tables): Replace XX with BND for near branch and call
428 instructions.
429 (prefix_table): Add new entries.
430 (mod_table): Likewise.
431 (names_bnd): New.
432 (intel_names_bnd): New.
433 (att_names_bnd): New.
434 (BND_PREFIX): New.
435 (prefix_name): Handle BND_PREFIX.
436 (print_insn): Initialize names_bnd.
437 (intel_operand_size): Handle new modes.
438 (OP_E_register): Likewise.
439 (OP_E_memory): Likewise.
440 (OP_G): Likewise.
441 * i386-gen.c (cpu_flag_init): Add CpuMPX.
442 (cpu_flags): Add CpuMPX.
443 (operand_type_init): Add RegBND.
444 (opcode_modifiers): Add BNDPrefixOk.
445 (operand_types): Add RegBND.
446 * i386-init.h: Regenerate.
447 * i386-opc.h (CpuMPX): New.
448 (CpuUnused): Comment out.
449 (i386_cpu_flags): Add cpumpx.
450 (BNDPrefixOk): New.
451 (i386_opcode_modifier): Add bndprefixok.
452 (RegBND): New.
453 (i386_operand_type): Add regbnd.
454 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
455 Add MPX instructions and bnd prefix.
456 * i386-reg.tbl: Add bnd0-bnd3 registers.
457 * i386-tbl.h: Regenerate.
458
b56e23fb
RS		 4592013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
460
461 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
462 ATTRIBUTE_UNUSED.
463
e7ae278d
RS		 4642013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
465
466 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
467 special rules.
468 * Makefile.in: Regenerate.
469 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
470 all fields. Reformat.
471
c3c07478
RS		 4722013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
473
474 * mips16-opc.c: Include mips-formats.h.
475 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
476 static arrays.
477 (decode_mips16_operand): New function.
478 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
479 (print_insn_arg): Handle OP_ENTRY_EXIT list.
480 Abort for OP_SAVE_RESTORE_LIST.
481 (print_mips16_insn_arg): Change interface. Use mips_operand
482 structures. Delete GET_OP_S. Move GET_OP definition to...
483 (print_insn_mips16): ...here. Call init_print_arg_state.
484 Update the call to print_mips16_insn_arg.
485
ab902481
RS		 4862013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
487
488 * mips-formats.h: New file.
489 * mips-opc.c: Include mips-formats.h.
490 (reg_0_map): New static array.
491 (decode_mips_operand): New function.
492 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
493 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
494 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
495 (int_c_map): New static arrays.
496 (decode_micromips_operand): New function.
497 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
498 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
499 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
500 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
501 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
502 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
503 (micromips_imm_b_map, micromips_imm_c_map): Delete.
504 (print_reg): New function.
505 (mips_print_arg_state): New structure.
506 (init_print_arg_state, print_insn_arg): New functions.
507 (print_insn_args): Change interface and use mips_operand structures.
508 Delete GET_OP_S. Move GET_OP definition to...
509 (print_insn_mips): ...here. Update the call to print_insn_args.
510 (print_insn_micromips): Use print_insn_args.
511
cc537e56
RS		 5122013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
513
514 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
515 in macros.
516
7a5f87ce
RS		 5172013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
518
519 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
520 ADDA.S, MULA.S and SUBA.S.
521
41741fa4
L		 5222013-07-08 H.J. Lu <hongjiu.lu@intel.com>
523
524 PR gas/13572
525 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
526 * i386-tbl.h: Regenerated.
527
f2ae14a1
RS		 5282013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
529
530 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
531 and SD A(B) macros up.
532 * micromips-opc.c (micromips_opcodes): Likewise.
533
04c9d415
RS		 5342013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
535
536 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
537 instructions.
538
5c324c16
RS		 5392013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
540
541 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
542 MDMX-like instructions.
543 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
544 printing "Q" operands for INSN_5400 instructions.
545
23e69e47
RS		 5462013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
547
548 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
549 "+S" for "cins".
550 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
551 Combine cases.
552
27c5c572
RS		 5532013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
554
555 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
556 "jalx".
557 * mips16-opc.c (mips16_opcodes): Likewise.
558 * micromips-opc.c (micromips_opcodes): Likewise.
559 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
560 (print_insn_mips16): Handle "+i".
561 (print_insn_micromips): Likewise. Conditionally preserve the
562 ISA bit for "a" but not for "+i".
563
e76ff5ab
RS		 5642013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
565
566 * micromips-opc.c (WR_mhi): Rename to..
567 (WR_mh): ...this.
568 (micromips_opcodes): Update "movep" entry accordingly. Replace
569 "mh,mi" with "mh".
570 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
571 (micromips_to_32_reg_h_map1): ...this.
572 (micromips_to_32_reg_i_map): Rename to...
573 (micromips_to_32_reg_h_map2): ...this.
574 (print_micromips_insn): Remove "mi" case. Print both registers
575 in the pair for "mh".
576
fa7616a4
RS		 5772013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
578
579 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
580 * micromips-opc.c (micromips_opcodes): Likewise.
581 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
582 and "+T" handling. Check for a "0" suffix when deciding whether to
583 use coprocessor 0 names. In that case, also check for ",H" selectors.
584
fb798c50
AK		 5852013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
586
587 * s390-opc.c (J12_12, J24_24): New macros.
588 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
589 (MASK_MII_UPI): Rename to MASK_MII_UPP.
590 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
591
58ae08f2
AM		 5922013-07-04 Alan Modra <amodra@gmail.com>
593
594 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
595
b5e04c2b
NC		 5962013-06-26 Nick Clifton <nickc@redhat.com>
597
598 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
599 field when checking for type 2 nop.
600 * rx-decode.c: Regenerate.
601
833794fc
MR		 6022013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
603
604 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
605 and "movep" macros.
606
1bbce132
MR		 6072013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
608
609 * mips-dis.c (is_mips16_plt_tail): New function.
610 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
611 word.
612 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
613
34c911a4
NC		 6142013-06-21 DJ Delorie <dj@redhat.com>
615
616 * msp430-decode.opc: New.
617 * msp430-decode.c: New/generated.
618 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
619 (MAINTAINER_CLEANFILES): Likewise.
620 Add rule to build msp430-decode.c frommsp430decode.opc
621 using the opc2c program.
622 * Makefile.in: Regenerate.
623 * configure.in: Add msp430-decode.lo to msp430 architecture files.
624 * configure: Regenerate.
625
b9eead84
YZ		 6262013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
627
628 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
629 (SYMTAB_AVAILABLE): Removed.
630 (#include "elf/aarch64.h): Ditto.
631
7f3c4072
CM		 6322013-06-17 Catherine Moore <clm@codesourcery.com>
633 Maciej W. Rozycki <macro@codesourcery.com>
634 Chao-Ying Fu <fu@mips.com>
635
636 * micromips-opc.c (EVA): Define.
637 (TLBINV): Define.
638 (micromips_opcodes): Add EVA opcodes.
639 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
640 (print_insn_args): Handle EVA offsets.
641 (print_insn_micromips): Likewise.
642 * mips-opc.c (EVA): Define.
643 (TLBINV): Define.
644 (mips_builtin_opcodes): Add EVA opcodes.
645
de40ceb6
AM		 6462013-06-17 Alan Modra <amodra@gmail.com>
647
648 * Makefile.am (mips-opc.lo): Add rules to create automatic
649 dependency files. Pass archdefs.
650 (micromips-opc.lo, mips16-opc.lo): Likewise.
651 * Makefile.in: Regenerate.
652
3531d549
DD		 6532013-06-14 DJ Delorie <dj@redhat.com>
654
655 * rx-decode.opc (rx_decode_opcode): Bit operations on
656 registers are 32-bit operations, not 8-bit operations.
657 * rx-decode.c: Regenerate.
658
ba92f7fb
CF		 6592013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
660
661 * micromips-opc.c (IVIRT): New define.
662 (IVIRT64): New define.
663 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
664 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
665
666 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
667 dmtgc0 to print cp0 names.
668
9daf7bab
SL		 6692013-06-09 Sandra Loosemore <sandra@codesourcery.com>
670
671 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
672 argument.
673
d301a56b
RS		 6742013-06-08 Catherine Moore <clm@codesourcery.com>
675 Richard Sandiford <rdsandiford@googlemail.com>
676
677 * micromips-opc.c (D32, D33, MC): Update definitions.
678 (micromips_opcodes): Initialize ase field.
679 * mips-dis.c (mips_arch_choice): Add ase field.
680 (mips_arch_choices): Initialize ase field.
681 (set_default_mips_dis_options): Declare and setup mips_ase.
682 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
683 MT32, MC): Update definitions.
684 (mips_builtin_opcodes): Initialize ase field.
685
a3dcb6c5
RS		 6862013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
687
688 * s390-opc.txt (flogr): Require a register pair destination.
689
6cf1d90c
AK		 6902013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
691
692 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
693 instruction format.
694
c77c0862
RS		 6952013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
696
697 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
698
c0637f3a
PB		 6992013-05-20 Peter Bergner <bergner@vnet.ibm.com>
700
701 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
702 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
703 XLS_MASK, PPCVSX2): New defines.
704 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
705 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
706 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
707 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
708 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
709 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
710 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
711 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
712 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
713 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
714 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
715 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
716 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
717 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
718 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
719 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
720 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
721 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
722 <lxvx, stxvx>: New extended mnemonics.
723
4934fdaf
AM		 7242013-05-17 Alan Modra <amodra@gmail.com>
725
726 * ia64-raw.tbl: Replace non-ASCII char.
727 * ia64-waw.tbl: Likewise.
728 * ia64-asmtab.c: Regenerate.
729
6091d651
SE		 7302013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
731
732 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
733 * i386-init.h: Regenerated.
734
d2865ed3
YZ		 7352013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
736
737 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
738 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
739 check from [0, 255] to [-128, 255].
740
b015e599
AP		 7412013-05-09 Andrew Pinski <apinski@cavium.com>
742
743 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
744 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
745 (parse_mips_dis_option): Handle the virt option.
746 (print_insn_args): Handle "+J".
747 (print_mips_disassembler_options): Print out message about virt64.
748 * mips-opc.c (IVIRT): New define.
749 (IVIRT64): New define.
750 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
751 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
752 Move rfe to the bottom as it conflicts with tlbgp.
753
9f0682fe
AM		 7542013-05-09 Alan Modra <amodra@gmail.com>
755
756 * ppc-opc.c (extract_vlesi): Properly sign extend.
757 (extract_vlensi): Likewise. Comment reason for setting invalid.
758
13761a11
NC		 7592013-05-02 Nick Clifton <nickc@redhat.com>
760
761 * msp430-dis.c: Add support for MSP430X instructions.
762
e3031850
SL		 7632013-04-24 Sandra Loosemore <sandra@codesourcery.com>
764
765 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
766 to "eccinj".
767
17310e56
NC		 7682013-04-17 Wei-chen Wang <cole945@gmail.com>
769
770 PR binutils/15369
771 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
772 of CGEN_CPU_ENDIAN.
773 (hash_insns_list): Likewise.
774
731df338
JK		 7752013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
776
777 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
778 warning workaround.
779
5f77db52
JB		 7802013-04-08 Jan Beulich <jbeulich@suse.com>
781
782 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
783 * i386-tbl.h: Re-generate.
784
0afd1215
DM		 7852013-04-06 David S. Miller <davem@davemloft.net>
786
787 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
788 of an opcode, prefer the one with F_PREFERRED set.
789 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
790 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
791 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
792 mark existing mnenomics as aliases. Add "cc" suffix to edge
793 instructions generating condition codes, mark existing mnenomics
794 as aliases. Add "fp" prefix to VIS compare instructions, mark
795 existing mnenomics as aliases.
796
41702d50
NC		 7972013-04-03 Nick Clifton <nickc@redhat.com>
798
799 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
800 destination address by subtracting the operand from the current
801 address.
802 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
803 a positive value in the insn.
804 (extract_u16_loop): Do not negate the returned value.
805 (D16_LOOP): Add V850_INVERSE_PCREL flag.
806
807 (ceilf.sw): Remove duplicate entry.
808 (cvtf.hs): New entry.
809 (cvtf.sh): Likewise.
810 (fmaf.s): Likewise.
811 (fmsf.s): Likewise.
812 (fnmaf.s): Likewise.
813 (fnmsf.s): Likewise.
814 (maddf.s): Restrict to E3V5 architectures.
815 (msubf.s): Likewise.
816 (nmaddf.s): Likewise.
817 (nmsubf.s): Likewise.
818
55cf16e1
L		 8192013-03-27 H.J. Lu <hongjiu.lu@intel.com>
820
821 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
822 check address mode.
823 (print_insn): Pass sizeflag to get_sib.
824
51dcdd4d
NC		 8252013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
826
827 PR binutils/15068
828 * tic6x-dis.c: Add support for displaying 16-bit insns.
829
795b8e6b
NC		 8302013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
831
832 PR gas/15095
833 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
834 individual msb and lsb halves in src1 & src2 fields. Discard the
835 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
836 follow what Ti SDK does in that case as any value in the src1
837 field yields the same output with SDK disassembler.
838
314d60dd
ME		 8392013-03-12 Michael Eager <eager@eagercon.com>
840
795b8e6b 841 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 842
dad60f8e
SL		 8432013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
844
845 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
846
f5cb796a
SL		 8472013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
848
849 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
850
21fde85c
SL		 8512013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
852
853 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
854
dd5181d5
KT		 8552013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
856
857 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
858 (thumb32_opcodes): Likewise.
859 (print_insn_thumb32): Handle 'S' control char.
860
87a8d6cb
NC		 8612013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
862
863 * lm32-desc.c: Regenerate.
864
99dce992
L		 8652013-03-01 H.J. Lu <hongjiu.lu@intel.com>
866
867 * i386-reg.tbl (riz): Add RegRex64.
868 * i386-tbl.h: Regenerated.
869
e60bb1dd
YZ		 8702013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
871
872 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
873 (aarch64_feature_crc): New static.
874 (CRC): New macro.
875 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
876 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
877 * aarch64-asm-2.c: Re-generate.
878 * aarch64-dis-2.c: Ditto.
879 * aarch64-opc-2.c: Ditto.
880
c7570fcd
AM		 8812013-02-27 Alan Modra <amodra@gmail.com>
882
883 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
884 * rl78-decode.c: Regenerate.
885
151fa98f
NC		 8862013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
887
888 * rl78-decode.opc: Fix encoding of DIVWU insn.
889 * rl78-decode.c: Regenerate.
890
5c111e37
L		 8912013-02-19 H.J. Lu <hongjiu.lu@intel.com>
892
893 PR gas/15159
894 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
895
896 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
897 (cpu_flags): Add CpuSMAP.
898
899 * i386-opc.h (CpuSMAP): New.
900 (i386_cpu_flags): Add cpusmap.
901
902 * i386-opc.tbl: Add clac and stac.
903
904 * i386-init.h: Regenerated.
905 * i386-tbl.h: Likewise.
906
9d1df426
NC		 9072013-02-15 Markos Chandras <markos.chandras@imgtec.com>
908
909 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
910 which also makes the disassembler output be in little
911 endian like it should be.
912
a1ccaec9
YZ		 9132013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
914
915 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
916 fields to NULL.
917 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
918
ef068ef4 9192013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 920
921 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
922 section disassembled.
923
6fe6ded9
RE		 9242013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
925
926 * arm-dis.c: Update strht pattern.
927
0aa27725
RS		 9282013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
929
930 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
931 single-float. Disable ll, lld, sc and scd for EE. Disable the
932 trunc.w.s macro for EE.
933
36591ba1
SL		 9342013-02-06 Sandra Loosemore <sandra@codesourcery.com>
935 Andrew Jenner <andrew@codesourcery.com>
936
937 Based on patches from Altera Corporation.
938
939 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
940 nios2-opc.c.
941 * Makefile.in: Regenerated.
942 * configure.in: Add case for bfd_nios2_arch.
943 * configure: Regenerated.
944 * disassemble.c (ARCH_nios2): Define.
945 (disassembler): Add case for bfd_arch_nios2.
946 * nios2-dis.c: New file.
947 * nios2-opc.c: New file.
948
545093a4
AM		 9492013-02-04 Alan Modra <amodra@gmail.com>
950
951 * po/POTFILES.in: Regenerate.
952 * rl78-decode.c: Regenerate.
953 * rx-decode.c: Regenerate.
954
e30181a5
YZ		 9552013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
956
957 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
958 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
959 * aarch64-asm.c (convert_xtl_to_shll): New function.
960 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
961 calling convert_xtl_to_shll.
962 * aarch64-dis.c (convert_shll_to_xtl): New function.
963 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
964 calling convert_shll_to_xtl.
965 * aarch64-gen.c: Update copyright year.
966 * aarch64-asm-2.c: Re-generate.
967 * aarch64-dis-2.c: Re-generate.
968 * aarch64-opc-2.c: Re-generate.
969
78c8d46c
NC		 9702013-01-24 Nick Clifton <nickc@redhat.com>
971
972 * v850-dis.c: Add support for e3v5 architecture.
973 * v850-opc.c: Likewise.
974
f5555712
YZ		 9752013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
976
977 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
978 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
979 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 980 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 981 alignment check; change to call set_sft_amount_out_of_range_error
982 instead of set_imm_out_of_range_error.
983 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
984 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
985 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
986 SIMD_IMM_SFT.
987
2f81ff92
L		 9882013-01-16 H.J. Lu <hongjiu.lu@intel.com>
989
990 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
991
992 * i386-init.h: Regenerated.
993 * i386-tbl.h: Likewise.
994
dd42f060
NC		 9952013-01-15 Nick Clifton <nickc@redhat.com>
996
997 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
998 values.
999 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1000
a4533ed8
NC		 10012013-01-14 Will Newton <will.newton@imgtec.com>
1002
1003 * metag-dis.c (REG_WIDTH): Increase to 64.
1004
5817ffd1
PB		 10052013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1006
1007 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1008 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1009 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1010 (SH6): Update.
1011 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1012 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1013 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1014 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1015
a3c62988
NC		 10162013-01-10 Will Newton <will.newton@imgtec.com>
1017
1018 * Makefile.am: Add Meta.
1019 * configure.in: Add Meta.
1020 * disassemble.c: Add Meta support.
1021 * metag-dis.c: New file.
1022 * Makefile.in: Regenerate.
1023 * configure: Regenerate.
1024
73335eae
NC		 10252013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1026
1027 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1028 (match_opcode): Rename to cr16_match_opcode.
1029
e407c74b
NC		 10302013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1031
1032 * mips-dis.c: Add names for CP0 registers of r5900.
1033 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1034 instructions sq and lq.
1035 Add support for MIPS r5900 CPU.
1036 Add support for 128 bit MMI (Multimedia Instructions).
1037 Add support for EE instructions (Emotion Engine).
1038 Disable unsupported floating point instructions (64 bit and
1039 undefined compare operations).
1040 Enable instructions of MIPS ISA IV which are supported by r5900.
1041 Disable 64 bit co processor instructions.
1042 Disable 64 bit multiplication and division instructions.
1043 Disable instructions for co-processor 2 and 3, because these are
1044 not supported (preparation for later VU0 support (Vector Unit)).
1045 Disable cvt.w.s because this behaves like trunc.w.s and the
1046 correct execution can't be ensured on r5900.
1047 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1048 will confuse less developers and compilers.
1049
a32c3ff8
NC		 10502013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1051
fb098a1e
YZ		 1052 * aarch64-opc.c (aarch64_print_operand): Change to print
1053 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1054 in comment.
1055 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1056 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1057 OP_MOV_IMM_WIDE.
1058
10592013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1060
1061 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1062 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1063
62658407
L		 10642013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1065
1066 * i386-gen.c (process_copyright): Update copyright year to 2013.
1067
bab4becb 10682013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1069
bab4becb
NC		 1070 * cr16-dis.c (match_opcode,make_instruction): Remove static
1071 declaration.
1072 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1073 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1074
bab4becb 1075For older changes see ChangeLog-2012
252b5132 1076\f
bab4becb 1077Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1078
1079Copying and distribution of this file, with or without modification,
1080are permitted in any medium without royalty provided the copyright
1081notice and this notice are preserved.
1082
252b5132 1083Local Variables:
2f6d2f85
NC		 1084mode: change-log
1085left-margin: 8
1086fill-column: 74
252b5132
RH		 1087version-control: never
1088End:
GDB Binutils - Deliverables
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