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0cc79db2
SN		 12020-10-05 Samanta Navarro <ferivoz@riseup.net>
2
3 * cgen-asm.c: Fix spelling mistakes.
4 * cgen-dis.c: Fix spelling mistakes.
5 * tic30-dis.c: Fix spelling mistakes.
6
5b316d90
L		 72020-10-05 H.J. Lu <hongjiu.lu@intel.com>
8
9 PR binutils/26704
10 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
11
0e9f3bf1
L		 122020-10-05 H.J. Lu <hongjiu.lu@intel.com>
13
14 PR binutils/26705
15 * i386-dis.c (print_insn): Clear modrm if not needed.
16 (putop): Check need_modrm for modrm.mod != 3. Don't check
17 need_modrm for modrm.mod == 3.
18
3454861d
PW		 192020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
20
12e35da6
PW		 21 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
22 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
23 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
24 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
25 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
26 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
27 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
28 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
29 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
30 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
31 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
32 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
33 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
34 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
3454861d 35
1ff8e401
PW		 362020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
37
12e35da6
PW		 38 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
39
402020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
41
42 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
43 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
1ff8e401 44
0be2fe67
AM		 452020-09-26 Alan Modra <amodra@gmail.com>
46
47 * csky-opc.h: Formatting.
48 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
49 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
50 and shift 1u.
51 (get_register_number): Likewise.
52 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
53
09d73035
CL		 542020-09-24 Lili Cui <lili.cui@intel.com>
55
56 PR 26654
0be2fe67 57 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
09d73035 58
011a045a
AB		 592020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
60
61 * csky-dis.c (csky_output_operand): Enclose body of if in curly
62 braces.
63
81d54bb7
CL		 642020-09-24 Lili Cui <lili.cui@intel.com>
65
66 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
67 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
68 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
69 X86_64_0F01_REG_1_RM_7_P_2.
70 (prefix_table): Likewise.
71 (x86_64_table): Likewise.
72 (rm_table): Likewise.
73 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
74 and CPU_ANY_TDX_FLAGS.
75 (cpu_flags): Add CpuTDX.
76 * i386-opc.h (enum): Add CpuTDX.
77 (i386_cpu_flags): Add cputdx.
78 * i386-opc.tbl: Add TDX insns.
79 * i386-init.h: Regenerate.
80 * i386-tbl.h: Likewise.
81
afdcafe8
CQ		 822020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
83
afdcafe8
CQ		 84 * csky-dis.c (using_abi): New.
85 (parse_csky_dis_options): New function.
86 (get_gr_name): New function.
87 (get_cr_name): New function.
88 (csky_output_operand): Use get_gr_name and get_cr_name to
89 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
90 (print_insn_csky): Parse disassembler options.
0be2fe67 91 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
afdcafe8
CQ		 92 (GENARAL_REG_BANK): Define.
93 (REG_SUPPORT_ALL): Define.
94 (REG_SUPPORT_ALL): New.
95 (ASH): Define.
96 (REG_SUPPORT_A): Define.
97 (REG_SUPPORT_B): Define.
98 (REG_SUPPORT_C): Define.
99 (REG_SUPPORT_D): Define.
100 (REG_SUPPORT_E): Define.
101 (csky_abiv1_general_regs): New.
102 (csky_abiv1_control_regs): New.
103 (csky_abiv2_general_regs): New.
104 (csky_abiv2_control_regs): New.
105 (get_register_name): New function.
106 (get_register_number): New function.
107 (csky_get_general_reg_name): New function.
108 (csky_get_general_regno): New function.
109 (csky_get_control_reg_name): New function.
110 (csky_get_control_regno): New function.
111 (csky_v2_opcodes): Prefer two oprerans format for bclri and
112 bseti, strengthen the operands legality check of addc, zext
113 and sext.
114
c4694f17
TG		 1152020-09-23 Lili Cui <lili.cui@intel.com>
116
117 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
118 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
119 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
120 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
121 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
122 (reg_table): New instructions (see prefixes above).
123 (prefix_table): Likewise.
124 (three_byte_table): Likewise.
125 (mod_table): Likewise
126 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
127 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
128 (cpu_flags): Likewise.
129 (operand_type_init): Likewise.
130 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
131 (i386_cpu_flags): Add cpukl and cpuwide_kl.
132 * i386-opc.tbl: Add KL and WIDE_KL insns.
133 * i386-init.h: Regenerate.
134 * i386-tbl.h: Likewise.
135
c73eac96
AM		 1362020-09-21 Alan Modra <amodra@gmail.com>
137
138 * rx-dis.c (flag_names): Add missing comma.
139 (register_names, flag_names, double_register_names),
140 (double_register_high_names, double_register_low_names),
141 (double_control_register_names, double_condition_names): Remove
142 trailing commas.
143
6e25f888
DF		 1442020-09-18 David Faust <david.faust@oracle.com>
145
146 * bpf-desc.c: Regenerate.
147 * bpf-desc.h: Likewise.
148 * bpf-opc.c: Likewise.
149 * bpf-opc.h: Likewise.
150
c568ac5f
AB		 1512020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
152
153 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
154 is no BFD.
155
c1229f84
AM		 1562020-09-16 Alan Modra <amodra@gmail.com>
157
158 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
159
7ad57880
NC		 1602020-09-10 Nick Clifton <nickc@redhat.com>
161
162 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
163 for hidden, local, no-type symbols.
164 (disassemble_init_powerpc): Point the symbol_is_valid field in the
165 info structure at the new function.
166
79c8d443
CQ		 1672020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
168
169 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
170 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
171 opcode fixing.
172
0332f662
NC		 1732020-09-10 Nick Clifton <nickc@redhat.com>
174
175 * csky-dis.c (csky_output_operand): Coerce the immediate values to
176 long before printing.
177
23bef3fe
AM		 1782020-09-10 Alan Modra <amodra@gmail.com>
179
180 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
181
6a1ed910
CQ		 1822020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
183
184 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
185 ISA flag.
186
1feede9b
CQ		 1872020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
188
189 * csky-dis.c (csky_output_operand): Add handlers for
190 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
191 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
192 to support FPUV3 instructions.
193 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
194 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
195 OPRND_TYPE_DFLOAT_FMOVI.
196 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
197 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
198 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
199 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
200 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
201 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
202 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
203 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
204 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
205 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
206 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
207 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
208 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
209 (csky_v2_opcodes): Add FPUV3 instructions.
210
38cf07a6
AC		 2112020-09-08 Alex Coplan <alex.coplan@arm.com>
212
213 * aarch64-dis.c (print_operands): Pass CPU features to
214 aarch64_print_operand().
215 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
216 preferred disassembly of system registers.
217 (SR_RNG): Refactor to use new SR_FEAT2 macro.
218 (SR_FEAT2): New.
219 (SR_V8_1_A): New.
220 (SR_V8_4_A): New.
221 (SR_V8_A): New.
222 (SR_V8_R): New.
223 (SR_EXPAND_ELx): New.
224 (SR_EXPAND_EL12): New.
225 (aarch64_sys_regs): Specify which registers are only on
226 A-profile, add R-profile system registers.
227 (ENC_BARLAR): New.
228 (PRBARn_ELx): New.
229 (PRLARn_ELx): New.
230 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
231 Armv8-R AArch64.
232
03fb3142
AC		 2332020-09-08 Alex Coplan <alex.coplan@arm.com>
234
235 * aarch64-tbl.h (aarch64_feature_v8_r): New.
236 (ARMV8_R): New.
237 (V8_R_INSN): New.
238 (aarch64_opcode_table): Add dfb.
239 * aarch64-opc-2.c: Regenerate.
240 * aarch64-asm-2.c: Regenerate.
241 * aarch64-dis-2.c: Regenerate.
242
95830c98
AC		 2432020-09-08 Alex Coplan <alex.coplan@arm.com>
244
245 * aarch64-dis.c (arch_variant): New.
246 (determine_disassembling_preference): Disassemble according to
247 arch variant.
248 (select_aarch64_variant): New.
249 (print_insn_aarch64): Set feature set.
250
7c80dd4c
AM		 2512020-09-02 Alan Modra <amodra@gmail.com>
252
253 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
254 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
255 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
256 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
257 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
258 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
259 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
260 for value parameter and update code to suit.
261 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
262 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
263
b4b39349
AM		 2642020-09-02 Alan Modra <amodra@gmail.com>
265
266 * i386-dis.c (OP_E_memory): Don't cast to signed type when
267 negating.
268 (get32, get32s): Use unsigned types in shift expressions.
269
caf4537a
AM		 2702020-09-02 Alan Modra <amodra@gmail.com>
271
272 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
273
3c5097ea
AM		 2742020-09-02 Alan Modra <amodra@gmail.com>
275
276 * crx-dis.c: Whitespace.
277 (print_arg): Use unsigned type for longdisp and mask variables,
278 and for left shift constant.
279
ae3e98b4
AM		 2802020-09-02 Alan Modra <amodra@gmail.com>
281
282 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
283 * bpf-ibld.c: Regenerate.
284 * epiphany-ibld.c: Regenerate.
285 * fr30-ibld.c: Regenerate.
286 * frv-ibld.c: Regenerate.
287 * ip2k-ibld.c: Regenerate.
288 * iq2000-ibld.c: Regenerate.
289 * lm32-ibld.c: Regenerate.
290 * m32c-ibld.c: Regenerate.
291 * m32r-ibld.c: Regenerate.
292 * mep-ibld.c: Regenerate.
293 * mt-ibld.c: Regenerate.
294 * or1k-ibld.c: Regenerate.
295 * xc16x-ibld.c: Regenerate.
296 * xstormy16-ibld.c: Regenerate.
297
427202d9
AM		 2982020-09-02 Alan Modra <amodra@gmail.com>
299
300 * bfin-dis.c (MASKBITS): Use SIGNBIT.
301
4211a340
CQ		 3022020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
303
304 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
305 to CSKYV2_ISA_3E3R3 instruction set.
306
8119cc38
CQ		 3072020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
308
309 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
310
8dbe96f0
AM		 3112020-09-01 Alan Modra <amodra@gmail.com>
312
313 * mep-ibld.c: Regenerate.
314
e2e82b11
CQ		 3152020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
316
317 * csky-dis.c (csky_output_operand): Assign dis_info.value for
318 OPRND_TYPE_VREG.
319
2781f857
AM		 3202020-08-30 Alan Modra <amodra@gmail.com>
321
322 * cr16-dis.c: Formatting.
323 (parameter): Delete struct typedef. Use dwordU instead
324 throughout file.
325 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
326 and tbitb.
327 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
328
0c0577f6
AM		 3292020-08-29 Alan Modra <amodra@gmail.com>
330
331 PR 26446
332 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
333 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
334
a1e60a1b
AM		 3352020-08-28 Alan Modra <amodra@gmail.com>
336
337 PR 26449
338 PR 26450
339 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
340 (extract_normal): Likewise.
341 (insert_normal): Likewise, and move past zero length test.
342 (put_insn_int_value): Handle mask for zero length, use 1UL.
343 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
344 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
345 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
346 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
347
0861f561
CQ		 3482020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
349
350 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
351 (csky_dis_info): Add member isa.
352 (csky_find_inst_info): Skip instructions that do not belong to
353 current CPU.
354 (csky_get_disassembler): Get infomation from attribute section.
355 (print_insn_csky): Set defualt ISA flag.
356 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
357 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
358 isa_flag32'type to unsigned 64 bits.
359
31b3f3e6
JM		 3602020-08-26 Jose E. Marchesi <jemarch@gnu.org>
361
362 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
363
4449c81a
DF		 3642020-08-26 David Faust <david.faust@oracle.com>
365
366 * bpf-desc.c: Regenerate.
367 * bpf-desc.h: Likewise.
368 * bpf-opc.c: Likewise.
369 * bpf-opc.h: Likewise.
370 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
371 ISA when appropriate.
372
8640c87d
AM		 3732020-08-25 Alan Modra <amodra@gmail.com>
374
375 PR 26504
376 * vax-dis.c (parse_disassembler_options): Always add at least one
377 to entry_addr_total_slots.
378
531c73a3
CQ		 3792020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
380
381 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
382 in other CPUs to speed up disassembling.
383 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
384 Change plsli.u16 to plsli.16, change sync's operand format.
385
d04aee0f
CQ		 3862020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
387
388 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
389
ccf61261
NC		 3902020-08-21 Nick Clifton <nickc@redhat.com>
391
392 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
393 symbols.
394
d285ba8d
CQ		 3952020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
396
397 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
398
18a8a00e
AM		 3992020-08-19 Alan Modra <amodra@gmail.com>
400
401 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
402 vcmpuq and xvtlsbb.
403
587a4371
PB		 4042020-08-18 Peter Bergner <bergner@linux.ibm.com>
405
406 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
407 <xvcvbf16spn>: ...to this.
408
2e49fd1e
AC		 4092020-08-12 Alex Coplan <alex.coplan@arm.com>
410
411 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
412
79ddc884
NC		 4132020-08-12 Nick Clifton <nickc@redhat.com>
414
415 * po/sr.po: Updated Serbian translation.
416
08770ec2
AM		 4172020-08-11 Alan Modra <amodra@gmail.com>
418
419 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
420
f7cb161e
PW		 4212020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
422
423 * aarch64-opc.c (aarch64_print_operand):
424 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
425 (aarch64_sys_reg_supported_p): Function removed.
426 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
427 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
428 into this function.
429
3eb65174
AM		 4302020-08-10 Alan Modra <amodra@gmail.com>
431
432 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
433 instructions.
434
8b2742a1
AM		 4352020-08-10 Alan Modra <amodra@gmail.com>
436
437 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
438 Enable icbt for power5, miso for power8.
439
5fbec329
AM		 4402020-08-10 Alan Modra <amodra@gmail.com>
441
442 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
443 mtvsrd, and similarly for mfvsrd.
444
563a3225
CG		 4452020-08-04 Christian Groessler <chris@groessler.org>
446 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
447
448 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
449 opcodes (special "out" to absolute address).
450 * z8k-opc.h: Regenerate.
451
41eb8e88
L		 4522020-07-30 H.J. Lu <hongjiu.lu@intel.com>
453
454 PR gas/26305
455 * i386-opc.h (Prefix_Disp8): New.
456 (Prefix_Disp16): Likewise.
457 (Prefix_Disp32): Likewise.
458 (Prefix_Load): Likewise.
459 (Prefix_Store): Likewise.
460 (Prefix_VEX): Likewise.
461 (Prefix_VEX3): Likewise.
462 (Prefix_EVEX): Likewise.
463 (Prefix_REX): Likewise.
464 (Prefix_NoOptimize): Likewise.
465 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
466 * i386-tbl.h: Regenerated.
467
98116973
AA		 4682020-07-29 Andreas Arnez <arnez@linux.ibm.com>
469
470 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
471 default case with abort() instead of printing an error message and
472 continuing, to avoid a maybe-uninitialized warning.
473
2dddfa20
NC		 4742020-07-24 Nick Clifton <nickc@redhat.com>
475
476 * po/de.po: Updated German translation.
477
bf4ba07c
JB		 4782020-07-21 Jan Beulich <jbeulich@suse.com>
479
480 * i386-dis.c (OP_E_memory): Revert previous change.
481
04c662e2
L		 4822020-07-15 H.J. Lu <hongjiu.lu@intel.com>
483
484 PR gas/26237
485 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
486 without base nor index registers.
487
f0e8d0ba
JB		 4882020-07-15 Jan Beulich <jbeulich@suse.com>
489
490 * i386-dis.c (putop): Move 'V' and 'W' handling.
491
c3f5525f
JB		 4922020-07-15 Jan Beulich <jbeulich@suse.com>
493
494 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
495 construct for push/pop of register.
496 (putop): Honor cond when handling 'P'. Drop handling of plain
497 'V'.
498
36938cab
JB		 4992020-07-15 Jan Beulich <jbeulich@suse.com>
500
501 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
502 description. Drop '&' description. Use P for push of immediate,
503 pushf/popf, enter, and leave. Use %LP for lret/retf.
504 (dis386_twobyte): Use P for push/pop of fs/gs.
505 (reg_table): Use P for push/pop. Use @ for near call/jmp.
506 (x86_64_table): Use P for far call/jmp.
507 (putop): Drop handling of 'U' and '&'. Move and adjust handling
508 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
509 labels.
510 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
511 and dqw_mode (unconditional).
512
8e58ef80
L		 5132020-07-14 H.J. Lu <hongjiu.lu@intel.com>
514
515 PR gas/26237
516 * i386-dis.c (OP_E_memory): Without base nor index registers,
517 32-bit displacement to 64 bits.
518
570b0ed6
CZ		 5192020-07-14 Claudiu Zissulescu <claziss@gmail.com>
520
521 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
522 faulty double register pair is detected.
523
bfbd9438
JB		 5242020-07-14 Jan Beulich <jbeulich@suse.com>
525
526 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
527
78467458
JB		 5282020-07-14 Jan Beulich <jbeulich@suse.com>
529
530 * i386-dis.c (OP_R, Rm): Delete.
531 (MOD_0F24, MOD_0F26): Rename to ...
532 (X86_64_0F24, X86_64_0F26): ... respectively.
533 (dis386): Update 'L' and 'Z' comments.
534 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
535 table references.
536 (mod_table): Move opcode 0F24 and 0F26 entries ...
537 (x86_64_table): ... here.
538 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
539 'Z' case block.
540
464d2b65
JB		 5412020-07-14 Jan Beulich <jbeulich@suse.com>
542
543 * i386-dis.c (Rd, Rdq, MaskR): Delete.
544 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
545 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
546 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
547 MOD_EVEX_0F387C): New enumerators.
548 (reg_table): Use Edq for rdssp.
549 (prefix_table): Use Edq for incssp.
550 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
551 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
552 ktest*, and kshift*. Use Edq / MaskE for kmov*.
553 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
554 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
555 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
556 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
557 0F3828_P_1 and 0F3838_P_1.
558 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
559 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
560
035e7389
JB		 5612020-07-14 Jan Beulich <jbeulich@suse.com>
562
563 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
564 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
565 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
566 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
567 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
568 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
569 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
570 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
571 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
572 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
573 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
574 (reg_table, prefix_table, three_byte_table, vex_table,
575 vex_len_table, mod_table, rm_table): Replace / remove respective
576 entries.
577 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
578 of PREFIX_DATA in used_prefixes.
579
bb5b3501
JB		 5802020-07-14 Jan Beulich <jbeulich@suse.com>
581
582 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
583 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
584 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
585 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
586 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
587 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
588 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
589 VEX_W_0F3A33_L_0): Delete.
590 (dis386): Adjust "BW" description.
591 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
592 0F3A31, 0F3A32, and 0F3A33.
593 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
594 entries.
595 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
596 entries.
597
7531c613
JB		 5982020-07-14 Jan Beulich <jbeulich@suse.com>
599
600 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
601 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
602 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
603 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
604 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
605 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
606 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
607 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
608 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
609 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
610 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
611 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
612 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
613 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
614 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
615 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
616 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
617 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
618 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
619 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
620 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
621 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
622 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
623 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
624 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
625 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
626 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
627 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
628 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
629 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
630 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
631 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
632 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
633 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
634 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
635 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
636 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
637 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
638 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
639 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
640 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
641 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
642 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
643 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
644 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
645 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
646 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
647 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
648 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
649 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
650 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
651 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
652 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
653 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
654 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
655 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
656 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
657 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
658 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
659 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
660 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
661 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
662 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
663 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
664 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
665 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
666 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
667 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
668 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
669 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
670 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
671 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
672 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
673 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
674 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
675 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
676 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
677 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
678 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
679 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
680 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
681 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
682 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
683 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
684 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
685 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
686 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
687 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
688 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
689 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
690 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
691 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
692 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
693 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
694 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
695 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
696 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
697 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
698 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
699 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
700 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
701 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
702 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
703 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
704 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
705 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
706 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
707 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
708 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
709 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
710 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
711 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
712 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
713 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
714 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
715 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
716 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
717 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
718 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
719 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
720 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
721 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
722 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
723 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
724 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
725 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
726 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
727 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
728 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
729 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
730 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
731 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
732 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
733 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
734 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
735 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
736 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
737 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
738 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
739 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
740 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
741 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
742 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
743 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
744 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
745 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
746 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
747 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
748 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
749 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
750 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
751 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
752 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
753 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
754 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
755 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
756 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
757 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
758 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
759 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
760 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
761 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
762 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
763 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
764 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
765 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
766 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
767 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
768 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
769 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
770 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
771 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
772 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
773 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
774 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
775 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
776 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
777 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
778 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
779 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
780 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
781 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
782 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
783 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
784 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
785 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
786 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
787 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
788 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
789 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
790 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
791 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
792 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
793 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
794 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
795 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
796 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
797 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
798 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
799 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
800 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
801 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
802 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
803 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
804 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
805 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
806 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
807 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
808 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
809 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
810 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
811 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
812 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
813 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
814 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
815 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
816 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
817 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
818 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
819 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
820 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
821 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
822 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
823 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
824 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
825 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
826 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
827 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
828 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
829 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
830 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
831 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
832 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
833 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
834 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
835 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
836 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
837 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
838 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
839 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
840 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
841 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
842 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
843 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
844 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
845 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
846 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
847 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
848 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
849 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
850 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
851 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
852 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
853 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
854 EVEX_W_0F3A72_P_2): Rename to ...
855 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
856 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
857 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
858 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
859 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
860 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
861 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
862 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
863 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
864 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
865 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
866 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
867 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
868 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
869 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
870 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
871 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
872 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
873 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
874 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
875 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
876 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
877 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
878 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
879 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
880 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
881 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
882 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
883 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
884 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
885 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
886 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
887 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
888 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
889 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
890 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
891 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
892 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
893 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
894 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
895 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
896 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
897 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
898 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
899 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
900 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
901 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
902 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
903 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
904 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
905 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
906 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
907 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
908 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
909 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
910 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
911 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
912 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
913 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
914 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
915 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
916 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
917 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
918 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
919 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
920 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
921 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
922 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
923 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
924 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
925 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
926 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
0be2fe67 927 respectively.
7531c613
JB		 928 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
929 vex_w_table, mod_table): Replace / remove respective entries.
930 (print_insn): Move up dp->prefix_requirement handling. Handle
931 PREFIX_DATA.
932 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
933 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
934 Replace / remove respective entries.
935
17d3c7ec
JB		 9362020-07-14 Jan Beulich <jbeulich@suse.com>
937
938 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
939 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
940 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
941 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
942 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
943 the latter two.
944 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
945 0F2C, 0F2D, 0F2E, and 0F2F.
946 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
947 0F2F table entries.
948
41f5efc6
JB		 9492020-07-14 Jan Beulich <jbeulich@suse.com>
950
951 * i386-dis.c (OP_VexR, VexScalarR): New.
952 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
953 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
954 need_vex_reg): Delete.
955 (prefix_table): Replace VexScalar by VexScalarR and
956 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
957 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
958 (vex_len_table): Replace EXqVexScalarS by EXqS.
959 (get_valid_dis386): Don't set need_vex_reg.
960 (print_insn): Don't initialize need_vex_reg.
961 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
962 q_scalar_swap_mode cases.
963 (OP_EX): Don't check for d_scalar_swap_mode and
964 q_scalar_swap_mode.
965 (OP_VEX): Done check need_vex_reg.
966 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
967 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
968 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
969
89e65d17
JB		 9702020-07-14 Jan Beulich <jbeulich@suse.com>
971
972 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
973 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
974 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
975 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
976 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
977 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
978 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
979 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
980 (vex_table): Replace Vex128 by Vex.
981 (vex_len_table): Likewise. Adjust referenced enum names.
982 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
983 referenced enum names.
984 (OP_VEX): Drop vex128_mode and vex256_mode cases.
985 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
986
492a76aa
JB		 9872020-07-14 Jan Beulich <jbeulich@suse.com>
988
989 * i386-dis.c (dis386): "LW" description now applies to "DQ".
990 (putop): Handle "DQ". Don't handle "LW" anymore.
991 (prefix_table, mod_table): Replace %LW by %DQ.
992 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
993
059edf8b
JB		 9942020-07-14 Jan Beulich <jbeulich@suse.com>
995
996 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
997 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
998 d_scalar_swap_mode case handling. Move shift adjsutment into
999 the case its applicable to.
1000
4726e9a4
JB		 10012020-07-14 Jan Beulich <jbeulich@suse.com>
1002
1003 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1004 (EXbScalar, EXwScalar): Fold to ...
1005 (EXbwUnit): ... this.
1006 (b_scalar_mode, w_scalar_mode): Fold to ...
1007 (bw_unit_mode): ... this.
1008 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1009 w_scalar_mode handling by bw_unit_mode one.
1010 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1011 ...
1012 * i386-dis-evex-prefix.h: ... here.
1013
b24d668c
JB		 10142020-07-14 Jan Beulich <jbeulich@suse.com>
1015
1016 * i386-dis.c (PCMPESTR_Fixup): Delete.
1017 (dis386): Adjust "LQ" description.
1018 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1019 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1020 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1021 vpcmpestrm, and vpcmpestri.
1022 (putop): Honor "cond" when handling LQ.
1023 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1024 vcvtsi2ss and vcvtusi2ss.
1025 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1026 vcvtsi2sd and vcvtusi2sd.
1027
c4de7606
JB		 10282020-07-14 Jan Beulich <jbeulich@suse.com>
1029
1030 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1031 (simd_cmp_op): Add const.
1032 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1033 (CMP_Fixup): Handle VEX case.
1034 (prefix_table): Replace VCMP by CMP.
1035 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1036
9ab00b61
JB		 10372020-07-14 Jan Beulich <jbeulich@suse.com>
1038
1039 * i386-dis.c (MOVBE_Fixup): Delete.
1040 (Mv): Define.
1041 (prefix_table): Use Mv for movbe entries.
1042
2875b28a
JB		 10432020-07-14 Jan Beulich <jbeulich@suse.com>
1044
1045 * i386-dis.c (CRC32_Fixup): Delete.
1046 (prefix_table): Use Eb/Ev for crc32 entries.
1047
e184e611
JB		 10482020-07-14 Jan Beulich <jbeulich@suse.com>
1049
1050 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1051 Conditionalize invocations of "USED_REX (0)".
1052
e8b5d5f9
JB		 10532020-07-14 Jan Beulich <jbeulich@suse.com>
1054
1055 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1056 CH, DH, BH, AX, DX): Delete.
1057 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1058 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1059 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1060
260cd341
LC		 10612020-07-10 Lili Cui <lili.cui@intel.com>
1062
1063 * i386-dis.c (TMM): New.
1064 (EXtmm): Likewise.
1065 (VexTmm): Likewise.
1066 (MVexSIBMEM): Likewise.
1067 (tmm_mode): Likewise.
1068 (vex_sibmem_mode): Likewise.
1069 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1070 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1071 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1072 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1073 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1074 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1075 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1076 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1077 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1078 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1079 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1080 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1081 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1082 (PREFIX_VEX_0F3849_X86_64): Likewise.
1083 (PREFIX_VEX_0F384B_X86_64): Likewise.
1084 (PREFIX_VEX_0F385C_X86_64): Likewise.
1085 (PREFIX_VEX_0F385E_X86_64): Likewise.
1086 (X86_64_VEX_0F3849): Likewise.
1087 (X86_64_VEX_0F384B): Likewise.
1088 (X86_64_VEX_0F385C): Likewise.
1089 (X86_64_VEX_0F385E): Likewise.
1090 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1091 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1092 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1093 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1094 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1095 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1096 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1097 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1098 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1099 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1100 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1101 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1102 (VEX_W_0F3849_X86_64_P_0): Likewise.
1103 (VEX_W_0F3849_X86_64_P_2): Likewise.
1104 (VEX_W_0F3849_X86_64_P_3): Likewise.
1105 (VEX_W_0F384B_X86_64_P_1): Likewise.
1106 (VEX_W_0F384B_X86_64_P_2): Likewise.
1107 (VEX_W_0F384B_X86_64_P_3): Likewise.
1108 (VEX_W_0F385C_X86_64_P_1): Likewise.
1109 (VEX_W_0F385E_X86_64_P_0): Likewise.
1110 (VEX_W_0F385E_X86_64_P_1): Likewise.
1111 (VEX_W_0F385E_X86_64_P_2): Likewise.
1112 (VEX_W_0F385E_X86_64_P_3): Likewise.
1113 (names_tmm): Likewise.
1114 (att_names_tmm): Likewise.
1115 (intel_operand_size): Handle void_mode.
1116 (OP_XMM): Handle tmm_mode.
1117 (OP_EX): Likewise.
1118 (OP_VEX): Likewise.
1119 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1120 CpuAMX_BF16 and CpuAMX_TILE.
1121 (operand_type_shorthands): Add RegTMM.
1122 (operand_type_init): Likewise.
1123 (operand_types): Add Tmmword.
1124 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1125 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1126 * i386-opc.h (CpuAMX_INT8): New.
1127 (CpuAMX_BF16): Likewise.
1128 (CpuAMX_TILE): Likewise.
1129 (SIBMEM): Likewise.
1130 (Tmmword): Likewise.
1131 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1132 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1133 (i386_operand_type): Add tmmword.
1134 * i386-opc.tbl: Add AMX instructions.
1135 * i386-reg.tbl: Add AMX registers.
1136 * i386-init.h: Regenerated.
1137 * i386-tbl.h: Likewise.
1138
467bbef0
JB		 11392020-07-08 Jan Beulich <jbeulich@suse.com>
1140
1141 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1142 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1143 Rename to ...
1144 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1145 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1146 respectively.
1147 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1148 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1149 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1150 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1151 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1152 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1153 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1154 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1155 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1156 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1157 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1158 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1159 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1160 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1161 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1162 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1163 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1164 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1165 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1166 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1167 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1168 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1169 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1170 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1171 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1172 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1173 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1174 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1175 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1176 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1177 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1178 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1179 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1180 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1181 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1182 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1183 (reg_table): Re-order XOP entries. Adjust their operands.
1184 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1185 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1186 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1187 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1188 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1189 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1190 entries by references ...
1191 (vex_len_table): ... to resepctive new entries here. For several
1192 new and existing entries reference ...
1193 (vex_w_table): ... new entries here.
1194 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1195
6384fd9e
JB		 11962020-07-08 Jan Beulich <jbeulich@suse.com>
1197
1198 * i386-dis.c (XMVexScalarI4): Define.
1199 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1200 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1201 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1202 (vex_len_table): Move scalar FMA4 entries ...
1203 (prefix_table): ... here.
1204 (OP_REG_VexI4): Handle scalar_mode.
1205 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1206 * i386-tbl.h: Re-generate.
1207
e6123d0c
JB		 12082020-07-08 Jan Beulich <jbeulich@suse.com>
1209
1210 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1211 Vex_2src_2): Delete.
1212 (OP_VexW, VexW): New.
1213 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1214 for shifts and rotates by register.
1215
93abb146
JB		 12162020-07-08 Jan Beulich <jbeulich@suse.com>
1217
1218 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1219 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1220 OP_EX_VexReg): Delete.
1221 (OP_VexI4, VexI4): New.
1222 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1223 (prefix_table): ... here.
1224 (print_insn): Drop setting of vex_w_done.
1225
b13b1bc0
JB		 12262020-07-08 Jan Beulich <jbeulich@suse.com>
1227
1228 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1229 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1230 (xop_table): Replace operands of 4-operand insns.
1231 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1232
f337259f
CZ		 12332020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1234
1235 * arc-opc.c (insert_rbd): New function.
1236 (RBD): Define.
1237 (RBDdup): Likewise.
1238 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1239 instructions.
1240
931452b6
JB		 12412020-07-07 Jan Beulich <jbeulich@suse.com>
1242
1243 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1244 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1245 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1246 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1247 Delete.
1248 (putop): Handle "BW".
1249 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1250 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1251 and 0F3A3F ...
1252 * i386-dis-evex-prefix.h: ... here.
1253
b5b098c2
JB		 12542020-07-06 Jan Beulich <jbeulich@suse.com>
1255
1256 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1257 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1258 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1259 VEX_W_0FXOP_09_83): New enumerators.
1260 (xop_table): Reference the above.
1261 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1262 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1263 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1264 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1265
21a3faeb
JB		 12662020-07-06 Jan Beulich <jbeulich@suse.com>
1267
1268 * i386-dis.c (EVEX_W_0F3838_P_1,
1269 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1270 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1271 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1272 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1273 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1274 (putop): Centralize management of last[]. Delete SAVE_LAST.
1275 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1276 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1277 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1278 * i386-dis-evex-prefix.h: here.
1279
bc152a17
JB		 12802020-07-06 Jan Beulich <jbeulich@suse.com>
1281
1282 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1283 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1284 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1285 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1286 enumerators.
1287 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1288 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1289 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1290 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1291 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1292 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1293 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1294 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1295 these, respectively.
1296 * i386-dis-evex-len.h: Adjust comments.
1297 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1298 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1299 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1300 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1301 MOD_EVEX_0F385B_P_2_W_1 table entries.
1302 * i386-dis-evex-w.h: Reference mod_table[] for
1303 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1304 EVEX_W_0F385B_P_2.
1305
c82a99a0
JB		 13062020-07-06 Jan Beulich <jbeulich@suse.com>
1307
1308 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1309 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1310 EXymm.
1311 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1312 Likewise. Mark 256-bit entries invalid.
1313
fedfb81e
JB		 13142020-07-06 Jan Beulich <jbeulich@suse.com>
1315
1316 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1317 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1318 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1319 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1320 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1321 PREFIX_EVEX_0F382B): Delete.
1322 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1323 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1324 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1325 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1326 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1327 to ...
1328 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1329 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1330 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1331 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1332 respectively.
1333 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1334 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1335 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1336 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1337 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1338 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1339 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1340 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1341 PREFIX_EVEX_0F382B): Remove table entries.
1342 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1343 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1344 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1345
3a57774c
JB		 13462020-07-06 Jan Beulich <jbeulich@suse.com>
1347
1348 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1349 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1350 enumerators.
1351 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1352 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1353 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1354 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1355 entries.
1356
e74d9fa9
JB		 13572020-07-06 Jan Beulich <jbeulich@suse.com>
1358
1359 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1360 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1361 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1362 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1363 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1364 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1365 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1366 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1367 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1368 entries.
1369
6431c801
JB		 13702020-07-06 Jan Beulich <jbeulich@suse.com>
1371
1372 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1373 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1374 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1375 respectively.
1376 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1377 entries.
1378 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1379 opcode 0F3A1D.
1380 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1381 entry.
1382 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1383
6df22cf6
JB		 13842020-07-06 Jan Beulich <jbeulich@suse.com>
1385
1386 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1387 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1388 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1389 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1390 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1391 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1392 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1393 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1394 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1395 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1396 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1397 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1398 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1399 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1400 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1401 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1402 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1403 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1404 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1405 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1406 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1407 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1408 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1409 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1410 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1411 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1412 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1413 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1414 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1415 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1416 (prefix_table): Add EXxEVexR to FMA table entries.
1417 (OP_Rounding): Move abort() invocation.
1418 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1419 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1420 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1421 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1422 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1423 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1424 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1425 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1426 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1427 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1428 0F3ACE, 0F3ACF.
1429 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1430 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1431 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1432 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1433 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1434 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1435 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1436 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1437 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1438 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1439 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1440 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1441 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1442 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1443 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1444 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1445 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1446 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1447 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1448 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1449 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1450 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1451 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1452 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1453 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1454 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1455 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1456 Delete table entries.
1457 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1458 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1459 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1460 Likewise.
1461
39e0f456
JB		 14622020-07-06 Jan Beulich <jbeulich@suse.com>
1463
1464 * i386-dis.c (EXqScalarS): Delete.
1465 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1466 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1467
5b872f7d
JB		 14682020-07-06 Jan Beulich <jbeulich@suse.com>
1469
1470 * i386-dis.c (safe-ctype.h): Include.
1471 (EXdScalar, EXqScalar): Delete.
1472 (d_scalar_mode, q_scalar_mode): Delete.
1473 (prefix_table, vex_len_table): Use EXxmm_md in place of
1474 EXdScalar and EXxmm_mq in place of EXqScalar.
1475 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1476 d_scalar_mode and q_scalar_mode.
1477 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1478 (vmovsd): Use EXxmm_mq.
1479
ddc73fa9
NC		 14802020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1481
1482 PR 26204
1483 * arc-dis.c: Fix spelling mistake.
1484 * po/opcodes.pot: Regenerate.
1485
17550be7
NC		 14862020-07-06 Nick Clifton <nickc@redhat.com>
1487
1488 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1489 * po/uk.po: Updated Ukranian translation.
1490
b19d852d
NC		 14912020-07-04 Nick Clifton <nickc@redhat.com>
1492
1493 * configure: Regenerate.
1494 * po/opcodes.pot: Regenerate.
1495
b115b9fd
NC		 14962020-07-04 Nick Clifton <nickc@redhat.com>
1497
1498 Binutils 2.35 branch created.
1499
c2ecccb3
L		 15002020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1501
1502 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1503 * i386-opc.h (VexSwapSources): New.
1504 (i386_opcode_modifier): Add vexswapsources.
1505 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1506 with two source operands swapped.
1507 * i386-tbl.h: Regenerated.
1508
08ccfccf
NC		 15092020-06-30 Nelson Chu <nelson.chu@sifive.com>
1510
1511 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1512 unprivileged CSR can also be initialized.
1513
279edac5
AM		 15142020-06-29 Alan Modra <amodra@gmail.com>
1515
1516 * arm-dis.c: Use C style comments.
1517 * cr16-opc.c: Likewise.
1518 * ft32-dis.c: Likewise.
1519 * moxie-opc.c: Likewise.
1520 * tic54x-dis.c: Likewise.
1521 * s12z-opc.c: Remove useless comment.
1522 * xgate-dis.c: Likewise.
1523
e978ad62
L		 15242020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1525
1526 * i386-opc.tbl: Add a blank line.
1527
63112cd6
L		 15282020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1529
1530 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1531 (VecSIB128): Renamed to ...
1532 (VECSIB128): This.
1533 (VecSIB256): Renamed to ...
1534 (VECSIB256): This.
1535 (VecSIB512): Renamed to ...
1536 (VECSIB512): This.
1537 (VecSIB): Renamed to ...
1538 (SIB): This.
1539 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 1540 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 1541 (VecSIB256): Likewise.
1542 (VecSIB512): Likewise.
79b32e73 1543 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 1544 and VecSIB512, respectively.
1545
d1c36125
JB		 15462020-06-26 Jan Beulich <jbeulich@suse.com>
1547
1548 * i386-dis.c: Adjust description of I macro.
1549 (x86_64_table): Drop use of I.
1550 (float_mem): Replace use of I.
1551 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1552
2a1bb84c
JB		 15532020-06-26 Jan Beulich <jbeulich@suse.com>
1554
1555 * i386-dis.c: (print_insn): Avoid straight assignment to
1556 priv.orig_sizeflag when processing -M sub-options.
1557
8f570d62
JB		 15582020-06-25 Jan Beulich <jbeulich@suse.com>
1559
1560 * i386-dis.c: Adjust description of J macro.
1561 (dis386, x86_64_table, mod_table): Replace J.
1562 (putop): Remove handling of J.
1563
464dc4af
JB		 15642020-06-25 Jan Beulich <jbeulich@suse.com>
1565
1566 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1567
589958d6
JB		 15682020-06-25 Jan Beulich <jbeulich@suse.com>
1569
1570 * i386-dis.c: Adjust description of "LQ" macro.
1571 (dis386_twobyte): Use LQ for sysret.
1572 (putop): Adjust handling of LQ.
1573
39ff0b81
NC		 15742020-06-22 Nelson Chu <nelson.chu@sifive.com>
1575
1576 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1577 * riscv-dis.c: Include elfxx-riscv.h.
1578
d27c357a
JB		 15792020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1580
1581 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1582
6fde587f
CL		 15832020-06-17 Lili Cui <lili.cui@intel.com>
1584
1585 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1586
efe30057
L		 15872020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1588
1589 PR gas/26115
1590 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1591 * i386-opc.tbl: Likewise.
1592 * i386-tbl.h: Regenerated.
1593
d8af286f
NC		 15942020-06-12 Nelson Chu <nelson.chu@sifive.com>
1595
1596 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1597
14962256
AC		 15982020-06-11 Alex Coplan <alex.coplan@arm.com>
1599
1600 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1601 (SR_CORE): Likewise.
1602 (SR_FEAT): Likewise.
1603 (SR_RNG): Likewise.
1604 (SR_V8_1): Likewise.
1605 (SR_V8_2): Likewise.
1606 (SR_V8_3): Likewise.
1607 (SR_V8_4): Likewise.
1608 (SR_PAN): Likewise.
1609 (SR_RAS): Likewise.
1610 (SR_SSBS): Likewise.
1611 (SR_SVE): Likewise.
1612 (SR_ID_PFR2): Likewise.
1613 (SR_PROFILE): Likewise.
1614 (SR_MEMTAG): Likewise.
1615 (SR_SCXTNUM): Likewise.
1616 (aarch64_sys_regs): Refactor to store feature information in the table.
1617 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1618 that now describe their own features.
1619 (aarch64_pstatefield_supported_p): Likewise.
1620
f9630fa6
L		 16212020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1622
1623 * i386-dis.c (prefix_table): Fix a typo in comments.
1624
73239888
JB		 16252020-06-09 Jan Beulich <jbeulich@suse.com>
1626
1627 * i386-dis.c (rex_ignored): Delete.
1628 (ckprefix): Drop rex_ignored initialization.
1629 (get_valid_dis386): Drop setting of rex_ignored.
1630 (print_insn): Drop checking of rex_ignored. Don't record data
1631 size prefix as used with VEX-and-alike encodings.
1632
18897deb
JB		 16332020-06-09 Jan Beulich <jbeulich@suse.com>
1634
1635 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1636 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1637 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1638 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1639 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1640 VEX_0F12, and VEX_0F16.
1641 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1642 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1643 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1644 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1645 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1646 MOD_VEX_0F16_PREFIX_2 entries.
1647
97e6786a
JB		 16482020-06-09 Jan Beulich <jbeulich@suse.com>
1649
1650 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1651 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1652 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1653 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1654 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1655 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1656 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1657 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1658 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1659 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1660 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1661 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1662 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1663 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1664 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1665 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1666 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1667 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1668 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1669 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1670 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1671 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1672 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1673 EVEX_W_0FC6_P_2): Delete.
1674 (print_insn): Add EVEX.W vs embedded prefix consistency check
1675 to prefix validation.
1676 * i386-dis-evex.h (evex_table): Don't further descend for
1677 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1678 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1679 and 0F2B.
1680 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1681 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1682 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1683 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1684 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1685 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1686 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1687 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1688 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1689 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1690 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1691 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1692 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1693 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1694 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1695 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1696 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1697 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1698 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1699 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1700 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1701 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1702 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1703 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1704 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1705 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1706 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1707
bf926894
JB		 17082020-06-09 Jan Beulich <jbeulich@suse.com>
1709
1710 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1711 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1712 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1713 vmovmskpX.
1714 (print_insn): Drop pointless check against bad_opcode. Split
1715 prefix validation into legacy and VEX-and-alike parts.
1716 (putop): Re-work 'X' macro handling.
1717
a5aaedb9
JB		 17182020-06-09 Jan Beulich <jbeulich@suse.com>
1719
1720 * i386-dis.c (MOD_0F51): Rename to ...
1721 (MOD_0F50): ... this.
1722
26417f19
AC		 17232020-06-08 Alex Coplan <alex.coplan@arm.com>
1724
1725 * arm-dis.c (arm_opcodes): Add dfb.
1726 (thumb32_opcodes): Add dfb.
1727
8a6fb3f9
JB		 17282020-06-08 Jan Beulich <jbeulich@suse.com>
1729
1730 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1731
1424c35d
AM		 17322020-06-06 Alan Modra <amodra@gmail.com>
1733
1734 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1735
d3d1cc7b
AM		 17362020-06-05 Alan Modra <amodra@gmail.com>
1737
1738 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1739 size is large enough.
1740
d8740be1
JM		 17412020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1742
1743 * disassemble.c (disassemble_init_for_target): Set endian_code for
1744 bpf targets.
1745 * bpf-desc.c: Regenerate.
1746 * bpf-opc.c: Likewise.
1747 * bpf-dis.c: Likewise.
1748
e9bffec9
JM		 17492020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1750
1751 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1752 (cgen_put_insn_value): Likewise.
1753 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1754 * cgen-dis.in (print_insn): Likewise.
1755 * cgen-ibld.in (insert_1): Likewise.
1756 (insert_1): Likewise.
1757 (insert_insn_normal): Likewise.
1758 (extract_1): Likewise.
1759 * bpf-dis.c: Regenerate.
1760 * bpf-ibld.c: Likewise.
1761 * bpf-ibld.c: Likewise.
1762 * cgen-dis.in: Likewise.
1763 * cgen-ibld.in: Likewise.
1764 * cgen-opc.c: Likewise.
1765 * epiphany-dis.c: Likewise.
1766 * epiphany-ibld.c: Likewise.
1767 * fr30-dis.c: Likewise.
1768 * fr30-ibld.c: Likewise.
1769 * frv-dis.c: Likewise.
1770 * frv-ibld.c: Likewise.
1771 * ip2k-dis.c: Likewise.
1772 * ip2k-ibld.c: Likewise.
1773 * iq2000-dis.c: Likewise.
1774 * iq2000-ibld.c: Likewise.
1775 * lm32-dis.c: Likewise.
1776 * lm32-ibld.c: Likewise.
1777 * m32c-dis.c: Likewise.
1778 * m32c-ibld.c: Likewise.
1779 * m32r-dis.c: Likewise.
1780 * m32r-ibld.c: Likewise.
1781 * mep-dis.c: Likewise.
1782 * mep-ibld.c: Likewise.
1783 * mt-dis.c: Likewise.
1784 * mt-ibld.c: Likewise.
1785 * or1k-dis.c: Likewise.
1786 * or1k-ibld.c: Likewise.
1787 * xc16x-dis.c: Likewise.
1788 * xc16x-ibld.c: Likewise.
1789 * xstormy16-dis.c: Likewise.
1790 * xstormy16-ibld.c: Likewise.
1791
b3db6d07
JM		 17922020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1793
1794 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1795 (print_insn_): Handle instruction endian.
1796 * bpf-dis.c: Regenerate.
1797 * bpf-desc.c: Regenerate.
1798 * epiphany-dis.c: Likewise.
1799 * epiphany-desc.c: Likewise.
1800 * fr30-dis.c: Likewise.
1801 * fr30-desc.c: Likewise.
1802 * frv-dis.c: Likewise.
1803 * frv-desc.c: Likewise.
1804 * ip2k-dis.c: Likewise.
1805 * ip2k-desc.c: Likewise.
1806 * iq2000-dis.c: Likewise.
1807 * iq2000-desc.c: Likewise.
1808 * lm32-dis.c: Likewise.
1809 * lm32-desc.c: Likewise.
1810 * m32c-dis.c: Likewise.
1811 * m32c-desc.c: Likewise.
1812 * m32r-dis.c: Likewise.
1813 * m32r-desc.c: Likewise.
1814 * mep-dis.c: Likewise.
1815 * mep-desc.c: Likewise.
1816 * mt-dis.c: Likewise.
1817 * mt-desc.c: Likewise.
1818 * or1k-dis.c: Likewise.
1819 * or1k-desc.c: Likewise.
1820 * xc16x-dis.c: Likewise.
1821 * xc16x-desc.c: Likewise.
1822 * xstormy16-dis.c: Likewise.
1823 * xstormy16-desc.c: Likewise.
1824
4ee4189f
NC		 18252020-06-03 Nick Clifton <nickc@redhat.com>
1826
1827 * po/sr.po: Updated Serbian translation.
1828
44730156
NC		 18292020-06-03 Nelson Chu <nelson.chu@sifive.com>
1830
1831 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1832 (riscv_get_priv_spec_class): Likewise.
1833
3c3d0376
AM		 18342020-06-01 Alan Modra <amodra@gmail.com>
1835
1836 * bpf-desc.c: Regenerate.
1837
78c1c354
JM		 18382020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1839 David Faust <david.faust@oracle.com>
1840
1841 * bpf-desc.c: Regenerate.
1842 * bpf-opc.h: Likewise.
1843 * bpf-opc.c: Likewise.
1844 * bpf-dis.c: Likewise.
1845
efcf5fb5
AM		 18462020-05-28 Alan Modra <amodra@gmail.com>
1847
1848 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1849 values.
1850
ab382d64
AM		 18512020-05-28 Alan Modra <amodra@gmail.com>
1852
1853 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1854 immediates.
1855 (print_insn_ns32k): Revert last change.
1856
151f5de4
NC		 18572020-05-28 Nick Clifton <nickc@redhat.com>
1858
1859 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1860 static.
1861
25e1eca8
SL		 18622020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1863
1864 Fix extraction of signed constants in nios2 disassembler (again).
1865
1866 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1867 extractions of signed fields.
1868
57b17940
SSF		 18692020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1870
1871 * s390-opc.txt: Relocate vector load/store instructions with
1872 additional alignment parameter and change architecture level
1873 constraint from z14 to z13.
1874
d96bf37b
AM		 18752020-05-21 Alan Modra <amodra@gmail.com>
1876
1877 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1878 * sparc-dis.c: Likewise.
1879 * tic4x-dis.c: Likewise.
1880 * xtensa-dis.c: Likewise.
1881 * bpf-desc.c: Regenerate.
1882 * epiphany-desc.c: Regenerate.
1883 * fr30-desc.c: Regenerate.
1884 * frv-desc.c: Regenerate.
1885 * ip2k-desc.c: Regenerate.
1886 * iq2000-desc.c: Regenerate.
1887 * lm32-desc.c: Regenerate.
1888 * m32c-desc.c: Regenerate.
1889 * m32r-desc.c: Regenerate.
1890 * mep-asm.c: Regenerate.
1891 * mep-desc.c: Regenerate.
1892 * mt-desc.c: Regenerate.
1893 * or1k-desc.c: Regenerate.
1894 * xc16x-desc.c: Regenerate.
1895 * xstormy16-desc.c: Regenerate.
1896
8f595e9b
NC		 18972020-05-20 Nelson Chu <nelson.chu@sifive.com>
1898
1899 * riscv-opc.c (riscv_ext_version_table): The table used to store
1900 all information about the supported spec and the corresponding ISA
1901 versions. Currently, only Zicsr is supported to verify the
1902 correctness of Z sub extension settings. Others will be supported
1903 in the future patches.
1904 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1905 classes and the corresponding strings.
1906 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1907 spec class by giving a ISA spec string.
1908 * riscv-opc.c (struct priv_spec_t): New structure.
1909 (struct priv_spec_t priv_specs): List for all supported privilege spec
1910 classes and the corresponding strings.
1911 (riscv_get_priv_spec_class): New function. Get the corresponding
1912 privilege spec class by giving a spec string.
1913 (riscv_get_priv_spec_name): New function. Get the corresponding
1914 privilege spec string by giving a CSR version class.
1915 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1916 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1917 according to the chosen version. Build a hash table riscv_csr_hash to
1918 store the valid CSR for the chosen pirv verison. Dump the direct
1919 CSR address rather than it's name if it is invalid.
1920 (parse_riscv_dis_option_without_args): New function. Parse the options
1921 without arguments.
1922 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1923 parse the options without arguments first, and then handle the options
1924 with arguments. Add the new option -Mpriv-spec, which has argument.
1925 * riscv-dis.c (print_riscv_disassembler_options): Add description
1926 about the new OBJDUMP option.
1927
3d205eb4
PB		 19282020-05-19 Peter Bergner <bergner@linux.ibm.com>
1929
1930 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1931 WC values on POWER10 sync, dcbf and wait instructions.
1932 (insert_pl, extract_pl): New functions.
1933 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1934 (LS3): New , 3-bit L for sync.
1935 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1936 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1937 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1938 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1939 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1940 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1941 <wait>: Enable PL operand on POWER10.
1942 <dcbf>: Enable L3OPT operand on POWER10.
1943 <sync>: Enable SC2 operand on POWER10.
1944
a501eb44
SH		 19452020-05-19 Stafford Horne <shorne@gmail.com>
1946
1947 PR 25184
1948 * or1k-asm.c: Regenerate.
1949 * or1k-desc.c: Regenerate.
1950 * or1k-desc.h: Regenerate.
1951 * or1k-dis.c: Regenerate.
1952 * or1k-ibld.c: Regenerate.
1953 * or1k-opc.c: Regenerate.
1954 * or1k-opc.h: Regenerate.
1955 * or1k-opinst.c: Regenerate.
1956
3b646889
AM		 19572020-05-11 Alan Modra <amodra@gmail.com>
1958
1959 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1960 xsmaxcqp, xsmincqp.
1961
9cc4ce88
AM		 19622020-05-11 Alan Modra <amodra@gmail.com>
1963
1964 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1965 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1966
5d57bc3f
AM		 19672020-05-11 Alan Modra <amodra@gmail.com>
1968
1969 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1970
66ef5847
AM		 19712020-05-11 Alan Modra <amodra@gmail.com>
1972
1973 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1974 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1975
4f3e9537
PB		 19762020-05-11 Peter Bergner <bergner@linux.ibm.com>
1977
1978 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1979 mnemonics.
1980
ec40e91c
AM		 19812020-05-11 Alan Modra <amodra@gmail.com>
1982
1983 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1984 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1985 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1986 (prefix_opcodes): Add xxeval.
1987
d7e97a76
AM		 19882020-05-11 Alan Modra <amodra@gmail.com>
1989
1990 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1991 xxgenpcvwm, xxgenpcvdm.
1992
fdefed7c
AM		 19932020-05-11 Alan Modra <amodra@gmail.com>
1994
1995 * ppc-opc.c (MP, VXVAM_MASK): Define.
1996 (VXVAPS_MASK): Use VXVA_MASK.
1997 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1998 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1999 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2000 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2001
aa3c112f
AM		 20022020-05-11 Alan Modra <amodra@gmail.com>
2003 Peter Bergner <bergner@linux.ibm.com>
2004
2005 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2006 New functions.
2007 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2008 YMSK2, XA6a, XA6ap, XB6a entries.
2009 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2010 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2011 (PPCVSX4): Define.
2012 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2013 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2014 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2015 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2016 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2017 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2018 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2019 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2020 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2021 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2022 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2023 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2024 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2025 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2026
6edbfd3b
AM		 20272020-05-11 Alan Modra <amodra@gmail.com>
2028
2029 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2030 (insert_xts, extract_xts): New functions.
2031 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2032 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2033 (VXRC_MASK, VXSH_MASK): Define.
2034 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2035 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2036 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2037 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2038 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2039 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2040 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2041
c7d7aea2
AM		 20422020-05-11 Alan Modra <amodra@gmail.com>
2043
2044 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2045 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2046 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2047 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2048 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2049
94ba9882
AM		 20502020-05-11 Alan Modra <amodra@gmail.com>
2051
2052 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2053 (XTP, DQXP, DQXP_MASK): Define.
2054 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2055 (prefix_opcodes): Add plxvp and pstxvp.
2056
f4791f1a
AM		 20572020-05-11 Alan Modra <amodra@gmail.com>
2058
2059 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2060 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2061 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2062
3ff0a5ba
PB		 20632020-05-11 Peter Bergner <bergner@linux.ibm.com>
2064
2065 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2066
afef4fe9
PB		 20672020-05-11 Peter Bergner <bergner@linux.ibm.com>
2068
2069 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2070 (L1OPT): Define.
2071 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2072
1224c05d
PB		 20732020-05-11 Peter Bergner <bergner@linux.ibm.com>
2074
2075 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2076
6bbb0c05
AM		 20772020-05-11 Alan Modra <amodra@gmail.com>
2078
2079 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2080
7c1f4227
AM		 20812020-05-11 Alan Modra <amodra@gmail.com>
2082
2083 * ppc-dis.c (ppc_opts): Add "power10" entry.
2084 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2085 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2086
73199c2b
NC		 20872020-05-11 Nick Clifton <nickc@redhat.com>
2088
2089 * po/fr.po: Updated French translation.
2090
09c1e68a
AC		 20912020-04-30 Alex Coplan <alex.coplan@arm.com>
2092
2093 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2094 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2095 (operand_general_constraint_met_p): validate
2096 AARCH64_OPND_UNDEFINED.
2097 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2098 for FLD_imm16_2.
2099 * aarch64-asm-2.c: Regenerated.
2100 * aarch64-dis-2.c: Regenerated.
2101 * aarch64-opc-2.c: Regenerated.
2102
9654d51a
NC		 21032020-04-29 Nick Clifton <nickc@redhat.com>
2104
2105 PR 22699
2106 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2107 and SETRC insns.
2108
c2e71e57
NC		 21092020-04-29 Nick Clifton <nickc@redhat.com>
2110
2111 * po/sv.po: Updated Swedish translation.
2112
5c936ef5
NC		 21132020-04-29 Nick Clifton <nickc@redhat.com>
2114
2115 PR 22699
2116 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2117 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2118 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2119 IMM0_8U case.
2120
bb2a1453
AS		 21212020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2122
2123 PR 25848
2124 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2125 cmpi only on m68020up and cpu32.
2126
c2e5c986
SD		 21272020-04-20 Sudakshina Das <sudi.das@arm.com>
2128
2129 * aarch64-asm.c (aarch64_ins_none): New.
2130 * aarch64-asm.h (ins_none): New declaration.
2131 * aarch64-dis.c (aarch64_ext_none): New.
2132 * aarch64-dis.h (ext_none): New declaration.
2133 * aarch64-opc.c (aarch64_print_operand): Update case for
2134 AARCH64_OPND_BARRIER_PSB.
2135 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2136 (AARCH64_OPERANDS): Update inserter/extracter for
2137 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2138 * aarch64-asm-2.c: Regenerated.
2139 * aarch64-dis-2.c: Regenerated.
2140 * aarch64-opc-2.c: Regenerated.
2141
8a6e1d1d
SD		 21422020-04-20 Sudakshina Das <sudi.das@arm.com>
2143
2144 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2145 (aarch64_feature_ras, RAS): Likewise.
2146 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2147 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2148 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2149 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2150 * aarch64-asm-2.c: Regenerated.
2151 * aarch64-dis-2.c: Regenerated.
2152 * aarch64-opc-2.c: Regenerated.
2153
e409955d
FS		 21542020-04-17 Fredrik Strupe <fredrik@strupe.net>
2155
2156 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2157 (print_insn_neon): Support disassembly of conditional
2158 instructions.
2159
c54a9b56
DF		 21602020-02-16 David Faust <david.faust@oracle.com>
2161
2162 * bpf-desc.c: Regenerate.
2163 * bpf-desc.h: Likewise.
2164 * bpf-opc.c: Regenerate.
2165 * bpf-opc.h: Likewise.
2166
bb651e8b
CL		 21672020-04-07 Lili Cui <lili.cui@intel.com>
2168
2169 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2170 (prefix_table): New instructions (see prefixes above).
2171 (rm_table): Likewise
2172 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2173 CPU_ANY_TSXLDTRK_FLAGS.
2174 (cpu_flags): Add CpuTSXLDTRK.
2175 * i386-opc.h (enum): Add CpuTSXLDTRK.
2176 (i386_cpu_flags): Add cputsxldtrk.
2177 * i386-opc.tbl: Add XSUSPLDTRK insns.
2178 * i386-init.h: Regenerate.
2179 * i386-tbl.h: Likewise.
2180
4b27d27c
L		 21812020-04-02 Lili Cui <lili.cui@intel.com>
2182
2183 * i386-dis.c (prefix_table): New instructions serialize.
2184 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2185 CPU_ANY_SERIALIZE_FLAGS.
2186 (cpu_flags): Add CpuSERIALIZE.
2187 * i386-opc.h (enum): Add CpuSERIALIZE.
2188 (i386_cpu_flags): Add cpuserialize.
2189 * i386-opc.tbl: Add SERIALIZE insns.
2190 * i386-init.h: Regenerate.
2191 * i386-tbl.h: Likewise.
2192
832a5807
AM		 21932020-03-26 Alan Modra <amodra@gmail.com>
2194
2195 * disassemble.h (opcodes_assert): Declare.
2196 (OPCODES_ASSERT): Define.
2197 * disassemble.c: Don't include assert.h. Include opintl.h.
2198 (opcodes_assert): New function.
2199 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2200 (bfd_h8_disassemble): Reduce size of data array. Correctly
2201 calculate maxlen. Omit insn decoding when insn length exceeds
2202 maxlen. Exit from nibble loop when looking for E, before
2203 accessing next data byte. Move processing of E outside loop.
2204 Replace tests of maxlen in loop with assertions.
2205
4c4addbe
AM		 22062020-03-26 Alan Modra <amodra@gmail.com>
2207
2208 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2209
a18cd0ca
AM		 22102020-03-25 Alan Modra <amodra@gmail.com>
2211
2212 * z80-dis.c (suffix): Init mybuf.
2213
57cb32b3
AM		 22142020-03-22 Alan Modra <amodra@gmail.com>
2215
2216 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2217 successflly read from section.
2218
beea5cc1
AM		 22192020-03-22 Alan Modra <amodra@gmail.com>
2220
2221 * arc-dis.c (find_format): Use ISO C string concatenation rather
2222 than line continuation within a string. Don't access needs_limm
2223 before testing opcode != NULL.
2224
03704c77
AM		 22252020-03-22 Alan Modra <amodra@gmail.com>
2226
2227 * ns32k-dis.c (print_insn_arg): Update comment.
2228 (print_insn_ns32k): Reduce size of index_offset array, and
2229 initialize, passing -1 to print_insn_arg for args that are not
2230 an index. Don't exit arg loop early. Abort on bad arg number.
2231
d1023b5d
AM		 22322020-03-22 Alan Modra <amodra@gmail.com>
2233
2234 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2235 * s12z-opc.c: Formatting.
2236 (operands_f): Return an int.
2237 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2238 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2239 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2240 (exg_sex_discrim): Likewise.
2241 (create_immediate_operand, create_bitfield_operand),
2242 (create_register_operand_with_size, create_register_all_operand),
2243 (create_register_all16_operand, create_simple_memory_operand),
2244 (create_memory_operand, create_memory_auto_operand): Don't
2245 segfault on malloc failure.
2246 (z_ext24_decode): Return an int status, negative on fail, zero
2247 on success.
2248 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2249 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2250 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2251 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2252 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2253 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2254 (loop_primitive_decode, shift_decode, psh_pul_decode),
2255 (bit_field_decode): Similarly.
2256 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2257 to return value, update callers.
2258 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2259 Don't segfault on NULL operand.
2260 (decode_operation): Return OP_INVALID on first fail.
2261 (decode_s12z): Check all reads, returning -1 on fail.
2262
340f3ac8
AM		 22632020-03-20 Alan Modra <amodra@gmail.com>
2264
2265 * metag-dis.c (print_insn_metag): Don't ignore status from
2266 read_memory_func.
2267
fe90ae8a
AM		 22682020-03-20 Alan Modra <amodra@gmail.com>
2269
2270 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2271 Initialize parts of buffer not written when handling a possible
2272 2-byte insn at end of section. Don't attempt decoding of such
2273 an insn by the 4-byte machinery.
2274
833d919c
AM		 22752020-03-20 Alan Modra <amodra@gmail.com>
2276
2277 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2278 partially filled buffer. Prevent lookup of 4-byte insns when
2279 only VLE 2-byte insns are possible due to section size. Print
2280 ".word" rather than ".long" for 2-byte leftovers.
2281
327ef784
NC		 22822020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2283
2284 PR 25641
2285 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2286
1673df32
JB		 22872020-03-13 Jan Beulich <jbeulich@suse.com>
2288
2289 * i386-dis.c (X86_64_0D): Rename to ...
2290 (X86_64_0E): ... this.
2291
384f3689
L		 22922020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2293
2294 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2295 * Makefile.in: Regenerated.
2296
865e2027
JB		 22972020-03-09 Jan Beulich <jbeulich@suse.com>
2298
2299 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2300 3-operand pseudos.
2301 * i386-tbl.h: Re-generate.
2302
2f13234b
JB		 23032020-03-09 Jan Beulich <jbeulich@suse.com>
2304
2305 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2306 vprot*, vpsha*, and vpshl*.
2307 * i386-tbl.h: Re-generate.
2308
3fabc179
JB		 23092020-03-09 Jan Beulich <jbeulich@suse.com>
2310
2311 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2312 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2313 * i386-tbl.h: Re-generate.
2314
3677e4c1
JB		 23152020-03-09 Jan Beulich <jbeulich@suse.com>
2316
2317 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2318 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2319 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2320 * i386-tbl.h: Re-generate.
2321
4c4898e8
JB		 23222020-03-09 Jan Beulich <jbeulich@suse.com>
2323
2324 * i386-gen.c (struct template_arg, struct template_instance,
2325 struct template_param, struct template, templates,
2326 parse_template, expand_templates): New.
2327 (process_i386_opcodes): Various local variables moved to
2328 expand_templates. Call parse_template and expand_templates.
2329 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2330 * i386-tbl.h: Re-generate.
2331
bc49bfd8
JB		 23322020-03-06 Jan Beulich <jbeulich@suse.com>
2333
2334 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2335 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2336 register and memory source templates. Replace VexW= by VexW*
2337 where applicable.
2338 * i386-tbl.h: Re-generate.
2339
4873e243
JB		 23402020-03-06 Jan Beulich <jbeulich@suse.com>
2341
2342 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2343 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2344 * i386-tbl.h: Re-generate.
2345
672a349b
JB		 23462020-03-06 Jan Beulich <jbeulich@suse.com>
2347
2348 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2349 * i386-tbl.h: Re-generate.
2350
4ed21b58
JB		 23512020-03-06 Jan Beulich <jbeulich@suse.com>
2352
2353 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2354 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2355 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2356 VexW0 on SSE2AVX variants.
2357 (vmovq): Drop NoRex64 from XMM/XMM variants.
2358 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2359 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2360 applicable use VexW0.
2361 * i386-tbl.h: Re-generate.
2362
643bb870
JB		 23632020-03-06 Jan Beulich <jbeulich@suse.com>
2364
2365 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2366 * i386-opc.h (Rex64): Delete.
2367 (struct i386_opcode_modifier): Remove rex64 field.
2368 * i386-opc.tbl (crc32): Drop Rex64.
2369 Replace Rex64 with Size64 everywhere else.
2370 * i386-tbl.h: Re-generate.
2371
a23b33b3
JB		 23722020-03-06 Jan Beulich <jbeulich@suse.com>
2373
2374 * i386-dis.c (OP_E_memory): Exclude recording of used address
2375 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2376 addressed memory operands for MPX insns.
2377
a0497384
JB		 23782020-03-06 Jan Beulich <jbeulich@suse.com>
2379
2380 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2381 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2382 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2383 (ptwrite): Split into non-64-bit and 64-bit forms.
2384 * i386-tbl.h: Re-generate.
2385
b630c145
JB		 23862020-03-06 Jan Beulich <jbeulich@suse.com>
2387
2388 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2389 template.
2390 * i386-tbl.h: Re-generate.
2391
a847e322
JB		 23922020-03-04 Jan Beulich <jbeulich@suse.com>
2393
2394 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2395 (prefix_table): Move vmmcall here. Add vmgexit.
2396 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2397 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2398 (cpu_flags): Add CpuSEV_ES entry.
2399 * i386-opc.h (CpuSEV_ES): New.
2400 (union i386_cpu_flags): Add cpusev_es field.
2401 * i386-opc.tbl (vmgexit): New.
2402 * i386-init.h, i386-tbl.h: Re-generate.
2403
3cd7f3e3
L		 24042020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2405
2406 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2407 with MnemonicSize.
2408 * i386-opc.h (IGNORESIZE): New.
2409 (DEFAULTSIZE): Likewise.
2410 (IgnoreSize): Removed.
2411 (DefaultSize): Likewise.
2412 (MnemonicSize): New.
2413 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2414 mnemonicsize.
2415 * i386-opc.tbl (IgnoreSize): New.
2416 (DefaultSize): Likewise.
2417 * i386-tbl.h: Regenerated.
2418
b8ba1385
SB		 24192020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2420
2421 PR 25627
2422 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2423 instructions.
2424
10d97a0f
L		 24252020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2426
2427 PR gas/25622
2428 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2429 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2430 * i386-tbl.h: Regenerated.
2431
dc1e8a47
AM		 24322020-02-26 Alan Modra <amodra@gmail.com>
2433
2434 * aarch64-asm.c: Indent labels correctly.
2435 * aarch64-dis.c: Likewise.
2436 * aarch64-gen.c: Likewise.
2437 * aarch64-opc.c: Likewise.
2438 * alpha-dis.c: Likewise.
2439 * i386-dis.c: Likewise.
2440 * nds32-asm.c: Likewise.
2441 * nfp-dis.c: Likewise.
2442 * visium-dis.c: Likewise.
2443
265b4673
CZ		 24442020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2445
2446 * arc-regs.h (int_vector_base): Make it available for all ARC
2447 CPUs.
2448
bd0cf5a6
NC		 24492020-02-20 Nelson Chu <nelson.chu@sifive.com>
2450
2451 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2452 changed.
2453
fa164239
JW		 24542020-02-19 Nelson Chu <nelson.chu@sifive.com>
2455
2456 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2457 c.mv/c.li if rs1 is zero.
2458
272a84b1
L		 24592020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2460
2461 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2462 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2463 CPU_POPCNT_FLAGS.
2464 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2465 * i386-opc.h (CpuABM): Removed.
2466 (CpuPOPCNT): New.
2467 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2468 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2469 popcnt. Remove CpuABM from lzcnt.
2470 * i386-init.h: Regenerated.
2471 * i386-tbl.h: Likewise.
2472
1f730c46
JB		 24732020-02-17 Jan Beulich <jbeulich@suse.com>
2474
2475 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2476 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2477 VexW1 instead of open-coding them.
2478 * i386-tbl.h: Re-generate.
2479
c8f8eebc
JB		 24802020-02-17 Jan Beulich <jbeulich@suse.com>
2481
2482 * i386-opc.tbl (AddrPrefixOpReg): Define.
2483 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2484 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2485 templates. Drop NoRex64.
2486 * i386-tbl.h: Re-generate.
2487
b9915cbc
JB		 24882020-02-17 Jan Beulich <jbeulich@suse.com>
2489
2490 PR gas/6518
2491 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2492 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2493 into Intel syntax instance (with Unpsecified) and AT&T one
2494 (without).
2495 (vcvtneps2bf16): Likewise, along with folding the two so far
2496 separate ones.
2497 * i386-tbl.h: Re-generate.
2498
ce504911
L		 24992020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2500
2501 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2502 CPU_ANY_SSE4A_FLAGS.
2503
dabec65d
AM		 25042020-02-17 Alan Modra <amodra@gmail.com>
2505
2506 * i386-gen.c (cpu_flag_init): Correct last change.
2507
af5c13b0
L		 25082020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2509
2510 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2511 CPU_ANY_SSE4_FLAGS.
2512
6867aac0
L		 25132020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2514
2515 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2516 (movzx): Likewise.
2517
65fca059
JB		 25182020-02-14 Jan Beulich <jbeulich@suse.com>
2519
2520 PR gas/25438
2521 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2522 destination for Cpu64-only variant.
2523 (movzx): Fold patterns.
2524 * i386-tbl.h: Re-generate.
2525
7deea9aa
JB		 25262020-02-13 Jan Beulich <jbeulich@suse.com>
2527
2528 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2529 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2530 CPU_ANY_SSE4_FLAGS entry.
2531 * i386-init.h: Re-generate.
2532
6c0946d0
JB		 25332020-02-12 Jan Beulich <jbeulich@suse.com>
2534
2535 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2536 with Unspecified, making the present one AT&T syntax only.
2537 * i386-tbl.h: Re-generate.
2538
ddb56fe6
JB		 25392020-02-12 Jan Beulich <jbeulich@suse.com>
2540
2541 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2542 * i386-tbl.h: Re-generate.
2543
5990e377
JB		 25442020-02-12 Jan Beulich <jbeulich@suse.com>
2545
2546 PR gas/24546
2547 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2548 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2549 Amd64 and Intel64 templates.
2550 (call, jmp): Likewise for far indirect variants. Dro
2551 Unspecified.
2552 * i386-tbl.h: Re-generate.
2553
50128d0c
JB		 25542020-02-11 Jan Beulich <jbeulich@suse.com>
2555
2556 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2557 * i386-opc.h (ShortForm): Delete.
2558 (struct i386_opcode_modifier): Remove shortform field.
2559 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2560 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2561 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2562 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2563 Drop ShortForm.
2564 * i386-tbl.h: Re-generate.
2565
1e05b5c4
JB		 25662020-02-11 Jan Beulich <jbeulich@suse.com>
2567
2568 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2569 fucompi): Drop ShortForm from operand-less templates.
2570 * i386-tbl.h: Re-generate.
2571
2f5dd314
AM		 25722020-02-11 Alan Modra <amodra@gmail.com>
2573
2574 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2575 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2576 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2577 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2578 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2579
5aae9ae9
MM		 25802020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2581
2582 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2583 (cde_opcodes): Add VCX* instructions.
2584
4934a27c
MM		 25852020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2586 Matthew Malcomson <matthew.malcomson@arm.com>
2587
2588 * arm-dis.c (struct cdeopcode32): New.
2589 (CDE_OPCODE): New macro.
2590 (cde_opcodes): New disassembly table.
2591 (regnames): New option to table.
2592 (cde_coprocs): New global variable.
2593 (print_insn_cde): New
2594 (print_insn_thumb32): Use print_insn_cde.
2595 (parse_arm_disassembler_options): Parse coprocN args.
2596
4b5aaf5f
L		 25972020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2598
2599 PR gas/25516
2600 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2601 with ISA64.
2602 * i386-opc.h (AMD64): Removed.
2603 (Intel64): Likewose.
2604 (AMD64): New.
2605 (INTEL64): Likewise.
2606 (INTEL64ONLY): Likewise.
2607 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2608 * i386-opc.tbl (Amd64): New.
2609 (Intel64): Likewise.
2610 (Intel64Only): Likewise.
2611 Replace AMD64 with Amd64. Update sysenter/sysenter with
2612 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2613 * i386-tbl.h: Regenerated.
2614
9fc0b501
SB		 26152020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2616
2617 PR 25469
2618 * z80-dis.c: Add support for GBZ80 opcodes.
2619
c5d7be0c
AM		 26202020-02-04 Alan Modra <amodra@gmail.com>
2621
2622 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2623
44e4546f
AM		 26242020-02-03 Alan Modra <amodra@gmail.com>
2625
2626 * m32c-ibld.c: Regenerate.
2627
b2b1453a
AM		 26282020-02-01 Alan Modra <amodra@gmail.com>
2629
2630 * frv-ibld.c: Regenerate.
2631
4102be5c
JB		 26322020-01-31 Jan Beulich <jbeulich@suse.com>
2633
2634 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2635 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2636 (OP_E_memory): Replace xmm_mdq_mode case label by
2637 vex_scalar_w_dq_mode one.
2638 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2639
825bd36c
JB		 26402020-01-31 Jan Beulich <jbeulich@suse.com>
2641
2642 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2643 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2644 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2645 (intel_operand_size): Drop vex_w_dq_mode case label.
2646
c3036ed0
RS		 26472020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2648
2649 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2650 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2651
0c115f84
AM		 26522020-01-30 Alan Modra <amodra@gmail.com>
2653
2654 * m32c-ibld.c: Regenerate.
2655
bd434cc4
JM		 26562020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2657
2658 * bpf-opc.c: Regenerate.
2659
aeab2b26
JB		 26602020-01-30 Jan Beulich <jbeulich@suse.com>
2661
2662 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2663 (dis386): Use them to replace C2/C3 table entries.
2664 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2665 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2666 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2667 * i386-tbl.h: Re-generate.
2668
62b3f548
JB		 26692020-01-30 Jan Beulich <jbeulich@suse.com>
2670
2671 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2672 forms.
2673 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2674 DefaultSize.
2675 * i386-tbl.h: Re-generate.
2676
1bd8ae10
AM		 26772020-01-30 Alan Modra <amodra@gmail.com>
2678
2679 * tic4x-dis.c (tic4x_dp): Make unsigned.
2680
bc31405e
L		 26812020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2682 Jan Beulich <jbeulich@suse.com>
2683
2684 PR binutils/25445
2685 * i386-dis.c (MOVSXD_Fixup): New function.
2686 (movsxd_mode): New enum.
2687 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2688 (intel_operand_size): Handle movsxd_mode.
2689 (OP_E_register): Likewise.
2690 (OP_G): Likewise.
2691 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2692 register on movsxd. Add movsxd with 16-bit destination register
2693 for AMD64 and Intel64 ISAs.
2694 * i386-tbl.h: Regenerated.
2695
7568c93b
TC		 26962020-01-27 Tamar Christina <tamar.christina@arm.com>
2697
2698 PR 25403
2699 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2700 * aarch64-asm-2.c: Regenerate
2701 * aarch64-dis-2.c: Likewise.
2702 * aarch64-opc-2.c: Likewise.
2703
c006a730
JB		 27042020-01-21 Jan Beulich <jbeulich@suse.com>
2705
2706 * i386-opc.tbl (sysret): Drop DefaultSize.
2707 * i386-tbl.h: Re-generate.
2708
c906a69a
JB		 27092020-01-21 Jan Beulich <jbeulich@suse.com>
2710
2711 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2712 Dword.
2713 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2714 * i386-tbl.h: Re-generate.
2715
26916852
NC		 27162020-01-20 Nick Clifton <nickc@redhat.com>
2717
2718 * po/de.po: Updated German translation.
2719 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2720 * po/uk.po: Updated Ukranian translation.
2721
4d6cbb64
AM		 27222020-01-20 Alan Modra <amodra@gmail.com>
2723
2724 * hppa-dis.c (fput_const): Remove useless cast.
2725
2bddb71a
AM		 27262020-01-20 Alan Modra <amodra@gmail.com>
2727
2728 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2729
1b1bb2c6
NC		 27302020-01-18 Nick Clifton <nickc@redhat.com>
2731
2732 * configure: Regenerate.
2733 * po/opcodes.pot: Regenerate.
2734
ae774686
NC		 27352020-01-18 Nick Clifton <nickc@redhat.com>
2736
2737 Binutils 2.34 branch created.
2738
07f1f3aa
CB		 27392020-01-17 Christian Biesinger <cbiesinger@google.com>
2740
2741 * opintl.h: Fix spelling error (seperate).
2742
42e04b36
L		 27432020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2744
2745 * i386-opc.tbl: Add {vex} pseudo prefix.
2746 * i386-tbl.h: Regenerated.
2747
2da2eaf4
AV		 27482020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2749
2750 PR 25376
0be2fe67 2751 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2da2eaf4
AV		 2752 (neon_opcodes): Likewise.
2753 (select_arm_features): Make sure we enable MVE bits when selecting
2754 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2755 any architecture.
2756
d0849eed
JB		 27572020-01-16 Jan Beulich <jbeulich@suse.com>
2758
2759 * i386-opc.tbl: Drop stale comment from XOP section.
2760
9cf70a44
JB		 27612020-01-16 Jan Beulich <jbeulich@suse.com>
2762
2763 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2764 (extractps): Add VexWIG to SSE2AVX forms.
2765 * i386-tbl.h: Re-generate.
2766
4814632e
JB		 27672020-01-16 Jan Beulich <jbeulich@suse.com>
2768
2769 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2770 Size64 from and use VexW1 on SSE2AVX forms.
2771 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2772 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2773 * i386-tbl.h: Re-generate.
2774
aad09917
AM		 27752020-01-15 Alan Modra <amodra@gmail.com>
2776
2777 * tic4x-dis.c (tic4x_version): Make unsigned long.
2778 (optab, optab_special, registernames): New file scope vars.
2779 (tic4x_print_register): Set up registernames rather than
2780 malloc'd registertable.
2781 (tic4x_disassemble): Delete optable and optable_special. Use
2782 optab and optab_special instead. Throw away old optab,
2783 optab_special and registernames when info->mach changes.
2784
7a6bf3be
SB		 27852020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2786
2787 PR 25377
2788 * z80-dis.c (suffix): Use .db instruction to generate double
2789 prefix.
2790
ca1eaac0
AM		 27912020-01-14 Alan Modra <amodra@gmail.com>
2792
2793 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2794 values to unsigned before shifting.
2795
1d67fe3b
TT		 27962020-01-13 Thomas Troeger <tstroege@gmx.de>
2797
2798 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2799 flow instructions.
2800 (print_insn_thumb16, print_insn_thumb32): Likewise.
2801 (print_insn): Initialize the insn info.
2802 * i386-dis.c (print_insn): Initialize the insn info fields, and
2803 detect jumps.
2804
0be2fe67 28052020-01-13 Claudiu Zissulescu <claziss@gmail.com>
5e4f7e05
CZ		 2806
2807 * arc-opc.c (C_NE): Make it required.
2808
0be2fe67 28092020-01-13 Claudiu Zissulescu <claziss@gmail.com>
b9fe6b8a 2810
0be2fe67 2811 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
b9fe6b8a
CZ		 2812 reserved register name.
2813
90dee485
AM		 28142020-01-13 Alan Modra <amodra@gmail.com>
2815
2816 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2817 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2818
febda64f
AM		 28192020-01-13 Alan Modra <amodra@gmail.com>
2820
2821 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2822 result of wasm_read_leb128 in a uint64_t and check that bits
2823 are not lost when copying to other locals. Use uint32_t for
2824 most locals. Use PRId64 when printing int64_t.
2825
df08b588
AM		 28262020-01-13 Alan Modra <amodra@gmail.com>
2827
2828 * score-dis.c: Formatting.
2829 * score7-dis.c: Formatting.
2830
b2c759ce
AM		 28312020-01-13 Alan Modra <amodra@gmail.com>
2832
2833 * score-dis.c (print_insn_score48): Use unsigned variables for
2834 unsigned values. Don't left shift negative values.
2835 (print_insn_score32): Likewise.
2836 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2837
5496abe1
AM		 28382020-01-13 Alan Modra <amodra@gmail.com>
2839
2840 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2841
202e762b
AM		 28422020-01-13 Alan Modra <amodra@gmail.com>
2843
2844 * fr30-ibld.c: Regenerate.
2845
7ef412cf
AM		 28462020-01-13 Alan Modra <amodra@gmail.com>
2847
2848 * xgate-dis.c (print_insn): Don't left shift signed value.
2849 (ripBits): Formatting, use 1u.
2850
7f578b95
AM		 28512020-01-10 Alan Modra <amodra@gmail.com>
2852
2853 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2854 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2855
441af85b
AM		 28562020-01-10 Alan Modra <amodra@gmail.com>
2857
2858 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2859 and XRREG value earlier to avoid a shift with negative exponent.
2860 * m10200-dis.c (disassemble): Similarly.
2861
bce58db4
NC		 28622020-01-09 Nick Clifton <nickc@redhat.com>
2863
2864 PR 25224
2865 * z80-dis.c (ld_ii_ii): Use correct cast.
2866
40c75bc8
SB		 28672020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2868
2869 PR 25224
2870 * z80-dis.c (ld_ii_ii): Use character constant when checking
2871 opcode byte value.
2872
d835a58b
JB		 28732020-01-09 Jan Beulich <jbeulich@suse.com>
2874
2875 * i386-dis.c (SEP_Fixup): New.
2876 (SEP): Define.
2877 (dis386_twobyte): Use it for sysenter/sysexit.
2878 (enum x86_64_isa): Change amd64 enumerator to value 1.
2879 (OP_J): Compare isa64 against intel64 instead of amd64.
2880 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2881 forms.
2882 * i386-tbl.h: Re-generate.
2883
030a2e78
AM		 28842020-01-08 Alan Modra <amodra@gmail.com>
2885
2886 * z8k-dis.c: Include libiberty.h
2887 (instr_data_s): Make max_fetched unsigned.
2888 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2889 Don't exceed byte_info bounds.
2890 (output_instr): Make num_bytes unsigned.
2891 (unpack_instr): Likewise for nibl_count and loop.
2892 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2893 idx unsigned.
2894 * z8k-opc.h: Regenerate.
2895
bb82aefe
SV		 28962020-01-07 Shahab Vahedi <shahab@synopsys.com>
2897
2898 * arc-tbl.h (llock): Use 'LLOCK' as class.
2899 (llockd): Likewise.
2900 (scond): Use 'SCOND' as class.
2901 (scondd): Likewise.
2902 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2903 (scondd): Likewise.
2904
cc6aa1a6
AM		 29052020-01-06 Alan Modra <amodra@gmail.com>
2906
2907 * m32c-ibld.c: Regenerate.
2908
660e62b1
AM		 29092020-01-06 Alan Modra <amodra@gmail.com>
2910
2911 PR 25344
2912 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2913 Peek at next byte to prevent recursion on repeated prefix bytes.
2914 Ensure uninitialised "mybuf" is not accessed.
2915 (print_insn_z80): Don't zero n_fetch and n_used here,..
2916 (print_insn_z80_buf): ..do it here instead.
2917
c9ae58fe
AM		 29182020-01-04 Alan Modra <amodra@gmail.com>
2919
2920 * m32r-ibld.c: Regenerate.
2921
5f57d4ec
AM		 29222020-01-04 Alan Modra <amodra@gmail.com>
2923
2924 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2925
2c5c1196
AM		 29262020-01-04 Alan Modra <amodra@gmail.com>
2927
2928 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2929
2e98c6c5
AM		 29302020-01-04 Alan Modra <amodra@gmail.com>
2931
2932 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2933
567dfba2
JB		 29342020-01-03 Jan Beulich <jbeulich@suse.com>
2935
5437a02a
JB		 2936 * aarch64-tbl.h (aarch64_opcode_table): Use
2937 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2938
29392020-01-03 Jan Beulich <jbeulich@suse.com>
2940
2941 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2942 forms of SUDOT and USDOT.
2943
8c45011a
JB		 29442020-01-03 Jan Beulich <jbeulich@suse.com>
2945
5437a02a 2946 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a 2947 uzip{1,2}.
0be2fe67 2948 * aarch64-dis-2.c: Re-generate.
8c45011a 2949
f4950f76
JB		 29502020-01-03 Jan Beulich <jbeulich@suse.com>
2951
5437a02a 2952 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76 2953 FMMLA encoding.
0be2fe67 2954 * aarch64-dis-2.c: Re-generate.
f4950f76 2955
6655dba2
SB		 29562020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2957
2958 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2959
b14ce8bf
AM		 29602020-01-01 Alan Modra <amodra@gmail.com>
2961
2962 Update year range in copyright notice of all files.
2963
0b114740 2964For older changes see ChangeLog-2019
3499769a 2965\f
0b114740 2966Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2967
2968Copying and distribution of this file, with or without modification,
2969are permitted in any medium without royalty provided the copyright
2970notice and this notice are preserved.
2971
2972Local Variables:
2973mode: change-log
2974left-margin: 8
2975fill-column: 74
2976version-control: never
2977End:
GDB Binutils - Deliverables
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