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[AArch64] Add ARMv8.2 instruction alias REV64.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
64357d2e
MW		 12015-11-27 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
7 "rev64".
8
d685192a
MW		 92015-11-27 Matthew Wahab <matthew.wahab@arm.com>
10
11 * aarch64-asm-2.c: Regenerate.
12 * aarch64-asm.c (convert_bfc_to_bfm): New.
13 (convert_to_real): Add case for OP_BFC.
14 * aarch64-dis-2.c: Regenerate.
15 * aarch64-dis.c: (convert_bfm_to_bfc): New.
16 (convert_to_alias): Add case for OP_BFC.
17 * aarch64-opc-2.c: Regenerate.
18 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
19 to allow width operand in three-operand instructions.
20 * aarch64-tbl.h (QL_BF1): New.
21 (aarch64_feature_v8_2): New.
22 (ARMV8_2): New.
23 (aarch64_opcode_table): Add "bfc".
24
35822b38
MW		 252015-11-27 Matthew Wahab <matthew.wahab@arm.com>
26
27 * aarch64-asm-2.c: Regenerate.
28 * aarch64-dis-2.c: Regenerate.
29 * aarch64-dis.c: Weaken assert.
30 * aarch64-gen.c: Include the instruction in the list of its
31 possible aliases.
32
1a04d1a7
MW		 332015-11-27 Matthew Wahab <matthew.wahab@arm.com>
34
35 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
36 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
37 feature test.
38
e49d43ff
TG		 392015-11-23 Tristan Gingold <gingold@adacore.com>
40
41 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
42
250aafa4
MW		 432015-11-20 Matthew Wahab <matthew.wahab@arm.com>
44
45 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
46 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
47 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
48 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
49 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
50 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
51 cnthv_ctl_el2, cnthv_cval_el2.
52 (aarch64_sys_reg_supported_p): Update for the new system
53 registers.
54
a915c10f
NC		 552015-11-20 Nick Clifton <nickc@redhat.com>
56
57 PR binutils/19224
58 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
59
f8c2a965
NC		 602015-11-20 Nick Clifton <nickc@redhat.com>
61
62 * po/zh_CN.po: Updated simplified Chinese translation.
63
c2825638
MW		 642015-11-19 Matthew Wahab <matthew.wahab@arm.com>
65
66 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
67 of MSR PAN immediate operand.
68
e7286c56
NC		 692015-11-16 Nick Clifton <nickc@redhat.com>
70
71 * rx-dis.c (condition_names): Replace always and never with
72 invalid, since the always/never conditions can never be legal.
73
d8bd95ef
TG		 742015-11-13 Tristan Gingold <gingold@adacore.com>
75
76 * configure: Regenerate.
77
a680de9a
PB		 782015-11-11 Alan Modra <amodra@gmail.com>
79 Peter Bergner <bergner@vnet.ibm.com>
80
81 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
82 Add PPC_OPCODE_VSX3 to the vsx entry.
83 (powerpc_init_dialect): Set default dialect to power9.
84 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
85 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
86 extract_l1 insert_xtq6, extract_xtq6): New static functions.
87 (insert_esync): Test for illegal L operand value.
88 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
89 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
90 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
91 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
92 PPCVSX3): New defines.
93 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
94 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
95 <mcrxr>: Use XBFRARB_MASK.
96 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
97 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
98 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
99 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
100 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
101 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
102 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
103 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
104 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
105 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
106 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
107 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
108 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
109 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
110 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
111 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
112 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
113 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
114 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
115 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
116 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
117 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
118 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
119 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
120 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
121 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
122 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
123 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
124 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
125 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
126 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
127 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
128
854eb72b
NC		 1292015-11-02 Nick Clifton <nickc@redhat.com>
130
131 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
132 instructions.
133 * rx-decode.c: Regenerate.
134
e292aa7a
NC		 1352015-11-02 Nick Clifton <nickc@redhat.com>
136
137 * rx-decode.opc (rx_disp): If the displacement is zero, set the
138 type to RX_Operand_Zero_Indirect.
139 * rx-decode.c: Regenerate.
140 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
141
43cdf5ae
YQ		 1422015-10-28 Yao Qi <yao.qi@linaro.org>
143
144 * aarch64-dis.c (aarch64_decode_insn): Add one argument
145 noaliases_p. Update comments. Pass noaliases_p rather than
146 no_aliases to aarch64_opcode_decode.
147 (print_insn_aarch64_word): Pass no_aliases to
148 aarch64_decode_insn.
149
c2f28758
VK		 1502015-10-27 Vinay <Vinay.G@kpit.com>
151
152 PR binutils/19159
153 * rl78-decode.opc (MOV): Added offset to DE register in index
154 addressing mode.
155 * rl78-decode.c: Regenerate.
156
46662804
VK		 1572015-10-27 Vinay Kumar <vinay.g@kpit.com>
158
159 PR binutils/19158
160 * rl78-decode.opc: Add 's' print operator to instructions that
161 access system registers.
162 * rl78-decode.c: Regenerate.
163 * rl78-dis.c (print_insn_rl78_common): Decode all system
164 registers.
165
02f12cd4
VK		 1662015-10-27 Vinay Kumar <vinay.g@kpit.com>
167
168 PR binutils/19157
169 * rl78-decode.opc: Add 'a' print operator to mov instructions
170 using stack pointer plus index addressing.
171 * rl78-decode.c: Regenerate.
172
485f23cf
AK		 1732015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
174
175 * s390-opc.c: Fix comment.
176 * s390-opc.txt: Change instruction type for troo, trot, trto, and
177 trtt to RRF_U0RER since the second parameter does not need to be a
178 register pair.
179
3f94e60d
NC		 1802015-10-08 Nick Clifton <nickc@redhat.com>
181
182 * arc-dis.c (print_insn_arc): Initiallise insn array.
183
875880c6
YQ		 1842015-10-07 Yao Qi <yao.qi@linaro.org>
185
186 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
187 'name' rather than 'template'.
188 * aarch64-opc.c (aarch64_print_operand): Likewise.
189
886a2506
NC		 1902015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
191
192 * arc-dis.c: Revamped file for ARC support
193 * arc-dis.h: Likewise.
194 * arc-ext.c: Likewise.
195 * arc-ext.h: Likewise.
196 * arc-opc.c: Likewise.
197 * arc-fxi.h: New file.
198 * arc-regs.h: Likewise.
199 * arc-tbl.h: Likewise.
200
36f4aab1
YQ		 2012015-10-02 Yao Qi <yao.qi@linaro.org>
202
203 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
204 argument insn type to aarch64_insn. Rename to ...
205 (aarch64_decode_insn): ... it.
206 (print_insn_aarch64_word): Caller updated.
207
7232d389
YQ		 2082015-10-02 Yao Qi <yao.qi@linaro.org>
209
210 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
211 (print_insn_aarch64_word): Caller updated.
212
7ecc513a
DV		 2132015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
214
215 * s390-mkopc.c (main): Parse htm and vx flag.
216 * s390-opc.txt: Mark instructions from the hardware transactional
217 memory and vector facilities with the "htm"/"vx" flag.
218
b08b78e7
NC		 2192015-09-28 Nick Clifton <nickc@redhat.com>
220
221 * po/de.po: Updated German translation.
222
36f7a941
TR		 2232015-09-28 Tom Rix <tom@bumblecow.com>
224
225 * ppc-opc.c (PPC500): Mark some opcodes as invalid
226
b6518b38
NC		 2272015-09-23 Nick Clifton <nickc@redhat.com>
228
229 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
230 function.
231 * tic30-dis.c (print_branch): Likewise.
232 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
233 value before left shifting.
234 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
235 * hppa-dis.c (print_insn_hppa): Likewise.
236 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
237 array.
238 * msp430-dis.c (msp430_singleoperand): Likewise.
239 (msp430_doubleoperand): Likewise.
240 (print_insn_msp430): Likewise.
241 * nds32-asm.c (parse_operand): Likewise.
242 * sh-opc.h (MASK): Likewise.
243 * v850-dis.c (get_operand_value): Likewise.
244
f04265ec
NC		 2452015-09-22 Nick Clifton <nickc@redhat.com>
246
247 * rx-decode.opc (bwl): Use RX_Bad_Size.
248 (sbwl): Likewise.
249 (ubwl): Likewise. Rename to ubw.
250 (uBWL): Rename to uBW.
251 Replace all references to uBWL with uBW.
252 * rx-decode.c: Regenerate.
253 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
254 (opsize_names): Likewise.
255 (print_insn_rx): Detect and report RX_Bad_Size.
256
6dca4fd1
AB		 2572015-09-22 Anton Blanchard <anton@samba.org>
258
259 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
260
38074311
JM		 2612015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
262
263 * sparc-dis.c (print_insn_sparc): Handle the privileged register
264 %pmcdper.
265
5f40e14d
JS		 2662015-08-24 Jan Stancek <jstancek@redhat.com>
267
268 * i386-dis.c (print_insn): Fix decoding of three byte operands.
269
ab4e4ed5
AF		 2702015-08-21 Alexander Fomin <alexander.fomin@intel.com>
271
272 PR binutils/18257
273 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
274 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
275 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
276 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
277 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
278 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
279 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
280 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
281 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
282 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
283 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
284 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
285 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
286 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
287 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
288 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
289 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
290 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
291 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
292 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
293 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
294 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
295 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
296 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
297 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
298 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
299 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
300 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
301 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
302 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
303 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
304 (vex_w_table): Replace terminals with MOD_TABLE entries for
305 most of mask instructions.
306
919b75f7
AM		 3072015-08-17 Alan Modra <amodra@gmail.com>
308
309 * cgen.sh: Trim trailing space from cgen output.
310 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
311 (print_dis_table): Likewise.
312 * opc2c.c (dump_lines): Likewise.
313 (orig_filename): Warning fix.
314 * ia64-asmtab.c: Regenerate.
315
4ab90a7a
AV		 3162015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
317
318 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
319 and higher with ARM instruction set will now mark the 26-bit
320 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
321 (arm_opcodes): Fix for unpredictable nop being recognized as a
322 teq.
323
40fc1451
SD		 3242015-08-12 Simon Dardis <simon.dardis@imgtec.com>
325
326 * micromips-opc.c (micromips_opcodes): Re-order table so that move
327 based on 'or' is first.
328 * mips-opc.c (mips_builtin_opcodes): Ditto.
329
922c5db5
NC		 3302015-08-11 Nick Clifton <nickc@redhat.com>
331
332 PR 18800
333 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
334 instruction.
335
75fb7498
RS		 3362015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
337
338 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
339
36aed29d
AP		 3402015-08-07 Amit Pawar <Amit.Pawar@amd.com>
341
342 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
343 * i386-init.h: Regenerated.
344
a8484f96
L		 3452015-07-30 H.J. Lu <hongjiu.lu@intel.com>
346
347 PR binutils/13571
348 * i386-dis.c (MOD_0FC3): New.
349 (PREFIX_0FC3): Renamed to ...
350 (PREFIX_MOD_0_0FC3): This.
351 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
352 (prefix_table): Replace Ma with Ev on movntiS.
353 (mod_table): Add MOD_0FC3.
354
37a42ee9
L		 3552015-07-27 H.J. Lu <hongjiu.lu@intel.com>
356
357 * configure: Regenerated.
358
070fe95d
AM		 3592015-07-23 Alan Modra <amodra@gmail.com>
360
361 PR 18708
362 * i386-dis.c (get64): Avoid signed integer overflow.
363
20c2a615
L		 3642015-07-22 Alexander Fomin <alexander.fomin@intel.com>
365
366 PR binutils/18631
367 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
368 "EXEvexHalfBcstXmmq" for the second operand.
369 (EVEX_W_0F79_P_2): Likewise.
370 (EVEX_W_0F7A_P_2): Likewise.
371 (EVEX_W_0F7B_P_2): Likewise.
372
6f1c2142
AM		 3732015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
374
375 * arm-dis.c (print_insn_coprocessor): Added support for quarter
376 float bitfield format.
377 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
378 quarter float bitfield format.
379
8a643cc3
L		 3802015-07-14 H.J. Lu <hongjiu.lu@intel.com>
381
382 * configure: Regenerated.
383
ef5a96d5
AM		 3842015-07-03 Alan Modra <amodra@gmail.com>
385
386 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
387 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
388 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
389
c8c8175b
SL		 3902015-07-01 Sandra Loosemore <sandra@codesourcery.com>
391 Cesar Philippidis <cesar@codesourcery.com>
392
393 * nios2-dis.c (nios2_extract_opcode): New.
394 (nios2_disassembler_state): New.
395 (nios2_find_opcode_hash): Use mach parameter to select correct
396 disassembler state.
397 (nios2_print_insn_arg): Extend to support new R2 argument letters
398 and formats.
399 (print_insn_nios2): Check for 16-bit instruction at end of memory.
400 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
401 (NIOS2_NUM_OPCODES): Rename to...
402 (NIOS2_NUM_R1_OPCODES): This.
403 (nios2_r2_opcodes): New.
404 (NIOS2_NUM_R2_OPCODES): New.
405 (nios2_num_r2_opcodes): New.
406 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
407 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
408 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
409 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
410 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
411
9916071f
AP		 4122015-06-30 Amit Pawar <Amit.Pawar@amd.com>
413
414 * i386-dis.c (OP_Mwaitx): New.
415 (rm_table): Add monitorx/mwaitx.
416 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
417 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
418 (operand_type_init): Add CpuMWAITX.
419 * i386-opc.h (CpuMWAITX): New.
420 (i386_cpu_flags): Add cpumwaitx.
421 * i386-opc.tbl: Add monitorx and mwaitx.
422 * i386-init.h: Regenerated.
423 * i386-tbl.h: Likewise.
424
7b934113
PB		 4252015-06-22 Peter Bergner <bergner@vnet.ibm.com>
426
427 * ppc-opc.c (insert_ls): Test for invalid LS operands.
428 (insert_esync): New function.
429 (LS, WC): Use insert_ls.
430 (ESYNC): Use insert_esync.
431
bdc4de1b
NC		 4322015-06-22 Nick Clifton <nickc@redhat.com>
433
434 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
435 requested region lies beyond it.
436 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
437 looking for 32-bit insns.
438 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
439 data.
440 * sh-dis.c (print_insn_sh): Likewise.
441 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
442 blocks of instructions.
443 * vax-dis.c (print_insn_vax): Check that the requested address
444 does not clash with the stop_vma.
445
11a0cf2e
PB		 4462015-06-19 Peter Bergner <bergner@vnet.ibm.com>
447
070fe95d 448 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 449 * ppc-opc.c (FXM4): Add non-zero optional value.
450 (TBR): Likewise.
451 (SXL): Likewise.
452 (insert_fxm): Handle new default operand value.
453 (extract_fxm): Likewise.
454 (insert_tbr): Likewise.
455 (extract_tbr): Likewise.
456
bdfa8b95
MW		 4572015-06-16 Matthew Wahab <matthew.wahab@arm.com>
458
459 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
460
24b4cf66
SN		 4612015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
462
463 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
464
99a2c561
PB		 4652015-06-12 Peter Bergner <bergner@vnet.ibm.com>
466
467 * ppc-opc.c: Add comment accidentally removed by old commit.
468 (MTMSRD_L): Delete.
469
40f77f82
AM		 4702015-06-04 Peter Bergner <bergner@vnet.ibm.com>
471
472 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
473
13be46a2
NC		 4742015-06-04 Nick Clifton <nickc@redhat.com>
475
476 PR 18474
477 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
478
ddfded2f
MW		 4792015-06-02 Matthew Wahab <matthew.wahab@arm.com>
480
481 * arm-dis.c (arm_opcodes): Add "setpan".
482 (thumb_opcodes): Add "setpan".
483
1af1dd51
MW		 4842015-06-02 Matthew Wahab <matthew.wahab@arm.com>
485
486 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
487 macros.
488
9e1f0fa7
MW		 4892015-06-02 Matthew Wahab <matthew.wahab@arm.com>
490
491 * aarch64-tbl.h (aarch64_feature_rdma): New.
492 (RDMA): New.
493 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
494 * aarch64-asm-2.c: Regenerate.
495 * aarch64-dis-2.c: Regenerate.
496 * aarch64-opc-2.c: Regenerate.
497
290806fd
MW		 4982015-06-02 Matthew Wahab <matthew.wahab@arm.com>
499
500 * aarch64-tbl.h (aarch64_feature_lor): New.
501 (LOR): New.
502 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
503 "stllrb", "stllrh".
504 * aarch64-asm-2.c: Regenerate.
505 * aarch64-dis-2.c: Regenerate.
506 * aarch64-opc-2.c: Regenerate.
507
f21cce2c
MW		 5082015-06-01 Matthew Wahab <matthew.wahab@arm.com>
509
510 * aarch64-opc.c (F_ARCHEXT): New.
511 (aarch64_sys_regs): Add "pan".
512 (aarch64_sys_reg_supported_p): New.
513 (aarch64_pstatefields): Add "pan".
514 (aarch64_pstatefield_supported_p): New.
515
d194d186
JB		 5162015-06-01 Jan Beulich <jbeulich@suse.com>
517
518 * i386-tbl.h: Regenerate.
519
3a8547d2
JB		 5202015-06-01 Jan Beulich <jbeulich@suse.com>
521
522 * i386-dis.c (print_insn): Swap rounding mode specifier and
523 general purpose register in Intel mode.
524
015c54d5
JB		 5252015-06-01 Jan Beulich <jbeulich@suse.com>
526
527 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
528 * i386-tbl.h: Regenerate.
529
071f0063
L		 5302015-05-18 H.J. Lu <hongjiu.lu@intel.com>
531
532 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
533 * i386-init.h: Regenerated.
534
5db04b09
L		 5352015-05-15 H.J. Lu <hongjiu.lu@intel.com>
536
537 PR binutis/18386
538 * i386-dis.c: Add comments for '@'.
539 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
540 (enum x86_64_isa): New.
541 (isa64): Likewise.
542 (print_i386_disassembler_options): Add amd64 and intel64.
543 (print_insn): Handle amd64 and intel64.
544 (putop): Handle '@'.
545 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
546 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
547 * i386-opc.h (AMD64): New.
548 (CpuIntel64): Likewise.
549 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
550 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
551 Mark direct call/jmp without Disp16|Disp32 as Intel64.
552 * i386-init.h: Regenerated.
553 * i386-tbl.h: Likewise.
554
4bc0608a
PB		 5552015-05-14 Peter Bergner <bergner@vnet.ibm.com>
556
557 * ppc-opc.c (IH) New define.
558 (powerpc_opcodes) <wait>: Do not enable for POWER7.
559 <tlbie>: Add RS operand for POWER7.
560 <slbia>: Add IH operand for POWER6.
561
70cead07
L		 5622015-05-11 H.J. Lu <hongjiu.lu@intel.com>
563
564 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
565 direct branch.
566 (jmp): Likewise.
567 * i386-tbl.h: Regenerated.
568
7b6d09fb
L		 5692015-05-11 H.J. Lu <hongjiu.lu@intel.com>
570
571 * configure.ac: Support bfd_iamcu_arch.
572 * disassemble.c (disassembler): Support bfd_iamcu_arch.
573 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
574 CPU_IAMCU_COMPAT_FLAGS.
575 (cpu_flags): Add CpuIAMCU.
576 * i386-opc.h (CpuIAMCU): New.
577 (i386_cpu_flags): Add cpuiamcu.
578 * configure: Regenerated.
579 * i386-init.h: Likewise.
580 * i386-tbl.h: Likewise.
581
31955f99
L		 5822015-05-08 H.J. Lu <hongjiu.lu@intel.com>
583
584 PR binutis/18386
585 * i386-dis.c (X86_64_E8): New.
586 (X86_64_E9): Likewise.
587 Update comments on 'T', 'U', 'V'. Add comments for '^'.
588 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
589 (x86_64_table): Add X86_64_E8 and X86_64_E9.
590 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
591 (putop): Handle '^'.
592 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
593 REX_W.
594
0952813b
DD		 5952015-04-30 DJ Delorie <dj@redhat.com>
596
597 * disassemble.c (disassembler): Choose suitable disassembler based
598 on E_ABI.
599 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
600 it to decode mul/div insns.
601 * rl78-decode.c: Regenerate.
602 * rl78-dis.c (print_insn_rl78): Rename to...
603 (print_insn_rl78_common): ...this, take ISA parameter.
604 (print_insn_rl78): New.
605 (print_insn_rl78_g10): New.
606 (print_insn_rl78_g13): New.
607 (print_insn_rl78_g14): New.
608 (rl78_get_disassembler): New.
609
f9d3ecaa
NC		 6102015-04-29 Nick Clifton <nickc@redhat.com>
611
612 * po/fr.po: Updated French translation.
613
4fff86c5
PB		 6142015-04-27 Peter Bergner <bergner@vnet.ibm.com>
615
616 * ppc-opc.c (DCBT_EO): New define.
617 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
618 <lharx>: Likewise.
619 <stbcx.>: Likewise.
620 <sthcx.>: Likewise.
621 <waitrsv>: Do not enable for POWER7 and later.
622 <waitimpl>: Likewise.
623 <dcbt>: Default to the two operand form of the instruction for all
624 "old" cpus. For "new" cpus, use the operand ordering that matches
625 whether the cpu is server or embedded.
626 <dcbtst>: Likewise.
627
3b78cfe1
AK		 6282015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
629
630 * s390-opc.c: New instruction type VV0UU2.
631 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
632 and WFC.
633
04d824a4
JB		 6342015-04-23 Jan Beulich <jbeulich@suse.com>
635
636 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
637 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
638 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
639 (vfpclasspd, vfpclassps): Add %XZ.
640
09708981
L		 6412015-04-15 H.J. Lu <hongjiu.lu@intel.com>
642
643 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
644 (PREFIX_UD_REPZ): Likewise.
645 (PREFIX_UD_REPNZ): Likewise.
646 (PREFIX_UD_DATA): Likewise.
647 (PREFIX_UD_ADDR): Likewise.
648 (PREFIX_UD_LOCK): Likewise.
649
3888916d
L		 6502015-04-15 H.J. Lu <hongjiu.lu@intel.com>
651
652 * i386-dis.c (prefix_requirement): Removed.
653 (print_insn): Don't set prefix_requirement. Check
654 dp->prefix_requirement instead of prefix_requirement.
655
f24bcbaa
L		 6562015-04-15 H.J. Lu <hongjiu.lu@intel.com>
657
658 PR binutils/17898
659 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
660 (PREFIX_MOD_0_0FC7_REG_6): This.
661 (PREFIX_MOD_3_0FC7_REG_6): New.
662 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
663 (prefix_table): Replace PREFIX_0FC7_REG_6 with
664 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
665 PREFIX_MOD_3_0FC7_REG_7.
666 (mod_table): Replace PREFIX_0FC7_REG_6 with
667 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
668 PREFIX_MOD_3_0FC7_REG_7.
669
507bd325
L		 6702015-04-15 H.J. Lu <hongjiu.lu@intel.com>
671
672 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
673 (PREFIX_MANDATORY_REPNZ): Likewise.
674 (PREFIX_MANDATORY_DATA): Likewise.
675 (PREFIX_MANDATORY_ADDR): Likewise.
676 (PREFIX_MANDATORY_LOCK): Likewise.
677 (PREFIX_MANDATORY): Likewise.
678 (PREFIX_UD_SHIFT): Set to 8
679 (PREFIX_UD_REPZ): Updated.
680 (PREFIX_UD_REPNZ): Likewise.
681 (PREFIX_UD_DATA): Likewise.
682 (PREFIX_UD_ADDR): Likewise.
683 (PREFIX_UD_LOCK): Likewise.
684 (PREFIX_IGNORED_SHIFT): New.
685 (PREFIX_IGNORED_REPZ): Likewise.
686 (PREFIX_IGNORED_REPNZ): Likewise.
687 (PREFIX_IGNORED_DATA): Likewise.
688 (PREFIX_IGNORED_ADDR): Likewise.
689 (PREFIX_IGNORED_LOCK): Likewise.
690 (PREFIX_OPCODE): Likewise.
691 (PREFIX_IGNORED): Likewise.
692 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
693 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
694 (three_byte_table): Likewise.
695 (mod_table): Likewise.
696 (mandatory_prefix): Renamed to ...
697 (prefix_requirement): This.
698 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
699 Update PREFIX_90 entry.
700 (get_valid_dis386): Check prefix_requirement to see if a prefix
701 should be ignored.
702 (print_insn): Replace mandatory_prefix with prefix_requirement.
703
f0fba320
RL		 7042015-04-15 Renlin Li <renlin.li@arm.com>
705
706 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
707 use it for ssat and ssat16.
708 (print_insn_thumb32): Add handle case for 'D' control code.
709
bf890a93
IT		 7102015-04-06 Ilya Tocar <ilya.tocar@intel.com>
711 H.J. Lu <hongjiu.lu@intel.com>
712
713 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
714 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
715 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
716 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
717 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
718 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
719 Fill prefix_requirement field.
720 (struct dis386): Add prefix_requirement field.
721 (dis386): Fill prefix_requirement field.
722 (dis386_twobyte): Ditto.
723 (twobyte_has_mandatory_prefix_: Remove.
724 (reg_table): Fill prefix_requirement field.
725 (prefix_table): Ditto.
726 (x86_64_table): Ditto.
727 (three_byte_table): Ditto.
728 (xop_table): Ditto.
729 (vex_table): Ditto.
730 (vex_len_table): Ditto.
731 (vex_w_table): Ditto.
732 (mod_table): Ditto.
733 (bad_opcode): Ditto.
734 (print_insn): Use prefix_requirement.
735 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
736 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
737 (float_reg): Ditto.
738
2f783c1f
MF		 7392015-03-30 Mike Frysinger <vapier@gentoo.org>
740
741 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
742
b9d94d62
L		 7432015-03-29 H.J. Lu <hongjiu.lu@intel.com>
744
745 * Makefile.in: Regenerated.
746
27c49e9a
AB		 7472015-03-25 Anton Blanchard <anton@samba.org>
748
749 * ppc-dis.c (disassemble_init_powerpc): Only initialise
750 powerpc_opcd_indices and vle_opcd_indices once.
751
c4e676f1
AB		 7522015-03-25 Anton Blanchard <anton@samba.org>
753
754 * ppc-opc.c (powerpc_opcodes): Add slbfee.
755
823d2571
TG		 7562015-03-24 Terry Guo <terry.guo@arm.com>
757
758 * arm-dis.c (opcode32): Updated to use new arm feature struct.
759 (opcode16): Likewise.
760 (coprocessor_opcodes): Replace bit with feature struct.
761 (neon_opcodes): Likewise.
762 (arm_opcodes): Likewise.
763 (thumb_opcodes): Likewise.
764 (thumb32_opcodes): Likewise.
765 (print_insn_coprocessor): Likewise.
766 (print_insn_arm): Likewise.
767 (select_arm_features): Follow new feature struct.
768
029f3522
GG		 7692015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
770
771 * i386-dis.c (rm_table): Add clzero.
772 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
773 Add CPU_CLZERO_FLAGS.
774 (cpu_flags): Add CpuCLZERO.
775 * i386-opc.h: Add CpuCLZERO.
776 * i386-opc.tbl: Add clzero.
777 * i386-init.h: Re-generated.
778 * i386-tbl.h: Re-generated.
779
6914869a
AB		 7802015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
781
782 * mips-opc.c (decode_mips_operand): Fix constraint issues
783 with u and y operands.
784
21e20815
AB		 7852015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
786
787 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
788
6b1d7593
AK		 7892015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
790
791 * s390-opc.c: Add new IBM z13 instructions.
792 * s390-opc.txt: Likewise.
793
c8f89a34
JW		 7942015-03-10 Renlin Li <renlin.li@arm.com>
795
796 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
797 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
798 related alias.
799 * aarch64-asm-2.c: Regenerate.
800 * aarch64-dis-2.c: Likewise.
801 * aarch64-opc-2.c: Likewise.
802
d8282f0e
JW		 8032015-03-03 Jiong Wang <jiong.wang@arm.com>
804
805 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
806
ac994365
OE		 8072015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
808
809 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
810 arch_sh_up.
811 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
812 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
813
fd63f640
V		 8142015-02-23 Vinay <Vinay.G@kpit.com>
815
816 * rl78-decode.opc (MOV): Added space between two operands for
817 'mov' instruction in index addressing mode.
818 * rl78-decode.c: Regenerate.
819
f63c1776
PA		 8202015-02-19 Pedro Alves <palves@redhat.com>
821
822 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
823
07774fcc
PA		 8242015-02-10 Pedro Alves <palves@redhat.com>
825 Tom Tromey <tromey@redhat.com>
826
827 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
828 microblaze_and, microblaze_xor.
829 * microblaze-opc.h (opcodes): Adjust.
830
3f8107ab
AM		 8312015-01-28 James Bowman <james.bowman@ftdichip.com>
832
833 * Makefile.am: Add FT32 files.
834 * configure.ac: Handle FT32.
835 * disassemble.c (disassembler): Call print_insn_ft32.
836 * ft32-dis.c: New file.
837 * ft32-opc.c: New file.
838 * Makefile.in: Regenerate.
839 * configure: Regenerate.
840 * po/POTFILES.in: Regenerate.
841
e5fe4957
KLC		 8422015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
843
844 * nds32-asm.c (keyword_sr): Add new system registers.
845
1e2e8c52
AK		 8462015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
847
848 * s390-dis.c (s390_extract_operand): Support vector register
849 operands.
850 (s390_print_insn_with_opcode): Support new operands types and add
851 new handling of optional operands.
852 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
853 and include opcode/s390.h instead.
854 (struct op_struct): New field `flags'.
855 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
856 (dumpTable): Dump flags.
857 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
858 string.
859 * s390-opc.c: Add new operands types, instruction formats, and
860 instruction masks.
861 (s390_opformats): Add new formats for .insn.
862 * s390-opc.txt: Add new instructions.
863
b90efa5b 8642015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 865
b90efa5b 866 Update year range in copyright notice of all files.
bffb6004 867
b90efa5b 868For older changes see ChangeLog-2014
252b5132 869\f
b90efa5b 870Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 871
872Copying and distribution of this file, with or without modification,
873are permitted in any medium without royalty provided the copyright
874notice and this notice are preserved.
875
252b5132 876Local Variables:
2f6d2f85
NC		 877mode: change-log
878left-margin: 8
879fill-column: 74
252b5132
RH		 880version-control: never
881End:
GDB Binutils - Deliverables
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