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MIPS16/GAS: Disallow EXTEND delay-slot scheduling
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
645c4556
MR		 12016-12-23 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
4 "extend".
5
9e76c212
MR		 62016-12-23 Maciej W. Rozycki <macro@imgtec.com>
7
8 * mips-dis.c (set_default_mips_dis_options): Use
9 HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
10 call to `bfd_mips_elf_get_abiflags'.
11 * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
12 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
13 * aclocal.m4: Regenerate.
14 * configure: Regenerate.
15 * config.in: Regenerate.
16 * Makefile.in: Regenerate.
17
99b5dbf2
TG		 182016-12-23 Tristan Gingold <gingold@adacore.com>
19
20 * configure: Regenerate.
21
e0e7a9d4
TG		 222016-12-23 Tristan Gingold <gingold@adacore.com>
23
24 * po/opcodes.pot: Regenerate.
25
b2c6190b 262016-12-21 Andrew Waterman <andrew@sifive.com>
58a6d3c9
AW		 27
28 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
29
11dd08e9
MR		 302016-12-20 Maciej W. Rozycki <macro@imgtec.com>
31
32 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
33 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
34 (print_insn_mips16): Check opcode entries for validity against
35 the ISA level and ASE set selected.
36
7fd53920
MR		 372016-12-20 Maciej W. Rozycki <macro@imgtec.com>
38
39 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
40 `insn' together, with `extend' as the high-order 16 bits.
41 (match_kind): New enum.
42 (print_insn_mips16): Rework for 32-bit instruction matching.
43 Do not dump EXTEND prefixes here.
44 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
45 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
46 "jalx" entries.
47
4ebce1a0
MR		 482016-12-20 Maciej W. Rozycki <macro@imgtec.com>
49
50 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
51 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
52 INSN_MACRO entries.
53
c97dda72
MR		 542016-12-20 Maciej W. Rozycki <macro@imgtec.com>
55
56 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
57 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
58 opcode).
59
3e67a378
AW		 602016-12-20 Andrew Waterman <andrew@sifive.com>
61
62 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
63 "*.aqrl".
64
04386d9e
AW		 652016-12-20 Andrew Waterman <andrew@sifive.com>
66
67 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
68 INSN_ALIAS.
69
755c5297
AW		 702016-12-20 Andrew Waterman <andrew@sifive.com>
71
72 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
73 format.
74
2922d21d
AW		 752016-12-20 Andrew Waterman <andrew@sifive.com>
76
77 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
78 XLEN when none is provided.
79
1d65abb5
AW		 802016-12-20 Andrew Waterman <andrew@sifive.com>
81
82 * riscv-opc.c: Formatting fixes.
83
dd1d944e
AM		 842016-12-20 Alan Modra <amodra@gmail.com>
85
86 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
87 * Makefile.in: Regenerate.
88 * po/POTFILES.in: Regenerate.
89
91068ec6
MR		 902016-12-19 Maciej W. Rozycki <macro@imgtec.com>
91
92 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
93 Only examine ELF file structures here.
94
4df995c7
MR		 952016-12-19 Maciej W. Rozycki <macro@imgtec.com>
96
97 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
98 `bfd_mips_elf_get_abiflags' here.
99
db7b55fa
NC		 1002016-12-16 Nick Clifton <nickc@redhat.com>
101
102 * arm-dis.c (print_insn_thumb32): Fix compile time warning
103 computing value_in_comment.
104
5e7fc731
MR		 1052016-12-14 Maciej W. Rozycki <macro@imgtec.com>
106
107 * mips-dis.c (mips_convert_abiflags_ases): New function.
108 (set_default_mips_dis_options): Also infer ASE flags from ELF
109 file structures.
110
8184783a
MR		 1112016-12-14 Maciej W. Rozycki <macro@imgtec.com>
112
113 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
114 header flag interpretation code.
115
353abf7c
MR		 1162016-12-14 Maciej W. Rozycki <macro@imgtec.com>
117
118 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
119 `pinfo2' with SP-relative "sd" entries.
120
63e014fc
MR		 1212016-12-14 Maciej W. Rozycki <macro@imgtec.com>
122
123 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
124 compact jumps.
125
a6a51754
RL		 1262016-12-13 Renlin Li <renlin.li@arm.com>
127
128 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
129 qualifier.
130 (operand_general_constraint_met_p): Remove case for CP_REG.
131 (aarch64_print_operand): Print CRn, CRm operand using imm field.
132 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
133 (QL_SYSL): Likewise.
134 (aarch64_opcode_table): Change CRn, CRm operand class and type.
135 * aarch64-opc-2.c : Regenerate.
136 * aarch64-asm-2.c : Likewise.
137 * aarch64-dis-2.c : Likewise.
138
029e9d52
YQ		 1392016-12-12 Yao Qi <yao.qi@linaro.org>
140
141 * rx-dis.c: Include <setjmp.h>
142 (struct private): New.
143 (rx_get_byte): Check return value of read_memory_func, and
144 call memory_error_func and OPCODES_SIGLONGJMP on error.
145 (print_insn_rx): Call OPCODES_SIGSETJMP.
146
3a0b8f7d
YQ		 1472016-12-12 Yao Qi <yao.qi@linaro.org>
148
149 * rl78-dis.c: Include <setjmp.h>.
150 (struct private): New.
151 (rl78_get_byte): Check return value of read_memory_func, and
152 call memory_error_func and OPCODES_SIGLONGJMP on error.
153 (print_insn_rl78_common): Call OPCODES_SIGJMP.
154
64c11183
MR		 1552016-12-09 Maciej W. Rozycki <macro@imgtec.com>
156
157 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
158
f17ecb4b
MR		 1592016-12-09 Maciej W. Rozycki <macro@imgtec.com>
160
161 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
162 than UINT.
163
55af4784
MR		 1642016-12-09 Maciej W. Rozycki <macro@imgtec.com>
165
166 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
167 to separate `extend' and its uninterpreted argument output.
168 Separate hexadecimal halves of undecoded extended instructions
169 output.
170
39f66f3a
MR		 1712016-12-08 Maciej W. Rozycki <macro@imgtec.com>
172
173 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
174 indentation space across.
175
860b03a8
MR		 1762016-12-08 Maciej W. Rozycki <macro@imgtec.com>
177
178 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
179 adjustment for PC-relative operations following MIPS16e compact
180 jumps or undefined RR/J(AL)R(C) encodings.
181
329d01f7
MR		 1822016-12-08 Maciej W. Rozycki <macro@imgtec.com>
183
184 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
185 variable to `reglane_index'.
186
3a2488dd
LM		 1872016-12-08 Luis Machado <lgustavo@codesourcery.com>
188
189 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
190
5f5c6e03
MR		 1912016-12-07 Maciej W. Rozycki <macro@imgtec.com>
192
193 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
194
343fa690
MR		 1952016-12-07 Maciej W. Rozycki <macro@imgtec.com>
196
197 * mips16-opc.c (mips16_opcodes): Update comment naming structure
198 members.
199
6725647c
MR		 2002016-12-07 Maciej W. Rozycki <macro@imgtec.com>
201
202 * mips-dis.c (print_mips_disassembler_options): Reformat output.
203
c28eeff2
SN		 2042016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
205
206 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
207 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
208
49e8a725
SN		 2092016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
210
211 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
212
a37a2806
NC		 2132016-12-01 Nick Clifton <nickc@redhat.com>
214
215 PR binutils/20893
216 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
217 opcode designator.
218
abe7c33b
CZ		 2192016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
220
221 * arc-opc.c (insert_ra_chk): New function.
222 (insert_rb_chk): Likewise.
223 (insert_rad): Update text error message.
224 (insert_rcd): Likewise.
225 (insert_rhv2): Likewise.
226 (insert_r0): Likewise.
227 (insert_r1): Likewise.
228 (insert_r2): Likewise.
229 (insert_r3): Likewise.
230 (insert_sp): Likewise.
231 (insert_gp): Likewise.
232 (insert_pcl): Likewise.
233 (insert_blink): Likewise.
234 (insert_ilink1): Likewise.
235 (insert_ilink2): Likewise.
236 (insert_ras): Likewise.
237 (insert_rbs): Likewise.
238 (insert_rcs): Likewise.
239 (insert_simm3s): Likewise.
240 (insert_rrange): Likewise.
241 (insert_fpel): Likewise.
242 (insert_blinkel): Likewise.
243 (insert_pcel): Likewise.
244 (insert_nps_3bit_dst): Likewise.
245 (insert_nps_3bit_dst_short): Likewise.
246 (insert_nps_3bit_src2_short): Likewise.
247 (insert_nps_bitop_size_2b): Likewise.
248 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
249 (RA_CHK): Define.
250 (RB): Adjust.
251 (RB_CHK): Define.
252 (RC): Adjust.
253 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
254 * arc-tbl.h (div, divu): All instructions are DIVREM class.
255 Change first insn argument to check for LP_COUNT usage.
256 (rem): Likewise.
257 (ld, ldd): All instructions are LOAD class. Change first insn
258 argument to check for LP_COUNT usage.
259 (st, std): All instructions are STORE class.
260 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
261 Change first insn argument to check for LP_COUNT usage.
262 (mov): All instructions are MOVE class. Change first insn
263 argument to check for LP_COUNT usage.
264
ee881e5d
CZ		 2652016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
266
267 * arc-dis.c (is_compatible_p): Remove function.
268 (skip_this_opcode): Don't add any decoding class to decode list.
269 Remove warning.
270 (find_format_from_table): Go through all opcodes, and warn if we
271 use a guessed mnemonic.
272
abfcb414
AP		 2732016-11-28 Ramiro Polla <ramiro@hex-rays.com>
274 Amit Pawar <amit.pawar@amd.com>
275
276 PR binutils/20637
277 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
278 instructions.
279
96fe4562
AM		 2802016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
281
282 * configure: Regenerate.
283
6884417a
JM		 2842016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
285
286 * sparc-opc.c (HWS_V8): Definition moved from
287 gas/config/tc-sparc.c.
288 (HWS_V9): Likewise.
289 (HWS_VA): Likewise.
290 (HWS_VB): Likewise.
291 (HWS_VC): Likewise.
292 (HWS_VD): Likewise.
293 (HWS_VE): Likewise.
294 (HWS_VV): Likewise.
295 (HWS_VM): Likewise.
296 (HWS2_VM): Likewise.
297 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
298 existing entries.
299
c4b943d7
CZ		 3002016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
301
302 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
303 instructions.
304
c2c4ff8d
SN		 3052016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
306
307 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
308 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
309 (aarch64_opcode_table): Add fcmla and fcadd.
310 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
311 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
312 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
313 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
314 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
315 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
316 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
317 (operand_general_constraint_met_p): Rotate and index range check.
318 (aarch64_print_operand): Handle rotate operand.
319 * aarch64-asm-2.c: Regenerate.
320 * aarch64-dis-2.c: Likewise.
321 * aarch64-opc-2.c: Likewise.
322
28617675
SN		 3232016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
324
325 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
326 * aarch64-asm-2.c: Regenerate.
327 * aarch64-dis-2.c: Regenerate.
328 * aarch64-opc-2.c: Regenerate.
329
ccfc90a3
SN		 3302016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
331
332 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
333 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
334 * aarch64-asm-2.c: Regenerate.
335 * aarch64-dis-2.c: Regenerate.
336 * aarch64-opc-2.c: Regenerate.
337
3f06e550
SN		 3382016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
339
340 * aarch64-tbl.h (QL_X1NIL): New.
341 (arch64_opcode_table): Add ldraa, ldrab.
342 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
343 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
344 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
345 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
346 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
347 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
348 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
349 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
350 (aarch64_print_operand): Likewise.
351 * aarch64-asm-2.c: Regenerate.
352 * aarch64-dis-2.c: Regenerate.
353 * aarch64-opc-2.c: Regenerate.
354
74f5402d
SN		 3552016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
356
357 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
358 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
359 * aarch64-asm-2.c: Regenerate.
360 * aarch64-dis-2.c: Regenerate.
361 * aarch64-opc-2.c: Regenerate.
362
c84364ec
SN		 3632016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
364
365 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
366 (AARCH64_OPERANDS): Add Rm_SP.
367 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
368 * aarch64-asm-2.c: Regenerate.
369 * aarch64-dis-2.c: Regenerate.
370 * aarch64-opc-2.c: Regenerate.
371
a2cfc830
SN		 3722016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
373
374 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
375 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
376 autdzb, xpaci, xpacd.
377 * aarch64-asm-2.c: Regenerate.
378 * aarch64-dis-2.c: Regenerate.
379 * aarch64-opc-2.c: Regenerate.
380
b0bfa7b5
SN		 3812016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
382
383 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
384 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
385 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
386 (aarch64_sys_reg_supported_p): Add feature test for new registers.
387
8787d804
SN		 3882016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
389
390 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
391 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
392 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
393 autibsp.
394 * aarch64-asm-2.c: Regenerate.
395 * aarch64-dis-2.c: Regenerate.
396
3d731f69
SN		 3972016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
398
399 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
400
60227d64
L		 4012016-11-09 H.J. Lu <hongjiu.lu@intel.com>
402
403 PR binutils/20799
404 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
405 * i386-dis.c (EdqwS): Removed.
406 (dqw_swap_mode): Likewise.
407 (intel_operand_size): Don't check dqw_swap_mode.
408 (OP_E_register): Likewise.
409 (OP_E_memory): Likewise.
410 (OP_G): Likewise.
411 (OP_EX): Likewise.
412 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
413 * i386-tbl.h: Regerated.
414
7efeed17
L		 4152016-11-09 H.J. Lu <hongjiu.lu@intel.com>
416
417 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 418 * i386-tbl.h: Regerated.
7efeed17 419
1f334aeb
L		 4202016-11-08 H.J. Lu <hongjiu.lu@intel.com>
421
422 PR binutils/20701
423 * i386-dis.c (THREE_BYTE_0F7A): Removed.
424 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
425 (three_byte_table): Remove THREE_BYTE_0F7A.
426
48c97fa1
L		 4272016-11-07 H.J. Lu <hongjiu.lu@intel.com>
428
429 PR binutils/20775
430 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
431 (FGRPd9_4): Replace 1 with 2.
432 (FGRPd9_5): Replace 2 with 3.
433 (FGRPd9_6): Replace 3 with 4.
434 (FGRPd9_7): Replace 4 with 5.
435 (FGRPda_5): Replace 5 with 6.
436 (FGRPdb_4): Replace 6 with 7.
437 (FGRPde_3): Replace 7 with 8.
438 (FGRPdf_4): Replace 8 with 9.
439 (fgrps): Add an entry for Bad_Opcode.
440
b437d035
AB		 4412016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
442
443 * arc-opc.c (arc_flag_operands): Add F_DI14.
444 (arc_flag_classes): Add C_DI14.
445 * arc-nps400-tbl.h: Add new exc instructions.
446
5a736821
GM		 4472016-11-03 Graham Markall <graham.markall@embecosm.com>
448
449 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
450 major opcode 0xa.
451 * arc-nps-400-tbl.h: Add dcmac instruction.
452 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
453 (insert_nps_rbdouble_64): Added.
454 (extract_nps_rbdouble_64): Added.
455 (insert_nps_proto_size): Added.
456 (extract_nps_proto_size): Added.
457
bdfe53e3
AB		 4582016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
459
460 * arc-dis.c (struct arc_operand_iterator): Remove all fields
461 relating to long instruction processing, add new limm field.
462 (OPCODE): Rename to...
463 (OPCODE_32BIT_INSN): ...this.
464 (OPCODE_AC): Delete.
465 (skip_this_opcode): Handle different instruction lengths, update
466 macro name.
467 (special_flag_p): Update parameter type.
468 (find_format_from_table): Update for more instruction lengths.
469 (find_format_long_instructions): Delete.
470 (find_format): Update for more instruction lengths.
471 (arc_insn_length): Likewise.
472 (extract_operand_value): Update for more instruction lengths.
473 (operand_iterator_next): Remove code relating to long
474 instructions.
475 (arc_opcode_to_insn_type): New function.
476 (print_insn_arc):Update for more instructions lengths.
477 * arc-ext.c (extInstruction_t): Change argument type.
478 * arc-ext.h (extInstruction_t): Change argument type.
479 * arc-fxi.h: Change type unsigned to unsigned long long
480 extensively throughout.
481 * arc-nps400-tbl.h: Add long instructions taken from
482 arc_long_opcodes table in arc-opc.c.
483 * arc-opc.c: Update parameter types on insert/extract handlers.
484 (arc_long_opcodes): Delete.
485 (arc_num_long_opcodes): Delete.
486 (arc_opcode_len): Update for more instruction lengths.
487
90f61cce
GM		 4882016-11-03 Graham Markall <graham.markall@embecosm.com>
489
490 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
491
06fe285f
GM		 4922016-11-03 Graham Markall <graham.markall@embecosm.com>
493
494 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
495 with arc_opcode_len.
496 (find_format_long_instructions): Likewise.
497 * arc-opc.c (arc_opcode_len): New function.
498
ecf64ec6
AB		 4992016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
500
501 * arc-nps400-tbl.h: Fix some instruction masks.
502
d039fef3
L		 5032016-11-03 H.J. Lu <hongjiu.lu@intel.com>
504
505 * i386-dis.c (REG_82): Removed.
506 (X86_64_82_REG_0): Likewise.
507 (X86_64_82_REG_1): Likewise.
508 (X86_64_82_REG_2): Likewise.
509 (X86_64_82_REG_3): Likewise.
510 (X86_64_82_REG_4): Likewise.
511 (X86_64_82_REG_5): Likewise.
512 (X86_64_82_REG_6): Likewise.
513 (X86_64_82_REG_7): Likewise.
514 (X86_64_82): New.
515 (dis386): Use X86_64_82 instead of REG_82.
516 (reg_table): Remove REG_82.
517 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
518 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
519 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
520 X86_64_82_REG_7.
521
8b89fe14
L		 5222016-11-03 H.J. Lu <hongjiu.lu@intel.com>
523
524 PR binutils/20754
525 * i386-dis.c (REG_82): New.
526 (X86_64_82_REG_0): Likewise.
527 (X86_64_82_REG_1): Likewise.
528 (X86_64_82_REG_2): Likewise.
529 (X86_64_82_REG_3): Likewise.
530 (X86_64_82_REG_4): Likewise.
531 (X86_64_82_REG_5): Likewise.
532 (X86_64_82_REG_6): Likewise.
533 (X86_64_82_REG_7): Likewise.
534 (dis386): Use REG_82.
535 (reg_table): Add REG_82.
536 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
537 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
538 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
539
7148c369
L		 5402016-11-03 H.J. Lu <hongjiu.lu@intel.com>
541
542 * i386-dis.c (REG_82): Renamed to ...
543 (REG_83): This.
544 (dis386): Updated.
545 (reg_table): Likewise.
546
47acf0bd
IT		 5472016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
548
549 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
550 * i386-dis-evex.h (evex_table): Updated.
551 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
552 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
553 (cpu_flags): Add CpuAVX512_4VNNIW.
554 * i386-opc.h (enum): (AVX512_4VNNIW): New.
555 (i386_cpu_flags): Add cpuavx512_4vnniw.
556 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
557 * i386-init.h: Regenerate.
558 * i386-tbl.h: Ditto.
559
920d2ddc
IT		 5602016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
561
562 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
563 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
564 * i386-dis-evex.h (evex_table): Updated.
565 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
566 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
567 (cpu_flags): Add CpuAVX512_4FMAPS.
568 (opcode_modifiers): Add ImplicitQuadGroup modifier.
569 * i386-opc.h (AVX512_4FMAP): New.
570 (i386_cpu_flags): Add cpuavx512_4fmaps.
571 (ImplicitQuadGroup): New.
572 (i386_opcode_modifier): Add implicitquadgroup.
573 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
574 * i386-init.h: Regenerate.
575 * i386-tbl.h: Ditto.
576
e23eba97
NC		 5772016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
578 Andrew Waterman <andrew@sifive.com>
579
580 Add support for RISC-V architecture.
581 * configure.ac: Add entry for bfd_riscv_arch.
582 * configure: Regenerate.
583 * disassemble.c (disassembler): Add support for riscv.
584 (disassembler_usage): Likewise.
585 * riscv-dis.c: New file.
586 * riscv-opc.c: New file.
587
b5cefcca
L		 5882016-10-21 H.J. Lu <hongjiu.lu@intel.com>
589
590 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
591 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
592 (rm_table): Update the RM_0FAE_REG_7 entry.
593 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
594 (cpu_flags): Remove CpuPCOMMIT.
595 * i386-opc.h (CpuPCOMMIT): Removed.
596 (i386_cpu_flags): Remove cpupcommit.
597 * i386-opc.tbl: Remove pcommit.
598 * i386-init.h: Regenerated.
599 * i386-tbl.h: Likewise.
600
9889cbb1
L		 6012016-10-20 H.J. Lu <hongjiu.lu@intel.com>
602
603 PR binutis/20705
604 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
605 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
606 32-bit mode. Don't check vex.register_specifier in 32-bit
607 mode.
608 (OP_VEX): Check for invalid mask registers.
609
28596323
L		 6102016-10-18 H.J. Lu <hongjiu.lu@intel.com>
611
612 PR binutis/20699
613 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
614 sizeflag.
615
da8d7d66
L		 6162016-10-18 H.J. Lu <hongjiu.lu@intel.com>
617
618 PR binutis/20704
619 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
620
eaf02703
MR		 6212016-10-18 Maciej W. Rozycki <macro@imgtec.com>
622
623 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
624 local variable to `index_regno'.
625
decf5bd1
CM		 6262016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
627
628 * arc-tbl.h: Removed any "inv.+" instructions from the table.
629
e5b06ef0
CZ		 6302016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
631
632 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
633 usage on ISA basis.
634
93562a34
JW		 6352016-10-11 Jiong Wang <jiong.wang@arm.com>
636
637 PR target/20666
638 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
639
362c0c4d
JW		 6402016-10-07 Jiong Wang <jiong.wang@arm.com>
641
642 PR target/20667
643 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
644 available.
645
1047201f
AM		 6462016-10-07 Alan Modra <amodra@gmail.com>
647
648 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
649
1a0670f3
AM		 6502016-10-06 Alan Modra <amodra@gmail.com>
651
652 * aarch64-opc.c: Spell fall through comments consistently.
653 * i386-dis.c: Likewise.
654 * aarch64-dis.c: Add missing fall through comments.
655 * aarch64-opc.c: Likewise.
656 * arc-dis.c: Likewise.
657 * arm-dis.c: Likewise.
658 * i386-dis.c: Likewise.
659 * m68k-dis.c: Likewise.
660 * mep-asm.c: Likewise.
661 * ns32k-dis.c: Likewise.
662 * sh-dis.c: Likewise.
663 * tic4x-dis.c: Likewise.
664 * tic6x-dis.c: Likewise.
665 * vax-dis.c: Likewise.
666
2b804145
AM		 6672016-10-06 Alan Modra <amodra@gmail.com>
668
669 * arc-ext.c (create_map): Add missing break.
670 * msp430-decode.opc (encode_as): Likewise.
671 * msp430-decode.c: Regenerate.
672
616ec358
AM		 6732016-10-06 Alan Modra <amodra@gmail.com>
674
675 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
676 * crx-dis.c (print_insn_crx): Likewise.
677
72da393d
L		 6782016-09-30 H.J. Lu <hongjiu.lu@intel.com>
679
680 PR binutils/20657
681 * i386-dis.c (putop): Don't assign alt twice.
682
744ce302
JW		 6832016-09-29 Jiong Wang <jiong.wang@arm.com>
684
685 PR target/20553
686 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
687
a5721ba2
AM		 6882016-09-29 Alan Modra <amodra@gmail.com>
689
690 * ppc-opc.c (L): Make compulsory.
691 (LOPT): New, optional form of L.
692 (HTM_R): Define as LOPT.
693 (L0, L1): Delete.
694 (L32OPT): New, optional for 32-bit L.
695 (L2OPT): New, 2-bit L for dcbf.
696 (SVC_LEC): Update.
697 (L2): Define.
698 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
699 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
700 <dcbf>: Use L2OPT.
701 <tlbiel, tlbie>: Use LOPT.
702 <wclr, wclrall>: Use L2.
703
c5da1932
VZ		 7042016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
705
706 * Makefile.in: Regenerate.
707 * configure: Likewise.
708
2b848ebd
CZ		 7092016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
710
711 * arc-ext-tbl.h (EXTINSN2OPF): Define.
712 (EXTINSN2OP): Use EXTINSN2OPF.
713 (bspeekm, bspop, modapp): New extension instructions.
714 * arc-opc.c (F_DNZ_ND): Define.
715 (F_DNZ_D): Likewise.
716 (F_SIZEB1): Changed.
717 (C_DNZ_D): Define.
718 (C_HARD): Changed.
719 * arc-tbl.h (dbnz): New instruction.
720 (prealloc): Allow it for ARC EM.
721 (xbfu): Likewise.
722
ad43e107
RS		 7232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
724
725 * aarch64-opc.c (print_immediate_offset_address): Print spaces
726 after commas in addresses.
727 (aarch64_print_operand): Likewise.
728
ab3b8fcf
RS		 7292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
730
731 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
732 rather than "should be" or "expected to be" in error messages.
733
bb7eff52
RS		 7342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
735
736 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
737 (print_mnemonic_name): ...here.
738 (print_comment): New function.
739 (print_aarch64_insn): Call it.
740 * aarch64-opc.c (aarch64_conds): Add SVE names.
741 (aarch64_print_operand): Print alternative condition names in
742 a comment.
743
c0890d26
RS		 7442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
745
746 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
747 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
748 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
749 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
750 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
751 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
752 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
753 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
754 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
755 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
756 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
757 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
758 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
759 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
760 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
761 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
762 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
763 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
764 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
765 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
766 (OP_SVE_XWU, OP_SVE_XXU): New macros.
767 (aarch64_feature_sve): New variable.
768 (SVE): New macro.
769 (_SVE_INSN): Likewise.
770 (aarch64_opcode_table): Add SVE instructions.
771 * aarch64-opc.h (extract_fields): Declare.
772 * aarch64-opc-2.c: Regenerate.
773 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
774 * aarch64-asm-2.c: Regenerate.
775 * aarch64-dis.c (extract_fields): Make global.
776 (do_misc_decoding): Handle the new SVE aarch64_ops.
777 * aarch64-dis-2.c: Regenerate.
778
116b6019
RS		 7792016-09-21 Richard Sandiford <richard.sandiford@arm.com>
780
781 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
782 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
783 aarch64_field_kinds.
784 * aarch64-opc.c (fields): Add corresponding entries.
785 * aarch64-asm.c (aarch64_get_variant): New function.
786 (aarch64_encode_variant_using_iclass): Likewise.
787 (aarch64_opcode_encode): Call it.
788 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
789 (aarch64_opcode_decode): Call it.
790
047cd301
RS		 7912016-09-21 Richard Sandiford <richard.sandiford@arm.com>
792
793 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
794 and FP register operands.
795 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
796 (FLD_SVE_Vn): New aarch64_field_kinds.
797 * aarch64-opc.c (fields): Add corresponding entries.
798 (aarch64_print_operand): Handle the new SVE core and FP register
799 operands.
800 * aarch64-opc-2.c: Regenerate.
801 * aarch64-asm-2.c: Likewise.
802 * aarch64-dis-2.c: Likewise.
803
165d4950
RS		 8042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
805
806 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
807 immediate operands.
808 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
809 * aarch64-opc.c (fields): Add corresponding entry.
810 (operand_general_constraint_met_p): Handle the new SVE FP immediate
811 operands.
812 (aarch64_print_operand): Likewise.
813 * aarch64-opc-2.c: Regenerate.
814 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
815 (ins_sve_float_zero_one): New inserters.
816 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
817 (aarch64_ins_sve_float_half_two): Likewise.
818 (aarch64_ins_sve_float_zero_one): Likewise.
819 * aarch64-asm-2.c: Regenerate.
820 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
821 (ext_sve_float_zero_one): New extractors.
822 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
823 (aarch64_ext_sve_float_half_two): Likewise.
824 (aarch64_ext_sve_float_zero_one): Likewise.
825 * aarch64-dis-2.c: Regenerate.
826
e950b345
RS		 8272016-09-21 Richard Sandiford <richard.sandiford@arm.com>
828
829 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
830 integer immediate operands.
831 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
832 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
833 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
834 * aarch64-opc.c (fields): Add corresponding entries.
835 (operand_general_constraint_met_p): Handle the new SVE integer
836 immediate operands.
837 (aarch64_print_operand): Likewise.
838 (aarch64_sve_dupm_mov_immediate_p): New function.
839 * aarch64-opc-2.c: Regenerate.
840 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
841 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
842 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
843 (aarch64_ins_limm): ...here.
844 (aarch64_ins_inv_limm): New function.
845 (aarch64_ins_sve_aimm): Likewise.
846 (aarch64_ins_sve_asimm): Likewise.
847 (aarch64_ins_sve_limm_mov): Likewise.
848 (aarch64_ins_sve_shlimm): Likewise.
849 (aarch64_ins_sve_shrimm): Likewise.
850 * aarch64-asm-2.c: Regenerate.
851 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
852 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
853 * aarch64-dis.c (decode_limm): New function, split out from...
854 (aarch64_ext_limm): ...here.
855 (aarch64_ext_inv_limm): New function.
856 (decode_sve_aimm): Likewise.
857 (aarch64_ext_sve_aimm): Likewise.
858 (aarch64_ext_sve_asimm): Likewise.
859 (aarch64_ext_sve_limm_mov): Likewise.
860 (aarch64_top_bit): Likewise.
861 (aarch64_ext_sve_shlimm): Likewise.
862 (aarch64_ext_sve_shrimm): Likewise.
863 * aarch64-dis-2.c: Regenerate.
864
98907a70
RS		 8652016-09-21 Richard Sandiford <richard.sandiford@arm.com>
866
867 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
868 operands.
869 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
870 the AARCH64_MOD_MUL_VL entry.
871 (value_aligned_p): Cope with non-power-of-two alignments.
872 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
873 (print_immediate_offset_address): Likewise.
874 (aarch64_print_operand): Likewise.
875 * aarch64-opc-2.c: Regenerate.
876 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
877 (ins_sve_addr_ri_s9xvl): New inserters.
878 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
879 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
880 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
881 * aarch64-asm-2.c: Regenerate.
882 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
883 (ext_sve_addr_ri_s9xvl): New extractors.
884 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
885 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
886 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
887 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
888 * aarch64-dis-2.c: Regenerate.
889
4df068de
RS		 8902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
891
892 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
893 address operands.
894 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
895 (FLD_SVE_xs_22): New aarch64_field_kinds.
896 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
897 (get_operand_specific_data): New function.
898 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
899 FLD_SVE_xs_14 and FLD_SVE_xs_22.
900 (operand_general_constraint_met_p): Handle the new SVE address
901 operands.
902 (sve_reg): New array.
903 (get_addr_sve_reg_name): New function.
904 (aarch64_print_operand): Handle the new SVE address operands.
905 * aarch64-opc-2.c: Regenerate.
906 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
907 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
908 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
909 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
910 (aarch64_ins_sve_addr_rr_lsl): Likewise.
911 (aarch64_ins_sve_addr_rz_xtw): Likewise.
912 (aarch64_ins_sve_addr_zi_u5): Likewise.
913 (aarch64_ins_sve_addr_zz): Likewise.
914 (aarch64_ins_sve_addr_zz_lsl): Likewise.
915 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
916 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
917 * aarch64-asm-2.c: Regenerate.
918 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
919 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
920 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
921 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
922 (aarch64_ext_sve_addr_ri_u6): Likewise.
923 (aarch64_ext_sve_addr_rr_lsl): Likewise.
924 (aarch64_ext_sve_addr_rz_xtw): Likewise.
925 (aarch64_ext_sve_addr_zi_u5): Likewise.
926 (aarch64_ext_sve_addr_zz): Likewise.
927 (aarch64_ext_sve_addr_zz_lsl): Likewise.
928 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
929 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
930 * aarch64-dis-2.c: Regenerate.
931
2442d846
RS		 9322016-09-21 Richard Sandiford <richard.sandiford@arm.com>
933
934 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
935 AARCH64_OPND_SVE_PATTERN_SCALED.
936 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
937 * aarch64-opc.c (fields): Add a corresponding entry.
938 (set_multiplier_out_of_range_error): New function.
939 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
940 (operand_general_constraint_met_p): Handle
941 AARCH64_OPND_SVE_PATTERN_SCALED.
942 (print_register_offset_address): Use PRIi64 to print the
943 shift amount.
944 (aarch64_print_operand): Likewise. Handle
945 AARCH64_OPND_SVE_PATTERN_SCALED.
946 * aarch64-opc-2.c: Regenerate.
947 * aarch64-asm.h (ins_sve_scale): New inserter.
948 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
949 * aarch64-asm-2.c: Regenerate.
950 * aarch64-dis.h (ext_sve_scale): New inserter.
951 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
952 * aarch64-dis-2.c: Regenerate.
953
245d2e3f
RS		 9542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
955
956 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
957 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
958 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
959 (FLD_SVE_prfop): Likewise.
960 * aarch64-opc.c: Include libiberty.h.
961 (aarch64_sve_pattern_array): New variable.
962 (aarch64_sve_prfop_array): Likewise.
963 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
964 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
965 AARCH64_OPND_SVE_PRFOP.
966 * aarch64-asm-2.c: Regenerate.
967 * aarch64-dis-2.c: Likewise.
968 * aarch64-opc-2.c: Likewise.
969
d50c751e
RS		 9702016-09-21 Richard Sandiford <richard.sandiford@arm.com>
971
972 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
973 AARCH64_OPND_QLF_P_[ZM].
974 (aarch64_print_operand): Print /z and /m where appropriate.
975
f11ad6bc
RS		 9762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
977
978 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
979 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
980 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
981 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
982 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
983 * aarch64-opc.c (fields): Add corresponding entries here.
984 (operand_general_constraint_met_p): Check that SVE register lists
985 have the correct length. Check the ranges of SVE index registers.
986 Check for cases where p8-p15 are used in 3-bit predicate fields.
987 (aarch64_print_operand): Handle the new SVE operands.
988 * aarch64-opc-2.c: Regenerate.
989 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
990 * aarch64-asm.c (aarch64_ins_sve_index): New function.
991 (aarch64_ins_sve_reglist): Likewise.
992 * aarch64-asm-2.c: Regenerate.
993 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
994 * aarch64-dis.c (aarch64_ext_sve_index): New function.
995 (aarch64_ext_sve_reglist): Likewise.
996 * aarch64-dis-2.c: Regenerate.
997
0c608d6b
RS		 9982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
999
1000 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
1001 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
1002 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
1003 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1004 tied operands.
1005
01dbfe4c
RS		 10062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1007
1008 * aarch64-opc.c (get_offset_int_reg_name): New function.
1009 (print_immediate_offset_address): Likewise.
1010 (print_register_offset_address): Take the base and offset
1011 registers as parameters.
1012 (aarch64_print_operand): Update caller accordingly. Use
1013 print_immediate_offset_address.
1014
72e9f319
RS		 10152016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1016
1017 * aarch64-opc.c (BANK): New macro.
1018 (R32, R64): Take a register number as argument
1019 (int_reg): Use BANK.
1020
8a7f0c1b
RS		 10212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1022
1023 * aarch64-opc.c (print_register_list): Add a prefix parameter.
1024 (aarch64_print_operand): Update accordingly.
1025
aa2aa4c6
RS		 10262016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1027
1028 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1029 for FPIMM.
1030 * aarch64-asm.h (ins_fpimm): New inserter.
1031 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1032 * aarch64-asm-2.c: Regenerate.
1033 * aarch64-dis.h (ext_fpimm): New extractor.
1034 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1035 (aarch64_ext_fpimm): New function.
1036 * aarch64-dis-2.c: Regenerate.
1037
b5464a68
RS		 10382016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1039
1040 * aarch64-asm.c: Include libiberty.h.
1041 (insert_fields): New function.
1042 (aarch64_ins_imm): Use it.
1043 * aarch64-dis.c (extract_fields): New function.
1044 (aarch64_ext_imm): Use it.
1045
42408347
RS		 10462016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1047
1048 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1049 with an esize parameter.
1050 (operand_general_constraint_met_p): Update accordingly.
1051 Fix misindented code.
1052 * aarch64-asm.c (aarch64_ins_limm): Update call to
1053 aarch64_logical_immediate_p.
1054
4989adac
RS		 10552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1056
1057 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1058
bd11d5d8
RS		 10592016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1060
1061 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1062
f807f43d
CZ		 10632016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1064
1065 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1066
fd486b63
PB		 10672016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1068
1069 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1070 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1071 xor3>: Delete mnemonics.
1072 <cp_abort>: Rename mnemonic from ...
1073 <cpabort>: ...to this.
1074 <setb>: Change to a X form instruction.
1075 <sync>: Change to 1 operand form.
1076 <copy>: Delete mnemonic.
1077 <copy_first>: Rename mnemonic from ...
1078 <copy>: ...to this.
1079 <paste, paste.>: Delete mnemonics.
1080 <paste_last>: Rename mnemonic from ...
1081 <paste.>: ...to this.
1082
dce08442
AK		 10832016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1084
1085 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1086
952c3f51
AK		 10872016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1088
1089 * s390-mkopc.c (main): Support alternate arch strings.
1090
8b71537b
PS		 10912016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1092
1093 * s390-opc.txt: Fix kmctr instruction type.
1094
5b64d091
L		 10952016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1096
1097 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1098 * i386-init.h: Regenerated.
1099
7763838e
CM		 11002016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1101
1102 * opcodes/arc-dis.c (print_insn_arc): Changed.
1103
1b8b6532
JM		 11042016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1105
1106 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1107 camellia_fl.
1108
1a336194
TP		 11092016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1110
1111 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1112 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1113 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1114
6b40c462
L		 11152016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1116
1117 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1118 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1119 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1120 PREFIX_MOD_3_0FAE_REG_4.
1121 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1122 PREFIX_MOD_3_0FAE_REG_4.
1123 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1124 (cpu_flags): Add CpuPTWRITE.
1125 * i386-opc.h (CpuPTWRITE): New.
1126 (i386_cpu_flags): Add cpuptwrite.
1127 * i386-opc.tbl: Add ptwrite instruction.
1128 * i386-init.h: Regenerated.
1129 * i386-tbl.h: Likewise.
1130
ab548d2d
AK		 11312016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1132
1133 * arc-dis.h: Wrap around in extern "C".
1134
344bde0a
RS		 11352016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1136
1137 * aarch64-tbl.h (V8_2_INSN): New macro.
1138 (aarch64_opcode_table): Use it.
1139
5ce912d8
RS		 11402016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1141
1142 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1143 CORE_INSN, __FP_INSN and SIMD_INSN.
1144
9d30b0bd
RS		 11452016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1146
1147 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1148 (aarch64_opcode_table): Update uses accordingly.
1149
dfdaec14
AJ		 11502016-07-25 Andrew Jenner <andrew@codesourcery.com>
1151 Kwok Cheung Yeung <kcy@codesourcery.com>
1152
1153 opcodes/
1154 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1155 'e_cmplwi' to 'e_cmpli' instead.
1156 (OPVUPRT, OPVUPRT_MASK): Define.
1157 (powerpc_opcodes): Add E200Z4 insns.
1158 (vle_opcodes): Add context save/restore insns.
1159
7bd374a4
MR		 11602016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1161
1162 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1163 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1164 "j".
1165
db18dbab
GM		 11662016-07-27 Graham Markall <graham.markall@embecosm.com>
1167
1168 * arc-nps400-tbl.h: Change block comments to GNU format.
1169 * arc-dis.c: Add new globals addrtypenames,
1170 addrtypenames_max, and addtypeunknown.
1171 (get_addrtype): New function.
1172 (print_insn_arc): Print colons and address types when
1173 required.
1174 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1175 define insert and extract functions for all address types.
1176 (arc_operands): Add operands for colon and all address
1177 types.
1178 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1179 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1180 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1181 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1182 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1183 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1184
fecd57f9
L		 11852016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1186
1187 * configure: Regenerated.
1188
37fd5ef3
CZ		 11892016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1190
1191 * arc-dis.c (skipclass): New structure.
1192 (decodelist): New variable.
1193 (is_compatible_p): New function.
1194 (new_element): Likewise.
1195 (skip_class_p): Likewise.
1196 (find_format_from_table): Use skip_class_p function.
1197 (find_format): Decode first the extension instructions.
1198 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1199 e_flags.
1200 (parse_option): New function.
1201 (parse_disassembler_options): Likewise.
1202 (print_arc_disassembler_options): Likewise.
1203 (print_insn_arc): Use parse_disassembler_options function. Proper
1204 select ARCv2 cpu variant.
1205 * disassemble.c (disassembler_usage): Add ARC disassembler
1206 options.
1207
92281a5b
MR		 12082016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1209
1210 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1211 annotation from the "nal" entry and reorder it beyond "bltzal".
1212
6e7ced37
JM		 12132016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1214
1215 * sparc-opc.c (ldtxa): New macro.
1216 (sparc_opcodes): Use the macro defined above to add entries for
1217 the LDTXA instructions.
1218 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1219 instruction.
1220
2f831b9a 12212016-07-07 James Bowman <james.bowman@ftdichip.com>
1222
1223 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1224 and "jmpc".
1225
c07315e0
JB		 12262016-07-01 Jan Beulich <jbeulich@suse.com>
1227
1228 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1229 (movzb): Adjust to cover all permitted suffixes.
1230 (movzw): New.
1231 * i386-tbl.h: Re-generate.
1232
9243100a
JB		 12332016-07-01 Jan Beulich <jbeulich@suse.com>
1234
1235 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1236 (lgdt): Remove Tbyte from non-64-bit variant.
1237 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1238 xsaves64, xsavec64): Remove Disp16.
1239 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1240 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1241 64-bit variants.
1242 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1243 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1244 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1245 64-bit variants.
1246 * i386-tbl.h: Re-generate.
1247
8325cc63
JB		 12482016-07-01 Jan Beulich <jbeulich@suse.com>
1249
1250 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1251 * i386-tbl.h: Re-generate.
1252
838441e4
YQ		 12532016-06-30 Yao Qi <yao.qi@linaro.org>
1254
1255 * arm-dis.c (print_insn): Fix typo in comment.
1256
dab26bf4
RS		 12572016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1258
1259 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1260 range of ldst_elemlist operands.
1261 (print_register_list): Use PRIi64 to print the index.
1262 (aarch64_print_operand): Likewise.
1263
5703197e
TS		 12642016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1265
1266 * mcore-opc.h: Remove sentinal.
1267 * mcore-dis.c (print_insn_mcore): Adjust.
1268
ce440d63
GM		 12692016-06-23 Graham Markall <graham.markall@embecosm.com>
1270
1271 * arc-opc.c: Correct description of availability of NPS400
1272 features.
1273
6fd3a02d
PB		 12742016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1275
1276 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1277 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1278 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1279 xor3>: New mnemonics.
1280 <setb>: Change to a VX form instruction.
1281 (insert_sh6): Add support for rldixor.
1282 (extract_sh6): Likewise.
1283
6b477896
TS		 12842016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1285
1286 * arc-ext.h: Wrap in extern C.
1287
bdd582db
GM		 12882016-06-21 Graham Markall <graham.markall@embecosm.com>
1289
1290 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1291 Use same method for determining instruction length on ARC700 and
1292 NPS-400.
1293 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1294 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1295 with the NPS400 subclass.
1296 * arc-opc.c: Likewise.
1297
96074adc
JM		 12982016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1299
1300 * sparc-opc.c (rdasr): New macro.
1301 (wrasr): Likewise.
1302 (rdpr): Likewise.
1303 (wrpr): Likewise.
1304 (rdhpr): Likewise.
1305 (wrhpr): Likewise.
1306 (sparc_opcodes): Use the macros above to fix and expand the
1307 definition of read/write instructions from/to
1308 asr/privileged/hyperprivileged instructions.
1309 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1310 %hva_mask_nz. Prefer softint_set and softint_clear over
1311 set_softint and clear_softint.
1312 (print_insn_sparc): Support %ver in Rd.
1313
7a10c22f
JM		 13142016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1315
1316 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1317 architecture according to the hardware capabilities they require.
1318
4f26fb3a
JM		 13192016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1320
1321 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1322 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1323 bfd_mach_sparc_v9{c,d,e,v,m}.
1324 * sparc-opc.c (MASK_V9C): Define.
1325 (MASK_V9D): Likewise.
1326 (MASK_V9E): Likewise.
1327 (MASK_V9V): Likewise.
1328 (MASK_V9M): Likewise.
1329 (v6): Add MASK_V9{C,D,E,V,M}.
1330 (v6notlet): Likewise.
1331 (v7): Likewise.
1332 (v8): Likewise.
1333 (v9): Likewise.
1334 (v9andleon): Likewise.
1335 (v9a): Likewise.
1336 (v9b): Likewise.
1337 (v9c): Define.
1338 (v9d): Likewise.
1339 (v9e): Likewise.
1340 (v9v): Likewise.
1341 (v9m): Likewise.
1342 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1343
3ee6e4fb
NC		 13442016-06-15 Nick Clifton <nickc@redhat.com>
1345
1346 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1347 constants to match expected behaviour.
1348 (nds32_parse_opcode): Likewise. Also for whitespace.
1349
02f3be19
AB		 13502016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1351
1352 * arc-opc.c (extract_rhv1): Extract value from insn.
1353
6f9f37ed 13542016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1355
1356 * arc-nps400-tbl.h: Add ldbit instruction.
1357 * arc-opc.c: Add flag classes required for ldbit.
1358
6f9f37ed 13592016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1360
1361 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1362 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1363 support the above instructions.
1364
6f9f37ed 13652016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1366
1367 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1368 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1369 csma, cbba, zncv, and hofs.
1370 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1371 support the above instructions.
1372
13732016-06-06 Graham Markall <graham.markall@embecosm.com>
1374
1375 * arc-nps400-tbl.h: Add andab and orab instructions.
1376
13772016-06-06 Graham Markall <graham.markall@embecosm.com>
1378
1379 * arc-nps400-tbl.h: Add addl-like instructions.
1380
13812016-06-06 Graham Markall <graham.markall@embecosm.com>
1382
1383 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1384
13852016-06-06 Graham Markall <graham.markall@embecosm.com>
1386
1387 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1388 instructions.
1389
b2cc3f6f
AK		 13902016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1391
1392 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1393 variable.
1394 (init_disasm): Handle new command line option "insnlength".
1395 (print_s390_disassembler_options): Mention new option in help
1396 output.
1397 (print_insn_s390): Use the encoded insn length when dumping
1398 unknown instructions.
1399
1857fe72
DC		 14002016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1401
1402 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1403 to the address and set as symbol address for LDS/ STS immediate operands.
1404
14b57c7c
AM		 14052016-06-07 Alan Modra <amodra@gmail.com>
1406
1407 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1408 cpu for "vle" to e500.
1409 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1410 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1411 (PPCNONE): Delete, substitute throughout.
1412 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1413 except for major opcode 4 and 31.
1414 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1415
4d1464f2
MW		 14162016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1417
1418 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1419 ARM_EXT_RAS in relevant entries.
1420
026122a6
PB		 14212016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1422
1423 PR binutils/20196
1424 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1425 opcodes for E6500.
1426
07f5af7d
L		 14272016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1428
1429 PR binutis/18386
1430 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1431 (indir_v_mode): New.
1432 Add comments for '&'.
1433 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1434 (putop): Handle '&'.
1435 (intel_operand_size): Handle indir_v_mode.
1436 (OP_E_register): Likewise.
1437 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1438 64-bit indirect call/jmp for AMD64.
1439 * i386-tbl.h: Regenerated
1440
4eb6f892
AB		 14412016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1442
1443 * arc-dis.c (struct arc_operand_iterator): New structure.
1444 (find_format_from_table): All the old content from find_format,
1445 with some minor adjustments, and parameter renaming.
1446 (find_format_long_instructions): New function.
1447 (find_format): Rewritten.
1448 (arc_insn_length): Add LSB parameter.
1449 (extract_operand_value): New function.
1450 (operand_iterator_next): New function.
1451 (print_insn_arc): Use new functions to find opcode, and iterator
1452 over operands.
1453 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1454 (extract_nps_3bit_dst_short): New function.
1455 (insert_nps_3bit_src2_short): New function.
1456 (extract_nps_3bit_src2_short): New function.
1457 (insert_nps_bitop1_size): New function.
1458 (extract_nps_bitop1_size): New function.
1459 (insert_nps_bitop2_size): New function.
1460 (extract_nps_bitop2_size): New function.
1461 (insert_nps_bitop_mod4_msb): New function.
1462 (extract_nps_bitop_mod4_msb): New function.
1463 (insert_nps_bitop_mod4_lsb): New function.
1464 (extract_nps_bitop_mod4_lsb): New function.
1465 (insert_nps_bitop_dst_pos3_pos4): New function.
1466 (extract_nps_bitop_dst_pos3_pos4): New function.
1467 (insert_nps_bitop_ins_ext): New function.
1468 (extract_nps_bitop_ins_ext): New function.
1469 (arc_operands): Add new operands.
1470 (arc_long_opcodes): New global array.
1471 (arc_num_long_opcodes): New global.
1472 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1473
1fe0971e
TS		 14742016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1475
1476 * nds32-asm.h: Add extern "C".
1477 * sh-opc.h: Likewise.
1478
315f180f
GM		 14792016-06-01 Graham Markall <graham.markall@embecosm.com>
1480
1481 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1482 0,b,limm to the rflt instruction.
1483
a2b5fccc
TS		 14842016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1485
1486 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1487 constant.
1488
0cbd0046
L		 14892016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1490
1491 PR gas/20145
1492 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1493 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1494 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1495 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1496 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1497 * i386-init.h: Regenerated.
1498
1848e567
L		 14992016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1500
1501 PR gas/20145
1502 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1503 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1504 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1505 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1506 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1507 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1508 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1509 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1510 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1511 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1512 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1513 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1514 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1515 CpuRegMask for AVX512.
1516 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1517 and CpuRegMask.
1518 (set_bitfield_from_cpu_flag_init): New function.
1519 (set_bitfield): Remove const on f. Call
1520 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1521 * i386-opc.h (CpuRegMMX): New.
1522 (CpuRegXMM): Likewise.
1523 (CpuRegYMM): Likewise.
1524 (CpuRegZMM): Likewise.
1525 (CpuRegMask): Likewise.
1526 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1527 and cpuregmask.
1528 * i386-init.h: Regenerated.
1529 * i386-tbl.h: Likewise.
1530
e92bae62
L		 15312016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1532
1533 PR gas/20154
1534 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1535 (opcode_modifiers): Add AMD64 and Intel64.
1536 (main): Properly verify CpuMax.
1537 * i386-opc.h (CpuAMD64): Removed.
1538 (CpuIntel64): Likewise.
1539 (CpuMax): Set to CpuNo64.
1540 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1541 (AMD64): New.
1542 (Intel64): Likewise.
1543 (i386_opcode_modifier): Add amd64 and intel64.
1544 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1545 on call and jmp.
1546 * i386-init.h: Regenerated.
1547 * i386-tbl.h: Likewise.
1548
e89c5eaa
L		 15492016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1550
1551 PR gas/20154
1552 * i386-gen.c (main): Fail if CpuMax is incorrect.
1553 * i386-opc.h (CpuMax): Set to CpuIntel64.
1554 * i386-tbl.h: Regenerated.
1555
77d66e7b
NC		 15562016-05-27 Nick Clifton <nickc@redhat.com>
1557
1558 PR target/20150
1559 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1560 (msp430dis_opcode_unsigned): New function.
1561 (msp430dis_opcode_signed): New function.
1562 (msp430_singleoperand): Use the new opcode reading functions.
1563 Only disassenmble bytes if they were successfully read.
1564 (msp430_doubleoperand): Likewise.
1565 (msp430_branchinstr): Likewise.
1566 (msp430x_callx_instr): Likewise.
1567 (print_insn_msp430): Check that it is safe to read bytes before
1568 attempting disassembly. Use the new opcode reading functions.
1569
19dfcc89
PB		 15702016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1571
1572 * ppc-opc.c (CY): New define. Document it.
1573 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1574
f3ad7637
L		 15752016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1576
1577 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1578 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1579 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1580 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1581 CPU_ANY_AVX_FLAGS.
1582 * i386-init.h: Regenerated.
1583
f1360d58
L		 15842016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1585
1586 PR gas/20141
1587 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1588 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1589 * i386-init.h: Regenerated.
1590
293f5f65
L		 15912016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1592
1593 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1594 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1595 * i386-init.h: Regenerated.
1596
d9eca1df
CZ		 15972016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1598
1599 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1600 information.
1601 (print_insn_arc): Set insn_type information.
1602 * arc-opc.c (C_CC): Add F_CLASS_COND.
1603 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1604 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1605 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1606 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1607 (brne, brne_s, jeq_s, jne_s): Likewise.
1608
87789e08
CZ		 16092016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1610
1611 * arc-tbl.h (neg): New instruction variant.
1612
c810e0b8
CZ		 16132016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1614
1615 * arc-dis.c (find_format, find_format, get_auxreg)
1616 (print_insn_arc): Changed.
1617 * arc-ext.h (INSERT_XOP): Likewise.
1618
3d207518
TS		 16192016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1620
1621 * tic54x-dis.c (sprint_mmr): Adjust.
1622 * tic54x-opc.c: Likewise.
1623
514e58b7
AM		 16242016-05-19 Alan Modra <amodra@gmail.com>
1625
1626 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1627
e43de63c
AM		 16282016-05-19 Alan Modra <amodra@gmail.com>
1629
1630 * ppc-opc.c: Formatting.
1631 (NSISIGNOPT): Define.
1632 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1633
1401d2fe
MR		 16342016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1635
1636 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1637 replacing references to `micromips_ase' throughout.
1638 (_print_insn_mips): Don't use file-level microMIPS annotation to
1639 determine the disassembly mode with the symbol table.
1640
1178da44
PB		 16412016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1642
1643 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1644
8f4f9071
MF		 16452016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1646
1647 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1648 mips64r6.
1649 * mips-opc.c (D34): New macro.
1650 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1651
8bc52696
AF		 16522016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1653
1654 * i386-dis.c (prefix_table): Add RDPID instruction.
1655 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1656 (cpu_flags): Add RDPID bitfield.
1657 * i386-opc.h (enum): Add RDPID element.
1658 (i386_cpu_flags): Add RDPID field.
1659 * i386-opc.tbl: Add RDPID instruction.
1660 * i386-init.h: Regenerate.
1661 * i386-tbl.h: Regenerate.
1662
39d911fc
TP		 16632016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1664
1665 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1666 branch type of a symbol.
1667 (print_insn): Likewise.
1668
16a1fa25
TP		 16692016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1670
1671 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1672 Mainline Security Extensions instructions.
1673 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1674 Extensions instructions.
1675 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1676 instructions.
1677 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1678 special registers.
1679
d751b79e
JM		 16802016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1681
1682 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1683
945e0f82
CZ		 16842016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1685
1686 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1687 (arcExtMap_genOpcode): Likewise.
1688 * arc-opc.c (arg_32bit_rc): Define new variable.
1689 (arg_32bit_u6): Likewise.
1690 (arg_32bit_limm): Likewise.
1691
20f55f38
SN		 16922016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1693
1694 * aarch64-gen.c (VERIFIER): Define.
1695 * aarch64-opc.c (VERIFIER): Define.
1696 (verify_ldpsw): Use static linkage.
1697 * aarch64-opc.h (verify_ldpsw): Remove.
1698 * aarch64-tbl.h: Use VERIFIER for verifiers.
1699
4bd13cde
NC		 17002016-04-28 Nick Clifton <nickc@redhat.com>
1701
1702 PR target/19722
1703 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1704 * aarch64-opc.c (verify_ldpsw): New function.
1705 * aarch64-opc.h (verify_ldpsw): New prototype.
1706 * aarch64-tbl.h: Add initialiser for verifier field.
1707 (LDPSW): Set verifier to verify_ldpsw.
1708
c0f92bf9
L		 17092016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1710
1711 PR binutils/19983
1712 PR binutils/19984
1713 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1714 smaller than address size.
1715
e6c7cdec
TS		 17162016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1717
1718 * alpha-dis.c: Regenerate.
1719 * crx-dis.c: Likewise.
1720 * disassemble.c: Likewise.
1721 * epiphany-opc.c: Likewise.
1722 * fr30-opc.c: Likewise.
1723 * frv-opc.c: Likewise.
1724 * ip2k-opc.c: Likewise.
1725 * iq2000-opc.c: Likewise.
1726 * lm32-opc.c: Likewise.
1727 * lm32-opinst.c: Likewise.
1728 * m32c-opc.c: Likewise.
1729 * m32r-opc.c: Likewise.
1730 * m32r-opinst.c: Likewise.
1731 * mep-opc.c: Likewise.
1732 * mt-opc.c: Likewise.
1733 * or1k-opc.c: Likewise.
1734 * or1k-opinst.c: Likewise.
1735 * tic80-opc.c: Likewise.
1736 * xc16x-opc.c: Likewise.
1737 * xstormy16-opc.c: Likewise.
1738
537aefaf
AB		 17392016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1740
1741 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1742 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1743 calcsd, and calcxd instructions.
1744 * arc-opc.c (insert_nps_bitop_size): Delete.
1745 (extract_nps_bitop_size): Delete.
1746 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1747 (extract_nps_qcmp_m3): Define.
1748 (extract_nps_qcmp_m2): Define.
1749 (extract_nps_qcmp_m1): Define.
1750 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1751 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1752 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1753 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1754 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1755 NPS_QCMP_M3.
1756
c8f785f2
AB		 17572016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1758
1759 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1760
6fd8e7c2
L		 17612016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1762
1763 * Makefile.in: Regenerated with automake 1.11.6.
1764 * aclocal.m4: Likewise.
1765
4b0c052e
AB		 17662016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1767
1768 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1769 instructions.
1770 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1771 (extract_nps_cmem_uimm16): New function.
1772 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1773
cb040366
AB		 17742016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1775
1776 * arc-dis.c (arc_insn_length): New function.
1777 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1778 (find_format): Change insnLen parameter to unsigned.
1779
accc0180
NC		 17802016-04-13 Nick Clifton <nickc@redhat.com>
1781
1782 PR target/19937
1783 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1784 the LD.B and LD.BU instructions.
1785
f36e33da
CZ		 17862016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1787
1788 * arc-dis.c (find_format): Check for extension flags.
1789 (print_flags): New function.
1790 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1791 .extAuxRegister.
1792 * arc-ext.c (arcExtMap_coreRegName): Use
1793 LAST_EXTENSION_CORE_REGISTER.
1794 (arcExtMap_coreReadWrite): Likewise.
1795 (dump_ARC_extmap): Update printing.
1796 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1797 (arc_aux_regs): Add cpu field.
1798 * arc-regs.h: Add cpu field, lower case name aux registers.
1799
1c2e355e
CZ		 18002016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1801
1802 * arc-tbl.h: Add rtsc, sleep with no arguments.
1803
b99747ae
CZ		 18042016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1805
1806 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1807 Initialize.
1808 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1809 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1810 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1811 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1812 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1813 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1814 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1815 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1816 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1817 (arc_opcode arc_opcodes): Null terminate the array.
1818 (arc_num_opcodes): Remove.
1819 * arc-ext.h (INSERT_XOP): Define.
1820 (extInstruction_t): Likewise.
1821 (arcExtMap_instName): Delete.
1822 (arcExtMap_insn): New function.
1823 (arcExtMap_genOpcode): Likewise.
1824 * arc-ext.c (ExtInstruction): Remove.
1825 (create_map): Zero initialize instruction fields.
1826 (arcExtMap_instName): Remove.
1827 (arcExtMap_insn): New function.
1828 (dump_ARC_extmap): More info while debuging.
1829 (arcExtMap_genOpcode): New function.
1830 * arc-dis.c (find_format): New function.
1831 (print_insn_arc): Use find_format.
1832 (arc_get_disassembler): Enable dump_ARC_extmap only when
1833 debugging.
1834
92708cec
MR		 18352016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1836
1837 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1838 instruction bits out.
1839
a42a4f84
AB		 18402016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1841
1842 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1843 * arc-opc.c (arc_flag_operands): Add new flags.
1844 (arc_flag_classes): Add new classes.
1845
1328504b
AB		 18462016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1847
1848 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1849
820f03ff
AB		 18502016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1851
1852 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1853 encode1, rflt, crc16, and crc32 instructions.
1854 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1855 (arc_flag_classes): Add C_NPS_R.
1856 (insert_nps_bitop_size_2b): New function.
1857 (extract_nps_bitop_size_2b): Likewise.
1858 (insert_nps_bitop_uimm8): Likewise.
1859 (extract_nps_bitop_uimm8): Likewise.
1860 (arc_operands): Add new operand entries.
1861
8ddf6b2a
CZ		 18622016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1863
b99747ae
CZ		 1864 * arc-regs.h: Add a new subclass field. Add double assist
1865 accumulator register values.
1866 * arc-tbl.h: Use DPA subclass to mark the double assist
1867 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1868 * arc-opc.c (RSP): Define instead of SP.
1869 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1870
589a7d88
JW		 18712016-04-05 Jiong Wang <jiong.wang@arm.com>
1872
1873 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1874
0a191de9 18752016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1876
1877 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1878 NPS_R_SRC1.
1879
0a106562
AB		 18802016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1881
1882 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1883 issues. No functional changes.
1884
bd05ac5f
CZ		 18852016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1886
b99747ae
CZ		 1887 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1888 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1889 (RTT): Remove duplicate.
1890 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1891 (PCT_CONFIG*): Remove.
1892 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1893
9885948f
CZ		 18942016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1895
b99747ae 1896 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1897
f2dd8838
CZ		 18982016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1899
b99747ae
CZ		 1900 * arc-tbl.h (invld07): Remove.
1901 * arc-ext-tbl.h: New file.
1902 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1903 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1904
0d2f91fe
JK		 19052016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1906
1907 Fix -Wstack-usage warnings.
1908 * aarch64-dis.c (print_operands): Substitute size.
1909 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1910
a6b71f42
JM		 19112016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1912
1913 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1914 to get a proper diagnostic when an invalid ASR register is used.
1915
9780e045
NC		 19162016-03-22 Nick Clifton <nickc@redhat.com>
1917
1918 * configure: Regenerate.
1919
e23e8ebe
AB		 19202016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1921
1922 * arc-nps400-tbl.h: New file.
1923 * arc-opc.c: Add top level comment.
1924 (insert_nps_3bit_dst): New function.
1925 (extract_nps_3bit_dst): New function.
1926 (insert_nps_3bit_src2): New function.
1927 (extract_nps_3bit_src2): New function.
1928 (insert_nps_bitop_size): New function.
1929 (extract_nps_bitop_size): New function.
1930 (arc_flag_operands): Add nps400 entries.
1931 (arc_flag_classes): Add nps400 entries.
1932 (arc_operands): Add nps400 entries.
1933 (arc_opcodes): Add nps400 include.
1934
1ae8ab47
AB		 19352016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1936
1937 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1938 the new class enum values.
1939
8699fc3e
AB		 19402016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1941
1942 * arc-dis.c (print_insn_arc): Handle nps400.
1943
24740d83
AB		 19442016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1945
1946 * arc-opc.c (BASE): Delete.
1947
8678914f
NC		 19482016-03-18 Nick Clifton <nickc@redhat.com>
1949
1950 PR target/19721
1951 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1952 of MOV insn that aliases an ORR insn.
1953
cc933301
JW		 19542016-03-16 Jiong Wang <jiong.wang@arm.com>
1955
1956 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1957
f86f5863
TS		 19582016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1959
1960 * mcore-opc.h: Add const qualifiers.
1961 * microblaze-opc.h (struct op_code_struct): Likewise.
1962 * sh-opc.h: Likewise.
1963 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1964 (tic4x_print_op): Likewise.
1965
62de1c63
AM		 19662016-03-02 Alan Modra <amodra@gmail.com>
1967
d11698cd 1968 * or1k-desc.h: Regenerate.
62de1c63 1969 * fr30-ibld.c: Regenerate.
c697cf0b 1970 * rl78-decode.c: Regenerate.
62de1c63 1971
020efce5
NC		 19722016-03-01 Nick Clifton <nickc@redhat.com>
1973
1974 PR target/19747
1975 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1976
b0c11777
RL		 19772016-02-24 Renlin Li <renlin.li@arm.com>
1978
1979 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1980 (print_insn_coprocessor): Support fp16 instructions.
1981
3e309328
RL		 19822016-02-24 Renlin Li <renlin.li@arm.com>
1983
1984 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1985 vminnm, vrint(mpna).
1986
8afc7bea
RL		 19872016-02-24 Renlin Li <renlin.li@arm.com>
1988
1989 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1990 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1991
4fd7268a
L		 19922016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1993
1994 * i386-dis.c (print_insn): Parenthesize expression to prevent
1995 truncated addresses.
1996 (OP_J): Likewise.
1997
4670103e
CZ		 19982016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1999 Janek van Oirschot <jvanoirs@synopsys.com>
2000
b99747ae
CZ		 2001 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
2002 variable.
4670103e 2003
c1d9289f
NC		 20042016-02-04 Nick Clifton <nickc@redhat.com>
2005
2006 PR target/19561
2007 * msp430-dis.c (print_insn_msp430): Add a special case for
2008 decoding an RRC instruction with the ZC bit set in the extension
2009 word.
2010
a143b004
AB		 20112016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2012
2013 * cgen-ibld.in (insert_normal): Rework calculation of shift.
2014 * epiphany-ibld.c: Regenerate.
2015 * fr30-ibld.c: Regenerate.
2016 * frv-ibld.c: Regenerate.
2017 * ip2k-ibld.c: Regenerate.
2018 * iq2000-ibld.c: Regenerate.
2019 * lm32-ibld.c: Regenerate.
2020 * m32c-ibld.c: Regenerate.
2021 * m32r-ibld.c: Regenerate.
2022 * mep-ibld.c: Regenerate.
2023 * mt-ibld.c: Regenerate.
2024 * or1k-ibld.c: Regenerate.
2025 * xc16x-ibld.c: Regenerate.
2026 * xstormy16-ibld.c: Regenerate.
2027
b89807c6
AB		 20282016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2029
2030 * epiphany-dis.c: Regenerated from latest cpu files.
2031
d8c823c8
MM		 20322016-02-01 Michael McConville <mmcco@mykolab.com>
2033
2034 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2035 test bit.
2036
5bc5ae88
RL		 20372016-01-25 Renlin Li <renlin.li@arm.com>
2038
2039 * arm-dis.c (mapping_symbol_for_insn): New function.
2040 (find_ifthen_state): Call mapping_symbol_for_insn().
2041
0bff6e2d
MW		 20422016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2043
2044 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2045 of MSR UAO immediate operand.
2046
100b4f2e
MR		 20472016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2048
2049 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2050 instruction support.
2051
5c14705f
AM		 20522016-01-17 Alan Modra <amodra@gmail.com>
2053
2054 * configure: Regenerate.
2055
4d82fe66
NC		 20562016-01-14 Nick Clifton <nickc@redhat.com>
2057
2058 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2059 instructions that can support stack pointer operations.
2060 * rl78-decode.c: Regenerate.
2061 * rl78-dis.c: Fix display of stack pointer in MOVW based
2062 instructions.
2063
651657fa
MW		 20642016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2065
2066 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2067 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2068 erxtatus_el1 and erxaddr_el1.
2069
105bde57
MW		 20702016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2071
2072 * arm-dis.c (arm_opcodes): Add "esb".
2073 (thumb_opcodes): Likewise.
2074
afa8d405
PB		 20752016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2076
2077 * ppc-opc.c <xscmpnedp>: Delete.
2078 <xvcmpnedp>: Likewise.
2079 <xvcmpnedp.>: Likewise.
2080 <xvcmpnesp>: Likewise.
2081 <xvcmpnesp.>: Likewise.
2082
83c3256e
AS		 20832016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2084
2085 PR gas/13050
2086 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2087 addition to ISA_A.
2088
6f2750fe
AM		 20892016-01-01 Alan Modra <amodra@gmail.com>
2090
2091 Update year range in copyright notice of all files.
2092
3499769a
AM		 2093For older changes see ChangeLog-2015
2094\f
2095Copyright (C) 2016 Free Software Foundation, Inc.
2096
2097Copying and distribution of this file, with or without modification,
2098are permitted in any medium without royalty provided the copyright
2099notice and this notice are preserved.
2100
2101Local Variables:
2102mode: change-log
2103left-margin: 8
2104fill-column: 74
2105version-control: never
2106End:
GDB Binutils - Deliverables
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