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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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4f6ffcd3
PB		 12013-07-29 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
4
43234a1e
L		 52013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
6 Alexander Ivchenko <alexander.ivchenko@intel.com>
7 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
8 Sergey Lega <sergey.s.lega@intel.com>
9 Anna Tikhonova <anna.tikhonova@intel.com>
10 Ilya Tocar <ilya.tocar@intel.com>
11 Andrey Turetskiy <andrey.turetskiy@intel.com>
12 Ilya Verbin <ilya.verbin@intel.com>
13 Kirill Yukhin <kirill.yukhin@intel.com>
14 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
15
16 * i386-dis-evex.h: New.
17 * i386-dis.c (OP_Rounding): New.
18 (VPCMP_Fixup): New.
19 (OP_Mask): New.
20 (Rdq): New.
21 (XMxmmq): New.
22 (EXdScalarS): New.
23 (EXymm): New.
24 (EXEvexHalfBcstXmmq): New.
25 (EXxmm_mdq): New.
26 (EXEvexXGscat): New.
27 (EXEvexXNoBcst): New.
28 (VPCMP): New.
29 (EXxEVexR): New.
30 (EXxEVexS): New.
31 (XMask): New.
32 (MaskG): New.
33 (MaskE): New.
34 (MaskR): New.
35 (MaskVex): New.
36 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
37 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
38 evex_rounding_mode, evex_sae_mode, mask_mode.
39 (USE_EVEX_TABLE): New.
40 (EVEX_TABLE): New.
41 (EVEX enum): New.
42 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
43 REG_EVEX_0F38C7.
44 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
45 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
46 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
47 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
48 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
49 MOD_EVEX_0F38C7_REG_6.
50 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
51 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
52 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
53 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
54 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
55 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
56 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
57 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
58 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
59 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
60 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
61 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
62 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
63 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
64 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
65 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
66 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
67 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
68 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
69 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
70 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
71 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
72 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
73 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
74 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
75 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
76 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
77 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
78 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
79 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
80 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
81 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
82 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
83 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
84 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
85 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
86 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
87 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
88 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
89 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
90 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
91 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
92 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
93 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
94 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
95 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
96 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
97 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
98 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
99 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
100 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
101 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
102 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
103 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
104 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
105 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
106 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
107 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
108 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
109 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
110 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
111 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
112 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
113 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
114 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
115 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
116 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
117 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
118 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
119 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
120 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
121 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
122 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
123 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
124 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
125 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
126 PREFIX_EVEX_0F3A55.
127 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
128 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
129 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
130 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
131 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
132 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
133 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
134 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
135 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
136 VEX_W_0F3A32_P_2_LEN_0.
137 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
138 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
139 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
140 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
141 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
142 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
143 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
144 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
145 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
146 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
147 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
148 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
149 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
150 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
151 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
152 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
153 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
154 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
155 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
156 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
157 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
158 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
159 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
160 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
161 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
162 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
163 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
164 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
165 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
166 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
167 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
168 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
169 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
170 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
171 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
172 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
173 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
174 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
175 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
176 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
177 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
178 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
179 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
180 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
181 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
182 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
183 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
184 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
185 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
186 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
187 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
188 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
189 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
190 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
191 (struct vex): Add fields evex, r, v, mask_register_specifier,
192 zeroing, ll, b.
193 (intel_names_xmm): Add upper 16 registers.
194 (att_names_xmm): Ditto.
195 (intel_names_ymm): Ditto.
196 (att_names_ymm): Ditto.
197 (names_zmm): New.
198 (intel_names_zmm): Ditto.
199 (att_names_zmm): Ditto.
200 (names_mask): Ditto.
201 (intel_names_mask): Ditto.
202 (att_names_mask): Ditto.
203 (names_rounding): Ditto.
204 (names_broadcast): Ditto.
205 (x86_64_table): Add escape to evex-table.
206 (reg_table): Include reg_table evex-entries from
207 i386-dis-evex.h. Fix prefetchwt1 instruction.
208 (prefix_table): Add entries for new instructions.
209 (vex_table): Ditto.
210 (vex_len_table): Ditto.
211 (vex_w_table): Ditto.
212 (mod_table): Ditto.
213 (get_valid_dis386): Properly handle new instructions.
214 (print_insn): Handle zmm and mask registers, print mask operand.
215 (intel_operand_size): Support EVEX, new modes and sizes.
216 (OP_E_register): Handle new modes.
217 (OP_E_memory): Ditto.
218 (OP_G): Ditto.
219 (OP_XMM): Ditto.
220 (OP_EX): Ditto.
221 (OP_VEX): Ditto.
222 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
223 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
224 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
225 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
226 CpuAVX512PF and CpuVREX.
227 (operand_type_init): Add OPERAND_TYPE_REGZMM,
228 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
229 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
230 StaticRounding, SAE, Disp8MemShift, NoDefMask.
231 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
232 * i386-init.h: Regenerate.
233 * i386-opc.h (CpuAVX512F): New.
234 (CpuAVX512CD): New.
235 (CpuAVX512ER): New.
236 (CpuAVX512PF): New.
237 (CpuVREX): New.
238 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
239 cpuavx512pf and cpuvrex fields.
240 (VecSIB): Add VecSIB512.
241 (EVex): New.
242 (Masking): New.
243 (VecESize): New.
244 (Broadcast): New.
245 (StaticRounding): New.
246 (SAE): New.
247 (Disp8MemShift): New.
248 (NoDefMask): New.
249 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
250 staticrounding, sae, disp8memshift and nodefmask.
251 (RegZMM): New.
252 (Zmmword): Ditto.
253 (Vec_Disp8): Ditto.
254 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
255 fields.
256 (RegVRex): New.
257 * i386-opc.tbl: Add AVX512 instructions.
258 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
259 registers, mask registers.
260 * i386-tbl.h: Regenerate.
261
1d2db237
RS		 2622013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
263
264 PR gas/15220
265 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
266 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
267
a0046408
L		 2682013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
269
270 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
271 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
272 PREFIX_0F3ACC.
273 (prefix_table): Updated.
274 (three_byte_table): Likewise.
275 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
276 (cpu_flags): Add CpuSHA.
277 (i386_cpu_flags): Add cpusha.
278 * i386-init.h: Regenerate.
279 * i386-opc.h (CpuSHA): New.
280 (CpuUnused): Restored.
281 (i386_cpu_flags): Add cpusha.
282 * i386-opc.tbl: Add SHA instructions.
283 * i386-tbl.h: Regenerate.
284
7e8b059b
L		 2852013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
286 Kirill Yukhin <kirill.yukhin@intel.com>
287 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
288
289 * i386-dis.c (BND_Fixup): New.
290 (Ebnd): New.
291 (Ev_bnd): New.
292 (Gbnd): New.
293 (BND): New.
294 (v_bnd_mode): New.
295 (bnd_mode): New.
c623f86c
L		 296 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
297 MOD_0F1B_PREFIX_1.
298 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 299 (dis tables): Replace XX with BND for near branch and call
300 instructions.
301 (prefix_table): Add new entries.
302 (mod_table): Likewise.
303 (names_bnd): New.
304 (intel_names_bnd): New.
305 (att_names_bnd): New.
306 (BND_PREFIX): New.
307 (prefix_name): Handle BND_PREFIX.
308 (print_insn): Initialize names_bnd.
309 (intel_operand_size): Handle new modes.
310 (OP_E_register): Likewise.
311 (OP_E_memory): Likewise.
312 (OP_G): Likewise.
313 * i386-gen.c (cpu_flag_init): Add CpuMPX.
314 (cpu_flags): Add CpuMPX.
315 (operand_type_init): Add RegBND.
316 (opcode_modifiers): Add BNDPrefixOk.
317 (operand_types): Add RegBND.
318 * i386-init.h: Regenerate.
319 * i386-opc.h (CpuMPX): New.
320 (CpuUnused): Comment out.
321 (i386_cpu_flags): Add cpumpx.
322 (BNDPrefixOk): New.
323 (i386_opcode_modifier): Add bndprefixok.
324 (RegBND): New.
325 (i386_operand_type): Add regbnd.
326 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
327 Add MPX instructions and bnd prefix.
328 * i386-reg.tbl: Add bnd0-bnd3 registers.
329 * i386-tbl.h: Regenerate.
330
b56e23fb
RS		 3312013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
332
333 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
334 ATTRIBUTE_UNUSED.
335
e7ae278d
RS		 3362013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
337
338 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
339 special rules.
340 * Makefile.in: Regenerate.
341 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
342 all fields. Reformat.
343
c3c07478
RS		 3442013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
345
346 * mips16-opc.c: Include mips-formats.h.
347 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
348 static arrays.
349 (decode_mips16_operand): New function.
350 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
351 (print_insn_arg): Handle OP_ENTRY_EXIT list.
352 Abort for OP_SAVE_RESTORE_LIST.
353 (print_mips16_insn_arg): Change interface. Use mips_operand
354 structures. Delete GET_OP_S. Move GET_OP definition to...
355 (print_insn_mips16): ...here. Call init_print_arg_state.
356 Update the call to print_mips16_insn_arg.
357
ab902481
RS		 3582013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
359
360 * mips-formats.h: New file.
361 * mips-opc.c: Include mips-formats.h.
362 (reg_0_map): New static array.
363 (decode_mips_operand): New function.
364 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
365 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
366 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
367 (int_c_map): New static arrays.
368 (decode_micromips_operand): New function.
369 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
370 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
371 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
372 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
373 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
374 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
375 (micromips_imm_b_map, micromips_imm_c_map): Delete.
376 (print_reg): New function.
377 (mips_print_arg_state): New structure.
378 (init_print_arg_state, print_insn_arg): New functions.
379 (print_insn_args): Change interface and use mips_operand structures.
380 Delete GET_OP_S. Move GET_OP definition to...
381 (print_insn_mips): ...here. Update the call to print_insn_args.
382 (print_insn_micromips): Use print_insn_args.
383
cc537e56
RS		 3842013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
385
386 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
387 in macros.
388
7a5f87ce
RS		 3892013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
390
391 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
392 ADDA.S, MULA.S and SUBA.S.
393
41741fa4
L		 3942013-07-08 H.J. Lu <hongjiu.lu@intel.com>
395
396 PR gas/13572
397 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
398 * i386-tbl.h: Regenerated.
399
f2ae14a1
RS		 4002013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
401
402 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
403 and SD A(B) macros up.
404 * micromips-opc.c (micromips_opcodes): Likewise.
405
04c9d415
RS		 4062013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
407
408 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
409 instructions.
410
5c324c16
RS		 4112013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
412
413 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
414 MDMX-like instructions.
415 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
416 printing "Q" operands for INSN_5400 instructions.
417
23e69e47
RS		 4182013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
419
420 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
421 "+S" for "cins".
422 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
423 Combine cases.
424
27c5c572
RS		 4252013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
426
427 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
428 "jalx".
429 * mips16-opc.c (mips16_opcodes): Likewise.
430 * micromips-opc.c (micromips_opcodes): Likewise.
431 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
432 (print_insn_mips16): Handle "+i".
433 (print_insn_micromips): Likewise. Conditionally preserve the
434 ISA bit for "a" but not for "+i".
435
e76ff5ab
RS		 4362013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
437
438 * micromips-opc.c (WR_mhi): Rename to..
439 (WR_mh): ...this.
440 (micromips_opcodes): Update "movep" entry accordingly. Replace
441 "mh,mi" with "mh".
442 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
443 (micromips_to_32_reg_h_map1): ...this.
444 (micromips_to_32_reg_i_map): Rename to...
445 (micromips_to_32_reg_h_map2): ...this.
446 (print_micromips_insn): Remove "mi" case. Print both registers
447 in the pair for "mh".
448
fa7616a4
RS		 4492013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
450
451 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
452 * micromips-opc.c (micromips_opcodes): Likewise.
453 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
454 and "+T" handling. Check for a "0" suffix when deciding whether to
455 use coprocessor 0 names. In that case, also check for ",H" selectors.
456
fb798c50
AK		 4572013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
458
459 * s390-opc.c (J12_12, J24_24): New macros.
460 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
461 (MASK_MII_UPI): Rename to MASK_MII_UPP.
462 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
463
58ae08f2
AM		 4642013-07-04 Alan Modra <amodra@gmail.com>
465
466 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
467
b5e04c2b
NC		 4682013-06-26 Nick Clifton <nickc@redhat.com>
469
470 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
471 field when checking for type 2 nop.
472 * rx-decode.c: Regenerate.
473
833794fc
MR		 4742013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
475
476 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
477 and "movep" macros.
478
1bbce132
MR		 4792013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
480
481 * mips-dis.c (is_mips16_plt_tail): New function.
482 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
483 word.
484 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
485
34c911a4
NC		 4862013-06-21 DJ Delorie <dj@redhat.com>
487
488 * msp430-decode.opc: New.
489 * msp430-decode.c: New/generated.
490 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
491 (MAINTAINER_CLEANFILES): Likewise.
492 Add rule to build msp430-decode.c frommsp430decode.opc
493 using the opc2c program.
494 * Makefile.in: Regenerate.
495 * configure.in: Add msp430-decode.lo to msp430 architecture files.
496 * configure: Regenerate.
497
b9eead84
YZ		 4982013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
499
500 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
501 (SYMTAB_AVAILABLE): Removed.
502 (#include "elf/aarch64.h): Ditto.
503
7f3c4072
CM		 5042013-06-17 Catherine Moore <clm@codesourcery.com>
505 Maciej W. Rozycki <macro@codesourcery.com>
506 Chao-Ying Fu <fu@mips.com>
507
508 * micromips-opc.c (EVA): Define.
509 (TLBINV): Define.
510 (micromips_opcodes): Add EVA opcodes.
511 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
512 (print_insn_args): Handle EVA offsets.
513 (print_insn_micromips): Likewise.
514 * mips-opc.c (EVA): Define.
515 (TLBINV): Define.
516 (mips_builtin_opcodes): Add EVA opcodes.
517
de40ceb6
AM		 5182013-06-17 Alan Modra <amodra@gmail.com>
519
520 * Makefile.am (mips-opc.lo): Add rules to create automatic
521 dependency files. Pass archdefs.
522 (micromips-opc.lo, mips16-opc.lo): Likewise.
523 * Makefile.in: Regenerate.
524
3531d549
DD		 5252013-06-14 DJ Delorie <dj@redhat.com>
526
527 * rx-decode.opc (rx_decode_opcode): Bit operations on
528 registers are 32-bit operations, not 8-bit operations.
529 * rx-decode.c: Regenerate.
530
ba92f7fb
CF		 5312013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
532
533 * micromips-opc.c (IVIRT): New define.
534 (IVIRT64): New define.
535 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
536 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
537
538 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
539 dmtgc0 to print cp0 names.
540
9daf7bab
SL		 5412013-06-09 Sandra Loosemore <sandra@codesourcery.com>
542
543 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
544 argument.
545
d301a56b
RS		 5462013-06-08 Catherine Moore <clm@codesourcery.com>
547 Richard Sandiford <rdsandiford@googlemail.com>
548
549 * micromips-opc.c (D32, D33, MC): Update definitions.
550 (micromips_opcodes): Initialize ase field.
551 * mips-dis.c (mips_arch_choice): Add ase field.
552 (mips_arch_choices): Initialize ase field.
553 (set_default_mips_dis_options): Declare and setup mips_ase.
554 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
555 MT32, MC): Update definitions.
556 (mips_builtin_opcodes): Initialize ase field.
557
a3dcb6c5
RS		 5582013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
559
560 * s390-opc.txt (flogr): Require a register pair destination.
561
6cf1d90c
AK		 5622013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
563
564 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
565 instruction format.
566
c77c0862
RS		 5672013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
568
569 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
570
c0637f3a
PB		 5712013-05-20 Peter Bergner <bergner@vnet.ibm.com>
572
573 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
574 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
575 XLS_MASK, PPCVSX2): New defines.
576 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
577 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
578 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
579 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
580 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
581 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
582 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
583 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
584 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
585 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
586 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
587 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
588 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
589 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
590 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
591 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
592 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
593 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
594 <lxvx, stxvx>: New extended mnemonics.
595
4934fdaf
AM		 5962013-05-17 Alan Modra <amodra@gmail.com>
597
598 * ia64-raw.tbl: Replace non-ASCII char.
599 * ia64-waw.tbl: Likewise.
600 * ia64-asmtab.c: Regenerate.
601
6091d651
SE		 6022013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
603
604 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
605 * i386-init.h: Regenerated.
606
d2865ed3
YZ		 6072013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
608
609 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
610 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
611 check from [0, 255] to [-128, 255].
612
b015e599
AP		 6132013-05-09 Andrew Pinski <apinski@cavium.com>
614
615 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
616 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
617 (parse_mips_dis_option): Handle the virt option.
618 (print_insn_args): Handle "+J".
619 (print_mips_disassembler_options): Print out message about virt64.
620 * mips-opc.c (IVIRT): New define.
621 (IVIRT64): New define.
622 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
623 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
624 Move rfe to the bottom as it conflicts with tlbgp.
625
9f0682fe
AM		 6262013-05-09 Alan Modra <amodra@gmail.com>
627
628 * ppc-opc.c (extract_vlesi): Properly sign extend.
629 (extract_vlensi): Likewise. Comment reason for setting invalid.
630
13761a11
NC		 6312013-05-02 Nick Clifton <nickc@redhat.com>
632
633 * msp430-dis.c: Add support for MSP430X instructions.
634
e3031850
SL		 6352013-04-24 Sandra Loosemore <sandra@codesourcery.com>
636
637 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
638 to "eccinj".
639
17310e56
NC		 6402013-04-17 Wei-chen Wang <cole945@gmail.com>
641
642 PR binutils/15369
643 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
644 of CGEN_CPU_ENDIAN.
645 (hash_insns_list): Likewise.
646
731df338
JK		 6472013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
648
649 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
650 warning workaround.
651
5f77db52
JB		 6522013-04-08 Jan Beulich <jbeulich@suse.com>
653
654 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
655 * i386-tbl.h: Re-generate.
656
0afd1215
DM		 6572013-04-06 David S. Miller <davem@davemloft.net>
658
659 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
660 of an opcode, prefer the one with F_PREFERRED set.
661 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
662 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
663 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
664 mark existing mnenomics as aliases. Add "cc" suffix to edge
665 instructions generating condition codes, mark existing mnenomics
666 as aliases. Add "fp" prefix to VIS compare instructions, mark
667 existing mnenomics as aliases.
668
41702d50
NC		 6692013-04-03 Nick Clifton <nickc@redhat.com>
670
671 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
672 destination address by subtracting the operand from the current
673 address.
674 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
675 a positive value in the insn.
676 (extract_u16_loop): Do not negate the returned value.
677 (D16_LOOP): Add V850_INVERSE_PCREL flag.
678
679 (ceilf.sw): Remove duplicate entry.
680 (cvtf.hs): New entry.
681 (cvtf.sh): Likewise.
682 (fmaf.s): Likewise.
683 (fmsf.s): Likewise.
684 (fnmaf.s): Likewise.
685 (fnmsf.s): Likewise.
686 (maddf.s): Restrict to E3V5 architectures.
687 (msubf.s): Likewise.
688 (nmaddf.s): Likewise.
689 (nmsubf.s): Likewise.
690
55cf16e1
L		 6912013-03-27 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
694 check address mode.
695 (print_insn): Pass sizeflag to get_sib.
696
51dcdd4d
NC		 6972013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
698
699 PR binutils/15068
700 * tic6x-dis.c: Add support for displaying 16-bit insns.
701
795b8e6b
NC		 7022013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
703
704 PR gas/15095
705 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
706 individual msb and lsb halves in src1 & src2 fields. Discard the
707 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
708 follow what Ti SDK does in that case as any value in the src1
709 field yields the same output with SDK disassembler.
710
314d60dd
ME		 7112013-03-12 Michael Eager <eager@eagercon.com>
712
795b8e6b 713 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 714
dad60f8e
SL		 7152013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
716
717 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
718
f5cb796a
SL		 7192013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
720
721 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
722
21fde85c
SL		 7232013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
724
725 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
726
dd5181d5
KT		 7272013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
728
729 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
730 (thumb32_opcodes): Likewise.
731 (print_insn_thumb32): Handle 'S' control char.
732
87a8d6cb
NC		 7332013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
734
735 * lm32-desc.c: Regenerate.
736
99dce992
L		 7372013-03-01 H.J. Lu <hongjiu.lu@intel.com>
738
739 * i386-reg.tbl (riz): Add RegRex64.
740 * i386-tbl.h: Regenerated.
741
e60bb1dd
YZ		 7422013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
743
744 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
745 (aarch64_feature_crc): New static.
746 (CRC): New macro.
747 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
748 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
749 * aarch64-asm-2.c: Re-generate.
750 * aarch64-dis-2.c: Ditto.
751 * aarch64-opc-2.c: Ditto.
752
c7570fcd
AM		 7532013-02-27 Alan Modra <amodra@gmail.com>
754
755 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
756 * rl78-decode.c: Regenerate.
757
151fa98f
NC		 7582013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
759
760 * rl78-decode.opc: Fix encoding of DIVWU insn.
761 * rl78-decode.c: Regenerate.
762
5c111e37
L		 7632013-02-19 H.J. Lu <hongjiu.lu@intel.com>
764
765 PR gas/15159
766 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
767
768 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
769 (cpu_flags): Add CpuSMAP.
770
771 * i386-opc.h (CpuSMAP): New.
772 (i386_cpu_flags): Add cpusmap.
773
774 * i386-opc.tbl: Add clac and stac.
775
776 * i386-init.h: Regenerated.
777 * i386-tbl.h: Likewise.
778
9d1df426
NC		 7792013-02-15 Markos Chandras <markos.chandras@imgtec.com>
780
781 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
782 which also makes the disassembler output be in little
783 endian like it should be.
784
a1ccaec9
YZ		 7852013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
786
787 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
788 fields to NULL.
789 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
790
ef068ef4 7912013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 792
793 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
794 section disassembled.
795
6fe6ded9
RE		 7962013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
797
798 * arm-dis.c: Update strht pattern.
799
0aa27725
RS		 8002013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
801
802 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
803 single-float. Disable ll, lld, sc and scd for EE. Disable the
804 trunc.w.s macro for EE.
805
36591ba1
SL		 8062013-02-06 Sandra Loosemore <sandra@codesourcery.com>
807 Andrew Jenner <andrew@codesourcery.com>
808
809 Based on patches from Altera Corporation.
810
811 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
812 nios2-opc.c.
813 * Makefile.in: Regenerated.
814 * configure.in: Add case for bfd_nios2_arch.
815 * configure: Regenerated.
816 * disassemble.c (ARCH_nios2): Define.
817 (disassembler): Add case for bfd_arch_nios2.
818 * nios2-dis.c: New file.
819 * nios2-opc.c: New file.
820
545093a4
AM		 8212013-02-04 Alan Modra <amodra@gmail.com>
822
823 * po/POTFILES.in: Regenerate.
824 * rl78-decode.c: Regenerate.
825 * rx-decode.c: Regenerate.
826
e30181a5
YZ		 8272013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
828
829 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
830 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
831 * aarch64-asm.c (convert_xtl_to_shll): New function.
832 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
833 calling convert_xtl_to_shll.
834 * aarch64-dis.c (convert_shll_to_xtl): New function.
835 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
836 calling convert_shll_to_xtl.
837 * aarch64-gen.c: Update copyright year.
838 * aarch64-asm-2.c: Re-generate.
839 * aarch64-dis-2.c: Re-generate.
840 * aarch64-opc-2.c: Re-generate.
841
78c8d46c
NC		 8422013-01-24 Nick Clifton <nickc@redhat.com>
843
844 * v850-dis.c: Add support for e3v5 architecture.
845 * v850-opc.c: Likewise.
846
f5555712
YZ		 8472013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
848
849 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
850 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
851 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 852 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 853 alignment check; change to call set_sft_amount_out_of_range_error
854 instead of set_imm_out_of_range_error.
855 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
856 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
857 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
858 SIMD_IMM_SFT.
859
2f81ff92
L		 8602013-01-16 H.J. Lu <hongjiu.lu@intel.com>
861
862 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
863
864 * i386-init.h: Regenerated.
865 * i386-tbl.h: Likewise.
866
dd42f060
NC		 8672013-01-15 Nick Clifton <nickc@redhat.com>
868
869 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
870 values.
871 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
872
a4533ed8
NC		 8732013-01-14 Will Newton <will.newton@imgtec.com>
874
875 * metag-dis.c (REG_WIDTH): Increase to 64.
876
5817ffd1
PB		 8772013-01-10 Peter Bergner <bergner@vnet.ibm.com>
878
879 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
880 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
881 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
882 (SH6): Update.
883 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
884 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
885 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
886 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
887
a3c62988
NC		 8882013-01-10 Will Newton <will.newton@imgtec.com>
889
890 * Makefile.am: Add Meta.
891 * configure.in: Add Meta.
892 * disassemble.c: Add Meta support.
893 * metag-dis.c: New file.
894 * Makefile.in: Regenerate.
895 * configure: Regenerate.
896
73335eae
NC		 8972013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
898
899 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
900 (match_opcode): Rename to cr16_match_opcode.
901
e407c74b
NC		 9022013-01-04 Juergen Urban <JuergenUrban@gmx.de>
903
904 * mips-dis.c: Add names for CP0 registers of r5900.
905 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
906 instructions sq and lq.
907 Add support for MIPS r5900 CPU.
908 Add support for 128 bit MMI (Multimedia Instructions).
909 Add support for EE instructions (Emotion Engine).
910 Disable unsupported floating point instructions (64 bit and
911 undefined compare operations).
912 Enable instructions of MIPS ISA IV which are supported by r5900.
913 Disable 64 bit co processor instructions.
914 Disable 64 bit multiplication and division instructions.
915 Disable instructions for co-processor 2 and 3, because these are
916 not supported (preparation for later VU0 support (Vector Unit)).
917 Disable cvt.w.s because this behaves like trunc.w.s and the
918 correct execution can't be ensured on r5900.
919 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
920 will confuse less developers and compilers.
921
a32c3ff8
NC		 9222013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
923
fb098a1e
YZ		 924 * aarch64-opc.c (aarch64_print_operand): Change to print
925 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
926 in comment.
927 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
928 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
929 OP_MOV_IMM_WIDE.
930
9312013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
932
933 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
934 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 935
62658407
L		 9362013-01-02 H.J. Lu <hongjiu.lu@intel.com>
937
938 * i386-gen.c (process_copyright): Update copyright year to 2013.
939
bab4becb 9402013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 941
bab4becb
NC		 942 * cr16-dis.c (match_opcode,make_instruction): Remove static
943 declaration.
944 (dwordU,wordU): Moved typedefs to opcode/cr16.h
945 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 946
bab4becb 947For older changes see ChangeLog-2012
252b5132 948\f
bab4becb 949Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 950
951Copying and distribution of this file, with or without modification,
952are permitted in any medium without royalty provided the copyright
953notice and this notice are preserved.
954
252b5132 955Local Variables:
2f6d2f85
NC		 956mode: change-log
957left-margin: 8
958fill-column: 74
252b5132
RH		 959version-control: never
960End:
GDB Binutils - Deliverables
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