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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ab4437c3
PB		 12012-10-22 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
4
9a176a4a
TT		 52012-10-18 Tom Tromey <tromey@redhat.com>
6
7 * tic54x-dis.c (print_instruction): Don't use K&R style.
8 (print_parallel_instruction, sprint_dual_address)
9 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
10 (sprint_cc2, sprint_condition): Likewise.
11
4ad3b7ef
KT		 122012-10-18 Kai Tietz <ktietz@redhat.com>
13
14 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
15 value with a default.
16 (do_special_encoding): Likewise.
17 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
18 variables with default.
19 * arc-dis.c (write_comments_): Don't use strncat due
20 size of state->commentBuffer pointer isn't predictable.
21
b7a54b55
YZ		 222012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
23
24 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
25 rmr_el3; remove daifset and daifclr.
26
9b61754a
YZ		 272012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
28
29 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
30 the alignment of addr.offset.imm instead of that of shifter.amount for
31 operand type AARCH64_OPND_ADDR_UIMM12.
32
f8ece37f
RE		 332012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
34
35 * arm-dis.c: Use preferred form of vrint instruction variants
36 for disassembly.
37
5e5c50d3
NE		 382012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
39
40 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
41 * i386-init.h: Regenerated.
42
c7a5aa9c
PB		 432012-10-05 Peter Bergner <bergner@vnet.ibm.com>
44
45 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
46 * ppc-opc.c (VBA): New define.
47 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
48 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
49
04ee5257
NC		 502012-10-04 Nick Clifton <nickc@redhat.com>
51
52 * v850-dis.c (disassemble): Place square parentheses around second
53 register operand of clr1, not1, set1 and tst1 instructions.
54
cfc72779
AK		 552012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
56
57 * s390-mkopc.c: Support new option zEC12.
58 * s390-opc.c: Add new instruction formats.
59 * s390-opc.txt: Add new instructions for zEC12.
60
1415a2a7
AG		 612012-09-27 Anthony Green <green@moxielogic.com>
62
63 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
64 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
65
160a30bb
L		 662012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
67
04ee5257
NC		 68 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
69 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 70 and CPU_BTVER2_FLAGS.
71 * i386-init.h: Regenerated.
72
60aa667e
L		 732012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
74
75 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
76 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
77 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
78 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
79 (cpu_flags): Add CpuCX16.
80 * i386-opc.h (CpuCX16): New.
81 (i386_cpu_flags): Add cpucx16.
82 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
83 * i386-tbl.h: Regenerate.
84 * i386-init.h: Likewise.
85
4b8c8c02
RE		 862012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
87
60aa667e 88 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 89 to lda and stl-form.
90
83ea18d0
MR		 912012-09-18 Chao-ying Fu <fu@mips.com>
92
93 * micromips-opc.c (micromips_opcodes): Correct the encoding of
94 the "swxc1" instruction.
95
062f38fa
RE		 962012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
97
98 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
99 the parameter 'inst'.
100 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
101 (convert_mov_to_movewide): Change to assert (0) when
102 aarch64_wide_constant_p returns FALSE.
103
b132a67d
DE		 1042012-09-14 David Edelsohn <dje.gcc@gmail.com>
105
106 * configure: Regenerate.
107
1f9b75dd
AG		 1082012-09-14 Anthony Green <green@moxielogic.com>
109
110 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
111 the address after the branch instruction.
112
e202fa84
AG		 1132012-09-13 Anthony Green <green@moxielogic.com>
114
115 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
116
00716ab1
AM		 1172012-09-10 Matthias Klose <doko@ubuntu.com>
118
119 * config.in: Disable sanity check for kfreebsd.
120
6d2920c8
L		 1212012-09-10 H.J. Lu <hongjiu.lu@intel.com>
122
123 * configure: Regenerated.
124
b3e14eda
L		 1252012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
126
127 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
128 * ia64-gen.c: Promote completer index type to longlong.
129 (irf_operand): Add new register recognition.
130 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
131 (lookup_specifier): Add new resource recognition.
132 (insert_bit_table_ent): Relax abort condition according to the
133 changed completer index type.
134 (print_dis_table): Fix printf format for completer index.
135 * ia64-ic.tbl: Add a new instruction class.
136 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
137 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
138 * ia64-opc.h: Define short names for new operand types.
139 * ia64-raw.tbl: Add new RAW resource for DAHR register.
140 * ia64-waw.tbl: Add new WAW resource for DAHR register.
141 * ia64-asmtab.c: Regenerate.
142
382c72e9
PB		 1432012-08-29 Peter Bergner <bergner@vnet.ibm.com>
144
145 * ppc-opc.c (VXASHB_MASK): New define.
146 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
147
fb048c26
PB		 1482012-08-28 Peter Bergner <bergner@vnet.ibm.com>
149
150 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
151 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
152 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
153 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
154 vupklsh>: Use VXVA_MASK.
155 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
156 <mfvscr>: Use VXVAVB_MASK.
157 <mtvscr>: Use VXVDVA_MASK.
158 <vspltb>: Use VXUIMM4_MASK.
159 <vsplth>: Use VXUIMM3_MASK.
160 <vspltw>: Use VXUIMM2_MASK.
161
3c9017d2
MGD		 1622012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
163
164 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
165
48adcd8e
MGD		 1662012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
167
168 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
169
4f51b4bd
MGD		 1702012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
171
172 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
173
91ff7894
MGD		 1742012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
175
176 * arm-dis.c (neon_opcodes): Add support for AES instructions.
177
c70a8987
MGD		 1782012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
179
180 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
181 conversions.
182
30bdf752
MGD		 1832012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
184
185 * arm-dis.c (coprocessor_opcodes): Add VRINT.
186 (neon_opcodes): Likewise.
187
7e8e6784
MGD		 1882012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
189
190 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
191 variants.
192 (neon_opcodes): Likewise.
193
73924fbc
MGD		 1942012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
195
196 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
197 (neon_opcodes): Likewise.
198
33399f07
MGD		 1992012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
200
201 * arm-dis.c (coprocessor_opcodes): Add VSEL.
202 (print_insn_coprocessor): Add new %<>c bitfield format
203 specifier.
204
9eb6c0f1
MGD		 2052012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
206
207 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
208 (thumb32_opcodes): Likewise.
209 (print_arm_insn): Add support for %<>T formatter.
210
8884b720
MGD		 2112012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
212
213 * arm-dis.c (arm_opcodes): Add HLT.
214 (thumb_opcodes): Likewise.
215
b79f7053
MGD		 2162012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
217
218 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
219
53c4b28b
MGD		 2202012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
221
222 * arm-dis.c (arm_opcodes): Add SEVL.
223 (thumb_opcodes): Likewise.
224 (thumb32_opcodes): Likewise.
225
e797f7e0
MGD		 2262012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
227
228 * arm-dis.c (data_barrier_option): New function.
229 (print_insn_arm): Use data_barrier_option.
230 (print_insn_thumb32): Use data_barrier_option.
231
e2efe87d
MGD		 2322012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
233
234 * arm-dis.c (COND_UNCOND): New constant.
235 (print_insn_coprocessor): Add support for %u format specifier.
236 (print_insn_neon): Likewise.
237
2c63854f
DM		 2382012-08-21 David S. Miller <davem@davemloft.net>
239
240 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
241 F3F4 macro.
242
e67ed0e8
AM		 2432012-08-20 Edmar Wienskoski <edmar@freescale.com>
244
245 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
246 vabsduh, vabsduw, mviwsplt.
247
7b458c12
L		 2482012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
249
250 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
251 CPU_BTVER2_FLAGS.
252
e67ed0e8 253 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 254
255 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
256 * i386-init.h: Regenerated.
257 * i386-tbl.h: Likewise.
258
eb80cb87
NC		 2592012-08-17 Nick Clifton <nickc@redhat.com>
260
261 * po/uk.po: New Ukranian translation.
262 * configure.in (ALL_LINGUAS): Add uk.
263 * configure: Regenerate.
264
8baf7b78
PB		 2652012-08-16 Peter Bergner <bergner@vnet.ibm.com>
266
267 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
268 RBX for the third operand.
269 <"lswi">: Use RAX for second and NBI for the third operand.
270
3d557b4c
DD		 2712012-08-15 DJ Delorie <dj@redhat.com>
272
273 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
274 operands, so that data addresses can be corrected when not
275 ES-overridden.
276 * rl78-decode.c: Regenerate.
277 * rl78-dis.c (print_insn_rl78): Make order of modifiers
278 irrelevent. When the 'e' specifier is used on an operand and no
279 ES prefix is provided, adjust address to make it absolute.
280
588925d0
PB		 2812012-08-15 Peter Bergner <bergner@vnet.ibm.com>
282
283 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
284
9f6a6cc0
PB		 2852012-08-15 Peter Bergner <bergner@vnet.ibm.com>
286
287 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
288
fc8c4fd1
MR		 2892012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
290
291 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
292 macros, use local variables for info struct member accesses,
293 update the type of the variable used to hold the instruction
294 word.
295 (print_insn_mips, print_mips16_insn_arg): Likewise.
296 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
297 local variables for info struct member accesses.
298 (print_insn_micromips): Add GET_OP_S local macro.
299 (_print_insn_mips): Update the type of the variable used to hold
300 the instruction word.
301
a06ea964 3022012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 303 Laurent Desnogues <laurent.desnogues@arm.com>
304 Jim MacArthur <jim.macarthur@arm.com>
305 Marcus Shawcroft <marcus.shawcroft@arm.com>
306 Nigel Stephens <nigel.stephens@arm.com>
307 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
308 Richard Earnshaw <rearnsha@arm.com>
309 Sofiane Naci <sofiane.naci@arm.com>
310 Tejas Belagod <tejas.belagod@arm.com>
311 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 312
313 * Makefile.am: Add AArch64.
314 * Makefile.in: Regenerate.
315 * aarch64-asm.c: New file.
316 * aarch64-asm.h: New file.
317 * aarch64-dis.c: New file.
318 * aarch64-dis.h: New file.
319 * aarch64-gen.c: New file.
320 * aarch64-opc.c: New file.
321 * aarch64-opc.h: New file.
322 * aarch64-tbl.h: New file.
323 * configure.in: Add AArch64.
324 * configure: Regenerate.
325 * disassemble.c: Add AArch64.
326 * aarch64-asm-2.c: New file (automatically generated).
327 * aarch64-dis-2.c: New file (automatically generated).
328 * aarch64-opc-2.c: New file (automatically generated).
329 * po/POTFILES.in: Regenerate.
330
35d0a169
MR		 3312012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
332
333 * micromips-opc.c (micromips_opcodes): Update comment.
334 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
335 instructions for IOCT as appropriate.
336 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
337 opcode_is_member.
338 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
339 the result of a check for the -Wno-missing-field-initializers
340 GCC option.
341 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
342 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
343 compilation.
344 (mips16-opc.lo): Likewise.
345 (micromips-opc.lo): Likewise.
346 * aclocal.m4: Regenerate.
347 * configure: Regenerate.
348 * Makefile.in: Regenerate.
349
5c5acbbd
L		 3502012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
351
352 PR gas/14423
353 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
354 * i386-init.h: Regenerated.
355
3c892704
NC		 3562012-08-09 Nick Clifton <nickc@redhat.com>
357
358 * po/vi.po: Updated Vietnamese translation.
359
d7189fa5
RM		 3602012-08-07 Roland McGrath <mcgrathr@google.com>
361
362 * i386-dis.c (reg_table): Fill out REG_0F0D table with
363 AMD-reserved cases as "prefetch".
364 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
365 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
366 (reg_table): Use those under REG_0F18.
367 (mod_table): Add those cases as "nop/reserved".
368
4c692bc7
JB		 3692012-08-07 Jan Beulich <jbeulich@suse.com>
370
371 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
372
de882298
RM		 3732012-08-06 Roland McGrath <mcgrathr@google.com>
374
375 * i386-dis.c (print_insn): Print spaces between multiple excess
376 prefixes. Return actual number of excess prefixes consumed,
377 not always one.
378
379 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
380
7bb15c6f
RM		 3812012-08-06 Roland McGrath <mcgrathr@google.com>
382 Victor Khimenko <khim@google.com>
383 H.J. Lu <hongjiu.lu@intel.com>
384
385 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
386 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
387 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
388 (OP_E_register): Likewise.
389 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
390
3843081d
JBG		 3912012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
392
393 * configure.in: Formatting.
394 * configure: Regenerate.
395
48891606
AM		 3962012-08-01 Alan Modra <amodra@gmail.com>
397
398 * h8300-dis.c: Fix printf arg warnings.
399 * i960-dis.c: Likewise.
400 * mips-dis.c: Likewise.
401 * pdp11-dis.c: Likewise.
402 * sh-dis.c: Likewise.
403 * v850-dis.c: Likewise.
404 * configure.in: Formatting.
405 * configure: Regenerate.
406 * rl78-decode.c: Regenerate.
407 * po/POTFILES.in: Regenerate.
408
03f66e8a 4092012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 410 Catherine Moore <clm@codesourcery.com>
411 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 412
413 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
414 (DSP_VOLA): Likewise.
415 (D32, D33): Likewise.
416 (micromips_opcodes): Add DSP ASE instructions.
48891606 417 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 418 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
419
94948e64
JB		 4202012-07-31 Jan Beulich <jbeulich@suse.com>
421
422 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
423 instruction group. Mark as requiring AVX2.
424 * i386-tbl.h: Re-generate.
425
a6dc81d2
NC		 4262012-07-30 Nick Clifton <nickc@redhat.com>
427
428 * po/opcodes.pot: Updated template.
429 * po/es.po: Updated Spanish translation.
430 * po/fi.po: Updated Finnish translation.
431
c4dd807e
MF		 4322012-07-27 Mike Frysinger <vapier@gentoo.org>
433
434 * configure.in (BFD_VERSION): Run bfd/configure --version and
435 parse the output of that.
436 * configure: Regenerate.
437
03edbe3b
JL		 4382012-07-25 James Lemke <jwlemke@codesourcery.com>
439
440 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
441
63d08c68
NC		 4422012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
443 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 444
445 PR binutils/13135
446 * arm-dis.c: Add necessary casts for printing integer values.
447 Use %s when printing string values.
448 * hppa-dis.c: Likewise.
449 * m68k-dis.c: Likewise.
450 * microblaze-dis.c: Likewise.
451 * mips-dis.c: Likewise.
452 * sparc-dis.c: Likewise.
453
ff688e1f
L		 4542012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
455
456 PR binutils/14355
457 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
458 (VEX_LEN_0FXOP_08_CD): Likewise.
459 (VEX_LEN_0FXOP_08_CE): Likewise.
460 (VEX_LEN_0FXOP_08_CF): Likewise.
461 (VEX_LEN_0FXOP_08_EC): Likewise.
462 (VEX_LEN_0FXOP_08_ED): Likewise.
463 (VEX_LEN_0FXOP_08_EE): Likewise.
464 (VEX_LEN_0FXOP_08_EF): Likewise.
465 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
466 vpcomub, vpcomuw, vpcomud, vpcomuq.
467 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
468 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
469 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
470 VEX_LEN_0FXOP_08_EF.
471
e2e1fcde
L		 4722012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
473
474 * i386-dis.c (PREFIX_0F38F6): New.
475 (prefix_table): Add adcx, adox instructions.
476 (three_byte_table): Use PREFIX_0F38F6.
477 (mod_table): Add rdseed instruction.
478 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
479 (cpu_flags): Likewise.
480 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
481 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
482 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
483 prefetchw.
484 * i386-tbl.h: Regenerate.
485 * i386-init.h: Likewise.
486
8b99bf0b
TS		 4872012-07-05 Thomas Schwinge <thomas@codesourcery.com>
488
f4263ca2 489 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 490
416cf80a
SK		 4912012-07-05 Sean Keys <skeys@ipdatasys.com>
492
493 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 494 always be false due to overlapping operand masks.
495 * xgate-opc.c: Corrected 'com' opcode entry and
496 fixed spacing.
416cf80a 497
9fa0f14a
RM		 4982012-07-02 Roland McGrath <mcgrathr@google.com>
499
500 * i386-opc.tbl: Add RepPrefixOk to nop.
501 * i386-tbl.h: Regenerate.
502
4c6a93d3
NC		 5032012-06-28 Nick Clifton <nickc@redhat.com>
504
505 * po/vi.po: Updated Vietnamese translation.
506
29c048b6
RM		 5072012-06-22 Roland McGrath <mcgrathr@google.com>
508
fe13e45b
RM		 509 * i386-opc.tbl: Add RepPrefixOk to ret.
510 * i386-tbl.h: Regenerate.
511
29c048b6
RM		 512 * i386-opc.h (RepPrefixOk): New enum constant.
513 (i386_opcode_modifier): New bitfield 'repprefixok'.
514 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
515 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
516 instructions that have IsString.
517 * i386-tbl.h: Regenerate.
518
c7a8dbf9
AS		 5192012-06-11 Andreas Schwab <schwab@linux-m68k.org>
520
521 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
522 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
523 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
524 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
525 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
526 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
527 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
528 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
529 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
530
94caa966
AM		 5312012-05-19 Alan Modra <amodra@gmail.com>
532
533 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
534 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
535
5eb3690e
AM		 5362012-05-18 Alan Modra <amodra@gmail.com>
537
71fe7bab
AM		 538 * ia64-opc.c: Remove #include "ansidecl.h".
539 * z8kgen.c: Include sysdep.h first.
540
5eb3690e
AM		 541 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
542 * bfin-dis.c: Likewise.
543 * i860-dis.c: Likewise.
544 * ia64-dis.c: Likewise.
545 * ia64-gen.c: Likewise.
546 * m68hc11-dis.c: Likewise.
547 * mmix-dis.c: Likewise.
548 * msp430-dis.c: Likewise.
549 * or32-dis.c: Likewise.
550 * rl78-dis.c: Likewise.
551 * rx-dis.c: Likewise.
552 * tic4x-dis.c: Likewise.
553 * tilegx-opc.c: Likewise.
554 * tilepro-opc.c: Likewise.
555 * rx-decode.c: Regenerate.
556
a4ebc835
AM		 5572012-05-17 James Lemke <jwlemke@codesourcery.com>
558
559 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
560
98c76446
AM		 5612012-05-17 James Lemke <jwlemke@codesourcery.com>
562
563 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
564
df7b86aa
NC		 5652012-05-17 Daniel Richard G. <skunk@iskunk.org>
566 Nick Clifton <nickc@redhat.com>
567
568 PR 14072
569 * configure.in: Add check that sysdep.h has been included before
570 any system header files.
571 * configure: Regenerate.
572 * config.in: Regenerate.
573 * sysdep.h: Generate an error if included before config.h.
574 * alpha-opc.c: Include sysdep.h before any other header file.
575 * alpha-dis.c: Likewise.
576 * avr-dis.c: Likewise.
577 * cgen-opc.c: Likewise.
578 * cr16-dis.c: Likewise.
579 * cris-dis.c: Likewise.
580 * crx-dis.c: Likewise.
581 * d10v-dis.c: Likewise.
582 * d10v-opc.c: Likewise.
583 * d30v-dis.c: Likewise.
584 * d30v-opc.c: Likewise.
585 * h8500-dis.c: Likewise.
586 * i370-dis.c: Likewise.
587 * i370-opc.c: Likewise.
588 * m10200-dis.c: Likewise.
589 * m10300-dis.c: Likewise.
590 * micromips-opc.c: Likewise.
591 * mips-opc.c: Likewise.
592 * mips61-opc.c: Likewise.
593 * moxie-dis.c: Likewise.
594 * or32-opc.c: Likewise.
595 * pj-dis.c: Likewise.
596 * ppc-dis.c: Likewise.
597 * ppc-opc.c: Likewise.
598 * s390-dis.c: Likewise.
599 * sh-dis.c: Likewise.
600 * sh64-dis.c: Likewise.
601 * sparc-dis.c: Likewise.
602 * sparc-opc.c: Likewise.
603 * spu-dis.c: Likewise.
604 * tic30-dis.c: Likewise.
605 * tic54x-dis.c: Likewise.
606 * tic80-dis.c: Likewise.
607 * tic80-opc.c: Likewise.
608 * tilegx-dis.c: Likewise.
609 * tilepro-dis.c: Likewise.
610 * v850-dis.c: Likewise.
611 * v850-opc.c: Likewise.
612 * vax-dis.c: Likewise.
613 * w65-dis.c: Likewise.
614 * xgate-dis.c: Likewise.
615 * xtensa-dis.c: Likewise.
616 * rl78-decode.opc: Likewise.
617 * rl78-decode.c: Regenerate.
618 * rx-decode.opc: Likewise.
619 * rx-decode.c: Regenerate.
620
e1dad58d
AM		 6212012-05-17 Alan Modra <amodra@gmail.com>
622
623 * ppc_dis.c: Don't include elf/ppc.h.
624
101af531
NC		 6252012-05-16 Meador Inge <meadori@codesourcery.com>
626
627 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
628 to PUSH/POP {reg}.
629
6927f982
NC		 6302012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
631 Stephane Carrez <stcarrez@nerim.fr>
632
633 * configure.in: Add S12X and XGATE co-processor support to m68hc11
634 target.
635 * disassemble.c: Likewise.
636 * configure: Regenerate.
637 * m68hc11-dis.c: Make objdump output more consistent, use hex
638 instead of decimal and use 0x prefix for hex.
639 * m68hc11-opc.c: Add S12X and XGATE opcodes.
640
b9c361e0
JL		 6412012-05-14 James Lemke <jwlemke@codesourcery.com>
642
643 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
644 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
645 (vle_opcd_indices): New array.
646 (lookup_vle): New function.
647 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
648 (print_insn_powerpc): Likewise.
649 * ppc-opc.c: Likewise.
650
6512012-05-14 Catherine Moore <clm@codesourcery.com>
652 Maciej W. Rozycki <macro@codesourcery.com>
653 Rhonda Wittels <rhonda@codesourcery.com>
654 Nathan Froyd <froydnj@codesourcery.com>
655
656 * ppc-opc.c (insert_arx, extract_arx): New functions.
657 (insert_ary, extract_ary): New functions.
658 (insert_li20, extract_li20): New functions.
659 (insert_rx, extract_rx): New functions.
660 (insert_ry, extract_ry): New functions.
661 (insert_sci8, extract_sci8): New functions.
662 (insert_sci8n, extract_sci8n): New functions.
663 (insert_sd4h, extract_sd4h): New functions.
664 (insert_sd4w, extract_sd4w): New functions.
665 (insert_vlesi, extract_vlesi): New functions.
666 (insert_vlensi, extract_vlensi): New functions.
667 (insert_vleui, extract_vleui): New functions.
668 (insert_vleil, extract_vleil): New functions.
669 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
670 (BI16, BI32, BO32, B8): New.
671 (B15, B24, CRD32, CRS): New.
672 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
673 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
674 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
675 (SH6_MASK): Use PPC_OPSHIFT_INV.
676 (SI8, UI5, OIMM5, UI7, BO16): New.
677 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
678 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
679 (ALLOW8_SPRG): New.
680 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
681 (OPVUP, OPVUP_MASK OPVUP): New
682 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
683 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
684 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
685 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
686 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
687 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
688 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
689 (SE_IM5, SE_IM5_MASK): New.
690 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
691 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
692 (BO32DNZ, BO32DZ): New.
693 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
694 (PPCVLE): New.
695 (powerpc_opcodes): Add new VLE instructions. Update existing
696 instruction to include PPCVLE if supported.
697 * ppc-dis.c (ppc_opts): Add vle entry.
698 (get_powerpc_dialect): New function.
699 (powerpc_init_dialect): VLE support.
700 (print_insn_big_powerpc): Call get_powerpc_dialect.
701 (print_insn_little_powerpc): Likewise.
702 (operand_value_powerpc): Handle negative shift counts.
703 (print_insn_powerpc): Handle 2-byte instruction lengths.
704
208a4923
NC		 7052012-05-11 Daniel Richard G. <skunk@iskunk.org>
706
707 PR binutils/14028
708 * configure.in: Invoke ACX_HEADER_STRING.
709 * configure: Regenerate.
710 * config.in: Regenerate.
711 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
712 string.h and strings.h.
713
6750a3a7
NC		 7142012-05-11 Nick Clifton <nickc@redhat.com>
715
716 PR binutils/14006
717 * arm-dis.c (print_insn): Fix detection of instruction mode in
718 files containing multiple executable sections.
719
f6c1a2d5
NC		 7202012-05-03 Sean Keys <skeys@ipdatasys.com>
721
722 * Makefile.in, configure: regenerate
723 * disassemble.c (disassembler): Recognize ARCH_XGATE.
724 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
725 New functions.
726 * configure.in: Recognize xgate.
727 * xgate-dis.c, xgate-opc.c: New files for support of xgate
728 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
729 and opcode generation for xgate.
730
78e98aab
DD		 7312012-04-30 DJ Delorie <dj@redhat.com>
732
733 * rx-decode.opc (MOV): Do not sign-extend immediates which are
734 already the maximum bit size.
735 * rx-decode.c: Regenerate.
736
ec668d69
DM		 7372012-04-27 David S. Miller <davem@davemloft.net>
738
2e52845b
DM		 739 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
740 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
741
58004e23
DM		 742 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
743 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
744
698544e1
DM		 745 * sparc-opc.c (CBCOND): New define.
746 (CBCOND_XCC): Likewise.
747 (cbcond): New helper macro.
748 (sparc_opcodes): Add compare-and-branch instructions.
749
6cda1326
DM		 750 * sparc-dis.c (print_insn_sparc): Handle ')'.
751 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
752
ec668d69
DM		 753 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
754 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
755
2615994e
DM		 7562012-04-12 David S. Miller <davem@davemloft.net>
757
758 * sparc-dis.c (X_DISP10): Define.
759 (print_insn_sparc): Handle '='.
760
5de10af0
MF		 7612012-04-01 Mike Frysinger <vapier@gentoo.org>
762
763 * bfin-dis.c (fmtconst): Replace decimal handling with a single
764 sprintf call and the '*' field width.
765
55a36193
MK		 7662012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
767
768 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
769
d6688282
AM		 7702012-03-16 Alan Modra <amodra@gmail.com>
771
772 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
773 (powerpc_opcd_indices): Bump array size.
774 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
775 corresponding to unused opcodes to following entry.
776 (lookup_powerpc): New function, extracted and optimised from..
777 (print_insn_powerpc): ..here.
778
b240011a
AM		 7792012-03-15 Alan Modra <amodra@gmail.com>
780 James Lemke <jwlemke@codesourcery.com>
781
782 * disassemble.c (disassemble_init_for_target): Handle ppc init.
783 * ppc-dis.c (private): New var.
784 (powerpc_init_dialect): Don't return calloc failure, instead use
785 private.
786 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
787 (powerpc_opcd_indices): New array.
788 (disassemble_init_powerpc): New function.
789 (print_insn_big_powerpc): Don't init dialect here.
790 (print_insn_little_powerpc): Likewise.
791 (print_insn_powerpc): Start search using powerpc_opcd_indices.
792
aea77599
AM		 7932012-03-10 Edmar Wienskoski <edmar@freescale.com>
794
795 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
796 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
797 (PPCVEC2, PPCTMR, E6500): New short names.
798 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
799 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
800 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
801 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
802 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
803 optional operands on sync instruction for E6500 target.
804
5333187a
AK		 8052012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
806
807 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
808
a597d2d3
AM		 8092012-02-27 Alan Modra <amodra@gmail.com>
810
811 * mt-dis.c: Regenerate.
812
3f26eb3a
AM		 8132012-02-27 Alan Modra <amodra@gmail.com>
814
815 * v850-opc.c (extract_v8): Rearrange to make it obvious this
816 is the inverse of corresponding insert function.
817 (extract_d22, extract_u9, extract_r4): Likewise.
818 (extract_d9): Correct sign extension.
819 (extract_d16_15): Don't assume "long" is 32 bits, and don't
820 rely on implementation defined behaviour for shift right of
821 signed types.
822 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
823 (extract_d23): Likewise, and correct mask.
824
1f42f8b3
AM		 8252012-02-27 Alan Modra <amodra@gmail.com>
826
827 * crx-dis.c (print_arg): Mask constant to 32 bits.
828 * crx-opc.c (cst4_map): Use int array.
829
cdb06235
AM		 8302012-02-27 Alan Modra <amodra@gmail.com>
831
832 * arc-dis.c (BITS): Don't use shifts to mask off bits.
833 (FIELDD): Sign extend with xor,sub.
834
6f7be959
WL		 8352012-02-25 Walter Lee <walt@tilera.com>
836
837 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
838 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
839 TILEPRO_OPC_LW_TLS_SN.
840
82c2def5
L		 8412012-02-21 H.J. Lu <hongjiu.lu@intel.com>
842
843 * i386-opc.h (HLEPrefixNone): New.
844 (HLEPrefixLock): Likewise.
845 (HLEPrefixAny): Likewise.
846 (HLEPrefixRelease): Likewise.
847
42164a71
L		 8482012-02-08 H.J. Lu <hongjiu.lu@intel.com>
849
850 * i386-dis.c (HLE_Fixup1): New.
851 (HLE_Fixup2): Likewise.
852 (HLE_Fixup3): Likewise.
853 (Ebh1): Likewise.
854 (Evh1): Likewise.
855 (Ebh2): Likewise.
856 (Evh2): Likewise.
857 (Ebh3): Likewise.
858 (Evh3): Likewise.
859 (MOD_C6_REG_7): Likewise.
860 (MOD_C7_REG_7): Likewise.
861 (RM_C6_REG_7): Likewise.
862 (RM_C7_REG_7): Likewise.
863 (XACQUIRE_PREFIX): Likewise.
864 (XRELEASE_PREFIX): Likewise.
865 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
866 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
867 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
868 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
869 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
870 MOD_C6_REG_7 and MOD_C7_REG_7.
871 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
872 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
873 xtest.
874 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
875 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
876
877 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
878 CPU_RTM_FLAGS.
879 (cpu_flags): Add CpuHLE and CpuRTM.
880 (opcode_modifiers): Add HLEPrefixOk.
881
882 * i386-opc.h (CpuHLE): New.
883 (CpuRTM): Likewise.
884 (HLEPrefixOk): Likewise.
885 (i386_cpu_flags): Add cpuhle and cpurtm.
886 (i386_opcode_modifier): Add hleprefixok.
887
888 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
889 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
890 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
891 operand. Add xacquire, xrelease, xabort, xbegin, xend and
892 xtest.
893 * i386-init.h: Regenerated.
894 * i386-tbl.h: Likewise.
895
21abe33a
DD		 8962012-01-24 DJ Delorie <dj@redhat.com>
897
898 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
899 * rl78-decode.c: Regenerate.
900
e20cc039
AM		 9012012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
902
903 PR binutils/10173
904 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
905
e143d25c
AS		 9062012-01-17 Andreas Schwab <schwab@linux-m68k.org>
907
908 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
909 register and move them after pmove with PSR/PCSR register.
910
8729a6f6
L		 9112012-01-13 H.J. Lu <hongjiu.lu@intel.com>
912
913 * i386-dis.c (mod_table): Add vmfunc.
914
915 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
916 (cpu_flags): CpuVMFUNC.
917
918 * i386-opc.h (CpuVMFUNC): New.
919 (i386_cpu_flags): Add cpuvmfunc.
920
921 * i386-opc.tbl: Add vmfunc.
922 * i386-init.h: Regenerated.
923 * i386-tbl.h: Likewise.
5011093d 924
23e1d329 925For older changes see ChangeLog-2011
252b5132
RH		 926\f
927Local Variables:
2f6d2f85
NC		 928mode: change-log
929left-margin: 8
930fill-column: 74
252b5132
RH		 931version-control: never
932End:
GDB Binutils - Deliverables
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