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ubsan: tic4x: segv and signed shifts
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
66152f16
AM		 12019-12-11 Alan Modra <amodra@gmail.com>
2
3 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
4 on NULL registertable entry.
5 (tic4x_hash_opcode): Use unsigned arithmetic.
6
205c426a
AM		 72019-12-11 Alan Modra <amodra@gmail.com>
8
9 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
10
fb4cb4e2
AM		 112019-12-11 Alan Modra <amodra@gmail.com>
12
13 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
14 (bit_extract_simple, sign_extend): Likewise.
15
96f1f604
AM		 162019-12-11 Alan Modra <amodra@gmail.com>
17
18 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
19
8c9b4171
AM		 202019-12-11 Alan Modra <amodra@gmail.com>
21
22 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
23
334175b6
AM		 242019-12-11 Alan Modra <amodra@gmail.com>
25
26 * m68k-dis.c (COERCE32): Cast value first.
27 (NEXTLONG, NEXTULONG): Avoid signed overflow.
28
f8a87c78
AM		 292019-12-11 Alan Modra <amodra@gmail.com>
30
31 * h8300-dis.c (extract_immediate): Avoid signed overflow.
32 (bfd_h8_disassemble): Likewise.
33
159653d8
AM		 342019-12-11 Alan Modra <amodra@gmail.com>
35
36 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
37 past end of operands array.
38
d93bba9e
AM		 392019-12-11 Alan Modra <amodra@gmail.com>
40
41 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
42 overflow when collecting bytes of a number.
43
c202f69e
AM		 442019-12-11 Alan Modra <amodra@gmail.com>
45
46 * cris-dis.c (print_with_operands): Avoid signed integer
47 overflow when collecting bytes of a 32-bit integer.
48
0ef562a4
AM		 492019-12-11 Alan Modra <amodra@gmail.com>
50
51 * cr16-dis.c (EXTRACT, SBM): Rewrite.
52 (cr16_match_opcode): Delete duplicate bcond test.
53
2fd2b153
AM		 542019-12-11 Alan Modra <amodra@gmail.com>
55
56 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
57 (SIGNBIT): New.
58 (MASKBITS, SIGNEXTEND): Rewrite.
59 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
60 unsigned arithmetic, instead assign result of SIGNEXTEND back
61 to x.
62 (fmtconst_val): Use 1u in shift expression.
63
a11db3e9
AM		 642019-12-11 Alan Modra <amodra@gmail.com>
65
66 * arc-dis.c (find_format_from_table): Use ull constant when
67 shifting by up to 32.
68
9d48687b
AM		 692019-12-11 Alan Modra <amodra@gmail.com>
70
71 PR 25270
72 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
73 false when field is zero for sve_size_tsz_bhs.
74
b8e61daa
AM		 752019-12-11 Alan Modra <amodra@gmail.com>
76
77 * epiphany-ibld.c: Regenerate.
78
20135676
AM		 792019-12-10 Alan Modra <amodra@gmail.com>
80
81 PR 24960
82 * disassemble.c (disassemble_free_target): New function.
83
103ebbc3
AM		 842019-12-10 Alan Modra <amodra@gmail.com>
85
86 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
87 * disassemble.c (disassemble_init_for_target): Likewise.
88 * bpf-dis.c: Regenerate.
89 * epiphany-dis.c: Regenerate.
90 * fr30-dis.c: Regenerate.
91 * frv-dis.c: Regenerate.
92 * ip2k-dis.c: Regenerate.
93 * iq2000-dis.c: Regenerate.
94 * lm32-dis.c: Regenerate.
95 * m32c-dis.c: Regenerate.
96 * m32r-dis.c: Regenerate.
97 * mep-dis.c: Regenerate.
98 * mt-dis.c: Regenerate.
99 * or1k-dis.c: Regenerate.
100 * xc16x-dis.c: Regenerate.
101 * xstormy16-dis.c: Regenerate.
102
6f0e0752
AM		 1032019-12-10 Alan Modra <amodra@gmail.com>
104
105 * ppc-dis.c (private): Delete variable.
106 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
107 (powerpc_init_dialect): Don't use global private.
108
e7c22a69
AM		 1092019-12-10 Alan Modra <amodra@gmail.com>
110
111 * s12z-opc.c: Formatting.
112
0a6aef6b
AM		 1132019-12-08 Alan Modra <amodra@gmail.com>
114
115 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
116 registers.
117
2dc4b12f
JB		 1182019-12-05 Jan Beulich <jbeulich@suse.com>
119
120 * aarch64-tbl.h (aarch64_feature_crypto,
121 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
122 CRYPTO_V8_2_INSN): Delete.
123
378fd436
AM		 1242019-12-05 Alan Modra <amodra@gmail.com>
125
126 PR 25249
127 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
128 (struct string_buf): New.
129 (strbuf): New function.
130 (get_field): Use strbuf rather than strdup of local temp.
131 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
132 (get_field_rfsl, get_field_imm15): Likewise.
133 (get_field_rd, get_field_r1, get_field_r2): Update macros.
134 (get_field_special): Likewise. Don't strcpy spr. Formatting.
135 (print_insn_microblaze): Formatting. Init and pass string_buf to
136 get_field functions.
137
0ba59a29
JB		 1382019-12-04 Jan Beulich <jbeulich@suse.com>
139
140 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
141 * i386-tbl.h: Re-generate.
142
77ad8092
JB		 1432019-12-04 Jan Beulich <jbeulich@suse.com>
144
145 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
146
3036c899
JB		 1472019-12-04 Jan Beulich <jbeulich@suse.com>
148
149 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
150 forms.
151 (xbegin): Drop DefaultSize.
152 * i386-tbl.h: Re-generate.
153
8b301fbb
MI		 1542019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
155
156 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
157 Change the coproc CRC conditions to use the extension
158 feature set, second word, base on ARM_EXT2_CRC.
159
6aa385b9
JB		 1602019-11-14 Jan Beulich <jbeulich@suse.com>
161
162 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
163 * i386-tbl.h: Re-generate.
164
0cfa3eb3
JB		 1652019-11-14 Jan Beulich <jbeulich@suse.com>
166
167 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
168 JumpInterSegment, and JumpAbsolute entries.
169 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
170 JUMP_ABSOLUTE): Define.
171 (struct i386_opcode_modifier): Extend jump field to 3 bits.
172 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
173 fields.
174 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
175 JumpInterSegment): Define.
176 * i386-tbl.h: Re-generate.
177
6f2f06be
JB		 1782019-11-14 Jan Beulich <jbeulich@suse.com>
179
180 * i386-gen.c (operand_type_init): Remove
181 OPERAND_TYPE_JUMPABSOLUTE entry.
182 (opcode_modifiers): Add JumpAbsolute entry.
183 (operand_types): Remove JumpAbsolute entry.
184 * i386-opc.h (JumpAbsolute): Move between enums.
185 (struct i386_opcode_modifier): Add jumpabsolute field.
186 (union i386_operand_type): Remove jumpabsolute field.
187 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
188 * i386-init.h, i386-tbl.h: Re-generate.
189
601e8564
JB		 1902019-11-14 Jan Beulich <jbeulich@suse.com>
191
192 * i386-gen.c (opcode_modifiers): Add AnySize entry.
193 (operand_types): Remove AnySize entry.
194 * i386-opc.h (AnySize): Move between enums.
195 (struct i386_opcode_modifier): Add anysize field.
196 (OTUnused): Un-comment.
197 (union i386_operand_type): Remove anysize field.
198 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
199 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
200 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
201 AnySize.
202 * i386-tbl.h: Re-generate.
203
7722d40a
JW		 2042019-11-12 Nelson Chu <nelson.chu@sifive.com>
205
206 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
207 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
208 use the floating point register (FPR).
209
ce760a76
MI		 2102019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
211
212 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
213 cmode 1101.
214 (is_mve_encoding_conflict): Update cmode conflict checks for
215 MVE_VMVN_IMM.
216
51c8edf6
JB		 2172019-11-12 Jan Beulich <jbeulich@suse.com>
218
219 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
220 entry.
221 (operand_types): Remove EsSeg entry.
222 (main): Replace stale use of OTMax.
223 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
224 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
225 (EsSeg): Delete.
226 (OTUnused): Comment out.
227 (union i386_operand_type): Remove esseg field.
228 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
229 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
230 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
231 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
232 * i386-init.h, i386-tbl.h: Re-generate.
233
474da251
JB		 2342019-11-12 Jan Beulich <jbeulich@suse.com>
235
236 * i386-gen.c (operand_instances): Add RegB entry.
237 * i386-opc.h (enum operand_instance): Add RegB.
238 * i386-opc.tbl (RegC, RegD, RegB): Define.
239 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
240 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
241 monitorx, mwaitx): Drop ImmExt and convert encodings
242 accordingly.
243 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
244 (edx, rdx): Add Instance=RegD.
245 (ebx, rbx): Add Instance=RegB.
246 * i386-tbl.h: Re-generate.
247
75e5731b
JB		 2482019-11-12 Jan Beulich <jbeulich@suse.com>
249
250 * i386-gen.c (operand_type_init): Adjust
251 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
252 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
253 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
254 (operand_instances): New.
255 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
256 (output_operand_type): New parameter "instance". Process it.
257 (process_i386_operand_type): New local variable "instance".
258 (main): Adjust static assertions.
259 * i386-opc.h (INSTANCE_WIDTH): Define.
260 (enum operand_instance): New.
261 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
262 (union i386_operand_type): Replace acc, inoutportreg, and
263 shiftcount by instance.
264 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
265 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
266 Add Instance=.
267 * i386-init.h, i386-tbl.h: Re-generate.
268
91802f3c
JB		 2692019-11-11 Jan Beulich <jbeulich@suse.com>
270
271 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
272 smaxp/sminp entries' "tied_operand" field to 2.
273
4f5fc85d
JB		 2742019-11-11 Jan Beulich <jbeulich@suse.com>
275
276 * aarch64-opc.c (operand_general_constraint_met_p): Replace
277 "index" local variable by that of the already existing "num".
278
dc2be329
L		 2792019-11-08 H.J. Lu <hongjiu.lu@intel.com>
280
281 PR gas/25167
282 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
283 * i386-tbl.h: Regenerated.
284
f74a6307
JB		 2852019-11-08 Jan Beulich <jbeulich@suse.com>
286
287 * i386-gen.c (operand_type_init): Add Class= to
288 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
289 OPERAND_TYPE_REGBND entry.
290 (operand_classes): Add RegMask and RegBND entries.
291 (operand_types): Drop RegMask and RegBND entry.
292 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
293 (RegMask, RegBND): Delete.
294 (union i386_operand_type): Remove regmask and regbnd fields.
295 * i386-opc.tbl (RegMask, RegBND): Define.
296 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
297 Class=RegBND.
298 * i386-init.h, i386-tbl.h: Re-generate.
299
3528c362
JB		 3002019-11-08 Jan Beulich <jbeulich@suse.com>
301
302 * i386-gen.c (operand_type_init): Add Class= to
303 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
304 OPERAND_TYPE_REGZMM entries.
305 (operand_classes): Add RegMMX and RegSIMD entries.
306 (operand_types): Drop RegMMX and RegSIMD entries.
307 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
308 (RegMMX, RegSIMD): Delete.
309 (union i386_operand_type): Remove regmmx and regsimd fields.
310 * i386-opc.tbl (RegMMX): Define.
311 (RegXMM, RegYMM, RegZMM): Add Class=.
312 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
313 Class=RegSIMD.
314 * i386-init.h, i386-tbl.h: Re-generate.
315
4a5c67ed
JB		 3162019-11-08 Jan Beulich <jbeulich@suse.com>
317
318 * i386-gen.c (operand_type_init): Add Class= to
319 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
320 entries.
321 (operand_classes): Add RegCR, RegDR, and RegTR entries.
322 (operand_types): Drop Control, Debug, and Test entries.
323 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
324 (Control, Debug, Test): Delete.
325 (union i386_operand_type): Remove control, debug, and test
326 fields.
327 * i386-opc.tbl (Control, Debug, Test): Define.
328 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
329 Class=RegDR, and Test by Class=RegTR.
330 * i386-init.h, i386-tbl.h: Re-generate.
331
00cee14f
JB		 3322019-11-08 Jan Beulich <jbeulich@suse.com>
333
334 * i386-gen.c (operand_type_init): Add Class= to
335 OPERAND_TYPE_SREG entry.
336 (operand_classes): Add SReg entry.
337 (operand_types): Drop SReg entry.
338 * i386-opc.h (enum operand_class): Add SReg.
339 (SReg): Delete.
340 (union i386_operand_type): Remove sreg field.
341 * i386-opc.tbl (SReg): Define.
342 * i386-reg.tbl: Replace SReg by Class=SReg.
343 * i386-init.h, i386-tbl.h: Re-generate.
344
bab6aec1
JB		 3452019-11-08 Jan Beulich <jbeulich@suse.com>
346
347 * i386-gen.c (operand_type_init): Add Class=. New
348 OPERAND_TYPE_ANYIMM entry.
349 (operand_classes): New.
350 (operand_types): Drop Reg entry.
351 (output_operand_type): New parameter "class". Process it.
352 (process_i386_operand_type): New local variable "class".
353 (main): Adjust static assertions.
354 * i386-opc.h (CLASS_WIDTH): Define.
355 (enum operand_class): New.
356 (Reg): Replace by Class. Adjust comment.
357 (union i386_operand_type): Replace reg by class.
358 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
359 Class=.
360 * i386-reg.tbl: Replace Reg by Class=Reg.
361 * i386-init.h: Re-generate.
362
1f4cd317
MM		 3632019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
364
365 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
366 (aarch64_opcode_table): Add data gathering hint mnemonic.
367 * opcodes/aarch64-dis-2.c: Account for new instruction.
368
616ce08e
MM		 3692019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
370
371 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
372
373
8382113f
MM		 3742019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
375
376 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
377 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
378 aarch64_feature_f64mm): New feature sets.
379 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
380 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
381 instructions.
382 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
383 macros.
384 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
385 (OP_SVE_QQQ): New qualifier.
386 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
387 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
388 the movprfx constraint.
389 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
390 (aarch64_opcode_table): Define new instructions smmla,
391 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
392 uzip{1/2}, trn{1/2}.
393 * aarch64-opc.c (operand_general_constraint_met_p): Handle
394 AARCH64_OPND_SVE_ADDR_RI_S4x32.
395 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
396 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
397 Account for new instructions.
398 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
399 S4x32 operand.
400 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
401
aab2c27d
MM		 4022019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4032019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
404
405 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
406 Armv8.6-A.
407 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
408 (neon_opcodes): Add bfloat SIMD instructions.
409 (print_insn_coprocessor): Add new control character %b to print
410 condition code without checking cp_num.
411 (print_insn_neon): Account for BFloat16 instructions that have no
412 special top-byte handling.
413
33593eaf
MM		 4142019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4152019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
416
417 * arm-dis.c (print_insn_coprocessor,
418 print_insn_generic_coprocessor): Create wrapper functions around
419 the implementation of the print_insn_coprocessor control codes.
420 (print_insn_coprocessor_1): Original print_insn_coprocessor
421 function that now takes which array to look at as an argument.
422 (print_insn_arm): Use both print_insn_coprocessor and
423 print_insn_generic_coprocessor.
424 (print_insn_thumb32): As above.
425
df678013
MM		 4262019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4272019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
428
429 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
430 in reglane special case.
431 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
432 aarch64_find_next_opcode): Account for new instructions.
433 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
434 in reglane special case.
435 * aarch64-opc.c (struct operand_qualifier_data): Add data for
436 new AARCH64_OPND_QLF_S_2H qualifier.
437 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
438 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
439 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
440 sets.
441 (BFLOAT_SVE, BFLOAT): New feature set macros.
442 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
443 instructions.
444 (aarch64_opcode_table): Define new instructions bfdot,
445 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
446 bfcvtn2, bfcvt.
447
8ae2d3d9
MM		 4482019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4492019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
450
451 * aarch64-tbl.h (ARMV8_6): New macro.
452
142861df
JB		 4532019-11-07 Jan Beulich <jbeulich@suse.com>
454
455 * i386-dis.c (prefix_table): Add mcommit.
456 (rm_table): Add rdpru.
457 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
458 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
459 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
460 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
461 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
462 * i386-opc.tbl (mcommit, rdpru): New.
463 * i386-init.h, i386-tbl.h: Re-generate.
464
081e283f
JB		 4652019-11-07 Jan Beulich <jbeulich@suse.com>
466
467 * i386-dis.c (OP_Mwait): Drop local variable "names", use
468 "names32" instead.
469 (OP_Monitor): Drop local variable "op1_names", re-purpose
470 "names" for it instead, and replace former "names" uses by
471 "names32" ones.
472
c050c89a
JB		 4732019-11-07 Jan Beulich <jbeulich@suse.com>
474
475 PR/gas 25167
476 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
477 operand-less forms.
478 * opcodes/i386-tbl.h: Re-generate.
479
7abb8d81
JB		 4802019-11-05 Jan Beulich <jbeulich@suse.com>
481
482 * i386-dis.c (OP_Mwaitx): Delete.
483 (prefix_table): Use OP_Mwait for mwaitx entry.
484 (OP_Mwait): Also handle mwaitx.
485
267b8516
JB		 4862019-11-05 Jan Beulich <jbeulich@suse.com>
487
488 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
489 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
490 (prefix_table): Add respective entries.
491 (rm_table): Link to those entries.
492
f8687e93
JB		 4932019-11-05 Jan Beulich <jbeulich@suse.com>
494
495 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
496 (REG_0F1C_P_0_MOD_0): ... this.
497 (REG_0F1E_MOD_3): Rename to ...
498 (REG_0F1E_P_1_MOD_3): ... this.
499 (RM_0F01_REG_5): Rename to ...
500 (RM_0F01_REG_5_MOD_3): ... this.
501 (RM_0F01_REG_7): Rename to ...
502 (RM_0F01_REG_7_MOD_3): ... this.
503 (RM_0F1E_MOD_3_REG_7): Rename to ...
504 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
505 (RM_0FAE_REG_6): Rename to ...
506 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
507 (RM_0FAE_REG_7): Rename to ...
508 (RM_0FAE_REG_7_MOD_3): ... this.
509 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
510 (PREFIX_0F01_REG_5_MOD_0): ... this.
511 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
512 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
513 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
514 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
515 (PREFIX_0FAE_REG_0): Rename to ...
516 (PREFIX_0FAE_REG_0_MOD_3): ... this.
517 (PREFIX_0FAE_REG_1): Rename to ...
518 (PREFIX_0FAE_REG_1_MOD_3): ... this.
519 (PREFIX_0FAE_REG_2): Rename to ...
520 (PREFIX_0FAE_REG_2_MOD_3): ... this.
521 (PREFIX_0FAE_REG_3): Rename to ...
522 (PREFIX_0FAE_REG_3_MOD_3): ... this.
523 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
524 (PREFIX_0FAE_REG_4_MOD_0): ... this.
525 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
526 (PREFIX_0FAE_REG_4_MOD_3): ... this.
527 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
528 (PREFIX_0FAE_REG_5_MOD_0): ... this.
529 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
530 (PREFIX_0FAE_REG_5_MOD_3): ... this.
531 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
532 (PREFIX_0FAE_REG_6_MOD_0): ... this.
533 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
534 (PREFIX_0FAE_REG_6_MOD_3): ... this.
535 (PREFIX_0FAE_REG_7): Rename to ...
536 (PREFIX_0FAE_REG_7_MOD_0): ... this.
537 (PREFIX_MOD_0_0FC3): Rename to ...
538 (PREFIX_0FC3_MOD_0): ... this.
539 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
540 (PREFIX_0FC7_REG_6_MOD_0): ... this.
541 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
542 (PREFIX_0FC7_REG_6_MOD_3): ... this.
543 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
544 (PREFIX_0FC7_REG_7_MOD_3): ... this.
545 (reg_table, prefix_table, mod_table, rm_table): Adjust
546 accordingly.
547
5103274f
NC		 5482019-11-04 Nick Clifton <nickc@redhat.com>
549
550 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
551 of a v850 system register. Move the v850_sreg_names array into
552 this function.
553 (get_v850_reg_name): Likewise for ordinary register names.
554 (get_v850_vreg_name): Likewise for vector register names.
555 (get_v850_cc_name): Likewise for condition codes.
556 * get_v850_float_cc_name): Likewise for floating point condition
557 codes.
558 (get_v850_cacheop_name): Likewise for cache-ops.
559 (get_v850_prefop_name): Likewise for pref-ops.
560 (disassemble): Use the new accessor functions.
561
1820262b
DB		 5622019-10-30 Delia Burduv <delia.burduv@arm.com>
563
564 * aarch64-opc.c (print_immediate_offset_address): Don't print the
565 immediate for the writeback form of ldraa/ldrab if it is 0.
566 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
567 * aarch64-opc-2.c: Regenerated.
568
3cc17af5
JB		 5692019-10-30 Jan Beulich <jbeulich@suse.com>
570
571 * i386-gen.c (operand_type_shorthands): Delete.
572 (operand_type_init): Expand previous shorthands.
573 (set_bitfield_from_shorthand): Rename back to ...
574 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
575 of operand_type_init[].
576 (set_bitfield): Adjust call to the above function.
577 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
578 RegXMM, RegYMM, RegZMM): Define.
579 * i386-reg.tbl: Expand prior shorthands.
580
a2cebd03
JB		 5812019-10-30 Jan Beulich <jbeulich@suse.com>
582
583 * i386-gen.c (output_i386_opcode): Change order of fields
584 emitted to output.
585 * i386-opc.h (struct insn_template): Move operands field.
586 Convert extension_opcode field to unsigned short.
587 * i386-tbl.h: Re-generate.
588
507916b8
JB		 5892019-10-30 Jan Beulich <jbeulich@suse.com>
590
591 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
592 of W.
593 * i386-opc.h (W): Extend comment.
594 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
595 general purpose variants not allowing for byte operands.
596 * i386-tbl.h: Re-generate.
597
efea62b4
NC		 5982019-10-29 Nick Clifton <nickc@redhat.com>
599
600 * tic30-dis.c (print_branch): Correct size of operand array.
601
9adb2591
NC		 6022019-10-29 Nick Clifton <nickc@redhat.com>
603
604 * d30v-dis.c (print_insn): Check that operand index is valid
605 before attempting to access the operands array.
606
993a00a9
NC		 6072019-10-29 Nick Clifton <nickc@redhat.com>
608
609 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
610 locating the bit to be tested.
611
66a66a17
NC		 6122019-10-29 Nick Clifton <nickc@redhat.com>
613
614 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
615 values.
616 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
617 (print_insn_s12z): Check for illegal size values.
618
1ee3542c
NC		 6192019-10-28 Nick Clifton <nickc@redhat.com>
620
621 * csky-dis.c (csky_chars_to_number): Check for a negative
622 count. Use an unsigned integer to construct the return value.
623
bbf9a0b5
NC		 6242019-10-28 Nick Clifton <nickc@redhat.com>
625
626 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
627 operand buffer. Set value to 15 not 13.
628 (get_register_operand): Use OPERAND_BUFFER_LEN.
629 (get_indirect_operand): Likewise.
630 (print_two_operand): Likewise.
631 (print_three_operand): Likewise.
632 (print_oar_insn): Likewise.
633
d1e304bc
NC		 6342019-10-28 Nick Clifton <nickc@redhat.com>
635
636 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
637 (bit_extract_simple): Likewise.
638 (bit_copy): Likewise.
639 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
640 index_offset array are not accessed.
641
dee33451
NC		 6422019-10-28 Nick Clifton <nickc@redhat.com>
643
644 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
645 operand.
646
27cee81d
NC		 6472019-10-25 Nick Clifton <nickc@redhat.com>
648
649 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
650 access to opcodes.op array element.
651
de6d8dc2
NC		 6522019-10-23 Nick Clifton <nickc@redhat.com>
653
654 * rx-dis.c (get_register_name): Fix spelling typo in error
655 message.
656 (get_condition_name, get_flag_name, get_double_register_name)
657 (get_double_register_high_name, get_double_register_low_name)
658 (get_double_control_register_name, get_double_condition_name)
659 (get_opsize_name, get_size_name): Likewise.
660
6207ed28
NC		 6612019-10-22 Nick Clifton <nickc@redhat.com>
662
663 * rx-dis.c (get_size_name): New function. Provides safe
664 access to name array.
665 (get_opsize_name): Likewise.
666 (print_insn_rx): Use the accessor functions.
667
12234dfd
NC		 6682019-10-16 Nick Clifton <nickc@redhat.com>
669
670 * rx-dis.c (get_register_name): New function. Provides safe
671 access to name array.
672 (get_condition_name, get_flag_name, get_double_register_name)
673 (get_double_register_high_name, get_double_register_low_name)
674 (get_double_control_register_name, get_double_condition_name):
675 Likewise.
676 (print_insn_rx): Use the accessor functions.
677
1d378749
NC		 6782019-10-09 Nick Clifton <nickc@redhat.com>
679
680 PR 25041
681 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
682 instructions.
683
d241b910
JB		 6842019-10-07 Jan Beulich <jbeulich@suse.com>
685
686 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
687 (cmpsd): Likewise. Move EsSeg to other operand.
688 * opcodes/i386-tbl.h: Re-generate.
689
f5c5b7c1
AM		 6902019-09-23 Alan Modra <amodra@gmail.com>
691
692 * m68k-dis.c: Include cpu-m68k.h
693
7beeaeb8
AM		 6942019-09-23 Alan Modra <amodra@gmail.com>
695
696 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
697 "elf/mips.h" earlier.
698
3f9aad11
JB		 6992018-09-20 Jan Beulich <jbeulich@suse.com>
700
701 PR gas/25012
702 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
703 with SReg operand.
704 * i386-tbl.h: Re-generate.
705
fd361982
AM		 7062019-09-18 Alan Modra <amodra@gmail.com>
707
708 * arc-ext.c: Update throughout for bfd section macro changes.
709
e0b2a78c
SM		 7102019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
711
712 * Makefile.in: Re-generate.
713 * configure: Re-generate.
714
7e9ad3a3
JW		 7152019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
716
717 * riscv-opc.c (riscv_opcodes): Change subset field
718 to insn_class field for all instructions.
719 (riscv_insn_types): Likewise.
720
bb695960
PB		 7212019-09-16 Phil Blundell <pb@pbcl.net>
722
723 * configure: Regenerated.
724
8063ab7e
MV		 7252019-09-10 Miod Vallat <miod@online.fr>
726
727 PR 24982
728 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
729
60391a25
PB		 7302019-09-09 Phil Blundell <pb@pbcl.net>
731
732 binutils 2.33 branch created.
733
f44b758d
NC		 7342019-09-03 Nick Clifton <nickc@redhat.com>
735
736 PR 24961
737 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
738 greater than zero before indexing via (bufcnt -1).
739
1e4b5e7d
NC		 7402019-09-03 Nick Clifton <nickc@redhat.com>
741
742 PR 24958
743 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
744 (MAX_SPEC_REG_NAME_LEN): Define.
745 (struct mmix_dis_info): Use defined constants for array lengths.
746 (get_reg_name): New function.
747 (get_sprec_reg_name): New function.
748 (print_insn_mmix): Use new functions.
749
c4a23bf8
SP		 7502019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
751
752 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
753 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
754 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
755
a051e2f3
KT		 7562019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
757
758 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
759 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
760 (aarch64_sys_reg_supported_p): Update checks for the above.
761
08132bdd
SP		 7622019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
763
764 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
765 cases MVE_SQRSHRL and MVE_UQRSHLL.
766 (print_insn_mve): Add case for specifier 'k' to check
767 specific bit of the instruction.
768
d88bdcb4
PA		 7692019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
770
771 PR 24854
772 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
773 encountering an unknown machine type.
774 (print_insn_arc): Handle arc_insn_length returning 0. In error
775 cases return -1 rather than calling abort.
776
bc750500
JB		 7772019-08-07 Jan Beulich <jbeulich@suse.com>
778
779 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
780 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
781 IgnoreSize.
782 * i386-tbl.h: Re-generate.
783
23d188c7
BW		 7842019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
785
786 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
787 instructions.
788
c0d6f62f
JW		 7892019-07-30 Mel Chen <mel.chen@sifive.com>
790
791 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
792 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
793
794 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
795 fscsr.
796
0f3f7167
CZ		 7972019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
798
799 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
800 and MPY class instructions.
801 (parse_option): Add nps400 option.
802 (print_arc_disassembler_options): Add nps400 info.
803
7e126ba3
CZ		 8042019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
805
806 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
807 (bspop): Likewise.
808 (modapp): Likewise.
809 * arc-opc.c (RAD_CHK): Add.
810 * arc-tbl.h: Regenerate.
811
a028026d
KT		 8122019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
813
814 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
815 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
816
ac79ff9e
NC		 8172019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
818
819 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
820 instructions as UNPREDICTABLE.
821
231097b0
JM		 8222019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
823
824 * bpf-desc.c: Regenerated.
825
1d942ae9
JB		 8262019-07-17 Jan Beulich <jbeulich@suse.com>
827
828 * i386-gen.c (static_assert): Define.
829 (main): Use it.
830 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
831 (Opcode_Modifier_Num): ... this.
832 (Mem): Delete.
833
dfd69174
JB		 8342019-07-16 Jan Beulich <jbeulich@suse.com>
835
836 * i386-gen.c (operand_types): Move RegMem ...
837 (opcode_modifiers): ... here.
838 * i386-opc.h (RegMem): Move to opcode modifer enum.
839 (union i386_operand_type): Move regmem field ...
840 (struct i386_opcode_modifier): ... here.
841 * i386-opc.tbl (RegMem): Define.
842 (mov, movq): Move RegMem on segment, control, debug, and test
843 register flavors.
844 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
845 to non-SSE2AVX flavor.
846 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
847 Move RegMem on register only flavors. Drop IgnoreSize from
848 legacy encoding flavors.
849 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
850 flavors.
851 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
852 register only flavors.
853 (vmovd): Move RegMem and drop IgnoreSize on register only
854 flavor. Change opcode and operand order to store form.
855 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
856
21df382b
JB		 8572019-07-16 Jan Beulich <jbeulich@suse.com>
858
859 * i386-gen.c (operand_type_init, operand_types): Replace SReg
860 entries.
861 * i386-opc.h (SReg2, SReg3): Replace by ...
862 (SReg): ... this.
863 (union i386_operand_type): Replace sreg fields.
864 * i386-opc.tbl (mov, ): Use SReg.
865 (push, pop): Likewies. Drop i386 and x86-64 specific segment
866 register flavors.
867 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
868 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
869
3719fd55
JM		 8702019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
871
872 * bpf-desc.c: Regenerate.
873 * bpf-opc.c: Likewise.
874 * bpf-opc.h: Likewise.
875
92434a14
JM		 8762019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
877
878 * bpf-desc.c: Regenerate.
879 * bpf-opc.c: Likewise.
880
43dd7626
HPN		 8812019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
882
883 * arm-dis.c (print_insn_coprocessor): Rename index to
884 index_operand.
885
98602811
JW		 8862019-07-05 Kito Cheng <kito.cheng@sifive.com>
887
888 * riscv-opc.c (riscv_insn_types): Add r4 type.
889
890 * riscv-opc.c (riscv_insn_types): Add b and j type.
891
892 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
893 format for sb type and correct s type.
894
01c1ee4a
RS		 8952019-07-02 Richard Sandiford <richard.sandiford@arm.com>
896
897 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
898 SVE FMOV alias of FCPY.
899
83adff69
RS		 9002019-07-02 Richard Sandiford <richard.sandiford@arm.com>
901
902 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
903 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
904
89418844
RS		 9052019-07-02 Richard Sandiford <richard.sandiford@arm.com>
906
907 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
908 registers in an instruction prefixed by MOVPRFX.
909
41be57ca
MM		 9102019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
911
912 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
913 sve_size_13 icode to account for variant behaviour of
914 pmull{t,b}.
915 * aarch64-dis-2.c: Regenerate.
916 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
917 sve_size_13 icode to account for variant behaviour of
918 pmull{t,b}.
919 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
920 (OP_SVE_VVV_Q_D): Add new qualifier.
921 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
922 (struct aarch64_opcode): Split pmull{t,b} into those requiring
923 AES and those not.
924
9d3bf266
JB		 9252019-07-01 Jan Beulich <jbeulich@suse.com>
926
927 * opcodes/i386-gen.c (operand_type_init): Remove
928 OPERAND_TYPE_VEC_IMM4 entry.
929 (operand_types): Remove Vec_Imm4.
930 * opcodes/i386-opc.h (Vec_Imm4): Delete.
931 (union i386_operand_type): Remove vec_imm4.
932 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
933 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
934
c3949f43
JB		 9352019-07-01 Jan Beulich <jbeulich@suse.com>
936
937 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
938 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
939 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
940 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
941 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
942 monitorx, mwaitx): Drop ImmExt from operand-less forms.
943 * i386-tbl.h: Re-generate.
944
5641ec01
JB		 9452019-07-01 Jan Beulich <jbeulich@suse.com>
946
947 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
948 register operands.
949 * i386-tbl.h: Re-generate.
950
79dec6b7
JB		 9512019-07-01 Jan Beulich <jbeulich@suse.com>
952
953 * i386-opc.tbl (C): New.
954 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
955 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
956 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
957 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
958 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
959 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
960 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
961 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
962 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
963 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
964 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
965 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
966 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
967 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
968 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
969 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
970 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
971 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
972 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
973 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
974 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
975 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
976 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
977 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
978 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
979 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
980 flavors.
981 * i386-tbl.h: Re-generate.
982
a0a1771e
JB		 9832019-07-01 Jan Beulich <jbeulich@suse.com>
984
985 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
986 register operands.
987 * i386-tbl.h: Re-generate.
988
cd546e7b
JB		 9892019-07-01 Jan Beulich <jbeulich@suse.com>
990
991 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
992 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
993 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
994 * i386-tbl.h: Re-generate.
995
e3bba3fc
JB		 9962019-07-01 Jan Beulich <jbeulich@suse.com>
997
998 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
999 Disp8MemShift from register only templates.
1000 * i386-tbl.h: Re-generate.
1001
36cc073e
JB		 10022019-07-01 Jan Beulich <jbeulich@suse.com>
1003
1004 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1005 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1006 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1007 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1008 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1009 EVEX_W_0F11_P_3_M_1): Delete.
1010 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1011 EVEX_W_0F11_P_3): New.
1012 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1013 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1014 MOD_EVEX_0F11_PREFIX_3 table entries.
1015 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1016 PREFIX_EVEX_0F11 table entries.
1017 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1018 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1019 EVEX_W_0F11_P_3_M_{0,1} table entries.
1020
219920a7
JB		 10212019-07-01 Jan Beulich <jbeulich@suse.com>
1022
1023 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1024 Delete.
1025
e395f487
L		 10262019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1027
1028 PR binutils/24719
1029 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1030 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1031 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1032 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1033 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1034 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1035 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1036 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1037 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1038 PREFIX_EVEX_0F38C6_REG_6 entries.
1039 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1040 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1041 EVEX_W_0F38C7_R_6_P_2 entries.
1042 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1043 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1044 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1045 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1046 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1047 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1048 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1049
2b7bcc87
JB		 10502019-06-27 Jan Beulich <jbeulich@suse.com>
1051
1052 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1053 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1054 VEX_LEN_0F2D_P_3): Delete.
1055 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1056 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1057 (prefix_table): ... here.
1058
c1dc7af5
JB		 10592019-06-27 Jan Beulich <jbeulich@suse.com>
1060
1061 * i386-dis.c (Iq): Delete.
1062 (Id): New.
1063 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1064 TBM insns.
1065 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1066 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1067 (OP_E_memory): Also honor needindex when deciding whether an
1068 address size prefix needs printing.
1069 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1070
d7560e2d
JW		 10712019-06-26 Jim Wilson <jimw@sifive.com>
1072
1073 PR binutils/24739
1074 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1075 Set info->display_endian to info->endian_code.
1076
2c703856
JB		 10772019-06-25 Jan Beulich <jbeulich@suse.com>
1078
1079 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1080 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1081 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1082 OPERAND_TYPE_ACC64 entries.
1083 * i386-init.h: Re-generate.
1084
54fbadc0
JB		 10852019-06-25 Jan Beulich <jbeulich@suse.com>
1086
1087 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1088 Delete.
1089 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1090 of dqa_mode.
1091 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1092 entries here.
1093 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1094 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1095
a280ab8e
JB		 10962019-06-25 Jan Beulich <jbeulich@suse.com>
1097
1098 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1099 variables.
1100
e1a1babd
JB		 11012019-06-25 Jan Beulich <jbeulich@suse.com>
1102
1103 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1104 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1105 movnti.
d7560e2d 1106 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1107 * i386-tbl.h: Re-generate.
1108
b8364fa7
JB		 11092019-06-25 Jan Beulich <jbeulich@suse.com>
1110
1111 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1112 * i386-tbl.h: Re-generate.
1113
ad692897
L		 11142019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1115
1116 * i386-dis-evex.h: Break into ...
1117 * i386-dis-evex-len.h: New file.
1118 * i386-dis-evex-mod.h: Likewise.
1119 * i386-dis-evex-prefix.h: Likewise.
1120 * i386-dis-evex-reg.h: Likewise.
1121 * i386-dis-evex-w.h: Likewise.
1122 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1123 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1124 i386-dis-evex-mod.h.
1125
f0a6222e
L		 11262019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1127
1128 PR binutils/24700
1129 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1130 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1131 EVEX_W_0F385B_P_2.
1132 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1133 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1134 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1135 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1136 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1137 EVEX_LEN_0F385B_P_2_W_1.
1138 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1139 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1140 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1141 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1142 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1143 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1144 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1145 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1146 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1147 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1148
6e1c90b7
L		 11492019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1150
1151 PR binutils/24691
1152 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1153 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1154 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1155 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1156 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1157 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1158 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1159 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1160 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1161 EVEX_LEN_0F3A43_P_2_W_1.
1162 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1163 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1164 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1165 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1166 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1167 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1168 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1169 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1170 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1171 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1172 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1173 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1174
bcc5a6eb
NC		 11752019-06-14 Nick Clifton <nickc@redhat.com>
1176
1177 * po/fr.po; Updated French translation.
1178
e4c4ac46
SH		 11792019-06-13 Stafford Horne <shorne@gmail.com>
1180
1181 * or1k-asm.c: Regenerated.
1182 * or1k-desc.c: Regenerated.
1183 * or1k-desc.h: Regenerated.
1184 * or1k-dis.c: Regenerated.
1185 * or1k-ibld.c: Regenerated.
1186 * or1k-opc.c: Regenerated.
1187 * or1k-opc.h: Regenerated.
1188 * or1k-opinst.c: Regenerated.
1189
a0e44ef5
PB		 11902019-06-12 Peter Bergner <bergner@linux.ibm.com>
1191
1192 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1193
12efd68d
L		 11942019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1195
1196 PR binutils/24633
1197 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1198 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1199 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1200 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1201 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1202 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1203 EVEX_LEN_0F3A1B_P_2_W_1.
1204 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1205 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1206 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1207 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1208 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1209 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1210 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1211 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1212
63c6fc6c
L		 12132019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1214
1215 PR binutils/24626
1216 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1217 EVEX.vvvv when disassembling VEX and EVEX instructions.
1218 (OP_VEX): Set vex.register_specifier to 0 after readding
1219 vex.register_specifier.
1220 (OP_Vex_2src_1): Likewise.
1221 (OP_Vex_2src_2): Likewise.
1222 (OP_LWP_E): Likewise.
1223 (OP_EX_Vex): Don't check vex.register_specifier.
1224 (OP_XMM_Vex): Likewise.
1225
9186c494
L		 12262019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1227 Lili Cui <lili.cui@intel.com>
1228
1229 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1230 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1231 instructions.
1232 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1233 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1234 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1235 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1236 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1237 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1238 * i386-init.h: Regenerated.
1239 * i386-tbl.h: Likewise.
1240
5d79adc4
L		 12412019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1242 Lili Cui <lili.cui@intel.com>
1243
1244 * doc/c-i386.texi: Document enqcmd.
1245 * testsuite/gas/i386/enqcmd-intel.d: New file.
1246 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1247 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1248 * testsuite/gas/i386/enqcmd.d: Likewise.
1249 * testsuite/gas/i386/enqcmd.s: Likewise.
1250 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1251 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1252 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1253 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1254 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1255 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1256 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1257 and x86-64-enqcmd.
1258
a9d96ab9
AH		 12592019-06-04 Alan Hayward <alan.hayward@arm.com>
1260
1261 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1262
4f6d070a
AM		 12632019-06-03 Alan Modra <amodra@gmail.com>
1264
1265 * ppc-dis.c (prefix_opcd_indices): Correct size.
1266
a2f4b66c
L		 12672019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1268
1269 PR gas/24625
1270 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1271 Disp8ShiftVL.
1272 * i386-tbl.h: Regenerated.
1273
405b5bd8
AM		 12742019-05-24 Alan Modra <amodra@gmail.com>
1275
1276 * po/POTFILES.in: Regenerate.
1277
8acf1435
PB		 12782019-05-24 Peter Bergner <bergner@linux.ibm.com>
1279 Alan Modra <amodra@gmail.com>
1280
1281 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1282 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1283 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1284 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1285 XTOP>): Define and add entries.
1286 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1287 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1288 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1289 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1290
dd7efa79
PB		 12912019-05-24 Peter Bergner <bergner@linux.ibm.com>
1292 Alan Modra <amodra@gmail.com>
1293
1294 * ppc-dis.c (ppc_opts): Add "future" entry.
1295 (PREFIX_OPCD_SEGS): Define.
1296 (prefix_opcd_indices): New array.
1297 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1298 (lookup_prefix): New function.
1299 (print_insn_powerpc): Handle 64-bit prefix instructions.
1300 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1301 (PMRR, POWERXX): Define.
1302 (prefix_opcodes): New instruction table.
1303 (prefix_num_opcodes): New constant.
1304
79472b45
JM		 13052019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1306
1307 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1308 * configure: Regenerated.
1309 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1310 and cpu/bpf.opc.
1311 (HFILES): Add bpf-desc.h and bpf-opc.h.
1312 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1313 bpf-ibld.c and bpf-opc.c.
1314 (BPF_DEPS): Define.
1315 * Makefile.in: Regenerated.
1316 * disassemble.c (ARCH_bpf): Define.
1317 (disassembler): Add case for bfd_arch_bpf.
1318 (disassemble_init_for_target): Likewise.
1319 (enum epbf_isa_attr): Define.
1320 * disassemble.h: extern print_insn_bpf.
1321 * bpf-asm.c: Generated.
1322 * bpf-opc.h: Likewise.
1323 * bpf-opc.c: Likewise.
1324 * bpf-ibld.c: Likewise.
1325 * bpf-dis.c: Likewise.
1326 * bpf-desc.h: Likewise.
1327 * bpf-desc.c: Likewise.
1328
ba6cd17f
SD		 13292019-05-21 Sudakshina Das <sudi.das@arm.com>
1330
1331 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1332 and VMSR with the new operands.
1333
e39c1607
SD		 13342019-05-21 Sudakshina Das <sudi.das@arm.com>
1335
1336 * arm-dis.c (enum mve_instructions): New enum
1337 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1338 and cneg.
1339 (mve_opcodes): New instructions as above.
1340 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1341 csneg and csel.
1342 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1343
23d00a41
SD		 13442019-05-21 Sudakshina Das <sudi.das@arm.com>
1345
1346 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1347 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1348 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1349 uqshl, urshrl and urshr.
1350 (is_mve_okay_in_it): Add new instructions to TRUE list.
1351 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1352 (print_insn_mve): Updated to accept new %j,
1353 %<bitfield>m and %<bitfield>n patterns.
1354
cd4797ee
FS		 13552019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1356
1357 * mips-opc.c (mips_builtin_opcodes): Change source register
1358 constraint for DAUI.
1359
999b073b
NC		 13602019-05-20 Nick Clifton <nickc@redhat.com>
1361
1362 * po/fr.po: Updated French translation.
1363
14b456f2
AV		 13642019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1365 Michael Collison <michael.collison@arm.com>
1366
1367 * arm-dis.c (thumb32_opcodes): Add new instructions.
1368 (enum mve_instructions): Likewise.
1369 (enum mve_undefined): Add new reasons.
1370 (is_mve_encoding_conflict): Handle new instructions.
1371 (is_mve_undefined): Likewise.
1372 (is_mve_unpredictable): Likewise.
1373 (print_mve_undefined): Likewise.
1374 (print_mve_size): Likewise.
1375
f49bb598
AV		 13762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1377 Michael Collison <michael.collison@arm.com>
1378
1379 * arm-dis.c (thumb32_opcodes): Add new instructions.
1380 (enum mve_instructions): Likewise.
1381 (is_mve_encoding_conflict): Handle new instructions.
1382 (is_mve_undefined): Likewise.
1383 (is_mve_unpredictable): Likewise.
1384 (print_mve_size): Likewise.
1385
56858bea
AV		 13862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1387 Michael Collison <michael.collison@arm.com>
1388
1389 * arm-dis.c (thumb32_opcodes): Add new instructions.
1390 (enum mve_instructions): Likewise.
1391 (is_mve_encoding_conflict): Likewise.
1392 (is_mve_unpredictable): Likewise.
1393 (print_mve_size): Likewise.
1394
e523f101
AV		 13952019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1396 Michael Collison <michael.collison@arm.com>
1397
1398 * arm-dis.c (thumb32_opcodes): Add new instructions.
1399 (enum mve_instructions): Likewise.
1400 (is_mve_encoding_conflict): Handle new instructions.
1401 (is_mve_undefined): Likewise.
1402 (is_mve_unpredictable): Likewise.
1403 (print_mve_size): Likewise.
1404
66dcaa5d
AV		 14052019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1406 Michael Collison <michael.collison@arm.com>
1407
1408 * arm-dis.c (thumb32_opcodes): Add new instructions.
1409 (enum mve_instructions): Likewise.
1410 (is_mve_encoding_conflict): Handle new instructions.
1411 (is_mve_undefined): Likewise.
1412 (is_mve_unpredictable): Likewise.
1413 (print_mve_size): Likewise.
1414 (print_insn_mve): Likewise.
1415
d052b9b7
AV		 14162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1417 Michael Collison <michael.collison@arm.com>
1418
1419 * arm-dis.c (thumb32_opcodes): Add new instructions.
1420 (print_insn_thumb32): Handle new instructions.
1421
ed63aa17
AV		 14222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1423 Michael Collison <michael.collison@arm.com>
1424
1425 * arm-dis.c (enum mve_instructions): Add new instructions.
1426 (enum mve_undefined): Add new reasons.
1427 (is_mve_encoding_conflict): Handle new instructions.
1428 (is_mve_undefined): Likewise.
1429 (is_mve_unpredictable): Likewise.
1430 (print_mve_undefined): Likewise.
1431 (print_mve_size): Likewise.
1432 (print_mve_shift_n): Likewise.
1433 (print_insn_mve): Likewise.
1434
897b9bbc
AV		 14352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1436 Michael Collison <michael.collison@arm.com>
1437
1438 * arm-dis.c (enum mve_instructions): Add new instructions.
1439 (is_mve_encoding_conflict): Handle new instructions.
1440 (is_mve_unpredictable): Likewise.
1441 (print_mve_rotate): Likewise.
1442 (print_mve_size): Likewise.
1443 (print_insn_mve): Likewise.
1444
1c8f2df8
AV		 14452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1446 Michael Collison <michael.collison@arm.com>
1447
1448 * arm-dis.c (enum mve_instructions): Add new instructions.
1449 (is_mve_encoding_conflict): Handle new instructions.
1450 (is_mve_unpredictable): Likewise.
1451 (print_mve_size): Likewise.
1452 (print_insn_mve): Likewise.
1453
d3b63143
AV		 14542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1455 Michael Collison <michael.collison@arm.com>
1456
1457 * arm-dis.c (enum mve_instructions): Add new instructions.
1458 (enum mve_undefined): Add new reasons.
1459 (is_mve_encoding_conflict): Handle new instructions.
1460 (is_mve_undefined): Likewise.
1461 (is_mve_unpredictable): Likewise.
1462 (print_mve_undefined): Likewise.
1463 (print_mve_size): Likewise.
1464 (print_insn_mve): Likewise.
1465
14925797
AV		 14662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1467 Michael Collison <michael.collison@arm.com>
1468
1469 * arm-dis.c (enum mve_instructions): Add new instructions.
1470 (is_mve_encoding_conflict): Handle new instructions.
1471 (is_mve_undefined): Likewise.
1472 (is_mve_unpredictable): Likewise.
1473 (print_mve_size): Likewise.
1474 (print_insn_mve): Likewise.
1475
c507f10b
AV		 14762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1477 Michael Collison <michael.collison@arm.com>
1478
1479 * arm-dis.c (enum mve_instructions): Add new instructions.
1480 (enum mve_unpredictable): Add new reasons.
1481 (enum mve_undefined): Likewise.
1482 (is_mve_okay_in_it): Handle new isntructions.
1483 (is_mve_encoding_conflict): Likewise.
1484 (is_mve_undefined): Likewise.
1485 (is_mve_unpredictable): Likewise.
1486 (print_mve_vmov_index): Likewise.
1487 (print_simd_imm8): Likewise.
1488 (print_mve_undefined): Likewise.
1489 (print_mve_unpredictable): Likewise.
1490 (print_mve_size): Likewise.
1491 (print_insn_mve): Likewise.
1492
bf0b396d
AV		 14932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1494 Michael Collison <michael.collison@arm.com>
1495
1496 * arm-dis.c (enum mve_instructions): Add new instructions.
1497 (enum mve_unpredictable): Add new reasons.
1498 (enum mve_undefined): Likewise.
1499 (is_mve_encoding_conflict): Handle new instructions.
1500 (is_mve_undefined): Likewise.
1501 (is_mve_unpredictable): Likewise.
1502 (print_mve_undefined): Likewise.
1503 (print_mve_unpredictable): Likewise.
1504 (print_mve_rounding_mode): Likewise.
1505 (print_mve_vcvt_size): Likewise.
1506 (print_mve_size): Likewise.
1507 (print_insn_mve): Likewise.
1508
ef1576a1
AV		 15092019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1510 Michael Collison <michael.collison@arm.com>
1511
1512 * arm-dis.c (enum mve_instructions): Add new instructions.
1513 (enum mve_unpredictable): Add new reasons.
1514 (enum mve_undefined): Likewise.
1515 (is_mve_undefined): Handle new instructions.
1516 (is_mve_unpredictable): Likewise.
1517 (print_mve_undefined): Likewise.
1518 (print_mve_unpredictable): Likewise.
1519 (print_mve_size): Likewise.
1520 (print_insn_mve): Likewise.
1521
aef6d006
AV		 15222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1523 Michael Collison <michael.collison@arm.com>
1524
1525 * arm-dis.c (enum mve_instructions): Add new instructions.
1526 (enum mve_undefined): Add new reasons.
1527 (insns): Add new instructions.
1528 (is_mve_encoding_conflict):
1529 (print_mve_vld_str_addr): New print function.
1530 (is_mve_undefined): Handle new instructions.
1531 (is_mve_unpredictable): Likewise.
1532 (print_mve_undefined): Likewise.
1533 (print_mve_size): Likewise.
1534 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1535 (print_insn_mve): Handle new operands.
1536
04d54ace
AV		 15372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1538 Michael Collison <michael.collison@arm.com>
1539
1540 * arm-dis.c (enum mve_instructions): Add new instructions.
1541 (enum mve_unpredictable): Add new reasons.
1542 (is_mve_encoding_conflict): Handle new instructions.
1543 (is_mve_unpredictable): Likewise.
1544 (mve_opcodes): Add new instructions.
1545 (print_mve_unpredictable): Handle new reasons.
1546 (print_mve_register_blocks): New print function.
1547 (print_mve_size): Handle new instructions.
1548 (print_insn_mve): Likewise.
1549
9743db03
AV		 15502019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1551 Michael Collison <michael.collison@arm.com>
1552
1553 * arm-dis.c (enum mve_instructions): Add new instructions.
1554 (enum mve_unpredictable): Add new reasons.
1555 (enum mve_undefined): Likewise.
1556 (is_mve_encoding_conflict): Handle new instructions.
1557 (is_mve_undefined): Likewise.
1558 (is_mve_unpredictable): Likewise.
1559 (coprocessor_opcodes): Move NEON VDUP from here...
1560 (neon_opcodes): ... to here.
1561 (mve_opcodes): Add new instructions.
1562 (print_mve_undefined): Handle new reasons.
1563 (print_mve_unpredictable): Likewise.
1564 (print_mve_size): Handle new instructions.
1565 (print_insn_neon): Handle vdup.
1566 (print_insn_mve): Handle new operands.
1567
143275ea
AV		 15682019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1569 Michael Collison <michael.collison@arm.com>
1570
1571 * arm-dis.c (enum mve_instructions): Add new instructions.
1572 (enum mve_unpredictable): Add new values.
1573 (mve_opcodes): Add new instructions.
1574 (vec_condnames): New array with vector conditions.
1575 (mve_predicatenames): New array with predicate suffixes.
1576 (mve_vec_sizename): New array with vector sizes.
1577 (enum vpt_pred_state): New enum with vector predication states.
1578 (struct vpt_block): New struct type for vpt blocks.
1579 (vpt_block_state): Global struct to keep track of state.
1580 (mve_extract_pred_mask): New helper function.
1581 (num_instructions_vpt_block): Likewise.
1582 (mark_outside_vpt_block): Likewise.
1583 (mark_inside_vpt_block): Likewise.
1584 (invert_next_predicate_state): Likewise.
1585 (update_next_predicate_state): Likewise.
1586 (update_vpt_block_state): Likewise.
1587 (is_vpt_instruction): Likewise.
1588 (is_mve_encoding_conflict): Add entries for new instructions.
1589 (is_mve_unpredictable): Likewise.
1590 (print_mve_unpredictable): Handle new cases.
1591 (print_instruction_predicate): Likewise.
1592 (print_mve_size): New function.
1593 (print_vec_condition): New function.
1594 (print_insn_mve): Handle vpt blocks and new print operands.
1595
f08d8ce3
AV		 15962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1597
1598 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1599 8, 14 and 15 for Armv8.1-M Mainline.
1600
73cd51e5
AV		 16012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1602 Michael Collison <michael.collison@arm.com>
1603
1604 * arm-dis.c (enum mve_instructions): New enum.
1605 (enum mve_unpredictable): Likewise.
1606 (enum mve_undefined): Likewise.
1607 (struct mopcode32): New struct.
1608 (is_mve_okay_in_it): New function.
1609 (is_mve_architecture): Likewise.
1610 (arm_decode_field): Likewise.
1611 (arm_decode_field_multiple): Likewise.
1612 (is_mve_encoding_conflict): Likewise.
1613 (is_mve_undefined): Likewise.
1614 (is_mve_unpredictable): Likewise.
1615 (print_mve_undefined): Likewise.
1616 (print_mve_unpredictable): Likewise.
1617 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1618 (print_insn_mve): New function.
1619 (print_insn_thumb32): Handle MVE architecture.
1620 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1621
3076e594
NC		 16222019-05-10 Nick Clifton <nickc@redhat.com>
1623
1624 PR 24538
1625 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1626 end of the table prematurely.
1627
387e7624
FS		 16282019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1629
1630 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1631 macros for R6.
1632
0067be51
AM		 16332019-05-11 Alan Modra <amodra@gmail.com>
1634
1635 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1636 when -Mraw is in effect.
1637
42e6288f
MM		 16382019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1639
1640 * aarch64-dis-2.c: Regenerate.
1641 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1642 (OP_SVE_BBB): New variant set.
1643 (OP_SVE_DDDD): New variant set.
1644 (OP_SVE_HHH): New variant set.
1645 (OP_SVE_HHHU): New variant set.
1646 (OP_SVE_SSS): New variant set.
1647 (OP_SVE_SSSU): New variant set.
1648 (OP_SVE_SHH): New variant set.
1649 (OP_SVE_SBBU): New variant set.
1650 (OP_SVE_DSS): New variant set.
1651 (OP_SVE_DHHU): New variant set.
1652 (OP_SVE_VMV_HSD_BHS): New variant set.
1653 (OP_SVE_VVU_HSD_BHS): New variant set.
1654 (OP_SVE_VVVU_SD_BH): New variant set.
1655 (OP_SVE_VVVU_BHSD): New variant set.
1656 (OP_SVE_VVV_QHD_DBS): New variant set.
1657 (OP_SVE_VVV_HSD_BHS): New variant set.
1658 (OP_SVE_VVV_HSD_BHS2): New variant set.
1659 (OP_SVE_VVV_BHS_HSD): New variant set.
1660 (OP_SVE_VV_BHS_HSD): New variant set.
1661 (OP_SVE_VVV_SD): New variant set.
1662 (OP_SVE_VVU_BHS_HSD): New variant set.
1663 (OP_SVE_VZVV_SD): New variant set.
1664 (OP_SVE_VZVV_BH): New variant set.
1665 (OP_SVE_VZV_SD): New variant set.
1666 (aarch64_opcode_table): Add sve2 instructions.
1667
28ed815a
MM		 16682019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1669
1670 * aarch64-asm-2.c: Regenerated.
1671 * aarch64-dis-2.c: Regenerated.
1672 * aarch64-opc-2.c: Regenerated.
1673 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1674 for SVE_SHLIMM_UNPRED_22.
1675 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1676 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1677 operand.
1678
fd1dc4a0
MM		 16792019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1680
1681 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1682 sve_size_tsz_bhs iclass encode.
1683 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1684 sve_size_tsz_bhs iclass decode.
1685
31e36ab3
MM		 16862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1687
1688 * aarch64-asm-2.c: Regenerated.
1689 * aarch64-dis-2.c: Regenerated.
1690 * aarch64-opc-2.c: Regenerated.
1691 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1692 for SVE_Zm4_11_INDEX.
1693 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1694 (fields): Handle SVE_i2h field.
1695 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1696 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1697
1be5f94f
MM		 16982019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1699
1700 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1701 sve_shift_tsz_bhsd iclass encode.
1702 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1703 sve_shift_tsz_bhsd iclass decode.
1704
3c17238b
MM		 17052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1706
1707 * aarch64-asm-2.c: Regenerated.
1708 * aarch64-dis-2.c: Regenerated.
1709 * aarch64-opc-2.c: Regenerated.
1710 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1711 (aarch64_encode_variant_using_iclass): Handle
1712 sve_shift_tsz_hsd iclass encode.
1713 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1714 sve_shift_tsz_hsd iclass decode.
1715 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1716 for SVE_SHRIMM_UNPRED_22.
1717 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1718 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1719 operand.
1720
cd50a87a
MM		 17212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1722
1723 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1724 sve_size_013 iclass encode.
1725 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1726 sve_size_013 iclass decode.
1727
3c705960
MM		 17282019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1729
1730 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1731 sve_size_bh iclass encode.
1732 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1733 sve_size_bh iclass decode.
1734
0a57e14f
MM		 17352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1736
1737 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1738 sve_size_sd2 iclass encode.
1739 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1740 sve_size_sd2 iclass decode.
1741 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1742 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1743
c469c864
MM		 17442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1745
1746 * aarch64-asm-2.c: Regenerated.
1747 * aarch64-dis-2.c: Regenerated.
1748 * aarch64-opc-2.c: Regenerated.
1749 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1750 for SVE_ADDR_ZX.
1751 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1752 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1753
116adc27
MM		 17542019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1755
1756 * aarch64-asm-2.c: Regenerated.
1757 * aarch64-dis-2.c: Regenerated.
1758 * aarch64-opc-2.c: Regenerated.
1759 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1760 for SVE_Zm3_11_INDEX.
1761 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1762 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1763 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1764 fields.
1765 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1766
3bd82c86
MM		 17672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1768
1769 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1770 sve_size_hsd2 iclass encode.
1771 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1772 sve_size_hsd2 iclass decode.
1773 * aarch64-opc.c (fields): Handle SVE_size field.
1774 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1775
adccc507
MM		 17762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1777
1778 * aarch64-asm-2.c: Regenerated.
1779 * aarch64-dis-2.c: Regenerated.
1780 * aarch64-opc-2.c: Regenerated.
1781 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1782 for SVE_IMM_ROT3.
1783 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1784 (fields): Handle SVE_rot3 field.
1785 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1786 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1787
5cd99750
MM		 17882019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1789
1790 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1791 instructions.
1792
7ce2460a
MM		 17932019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1794
1795 * aarch64-tbl.h
1796 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1797 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1798 aarch64_feature_sve2bitperm): New feature sets.
1799 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1800 for feature set addresses.
1801 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1802 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1803
41cee089
FS		 18042019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1805 Faraz Shahbazker <fshahbazker@wavecomp.com>
1806
1807 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1808 argument and set ASE_EVA_R6 appropriately.
1809 (set_default_mips_dis_options): Pass ISA to above.
1810 (parse_mips_dis_option): Likewise.
1811 * mips-opc.c (EVAR6): New macro.
1812 (mips_builtin_opcodes): Add llwpe, scwpe.
1813
b83b4b13
SD		 18142019-05-01 Sudakshina Das <sudi.das@arm.com>
1815
1816 * aarch64-asm-2.c: Regenerated.
1817 * aarch64-dis-2.c: Regenerated.
1818 * aarch64-opc-2.c: Regenerated.
1819 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1820 AARCH64_OPND_TME_UIMM16.
1821 (aarch64_print_operand): Likewise.
1822 * aarch64-tbl.h (QL_IMM_NIL): New.
1823 (TME): New.
1824 (_TME_INSN): New.
1825 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1826
4a90ce95
JD		 18272019-04-29 John Darrington <john@darrington.wattle.id.au>
1828
1829 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1830
a45328b9
AB		 18312019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1832 Faraz Shahbazker <fshahbazker@wavecomp.com>
1833
1834 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1835
d10be0cb
JD		 18362019-04-24 John Darrington <john@darrington.wattle.id.au>
1837
1838 * s12z-opc.h: Add extern "C" bracketing to help
1839 users who wish to use this interface in c++ code.
1840
a679f24e
JD		 18412019-04-24 John Darrington <john@darrington.wattle.id.au>
1842
1843 * s12z-opc.c (bm_decode): Handle bit map operations with the
1844 "reserved0" mode.
1845
32c36c3c
AV		 18462019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1847
1848 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1849 specifier. Add entries for VLDR and VSTR of system registers.
1850 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1851 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1852 of %J and %K format specifier.
1853
efd6b359
AV		 18542019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1855
1856 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1857 Add new entries for VSCCLRM instruction.
1858 (print_insn_coprocessor): Handle new %C format control code.
1859
6b0dd094
AV		 18602019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1861
1862 * arm-dis.c (enum isa): New enum.
1863 (struct sopcode32): New structure.
1864 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1865 set isa field of all current entries to ANY.
1866 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1867 Only match an entry if its isa field allows the current mode.
1868
4b5a202f
AV		 18692019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1870
1871 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1872 CLRM.
1873 (print_insn_thumb32): Add logic to print %n CLRM register list.
1874
60f993ce
AV		 18752019-04-15 Sudakshina Das <sudi.das@arm.com>
1876
1877 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1878 and %Q patterns.
1879
f6b2b12d
AV		 18802019-04-15 Sudakshina Das <sudi.das@arm.com>
1881
1882 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1883 (print_insn_thumb32): Edit the switch case for %Z.
1884
1889da70
AV		 18852019-04-15 Sudakshina Das <sudi.das@arm.com>
1886
1887 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1888
65d1bc05
AV		 18892019-04-15 Sudakshina Das <sudi.das@arm.com>
1890
1891 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1892
1caf72a5
AV		 18932019-04-15 Sudakshina Das <sudi.das@arm.com>
1894
1895 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1896
f1c7f421
AV		 18972019-04-15 Sudakshina Das <sudi.das@arm.com>
1898
1899 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1900 Arm register with r13 and r15 unpredictable.
1901 (thumb32_opcodes): New instructions for bfx and bflx.
1902
4389b29a
AV		 19032019-04-15 Sudakshina Das <sudi.das@arm.com>
1904
1905 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1906
e5d6e09e
AV		 19072019-04-15 Sudakshina Das <sudi.das@arm.com>
1908
1909 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1910
e12437dc
AV		 19112019-04-15 Sudakshina Das <sudi.das@arm.com>
1912
1913 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1914
031254f2
AV		 19152019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1916
1917 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1918
e5a557ac
JD		 19192019-04-12 John Darrington <john@darrington.wattle.id.au>
1920
1921 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1922 "optr". ("operator" is a reserved word in c++).
1923
bd7ceb8d
SD		 19242019-04-11 Sudakshina Das <sudi.das@arm.com>
1925
1926 * aarch64-opc.c (aarch64_print_operand): Add case for
1927 AARCH64_OPND_Rt_SP.
1928 (verify_constraints): Likewise.
1929 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1930 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1931 to accept Rt|SP as first operand.
1932 (AARCH64_OPERANDS): Add new Rt_SP.
1933 * aarch64-asm-2.c: Regenerated.
1934 * aarch64-dis-2.c: Regenerated.
1935 * aarch64-opc-2.c: Regenerated.
1936
e54010f1
SD		 19372019-04-11 Sudakshina Das <sudi.das@arm.com>
1938
1939 * aarch64-asm-2.c: Regenerated.
1940 * aarch64-dis-2.c: Likewise.
1941 * aarch64-opc-2.c: Likewise.
1942 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1943
7e96e219
RS		 19442019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1945
1946 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1947
6f2791d5
L		 19482019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1949
1950 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1951 * i386-init.h: Regenerated.
1952
e392bad3
AM		 19532019-04-07 Alan Modra <amodra@gmail.com>
1954
1955 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1956 op_separator to control printing of spaces, comma and parens
1957 rather than need_comma, need_paren and spaces vars.
1958
dffaa15c
AM		 19592019-04-07 Alan Modra <amodra@gmail.com>
1960
1961 PR 24421
1962 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1963 (print_insn_neon, print_insn_arm): Likewise.
1964
d6aab7a1
XG		 19652019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1966
1967 * i386-dis-evex.h (evex_table): Updated to support BF16
1968 instructions.
1969 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1970 and EVEX_W_0F3872_P_3.
1971 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1972 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1973 * i386-opc.h (enum): Add CpuAVX512_BF16.
1974 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1975 * i386-opc.tbl: Add AVX512 BF16 instructions.
1976 * i386-init.h: Regenerated.
1977 * i386-tbl.h: Likewise.
1978
66e85460
AM		 19792019-04-05 Alan Modra <amodra@gmail.com>
1980
1981 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1982 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1983 to favour printing of "-" branch hint when using the "y" bit.
1984 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1985
c2b1c275
AM		 19862019-04-05 Alan Modra <amodra@gmail.com>
1987
1988 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1989 opcode until first operand is output.
1990
aae9718e
PB		 19912019-04-04 Peter Bergner <bergner@linux.ibm.com>
1992
1993 PR gas/24349
1994 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1995 (valid_bo_post_v2): Add support for 'at' branch hints.
1996 (insert_bo): Only error on branch on ctr.
1997 (get_bo_hint_mask): New function.
1998 (insert_boe): Add new 'branch_taken' formal argument. Add support
1999 for inserting 'at' branch hints.
2000 (extract_boe): Add new 'branch_taken' formal argument. Add support
2001 for extracting 'at' branch hints.
2002 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2003 (BOE): Delete operand.
2004 (BOM, BOP): New operands.
2005 (RM): Update value.
2006 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2007 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2008 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2009 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2010 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2011 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2012 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2013 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2014 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2015 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2016 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2017 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2018 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2019 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2020 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2021 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2022 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2023 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2024 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2025 bttarl+>: New extended mnemonics.
2026
96a86c01
AM		 20272019-03-28 Alan Modra <amodra@gmail.com>
2028
2029 PR 24390
2030 * ppc-opc.c (BTF): Define.
2031 (powerpc_opcodes): Use for mtfsb*.
2032 * ppc-dis.c (print_insn_powerpc): Print fields with both
2033 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2034
796d6298
TC		 20352019-03-25 Tamar Christina <tamar.christina@arm.com>
2036
2037 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2038 (mapping_symbol_for_insn): Implement new algorithm.
2039 (print_insn): Remove duplicate code.
2040
60df3720
TC		 20412019-03-25 Tamar Christina <tamar.christina@arm.com>
2042
2043 * aarch64-dis.c (print_insn_aarch64):
2044 Implement override.
2045
51457761
TC		 20462019-03-25 Tamar Christina <tamar.christina@arm.com>
2047
2048 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2049 order.
2050
53b2f36b
TC		 20512019-03-25 Tamar Christina <tamar.christina@arm.com>
2052
2053 * aarch64-dis.c (last_stop_offset): New.
2054 (print_insn_aarch64): Use stop_offset.
2055
89199bb5
L		 20562019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2057
2058 PR gas/24359
2059 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2060 CPU_ANY_AVX2_FLAGS.
2061 * i386-init.h: Regenerated.
2062
97ed31ae
L		 20632019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2064
2065 PR gas/24348
2066 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2067 vmovdqu16, vmovdqu32 and vmovdqu64.
2068 * i386-tbl.h: Regenerated.
2069
0919bfe9
AK		 20702019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2071
2072 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2073 from vstrszb, vstrszh, and vstrszf.
2074
20752019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2076
2077 * s390-opc.txt: Add instruction descriptions.
2078
21820ebe
JW		 20792019-02-08 Jim Wilson <jimw@sifive.com>
2080
2081 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2082 <bne>: Likewise.
2083
f7dd2fb2
TC		 20842019-02-07 Tamar Christina <tamar.christina@arm.com>
2085
2086 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2087
6456d318
TC		 20882019-02-07 Tamar Christina <tamar.christina@arm.com>
2089
2090 PR binutils/23212
2091 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2092 * aarch64-opc.c (verify_elem_sd): New.
2093 (fields): Add FLD_sz entr.
2094 * aarch64-tbl.h (_SIMD_INSN): New.
2095 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2096 fmulx scalar and vector by element isns.
2097
4a83b610
NC		 20982019-02-07 Nick Clifton <nickc@redhat.com>
2099
2100 * po/sv.po: Updated Swedish translation.
2101
fc60b8c8
AK		 21022019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2103
2104 * s390-mkopc.c (main): Accept arch13 as cpu string.
2105 * s390-opc.c: Add new instruction formats and instruction opcode
2106 masks.
2107 * s390-opc.txt: Add new arch13 instructions.
2108
e10620d3
TC		 21092019-01-25 Sudakshina Das <sudi.das@arm.com>
2110
2111 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2112 (aarch64_opcode): Change encoding for stg, stzg
2113 st2g and st2zg.
2114 * aarch64-asm-2.c: Regenerated.
2115 * aarch64-dis-2.c: Regenerated.
2116 * aarch64-opc-2.c: Regenerated.
2117
20a4ca55
SD		 21182019-01-25 Sudakshina Das <sudi.das@arm.com>
2119
2120 * aarch64-asm-2.c: Regenerated.
2121 * aarch64-dis-2.c: Likewise.
2122 * aarch64-opc-2.c: Likewise.
2123 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2124
550fd7bf
SD		 21252019-01-25 Sudakshina Das <sudi.das@arm.com>
2126 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2127
2128 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2129 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2130 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2131 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2132 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2133 case for ldstgv_indexed.
2134 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2135 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2136 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2137 * aarch64-asm-2.c: Regenerated.
2138 * aarch64-dis-2.c: Regenerated.
2139 * aarch64-opc-2.c: Regenerated.
2140
d9938630
NC		 21412019-01-23 Nick Clifton <nickc@redhat.com>
2142
2143 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2144
375cd423
NC		 21452019-01-21 Nick Clifton <nickc@redhat.com>
2146
2147 * po/de.po: Updated German translation.
2148 * po/uk.po: Updated Ukranian translation.
2149
57299f48
CX		 21502019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2151 * mips-dis.c (mips_arch_choices): Fix typo in
2152 gs464, gs464e and gs264e descriptors.
2153
f48dfe41
NC		 21542019-01-19 Nick Clifton <nickc@redhat.com>
2155
2156 * configure: Regenerate.
2157 * po/opcodes.pot: Regenerate.
2158
f974f26c
NC		 21592018-06-24 Nick Clifton <nickc@redhat.com>
2160
2161 2.32 branch created.
2162
39f286cd
JD		 21632019-01-09 John Darrington <john@darrington.wattle.id.au>
2164
448b8ca8
JD		 2165 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2166 if it is null.
2167 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2168 zero.
2169
3107326d
AP		 21702019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2171
2172 * configure: Regenerate.
2173
7e9ca91e
AM		 21742019-01-07 Alan Modra <amodra@gmail.com>
2175
2176 * configure: Regenerate.
2177 * po/POTFILES.in: Regenerate.
2178
ef1ad42b
JD		 21792019-01-03 John Darrington <john@darrington.wattle.id.au>
2180
2181 * s12z-opc.c: New file.
2182 * s12z-opc.h: New file.
2183 * s12z-dis.c: Removed all code not directly related to display
2184 of instructions. Used the interface provided by the new files
2185 instead.
2186 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2187 * Makefile.in: Regenerate.
ef1ad42b 2188 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2189 * configure: Regenerate.
ef1ad42b 2190
82704155
AM		 21912019-01-01 Alan Modra <amodra@gmail.com>
2192
2193 Update year range in copyright notice of all files.
2194
d5c04e1b 2195For older changes see ChangeLog-2018
3499769a 2196\f
d5c04e1b 2197Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2198
2199Copying and distribution of this file, with or without modification,
2200are permitted in any medium without royalty provided the copyright
2201notice and this notice are preserved.
2202
2203Local Variables:
2204mode: change-log
2205left-margin: 8
2206fill-column: 74
2207version-control: never
2208End:
GDB Binutils - Deliverables
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