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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d17dce55
AM		 12012-11-05 Alan Modra <amodra@gmail.com>
2
3 * configure.in: Apply 2012-09-10 change to config.in here.
4
aac129d7
AK		 52012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
6
7 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
d17dce55
AM		 8 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
9 and RRF_RMRR.
aac129d7
AK		 10 * s390-opc.txt: Add new instructions. New instruction type for lptea.
11
747a4ac1
CG		 122012-10-26 Christian Groessler <chris@groessler.org>
13
14 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
15 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
16 non-existing opcode trtrb.
17 * z8k-opc.h: Regenerate.
18
62082a42
AM		 192012-10-26 Alan Modra <amodra@gmail.com>
20
21 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
22
6c067bbb
RM		 232012-10-24 Roland McGrath <mcgrathr@google.com>
24
25 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
26 set rex_used to rex.
27
ab4437c3
PB		 282012-10-22 Peter Bergner <bergner@vnet.ibm.com>
29
30 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
31
9a176a4a
TT		 322012-10-18 Tom Tromey <tromey@redhat.com>
33
34 * tic54x-dis.c (print_instruction): Don't use K&R style.
35 (print_parallel_instruction, sprint_dual_address)
36 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
37 (sprint_cc2, sprint_condition): Likewise.
38
4ad3b7ef
KT		 392012-10-18 Kai Tietz <ktietz@redhat.com>
40
41 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
42 value with a default.
43 (do_special_encoding): Likewise.
44 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
45 variables with default.
46 * arc-dis.c (write_comments_): Don't use strncat due
47 size of state->commentBuffer pointer isn't predictable.
48
b7a54b55
YZ		 492012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
50
51 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
52 rmr_el3; remove daifset and daifclr.
53
9b61754a
YZ		 542012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
55
56 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
57 the alignment of addr.offset.imm instead of that of shifter.amount for
58 operand type AARCH64_OPND_ADDR_UIMM12.
59
f8ece37f
RE		 602012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
61
62 * arm-dis.c: Use preferred form of vrint instruction variants
63 for disassembly.
64
5e5c50d3
NE		 652012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
66
67 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
68 * i386-init.h: Regenerated.
69
c7a5aa9c
PB		 702012-10-05 Peter Bergner <bergner@vnet.ibm.com>
71
72 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
73 * ppc-opc.c (VBA): New define.
74 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
75 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
76
04ee5257
NC		 772012-10-04 Nick Clifton <nickc@redhat.com>
78
79 * v850-dis.c (disassemble): Place square parentheses around second
80 register operand of clr1, not1, set1 and tst1 instructions.
81
cfc72779
AK		 822012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
83
84 * s390-mkopc.c: Support new option zEC12.
85 * s390-opc.c: Add new instruction formats.
86 * s390-opc.txt: Add new instructions for zEC12.
87
1415a2a7
AG		 882012-09-27 Anthony Green <green@moxielogic.com>
89
90 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
91 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
92
160a30bb
L		 932012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
94
04ee5257
NC		 95 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
96 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 97 and CPU_BTVER2_FLAGS.
98 * i386-init.h: Regenerated.
99
60aa667e
L		 1002012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
101
102 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
103 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
104 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
105 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
106 (cpu_flags): Add CpuCX16.
107 * i386-opc.h (CpuCX16): New.
108 (i386_cpu_flags): Add cpucx16.
109 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
110 * i386-tbl.h: Regenerate.
111 * i386-init.h: Likewise.
112
4b8c8c02
RE		 1132012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
114
60aa667e 115 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 116 to lda and stl-form.
117
83ea18d0
MR		 1182012-09-18 Chao-ying Fu <fu@mips.com>
119
120 * micromips-opc.c (micromips_opcodes): Correct the encoding of
121 the "swxc1" instruction.
122
062f38fa
RE		 1232012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
124
125 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
126 the parameter 'inst'.
127 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
128 (convert_mov_to_movewide): Change to assert (0) when
129 aarch64_wide_constant_p returns FALSE.
130
b132a67d
DE		 1312012-09-14 David Edelsohn <dje.gcc@gmail.com>
132
133 * configure: Regenerate.
134
1f9b75dd
AG		 1352012-09-14 Anthony Green <green@moxielogic.com>
136
137 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
138 the address after the branch instruction.
139
e202fa84
AG		 1402012-09-13 Anthony Green <green@moxielogic.com>
141
142 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
143
00716ab1
AM		 1442012-09-10 Matthias Klose <doko@ubuntu.com>
145
146 * config.in: Disable sanity check for kfreebsd.
147
6d2920c8
L		 1482012-09-10 H.J. Lu <hongjiu.lu@intel.com>
149
150 * configure: Regenerated.
151
b3e14eda
L		 1522012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
153
154 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
155 * ia64-gen.c: Promote completer index type to longlong.
156 (irf_operand): Add new register recognition.
157 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
158 (lookup_specifier): Add new resource recognition.
159 (insert_bit_table_ent): Relax abort condition according to the
160 changed completer index type.
161 (print_dis_table): Fix printf format for completer index.
162 * ia64-ic.tbl: Add a new instruction class.
163 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
164 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
165 * ia64-opc.h: Define short names for new operand types.
166 * ia64-raw.tbl: Add new RAW resource for DAHR register.
167 * ia64-waw.tbl: Add new WAW resource for DAHR register.
168 * ia64-asmtab.c: Regenerate.
169
382c72e9
PB		 1702012-08-29 Peter Bergner <bergner@vnet.ibm.com>
171
172 * ppc-opc.c (VXASHB_MASK): New define.
173 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
174
fb048c26
PB		 1752012-08-28 Peter Bergner <bergner@vnet.ibm.com>
176
177 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
178 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
179 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
180 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
181 vupklsh>: Use VXVA_MASK.
182 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
183 <mfvscr>: Use VXVAVB_MASK.
184 <mtvscr>: Use VXVDVA_MASK.
185 <vspltb>: Use VXUIMM4_MASK.
186 <vsplth>: Use VXUIMM3_MASK.
187 <vspltw>: Use VXUIMM2_MASK.
188
3c9017d2
MGD		 1892012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
190
191 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
192
48adcd8e
MGD		 1932012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
194
195 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
196
4f51b4bd
MGD		 1972012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
198
199 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
200
91ff7894
MGD		 2012012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
202
203 * arm-dis.c (neon_opcodes): Add support for AES instructions.
204
c70a8987
MGD		 2052012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
206
207 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
208 conversions.
209
30bdf752
MGD		 2102012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
211
212 * arm-dis.c (coprocessor_opcodes): Add VRINT.
213 (neon_opcodes): Likewise.
214
7e8e6784
MGD		 2152012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
216
217 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
218 variants.
219 (neon_opcodes): Likewise.
220
73924fbc
MGD		 2212012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
222
223 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
224 (neon_opcodes): Likewise.
225
33399f07
MGD		 2262012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
227
228 * arm-dis.c (coprocessor_opcodes): Add VSEL.
229 (print_insn_coprocessor): Add new %<>c bitfield format
230 specifier.
231
9eb6c0f1
MGD		 2322012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
233
234 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
235 (thumb32_opcodes): Likewise.
236 (print_arm_insn): Add support for %<>T formatter.
237
8884b720
MGD		 2382012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
239
240 * arm-dis.c (arm_opcodes): Add HLT.
241 (thumb_opcodes): Likewise.
242
b79f7053
MGD		 2432012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
244
245 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
246
53c4b28b
MGD		 2472012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
248
249 * arm-dis.c (arm_opcodes): Add SEVL.
250 (thumb_opcodes): Likewise.
251 (thumb32_opcodes): Likewise.
252
e797f7e0
MGD		 2532012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
254
255 * arm-dis.c (data_barrier_option): New function.
256 (print_insn_arm): Use data_barrier_option.
257 (print_insn_thumb32): Use data_barrier_option.
258
e2efe87d
MGD		 2592012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
260
261 * arm-dis.c (COND_UNCOND): New constant.
262 (print_insn_coprocessor): Add support for %u format specifier.
263 (print_insn_neon): Likewise.
264
2c63854f
DM		 2652012-08-21 David S. Miller <davem@davemloft.net>
266
267 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
268 F3F4 macro.
269
e67ed0e8
AM		 2702012-08-20 Edmar Wienskoski <edmar@freescale.com>
271
272 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
273 vabsduh, vabsduw, mviwsplt.
274
7b458c12
L		 2752012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
276
277 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
278 CPU_BTVER2_FLAGS.
279
e67ed0e8 280 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 281
282 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
283 * i386-init.h: Regenerated.
284 * i386-tbl.h: Likewise.
285
eb80cb87
NC		 2862012-08-17 Nick Clifton <nickc@redhat.com>
287
288 * po/uk.po: New Ukranian translation.
289 * configure.in (ALL_LINGUAS): Add uk.
290 * configure: Regenerate.
291
8baf7b78
PB		 2922012-08-16 Peter Bergner <bergner@vnet.ibm.com>
293
294 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
295 RBX for the third operand.
296 <"lswi">: Use RAX for second and NBI for the third operand.
297
3d557b4c
DD		 2982012-08-15 DJ Delorie <dj@redhat.com>
299
300 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
301 operands, so that data addresses can be corrected when not
302 ES-overridden.
303 * rl78-decode.c: Regenerate.
304 * rl78-dis.c (print_insn_rl78): Make order of modifiers
305 irrelevent. When the 'e' specifier is used on an operand and no
306 ES prefix is provided, adjust address to make it absolute.
307
588925d0
PB		 3082012-08-15 Peter Bergner <bergner@vnet.ibm.com>
309
310 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
311
9f6a6cc0
PB		 3122012-08-15 Peter Bergner <bergner@vnet.ibm.com>
313
314 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
315
fc8c4fd1
MR		 3162012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
317
318 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
319 macros, use local variables for info struct member accesses,
320 update the type of the variable used to hold the instruction
321 word.
322 (print_insn_mips, print_mips16_insn_arg): Likewise.
323 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
324 local variables for info struct member accesses.
325 (print_insn_micromips): Add GET_OP_S local macro.
326 (_print_insn_mips): Update the type of the variable used to hold
327 the instruction word.
328
a06ea964 3292012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 330 Laurent Desnogues <laurent.desnogues@arm.com>
331 Jim MacArthur <jim.macarthur@arm.com>
332 Marcus Shawcroft <marcus.shawcroft@arm.com>
333 Nigel Stephens <nigel.stephens@arm.com>
334 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
335 Richard Earnshaw <rearnsha@arm.com>
336 Sofiane Naci <sofiane.naci@arm.com>
337 Tejas Belagod <tejas.belagod@arm.com>
338 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 339
340 * Makefile.am: Add AArch64.
341 * Makefile.in: Regenerate.
342 * aarch64-asm.c: New file.
343 * aarch64-asm.h: New file.
344 * aarch64-dis.c: New file.
345 * aarch64-dis.h: New file.
346 * aarch64-gen.c: New file.
347 * aarch64-opc.c: New file.
348 * aarch64-opc.h: New file.
349 * aarch64-tbl.h: New file.
350 * configure.in: Add AArch64.
351 * configure: Regenerate.
352 * disassemble.c: Add AArch64.
353 * aarch64-asm-2.c: New file (automatically generated).
354 * aarch64-dis-2.c: New file (automatically generated).
355 * aarch64-opc-2.c: New file (automatically generated).
356 * po/POTFILES.in: Regenerate.
357
35d0a169
MR		 3582012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
359
360 * micromips-opc.c (micromips_opcodes): Update comment.
361 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
362 instructions for IOCT as appropriate.
363 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
364 opcode_is_member.
365 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
366 the result of a check for the -Wno-missing-field-initializers
367 GCC option.
368 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
369 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
370 compilation.
371 (mips16-opc.lo): Likewise.
372 (micromips-opc.lo): Likewise.
373 * aclocal.m4: Regenerate.
374 * configure: Regenerate.
375 * Makefile.in: Regenerate.
376
5c5acbbd
L		 3772012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
378
379 PR gas/14423
380 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
381 * i386-init.h: Regenerated.
382
3c892704
NC		 3832012-08-09 Nick Clifton <nickc@redhat.com>
384
385 * po/vi.po: Updated Vietnamese translation.
386
d7189fa5
RM		 3872012-08-07 Roland McGrath <mcgrathr@google.com>
388
389 * i386-dis.c (reg_table): Fill out REG_0F0D table with
390 AMD-reserved cases as "prefetch".
391 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
392 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
393 (reg_table): Use those under REG_0F18.
394 (mod_table): Add those cases as "nop/reserved".
395
4c692bc7
JB		 3962012-08-07 Jan Beulich <jbeulich@suse.com>
397
398 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
399
de882298
RM		 4002012-08-06 Roland McGrath <mcgrathr@google.com>
401
402 * i386-dis.c (print_insn): Print spaces between multiple excess
403 prefixes. Return actual number of excess prefixes consumed,
404 not always one.
405
406 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
407
7bb15c6f
RM		 4082012-08-06 Roland McGrath <mcgrathr@google.com>
409 Victor Khimenko <khim@google.com>
410 H.J. Lu <hongjiu.lu@intel.com>
411
412 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
413 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
414 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
415 (OP_E_register): Likewise.
416 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
417
3843081d
JBG		 4182012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
419
420 * configure.in: Formatting.
421 * configure: Regenerate.
422
48891606
AM		 4232012-08-01 Alan Modra <amodra@gmail.com>
424
425 * h8300-dis.c: Fix printf arg warnings.
426 * i960-dis.c: Likewise.
427 * mips-dis.c: Likewise.
428 * pdp11-dis.c: Likewise.
429 * sh-dis.c: Likewise.
430 * v850-dis.c: Likewise.
431 * configure.in: Formatting.
432 * configure: Regenerate.
433 * rl78-decode.c: Regenerate.
434 * po/POTFILES.in: Regenerate.
435
03f66e8a 4362012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 437 Catherine Moore <clm@codesourcery.com>
438 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 439
440 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
441 (DSP_VOLA): Likewise.
442 (D32, D33): Likewise.
443 (micromips_opcodes): Add DSP ASE instructions.
48891606 444 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 445 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
446
94948e64
JB		 4472012-07-31 Jan Beulich <jbeulich@suse.com>
448
449 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
450 instruction group. Mark as requiring AVX2.
451 * i386-tbl.h: Re-generate.
452
a6dc81d2
NC		 4532012-07-30 Nick Clifton <nickc@redhat.com>
454
455 * po/opcodes.pot: Updated template.
456 * po/es.po: Updated Spanish translation.
457 * po/fi.po: Updated Finnish translation.
458
c4dd807e
MF		 4592012-07-27 Mike Frysinger <vapier@gentoo.org>
460
461 * configure.in (BFD_VERSION): Run bfd/configure --version and
462 parse the output of that.
463 * configure: Regenerate.
464
03edbe3b
JL		 4652012-07-25 James Lemke <jwlemke@codesourcery.com>
466
467 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
468
63d08c68
NC		 4692012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
470 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 471
472 PR binutils/13135
473 * arm-dis.c: Add necessary casts for printing integer values.
474 Use %s when printing string values.
475 * hppa-dis.c: Likewise.
476 * m68k-dis.c: Likewise.
477 * microblaze-dis.c: Likewise.
478 * mips-dis.c: Likewise.
479 * sparc-dis.c: Likewise.
480
ff688e1f
L		 4812012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
482
483 PR binutils/14355
484 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
485 (VEX_LEN_0FXOP_08_CD): Likewise.
486 (VEX_LEN_0FXOP_08_CE): Likewise.
487 (VEX_LEN_0FXOP_08_CF): Likewise.
488 (VEX_LEN_0FXOP_08_EC): Likewise.
489 (VEX_LEN_0FXOP_08_ED): Likewise.
490 (VEX_LEN_0FXOP_08_EE): Likewise.
491 (VEX_LEN_0FXOP_08_EF): Likewise.
492 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
493 vpcomub, vpcomuw, vpcomud, vpcomuq.
494 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
495 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
496 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
497 VEX_LEN_0FXOP_08_EF.
498
e2e1fcde
L		 4992012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
500
501 * i386-dis.c (PREFIX_0F38F6): New.
502 (prefix_table): Add adcx, adox instructions.
503 (three_byte_table): Use PREFIX_0F38F6.
504 (mod_table): Add rdseed instruction.
505 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
506 (cpu_flags): Likewise.
507 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
508 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
509 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
510 prefetchw.
511 * i386-tbl.h: Regenerate.
512 * i386-init.h: Likewise.
513
8b99bf0b
TS		 5142012-07-05 Thomas Schwinge <thomas@codesourcery.com>
515
f4263ca2 516 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 517
416cf80a
SK		 5182012-07-05 Sean Keys <skeys@ipdatasys.com>
519
520 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 521 always be false due to overlapping operand masks.
522 * xgate-opc.c: Corrected 'com' opcode entry and
523 fixed spacing.
416cf80a 524
9fa0f14a
RM		 5252012-07-02 Roland McGrath <mcgrathr@google.com>
526
527 * i386-opc.tbl: Add RepPrefixOk to nop.
528 * i386-tbl.h: Regenerate.
529
4c6a93d3
NC		 5302012-06-28 Nick Clifton <nickc@redhat.com>
531
532 * po/vi.po: Updated Vietnamese translation.
533
29c048b6
RM		 5342012-06-22 Roland McGrath <mcgrathr@google.com>
535
fe13e45b
RM		 536 * i386-opc.tbl: Add RepPrefixOk to ret.
537 * i386-tbl.h: Regenerate.
538
29c048b6
RM		 539 * i386-opc.h (RepPrefixOk): New enum constant.
540 (i386_opcode_modifier): New bitfield 'repprefixok'.
541 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
542 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
543 instructions that have IsString.
544 * i386-tbl.h: Regenerate.
545
c7a8dbf9
AS		 5462012-06-11 Andreas Schwab <schwab@linux-m68k.org>
547
548 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
549 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
550 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
551 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
552 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
553 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
554 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
555 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
556 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
557
94caa966
AM		 5582012-05-19 Alan Modra <amodra@gmail.com>
559
560 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
561 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
562
5eb3690e
AM		 5632012-05-18 Alan Modra <amodra@gmail.com>
564
71fe7bab
AM		 565 * ia64-opc.c: Remove #include "ansidecl.h".
566 * z8kgen.c: Include sysdep.h first.
567
5eb3690e
AM		 568 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
569 * bfin-dis.c: Likewise.
570 * i860-dis.c: Likewise.
571 * ia64-dis.c: Likewise.
572 * ia64-gen.c: Likewise.
573 * m68hc11-dis.c: Likewise.
574 * mmix-dis.c: Likewise.
575 * msp430-dis.c: Likewise.
576 * or32-dis.c: Likewise.
577 * rl78-dis.c: Likewise.
578 * rx-dis.c: Likewise.
579 * tic4x-dis.c: Likewise.
580 * tilegx-opc.c: Likewise.
581 * tilepro-opc.c: Likewise.
582 * rx-decode.c: Regenerate.
583
a4ebc835
AM		 5842012-05-17 James Lemke <jwlemke@codesourcery.com>
585
586 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
587
98c76446
AM		 5882012-05-17 James Lemke <jwlemke@codesourcery.com>
589
590 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
591
df7b86aa
NC		 5922012-05-17 Daniel Richard G. <skunk@iskunk.org>
593 Nick Clifton <nickc@redhat.com>
594
595 PR 14072
596 * configure.in: Add check that sysdep.h has been included before
597 any system header files.
598 * configure: Regenerate.
599 * config.in: Regenerate.
600 * sysdep.h: Generate an error if included before config.h.
601 * alpha-opc.c: Include sysdep.h before any other header file.
602 * alpha-dis.c: Likewise.
603 * avr-dis.c: Likewise.
604 * cgen-opc.c: Likewise.
605 * cr16-dis.c: Likewise.
606 * cris-dis.c: Likewise.
607 * crx-dis.c: Likewise.
608 * d10v-dis.c: Likewise.
609 * d10v-opc.c: Likewise.
610 * d30v-dis.c: Likewise.
611 * d30v-opc.c: Likewise.
612 * h8500-dis.c: Likewise.
613 * i370-dis.c: Likewise.
614 * i370-opc.c: Likewise.
615 * m10200-dis.c: Likewise.
616 * m10300-dis.c: Likewise.
617 * micromips-opc.c: Likewise.
618 * mips-opc.c: Likewise.
619 * mips61-opc.c: Likewise.
620 * moxie-dis.c: Likewise.
621 * or32-opc.c: Likewise.
622 * pj-dis.c: Likewise.
623 * ppc-dis.c: Likewise.
624 * ppc-opc.c: Likewise.
625 * s390-dis.c: Likewise.
626 * sh-dis.c: Likewise.
627 * sh64-dis.c: Likewise.
628 * sparc-dis.c: Likewise.
629 * sparc-opc.c: Likewise.
630 * spu-dis.c: Likewise.
631 * tic30-dis.c: Likewise.
632 * tic54x-dis.c: Likewise.
633 * tic80-dis.c: Likewise.
634 * tic80-opc.c: Likewise.
635 * tilegx-dis.c: Likewise.
636 * tilepro-dis.c: Likewise.
637 * v850-dis.c: Likewise.
638 * v850-opc.c: Likewise.
639 * vax-dis.c: Likewise.
640 * w65-dis.c: Likewise.
641 * xgate-dis.c: Likewise.
642 * xtensa-dis.c: Likewise.
643 * rl78-decode.opc: Likewise.
644 * rl78-decode.c: Regenerate.
645 * rx-decode.opc: Likewise.
646 * rx-decode.c: Regenerate.
647
e1dad58d
AM		 6482012-05-17 Alan Modra <amodra@gmail.com>
649
650 * ppc_dis.c: Don't include elf/ppc.h.
651
101af531
NC		 6522012-05-16 Meador Inge <meadori@codesourcery.com>
653
654 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
655 to PUSH/POP {reg}.
656
6927f982
NC		 6572012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
658 Stephane Carrez <stcarrez@nerim.fr>
659
660 * configure.in: Add S12X and XGATE co-processor support to m68hc11
661 target.
662 * disassemble.c: Likewise.
663 * configure: Regenerate.
664 * m68hc11-dis.c: Make objdump output more consistent, use hex
665 instead of decimal and use 0x prefix for hex.
666 * m68hc11-opc.c: Add S12X and XGATE opcodes.
667
b9c361e0
JL		 6682012-05-14 James Lemke <jwlemke@codesourcery.com>
669
670 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
671 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
672 (vle_opcd_indices): New array.
673 (lookup_vle): New function.
674 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
675 (print_insn_powerpc): Likewise.
676 * ppc-opc.c: Likewise.
677
6782012-05-14 Catherine Moore <clm@codesourcery.com>
679 Maciej W. Rozycki <macro@codesourcery.com>
680 Rhonda Wittels <rhonda@codesourcery.com>
681 Nathan Froyd <froydnj@codesourcery.com>
682
683 * ppc-opc.c (insert_arx, extract_arx): New functions.
684 (insert_ary, extract_ary): New functions.
685 (insert_li20, extract_li20): New functions.
686 (insert_rx, extract_rx): New functions.
687 (insert_ry, extract_ry): New functions.
688 (insert_sci8, extract_sci8): New functions.
689 (insert_sci8n, extract_sci8n): New functions.
690 (insert_sd4h, extract_sd4h): New functions.
691 (insert_sd4w, extract_sd4w): New functions.
692 (insert_vlesi, extract_vlesi): New functions.
693 (insert_vlensi, extract_vlensi): New functions.
694 (insert_vleui, extract_vleui): New functions.
695 (insert_vleil, extract_vleil): New functions.
696 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
697 (BI16, BI32, BO32, B8): New.
698 (B15, B24, CRD32, CRS): New.
699 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
700 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
701 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
702 (SH6_MASK): Use PPC_OPSHIFT_INV.
703 (SI8, UI5, OIMM5, UI7, BO16): New.
704 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
705 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
706 (ALLOW8_SPRG): New.
707 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
708 (OPVUP, OPVUP_MASK OPVUP): New
709 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
710 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
711 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
712 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
713 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
714 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
715 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
716 (SE_IM5, SE_IM5_MASK): New.
717 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
718 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
719 (BO32DNZ, BO32DZ): New.
720 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
721 (PPCVLE): New.
722 (powerpc_opcodes): Add new VLE instructions. Update existing
723 instruction to include PPCVLE if supported.
724 * ppc-dis.c (ppc_opts): Add vle entry.
725 (get_powerpc_dialect): New function.
726 (powerpc_init_dialect): VLE support.
727 (print_insn_big_powerpc): Call get_powerpc_dialect.
728 (print_insn_little_powerpc): Likewise.
729 (operand_value_powerpc): Handle negative shift counts.
730 (print_insn_powerpc): Handle 2-byte instruction lengths.
731
208a4923
NC		 7322012-05-11 Daniel Richard G. <skunk@iskunk.org>
733
734 PR binutils/14028
735 * configure.in: Invoke ACX_HEADER_STRING.
736 * configure: Regenerate.
737 * config.in: Regenerate.
738 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
739 string.h and strings.h.
740
6750a3a7
NC		 7412012-05-11 Nick Clifton <nickc@redhat.com>
742
743 PR binutils/14006
744 * arm-dis.c (print_insn): Fix detection of instruction mode in
745 files containing multiple executable sections.
746
f6c1a2d5
NC		 7472012-05-03 Sean Keys <skeys@ipdatasys.com>
748
749 * Makefile.in, configure: regenerate
750 * disassemble.c (disassembler): Recognize ARCH_XGATE.
751 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
752 New functions.
753 * configure.in: Recognize xgate.
754 * xgate-dis.c, xgate-opc.c: New files for support of xgate
755 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
756 and opcode generation for xgate.
757
78e98aab
DD		 7582012-04-30 DJ Delorie <dj@redhat.com>
759
760 * rx-decode.opc (MOV): Do not sign-extend immediates which are
761 already the maximum bit size.
762 * rx-decode.c: Regenerate.
763
ec668d69
DM		 7642012-04-27 David S. Miller <davem@davemloft.net>
765
2e52845b
DM		 766 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
767 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
768
58004e23
DM		 769 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
770 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
771
698544e1
DM		 772 * sparc-opc.c (CBCOND): New define.
773 (CBCOND_XCC): Likewise.
774 (cbcond): New helper macro.
775 (sparc_opcodes): Add compare-and-branch instructions.
776
6cda1326
DM		 777 * sparc-dis.c (print_insn_sparc): Handle ')'.
778 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
779
ec668d69
DM		 780 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
781 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
782
2615994e
DM		 7832012-04-12 David S. Miller <davem@davemloft.net>
784
785 * sparc-dis.c (X_DISP10): Define.
786 (print_insn_sparc): Handle '='.
787
5de10af0
MF		 7882012-04-01 Mike Frysinger <vapier@gentoo.org>
789
790 * bfin-dis.c (fmtconst): Replace decimal handling with a single
791 sprintf call and the '*' field width.
792
55a36193
MK		 7932012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
794
795 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
796
d6688282
AM		 7972012-03-16 Alan Modra <amodra@gmail.com>
798
799 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
800 (powerpc_opcd_indices): Bump array size.
801 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
802 corresponding to unused opcodes to following entry.
803 (lookup_powerpc): New function, extracted and optimised from..
804 (print_insn_powerpc): ..here.
805
b240011a
AM		 8062012-03-15 Alan Modra <amodra@gmail.com>
807 James Lemke <jwlemke@codesourcery.com>
808
809 * disassemble.c (disassemble_init_for_target): Handle ppc init.
810 * ppc-dis.c (private): New var.
811 (powerpc_init_dialect): Don't return calloc failure, instead use
812 private.
813 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
814 (powerpc_opcd_indices): New array.
815 (disassemble_init_powerpc): New function.
816 (print_insn_big_powerpc): Don't init dialect here.
817 (print_insn_little_powerpc): Likewise.
818 (print_insn_powerpc): Start search using powerpc_opcd_indices.
819
aea77599
AM		 8202012-03-10 Edmar Wienskoski <edmar@freescale.com>
821
822 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
823 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
824 (PPCVEC2, PPCTMR, E6500): New short names.
825 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
826 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
827 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
828 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
829 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
830 optional operands on sync instruction for E6500 target.
831
5333187a
AK		 8322012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
833
834 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
835
a597d2d3
AM		 8362012-02-27 Alan Modra <amodra@gmail.com>
837
838 * mt-dis.c: Regenerate.
839
3f26eb3a
AM		 8402012-02-27 Alan Modra <amodra@gmail.com>
841
842 * v850-opc.c (extract_v8): Rearrange to make it obvious this
843 is the inverse of corresponding insert function.
844 (extract_d22, extract_u9, extract_r4): Likewise.
845 (extract_d9): Correct sign extension.
846 (extract_d16_15): Don't assume "long" is 32 bits, and don't
847 rely on implementation defined behaviour for shift right of
848 signed types.
849 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
850 (extract_d23): Likewise, and correct mask.
851
1f42f8b3
AM		 8522012-02-27 Alan Modra <amodra@gmail.com>
853
854 * crx-dis.c (print_arg): Mask constant to 32 bits.
855 * crx-opc.c (cst4_map): Use int array.
856
cdb06235
AM		 8572012-02-27 Alan Modra <amodra@gmail.com>
858
859 * arc-dis.c (BITS): Don't use shifts to mask off bits.
860 (FIELDD): Sign extend with xor,sub.
861
6f7be959
WL		 8622012-02-25 Walter Lee <walt@tilera.com>
863
864 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
865 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
866 TILEPRO_OPC_LW_TLS_SN.
867
82c2def5
L		 8682012-02-21 H.J. Lu <hongjiu.lu@intel.com>
869
870 * i386-opc.h (HLEPrefixNone): New.
871 (HLEPrefixLock): Likewise.
872 (HLEPrefixAny): Likewise.
873 (HLEPrefixRelease): Likewise.
874
42164a71
L		 8752012-02-08 H.J. Lu <hongjiu.lu@intel.com>
876
877 * i386-dis.c (HLE_Fixup1): New.
878 (HLE_Fixup2): Likewise.
879 (HLE_Fixup3): Likewise.
880 (Ebh1): Likewise.
881 (Evh1): Likewise.
882 (Ebh2): Likewise.
883 (Evh2): Likewise.
884 (Ebh3): Likewise.
885 (Evh3): Likewise.
886 (MOD_C6_REG_7): Likewise.
887 (MOD_C7_REG_7): Likewise.
888 (RM_C6_REG_7): Likewise.
889 (RM_C7_REG_7): Likewise.
890 (XACQUIRE_PREFIX): Likewise.
891 (XRELEASE_PREFIX): Likewise.
892 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
893 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
894 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
895 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
896 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
897 MOD_C6_REG_7 and MOD_C7_REG_7.
898 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
899 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
900 xtest.
901 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
902 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
903
904 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
905 CPU_RTM_FLAGS.
906 (cpu_flags): Add CpuHLE and CpuRTM.
907 (opcode_modifiers): Add HLEPrefixOk.
908
909 * i386-opc.h (CpuHLE): New.
910 (CpuRTM): Likewise.
911 (HLEPrefixOk): Likewise.
912 (i386_cpu_flags): Add cpuhle and cpurtm.
913 (i386_opcode_modifier): Add hleprefixok.
914
915 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
916 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
917 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
918 operand. Add xacquire, xrelease, xabort, xbegin, xend and
919 xtest.
920 * i386-init.h: Regenerated.
921 * i386-tbl.h: Likewise.
922
21abe33a
DD		 9232012-01-24 DJ Delorie <dj@redhat.com>
924
925 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
926 * rl78-decode.c: Regenerate.
927
e20cc039
AM		 9282012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
929
930 PR binutils/10173
931 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
932
e143d25c
AS		 9332012-01-17 Andreas Schwab <schwab@linux-m68k.org>
934
935 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
936 register and move them after pmove with PSR/PCSR register.
937
8729a6f6
L		 9382012-01-13 H.J. Lu <hongjiu.lu@intel.com>
939
940 * i386-dis.c (mod_table): Add vmfunc.
941
942 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
943 (cpu_flags): CpuVMFUNC.
944
945 * i386-opc.h (CpuVMFUNC): New.
946 (i386_cpu_flags): Add cpuvmfunc.
947
948 * i386-opc.tbl: Add vmfunc.
949 * i386-init.h: Regenerated.
950 * i386-tbl.h: Likewise.
5011093d 951
23e1d329 952For older changes see ChangeLog-2011
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RH		 953\f
954Local Variables:
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NC		 955mode: change-log
956left-margin: 8
957fill-column: 74
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RH		 958version-control: never
959End:
GDB Binutils - Deliverables
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