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2005-02-14 Andrew Cagney <cagney@gnu.org>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5a84f3e0
NC		 12005-02-11 Nick Clifton <nickc@redhat.com>
2
bc18c937
NC		 3 * iq2000-asm.c: Regenerate.
4
5a84f3e0
NC		 5 * frv-dis.c: Regenerate.
6
0a40490e
JB		 72005-02-07 Jim Blandy <jimb@redhat.com>
8
9 * Makefile.am (CGEN): Load guile.scm before calling the main
10 application script.
11 * Makefile.in: Regenerated.
12 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
13 Simply pass the cgen-opc.scm path to ${cgen} as its first
14 argument; ${cgen} itself now contains the '-s', or whatever is
15 appropriate for the Scheme being used.
16
c46f8c51
AC		 172005-01-31 Andrew Cagney <cagney@gnu.org>
18
19 * configure: Regenerate to track ../gettext.m4.
20
60b9a617
JB		 212005-01-31 Jan Beulich <jbeulich@novell.com>
22
23 * ia64-gen.c (NELEMS): Define.
24 (shrink): Generate alias with missing second predicate register when
25 opcode has two outputs and these are both predicates.
26 * ia64-opc-i.c (FULL17): Define.
27 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
28 here to generate output template.
29 (TBITCM, TNATCM): Undefine after use.
30 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
31 first input. Add ld16 aliases without ar.csd as second output. Add
32 st16 aliases without ar.csd as second input. Add cmpxchg aliases
33 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
34 ar.ccv as third/fourth inputs. Consolidate through...
35 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
36 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
37 * ia64-asmtab.c: Regenerate.
38
a53bf506
AC		 392005-01-27 Andrew Cagney <cagney@gnu.org>
40
41 * configure: Regenerate to track ../gettext.m4 change.
42
90219bd0
AO		 432005-01-25 Alexandre Oliva <aoliva@redhat.com>
44
45 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
46 * frv-asm.c: Rebuilt.
47 * frv-desc.c: Rebuilt.
48 * frv-desc.h: Rebuilt.
49 * frv-dis.c: Rebuilt.
50 * frv-ibld.c: Rebuilt.
51 * frv-opc.c: Rebuilt.
52 * frv-opc.h: Rebuilt.
53
45181ed1
AC		 542005-01-24 Andrew Cagney <cagney@gnu.org>
55
56 * configure: Regenerate, ../gettext.m4 was updated.
57
9e836e3d
FF		 582005-01-21 Fred Fish <fnf@specifixinc.com>
59
60 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
61 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
62 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
63 * mips-dis.c: Ditto.
64
5e8cb021
AM		 652005-01-20 Alan Modra <amodra@bigpond.net.au>
66
67 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
68
986e18a5
FF		 692005-01-19 Fred Fish <fnf@specifixinc.com>
70
71 * mips-dis.c (no_aliases): New disassembly option flag.
72 (set_default_mips_dis_options): Init no_aliases to zero.
73 (parse_mips_dis_option): Handle no-aliases option.
74 (print_insn_mips): Ignore table entries that are aliases
75 if no_aliases is set.
76 (print_insn_mips16): Ditto.
77 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
78 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
79 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
80 * mips16-opc.c (mips16_opcodes): Ditto.
81
e38bc3b5
NC		 822005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
83
84 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
85 (inheritance diagram): Add missing edge.
86 (arch_sh1_up): Rename arch_sh_up to match external name to make life
87 easier for the testsuite.
88 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
89 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
90 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
91 arch_sh2a_or_sh4_up child.
92 (sh_table): Do renaming as above.
93 Correct comment for ldc.l for gas testsuite to read.
94 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
95 Correct comments for movy.w and movy.l for gas testsuite to read.
96 Correct comments for fmov.d and fmov.s for gas testsuite to read.
97
9df48ba9
L		 982005-01-12 H.J. Lu <hongjiu.lu@intel.com>
99
100 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
101
2033b4b9
L		 1022005-01-12 H.J. Lu <hongjiu.lu@intel.com>
103
104 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
105
0bcb06d2
AS		 1062005-01-10 Andreas Schwab <schwab@suse.de>
107
108 * disassemble.c (disassemble_init_for_target) <case
109 bfd_arch_ia64>: Set skip_zeroes to 16.
110 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
111
47add74d
TL		 1122004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
113
114 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
115
246f4c05
SS		 1162004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
117
118 * avr-dis.c: Prettyprint. Added printing of symbol names in all
119 memory references. Convert avr_operand() to C90 formatting.
120
0e1200e5
TL		 1212004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
122
123 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
124
89a649f7
TL		 1252004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
126
127 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
128 (no_op_insn): Initialize array with instructions that have no
129 operands.
130 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
131
6255809c
RE		 1322004-11-29 Richard Earnshaw <rearnsha@arm.com>
133
134 * arm-dis.c: Correct top-level comment.
135
2fbad815
RE		 1362004-11-27 Richard Earnshaw <rearnsha@arm.com>
137
138 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
139 architecuture defining the insn.
140 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 141 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
142 field.
2fbad815
RE		 143 Also include opcode/arm.h.
144 * Makefile.am (arm-dis.lo): Update dependency list.
145 * Makefile.in: Regenerate.
146
d81acc42
NC		 1472004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
148
149 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
150 reflect the change to the short immediate syntax.
151
ca4f2377
AM		 1522004-11-19 Alan Modra <amodra@bigpond.net.au>
153
5da8bf1b
AM		 154 * or32-opc.c (debug): Warning fix.
155 * po/POTFILES.in: Regenerate.
156
ca4f2377
AM		 157 * maxq-dis.c: Formatting.
158 (print_insn): Warning fix.
159
b7693d02
DJ		 1602004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
161
162 * arm-dis.c (WORD_ADDRESS): Define.
163 (print_insn): Use it. Correct big-endian end-of-section handling.
164
300dac7e
NC		 1652004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
166 Vineet Sharma <vineets@noida.hcltech.com>
167
168 * maxq-dis.c: New file.
169 * disassemble.c (ARCH_maxq): Define.
170 (disassembler): Add 'print_insn_maxq_little' for handling maxq
171 instructions..
172 * configure.in: Add case for bfd_maxq_arch.
173 * configure: Regenerate.
174 * Makefile.am: Add support for maxq-dis.c
175 * Makefile.in: Regenerate.
176 * aclocal.m4: Regenerate.
177
42048ee7
TL		 1782004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
179
180 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
181 mode.
182 * crx-dis.c: Likewise.
183
bd21e58e
HPN		 1842004-11-04 Hans-Peter Nilsson <hp@axis.com>
185
186 Generally, handle CRISv32.
187 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
188 (struct cris_disasm_data): New type.
189 (format_reg, format_hex, cris_constraint, print_flags)
190 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
191 callers changed.
192 (format_sup_reg, print_insn_crisv32_with_register_prefix)
193 (print_insn_crisv32_without_register_prefix)
194 (print_insn_crisv10_v32_with_register_prefix)
195 (print_insn_crisv10_v32_without_register_prefix)
196 (cris_parse_disassembler_options): New functions.
197 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
198 parameter. All callers changed.
199 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
200 failure.
201 (cris_constraint) <case 'Y', 'U'>: New cases.
202 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
203 for constraint 'n'.
204 (print_with_operands) <case 'Y'>: New case.
205 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
206 <case 'N', 'Y', 'Q'>: New cases.
207 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
208 (print_insn_cris_with_register_prefix)
209 (print_insn_cris_without_register_prefix): Call
210 cris_parse_disassembler_options.
211 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
212 for CRISv32 and the size of immediate operands. New v32-only
213 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
214 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
215 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
216 Change brp to be v3..v10.
217 (cris_support_regs): New vector.
218 (cris_opcodes): Update head comment. New format characters '[',
219 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
220 Add new opcodes for v32 and adjust existing opcodes to accommodate
221 differences to earlier variants.
222 (cris_cond15s): New vector.
223
9306ca4a
JB		 2242004-11-04 Jan Beulich <jbeulich@novell.com>
225
226 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
227 (indirEb): Remove.
228 (Mp): Use f_mode rather than none at all.
229 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
230 replaces what previously was x_mode; x_mode now means 128-bit SSE
231 operands.
232 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
233 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
234 pinsrw's second operand is Edqw.
235 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
236 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
237 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
238 mode when an operand size override is present or always suffixing.
239 More instructions will need to be added to this group.
240 (putop): Handle new macro chars 'C' (short/long suffix selector),
241 'I' (Intel mode override for following macro char), and 'J' (for
242 adding the 'l' prefix to far branches in AT&T mode). When an
243 alternative was specified in the template, honor macro character when
244 specified for Intel mode.
245 (OP_E): Handle new *_mode values. Correct pointer specifications for
246 memory operands. Consolidate output of index register.
247 (OP_G): Handle new *_mode values.
248 (OP_I): Handle const_1_mode.
249 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
250 respective opcode prefix bits have been consumed.
251 (OP_EM, OP_EX): Provide some default handling for generating pointer
252 specifications.
253
f39c96a9
TL		 2542004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
255
256 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
257 COP_INST macro.
258
812337be
TL		 2592004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
260
261 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
262 (getregliststring): Support HI/LO and user registers.
263 * crx-opc.c (crx_instruction): Update data structure according to the
264 rearrangement done in CRX opcode header file.
265 (crx_regtab): Likewise.
266 (crx_optab): Likewise.
267 (crx_instruction): Reorder load/stor instructions, remove unsupported
268 formats.
269 support new Co-Processor instruction 'cpi'.
270
4030fa5a
NC		 2712004-10-27 Nick Clifton <nickc@redhat.com>
272
273 * opcodes/iq2000-asm.c: Regenerate.
274 * opcodes/iq2000-desc.c: Regenerate.
275 * opcodes/iq2000-desc.h: Regenerate.
276 * opcodes/iq2000-dis.c: Regenerate.
277 * opcodes/iq2000-ibld.c: Regenerate.
278 * opcodes/iq2000-opc.c: Regenerate.
279 * opcodes/iq2000-opc.h: Regenerate.
280
fc3d45e8
TL		 2812004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
282
283 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
284 us4, us5 (respectively).
285 Remove unsupported 'popa' instruction.
286 Reverse operands order in store co-processor instructions.
287
3c55da70
AM		 2882004-10-15 Alan Modra <amodra@bigpond.net.au>
289
290 * Makefile.am: Run "make dep-am"
291 * Makefile.in: Regenerate.
292
7fa3d080
BW		 2932004-10-12 Bob Wilson <bob.wilson@acm.org>
294
295 * xtensa-dis.c: Use ISO C90 formatting.
296
e612bb4d
AM		 2972004-10-09 Alan Modra <amodra@bigpond.net.au>
298
299 * ppc-opc.c: Revert 2004-09-09 change.
300
43cd72b9
BW		 3012004-10-07 Bob Wilson <bob.wilson@acm.org>
302
303 * xtensa-dis.c (state_names): Delete.
304 (fetch_data): Use xtensa_isa_maxlength.
305 (print_xtensa_operand): Replace operand parameter with opcode/operand
306 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
307 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
308 instruction bundles. Use xmalloc instead of malloc.
309
bbac1f2a
NC		 3102004-10-07 David Gibson <david@gibson.dropbear.id.au>
311
312 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
313 initializers.
314
48c9f030
NC		 3152004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
316
317 * crx-opc.c (crx_instruction): Support Co-processor insns.
318 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
319 (getregliststring): Change function to use the above enum.
320 (print_arg): Handle CO-Processor insns.
321 (crx_cinvs): Add 'b' option to invalidate the branch-target
322 cache.
323
12c64a4e
AH		 3242004-10-06 Aldy Hernandez <aldyh@redhat.com>
325
326 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
327 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
328 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
329 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
330 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
331
14127cc4
NC		 3322004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
333
334 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
335 rather than add it.
336
0dd132b6
NC		 3372004-09-30 Paul Brook <paul@codesourcery.com>
338
339 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
340 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
341
3f85e526
L		 3422004-09-17 H.J. Lu <hongjiu.lu@intel.com>
343
344 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
345 (CONFIG_STATUS_DEPENDENCIES): New.
346 (Makefile): Removed.
347 (config.status): Likewise.
348 * Makefile.in: Regenerated.
349
8ae85421
AM		 3502004-09-17 Alan Modra <amodra@bigpond.net.au>
351
352 * Makefile.am: Run "make dep-am".
353 * Makefile.in: Regenerate.
354 * aclocal.m4: Regenerate.
355 * configure: Regenerate.
356 * po/POTFILES.in: Regenerate.
357 * po/opcodes.pot: Regenerate.
358
24443139
AS		 3592004-09-11 Andreas Schwab <schwab@suse.de>
360
361 * configure: Rebuild.
362
2a309db0
AM		 3632004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
364
365 * ppc-opc.c (L): Make this field not optional.
366
42851540
NC		 3672004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
368
369 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
370 Fix parameter to 'm[t|f]csr' insns.
371
979273e3
NN		 3722004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
373
374 * configure.in: Autoupdate to autoconf 2.59.
375 * aclocal.m4: Rebuild with aclocal 1.4p6.
376 * configure: Rebuild with autoconf 2.59.
377 * Makefile.in: Rebuild with automake 1.4p6 (picking up
378 bfd changes for autoconf 2.59 on the way).
379 * config.in: Rebuild with autoheader 2.59.
380
ac28a1cb
RS		 3812004-08-27 Richard Sandiford <rsandifo@redhat.com>
382
383 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
384
30d1c836
ML		 3852004-07-30 Michal Ludvig <mludvig@suse.cz>
386
387 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
388 (GRPPADLCK2): New define.
389 (twobyte_has_modrm): True for 0xA6.
390 (grps): GRPPADLCK2 for opcode 0xA6.
391
0b0ac059
AO		 3922004-07-29 Alexandre Oliva <aoliva@redhat.com>
393
394 Introduce SH2a support.
395 * sh-opc.h (arch_sh2a_base): Renumber.
396 (arch_sh2a_nofpu_base): Remove.
397 (arch_sh_base_mask): Adjust.
398 (arch_opann_mask): New.
399 (arch_sh2a, arch_sh2a_nofpu): Adjust.
400 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
401 (sh_table): Adjust whitespace.
402 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
403 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
404 instruction list throughout.
405 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
406 of arch_sh2a in instruction list throughout.
407 (arch_sh2e_up): Accomodate above changes.
408 (arch_sh2_up): Ditto.
409 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
410 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
411 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
412 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
413 * sh-opc.h (arch_sh2a_nofpu): New.
414 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
415 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
416 instruction.
417 2004-01-20 DJ Delorie <dj@redhat.com>
418 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
419 2003-12-29 DJ Delorie <dj@redhat.com>
420 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
421 sh_opcode_info, sh_table): Add sh2a support.
422 (arch_op32): New, to tag 32-bit opcodes.
423 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
424 2003-12-02 Michael Snyder <msnyder@redhat.com>
425 * sh-opc.h (arch_sh2a): Add.
426 * sh-dis.c (arch_sh2a): Handle.
427 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
428
670ec21d
NC		 4292004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
430
431 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
432
ed049af3
NC		 4332004-07-22 Nick Clifton <nickc@redhat.com>
434
435 PR/280
436 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
437 insns - this is done by objdump itself.
438 * h8500-dis.c (print_insn_h8500): Likewise.
439
20f0a1fc
NC		 4402004-07-21 Jan Beulich <jbeulich@novell.com>
441
442 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
443 regardless of address size prefix in effect.
444 (ptr_reg): Size or address registers does not depend on rex64, but
445 on the presence of an address size override.
446 (OP_MMX): Use rex.x only for xmm registers.
447 (OP_EM): Use rex.z only for xmm registers.
448
6f14957b
MR		 4492004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
450
451 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
452 move/branch operations to the bottom so that VR5400 multimedia
453 instructions take precedence in disassembly.
454
1586d91e
MR		 4552004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
456
457 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
458 ISA-specific "break" encoding.
459
982de27a
NC		 4602004-07-13 Elvis Chiang <elvisfb@gmail.com>
461
462 * arm-opc.h: Fix typo in comment.
463
4300ab10
AS		 4642004-07-11 Andreas Schwab <schwab@suse.de>
465
466 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
467
8577e690
AS		 4682004-07-09 Andreas Schwab <schwab@suse.de>
469
470 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
471
1fe1f39c
NC		 4722004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
473
474 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
475 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
476 (crx-dis.lo): New target.
477 (crx-opc.lo): Likewise.
478 * Makefile.in: Regenerate.
479 * configure.in: Handle bfd_crx_arch.
480 * configure: Regenerate.
481 * crx-dis.c: New file.
482 * crx-opc.c: New file.
483 * disassemble.c (ARCH_crx): Define.
484 (disassembler): Handle ARCH_crx.
485
7a33b495
JW		 4862004-06-29 James E Wilson <wilson@specifixinc.com>
487
488 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
489 * ia64-asmtab.c: Regnerate.
490
98e69875
AM		 4912004-06-28 Alan Modra <amodra@bigpond.net.au>
492
493 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
494 (extract_fxm): Don't test dialect.
495 (XFXFXM_MASK): Include the power4 bit.
496 (XFXM): Add p4 param.
497 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
498
a53b85e2
AO		 4992004-06-27 Alexandre Oliva <aoliva@redhat.com>
500
501 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
502 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
503
d0618d1c
AM		 5042004-06-26 Alan Modra <amodra@bigpond.net.au>
505
506 * ppc-opc.c (BH, XLBH_MASK): Define.
507 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
508
1d9f512f
AM		 5092004-06-24 Alan Modra <amodra@bigpond.net.au>
510
511 * i386-dis.c (x_mode): Comment.
512 (two_source_ops): File scope.
513 (float_mem): Correct fisttpll and fistpll.
514 (float_mem_mode): New table.
515 (dofloat): Use it.
516 (OP_E): Correct intel mode PTR output.
517 (ptr_reg): Use open_char and close_char.
518 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
519 operands. Set two_source_ops.
520
52886d70
AM		 5212004-06-15 Alan Modra <amodra@bigpond.net.au>
522
523 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
524 instead of _raw_size.
525
bad9ceea
JJ		 5262004-06-08 Jakub Jelinek <jakub@redhat.com>
527
528 * ia64-gen.c (in_iclass): Handle more postinc st
529 and ld variants.
530 * ia64-asmtab.c: Rebuilt.
531
0451f5df
MS		 5322004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
533
534 * s390-opc.txt: Correct architecture mask for some opcodes.
535 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
536 in the esa mode as well.
537
f6f9408f
JR		 5382004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
539
540 * sh-dis.c (target_arch): Make unsigned.
541 (print_insn_sh): Replace (most of) switch with a call to
542 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
543 * sh-opc.h: Redefine architecture flags values.
544 Add sh3-nommu architecture.
545 Reorganise <arch>_up macros so they make more visual sense.
546 (SH_MERGE_ARCH_SET): Define new macro.
547 (SH_VALID_BASE_ARCH_SET): Likewise.
548 (SH_VALID_MMU_ARCH_SET): Likewise.
549 (SH_VALID_CO_ARCH_SET): Likewise.
550 (SH_VALID_ARCH_SET): Likewise.
551 (SH_MERGE_ARCH_SET_VALID): Likewise.
552 (SH_ARCH_SET_HAS_FPU): Likewise.
553 (SH_ARCH_SET_HAS_DSP): Likewise.
554 (SH_ARCH_UNKNOWN_ARCH): Likewise.
555 (sh_get_arch_from_bfd_mach): Add prototype.
556 (sh_get_arch_up_from_bfd_mach): Likewise.
557 (sh_get_bfd_mach_from_arch_set): Likewise.
558 (sh_merge_bfd_arc): Likewise.
559
be8c092b
NC		 5602004-05-24 Peter Barada <peter@the-baradas.com>
561
562 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
563 into new match_insn_m68k function. Loop over canidate
564 matches and select first that completely matches.
565 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
566 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
567 to verify addressing for MAC/EMAC.
568 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
569 reigster halves since 'fpu' and 'spl' look misleading.
570 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
571 * m68k-opc.c: Rearragne mac/emac cases to use longest for
572 first, tighten up match masks.
573 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
574 'size' from special case code in print_insn_m68k to
575 determine decode size of insns.
576
a30e9cc4
AM		 5772004-05-19 Alan Modra <amodra@bigpond.net.au>
578
579 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
580 well as when -mpower4.
581
9598fbe5
NC		 5822004-05-13 Nick Clifton <nickc@redhat.com>
583
584 * po/fr.po: Updated French translation.
585
6b6e92f4
NC		 5862004-05-05 Peter Barada <peter@the-baradas.com>
587
588 * m68k-dis.c(print_insn_m68k): Add new chips, use core
589 variants in arch_mask. Only set m68881/68851 for 68k chips.
590 * m68k-op.c: Switch from ColdFire chips to core variants.
591
a404d431
AM		 5922004-05-05 Alan Modra <amodra@bigpond.net.au>
593
a30e9cc4 594 PR 147.
a404d431
AM		 595 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
596
f3806e43
BE		 5972004-04-29 Ben Elliston <bje@au.ibm.com>
598
520ceea4
BE		 599 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
600 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 601
1f1799d5
KK		 6022004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
603
604 * sh-dis.c (print_insn_sh): Print the value in constant pool
605 as a symbol if it looks like a symbol.
606
fd99574b
NC		 6072004-04-22 Peter Barada <peter@the-baradas.com>
608
609 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
610 appropriate ColdFire architectures.
611 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
612 mask addressing.
613 Add EMAC instructions, fix MAC instructions. Remove
614 macmw/macml/msacmw/msacml instructions since mask addressing now
615 supported.
616
b4781d44
JJ		 6172004-04-20 Jakub Jelinek <jakub@redhat.com>
618
619 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
620 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
621 suffix. Use fmov*x macros, create all 3 fpsize variants in one
622 macro. Adjust all users.
623
91809fda
NC		 6242004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
625
626 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
627 separately.
628
f4453dfa
NC		 6292004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
630
631 * m32r-asm.c: Regenerate.
632
9b0de91a
SS		 6332004-03-29 Stan Shebs <shebs@apple.com>
634
635 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
636 used.
637
e20c0b3d
AM		 6382004-03-19 Alan Modra <amodra@bigpond.net.au>
639
640 * aclocal.m4: Regenerate.
641 * config.in: Regenerate.
642 * configure: Regenerate.
643 * po/POTFILES.in: Regenerate.
644 * po/opcodes.pot: Regenerate.
645
fdd12ef3
AM		 6462004-03-16 Alan Modra <amodra@bigpond.net.au>
647
648 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
649 PPC_OPERANDS_GPR_0.
650 * ppc-opc.c (RA0): Define.
651 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
652 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 653 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 654
2dc111b3 6552004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 656
657 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 658
7bfeee7b
AM		 6592004-03-15 Alan Modra <amodra@bigpond.net.au>
660
661 * sparc-dis.c (print_insn_sparc): Update getword prototype.
662
7ffdda93
ML		 6632004-03-12 Michal Ludvig <mludvig@suse.cz>
664
665 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 666 (grps): Delete GRPPLOCK entry.
7ffdda93 667
cc0ec051
AM		 6682004-03-12 Alan Modra <amodra@bigpond.net.au>
669
670 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
671 (M, Mp): Use OP_M.
672 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
673 (GRPPADLCK): Define.
674 (dis386): Use NOP_Fixup on "nop".
675 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
676 (twobyte_has_modrm): Set for 0xa7.
677 (padlock_table): Delete. Move to..
678 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
679 and clflush.
680 (print_insn): Revert PADLOCK_SPECIAL code.
681 (OP_E): Delete sfence, lfence, mfence checks.
682
4fd61dcb
JJ		 6832004-03-12 Jakub Jelinek <jakub@redhat.com>
684
685 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
686 (INVLPG_Fixup): New function.
687 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
688
0f10071e
ML		 6892004-03-12 Michal Ludvig <mludvig@suse.cz>
690
691 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
692 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
693 (padlock_table): New struct with PadLock instructions.
694 (print_insn): Handle PADLOCK_SPECIAL.
695
c02908d2
AM		 6962004-03-12 Alan Modra <amodra@bigpond.net.au>
697
698 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
699 (OP_E): Twiddle clflush to sfence here.
700
d5bb7600
NC		 7012004-03-08 Nick Clifton <nickc@redhat.com>
702
703 * po/de.po: Updated German translation.
704
ae51a426
JR		 7052003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
706
707 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
708 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
709 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
710 accordingly.
711
676a64f4
RS		 7122004-03-01 Richard Sandiford <rsandifo@redhat.com>
713
714 * frv-asm.c: Regenerate.
715 * frv-desc.c: Regenerate.
716 * frv-desc.h: Regenerate.
717 * frv-dis.c: Regenerate.
718 * frv-ibld.c: Regenerate.
719 * frv-opc.c: Regenerate.
720 * frv-opc.h: Regenerate.
721
c7a48b9a
RS		 7222004-03-01 Richard Sandiford <rsandifo@redhat.com>
723
724 * frv-desc.c, frv-opc.c: Regenerate.
725
8ae0baa2
RS		 7262004-03-01 Richard Sandiford <rsandifo@redhat.com>
727
728 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
729
ce11586c
JR		 7302004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
731
732 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
733 Also correct mistake in the comment.
734
6a5709a5
JR		 7352004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
736
737 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
738 ensure that double registers have even numbers.
739 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
740 that reserved instruction 0xfffd does not decode the same
741 as 0xfdfd (ftrv).
742 * sh-opc.h: Add REG_N_D nibble type and use it whereever
743 REG_N refers to a double register.
744 Add REG_N_B01 nibble type and use it instead of REG_NM
745 in ftrv.
746 Adjust the bit patterns in a few comments.
747
e5d2b64f 7482004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 749
750 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 751
1f04b05f
AH		 7522004-02-20 Aldy Hernandez <aldyh@redhat.com>
753
754 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
755
2f3b8700
AH		 7562004-02-20 Aldy Hernandez <aldyh@redhat.com>
757
758 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
759
f0b26da6 7602004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 761
762 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
763 mtivor32, mtivor33, mtivor34.
f0b26da6 764
23d59c56 7652004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 766
767 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 768
34920d91
NC		 7692004-02-10 Petko Manolov <petkan@nucleusys.com>
770
771 * arm-opc.h Maverick accumulator register opcode fixes.
772
44d86481
BE		 7732004-02-13 Ben Elliston <bje@wasabisystems.com>
774
775 * m32r-dis.c: Regenerate.
776
17707c23
MS		 7772004-01-27 Michael Snyder <msnyder@redhat.com>
778
779 * sh-opc.h (sh_table): "fsrra", not "fssra".
780
fe3a9bc4
NC		 7812004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
782
783 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
784 contraints.
785
ff24f124
JJ		 7862004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
787
788 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
789
a02a862a
AM		 7902004-01-19 Alan Modra <amodra@bigpond.net.au>
791
792 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
793 1. Don't print scale factor on AT&T mode when index missing.
794
d164ea7f
AO		 7952004-01-16 Alexandre Oliva <aoliva@redhat.com>
796
797 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
798 when loaded into XR registers.
799
cb10e79a
RS		 8002004-01-14 Richard Sandiford <rsandifo@redhat.com>
801
802 * frv-desc.h: Regenerate.
803 * frv-desc.c: Regenerate.
804 * frv-opc.c: Regenerate.
805
f532f3fa
MS		 8062004-01-13 Michael Snyder <msnyder@redhat.com>
807
808 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
809
e45d0630
PB		 8102004-01-09 Paul Brook <paul@codesourcery.com>
811
812 * arm-opc.h (arm_opcodes): Move generic mcrr after known
813 specific opcodes.
814
3ba7a1aa
DJ		 8152004-01-07 Daniel Jacobowitz <drow@mvista.com>
816
817 * Makefile.am (libopcodes_la_DEPENDENCIES)
818 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
819 comment about the problem.
820 * Makefile.in: Regenerate.
821
ba2d3f07
AO		 8222004-01-06 Alexandre Oliva <aoliva@redhat.com>
823
824 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
825 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
826 cut&paste errors in shifting/truncating numerical operands.
827 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
828 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
829 (parse_uslo16): Likewise.
830 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
831 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
832 (parse_s12): Likewise.
833 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
834 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
835 (parse_uslo16): Likewise.
836 (parse_uhi16): Parse gothi and gotfuncdeschi.
837 (parse_d12): Parse got12 and gotfuncdesc12.
838 (parse_s12): Likewise.
839
3ab48931
NC		 8402004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
841
842 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
843 instruction which looks similar to an 'rla' instruction.
a0bd404e 844
c9e214e5 845For older changes see ChangeLog-0203
252b5132
RH		 846\f
847Local Variables:
2f6d2f85
NC		 848mode: change-log
849left-margin: 8
850fill-column: 74
252b5132
RH		 851version-control: never
852End:
GDB Binutils - Deliverables
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