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PR23430, Indices misspelled
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
67ce483b
AM		 12018-07-24 Alan Modra <amodra@gmail.com>
2
3 PR 23430
4 * or1k-desc.h: Regenerate.
5
4174bfff
JB		 62018-07-24 Jan Beulich <jbeulich@suse.com>
7
8 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
9 vcvtusi2ss, and vcvtusi2sd.
10 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
11 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
12 * i386-tbl.h: Re-generate.
13
04e65276
CZ		 142018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
15
16 * arc-opc.c (extract_w6): Fix extending the sign.
17
47e6f81c
CZ		 182018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
19
20 * arc-tbl.h (vewt): Allow it for ARC EM family.
21
bb71536f
AM		 222018-07-23 Alan Modra <amodra@gmail.com>
23
24 PR 23419
25 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
26 opcode variants for mtspr/mfspr encodings.
27
8095d2f7
CX		 282018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
29 Maciej W. Rozycki <macro@mips.com>
30
31 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
32 loongson3a descriptors.
33 (parse_mips_ase_option): Handle -M loongson-mmi option.
34 (print_mips_disassembler_options): Document -M loongson-mmi.
35 * mips-opc.c (LMMI): New macro.
36 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
37 instructions.
38
5f32791e
JB		 392018-07-19 Jan Beulich <jbeulich@suse.com>
40
41 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
42 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
43 IgnoreSize and [XYZ]MMword where applicable.
44 * i386-tbl.h: Re-generate.
45
625cbd7a
JB		 462018-07-19 Jan Beulich <jbeulich@suse.com>
47
48 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
49 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
50 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
51 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
52 * i386-tbl.h: Re-generate.
53
86b15c32
JB		 542018-07-19 Jan Beulich <jbeulich@suse.com>
55
56 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
57 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
58 VPCLMULQDQ templates into their respective AVX512VL counterparts
59 where possible, using Disp8ShiftVL and CheckRegSize instead of
60 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
61 * i386-tbl.h: Re-generate.
62
cf769ed5
JB		 632018-07-19 Jan Beulich <jbeulich@suse.com>
64
65 * i386-opc.tbl: Fold AVX512DQ templates into their respective
66 AVX512VL counterparts where possible, using Disp8ShiftVL and
67 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
68 IgnoreSize) as appropriate.
69 * i386-tbl.h: Re-generate.
70
8282b7ad
JB		 712018-07-19 Jan Beulich <jbeulich@suse.com>
72
73 * i386-opc.tbl: Fold AVX512BW templates into their respective
74 AVX512VL counterparts where possible, using Disp8ShiftVL and
75 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
76 IgnoreSize) as appropriate.
77 * i386-tbl.h: Re-generate.
78
755908cc
JB		 792018-07-19 Jan Beulich <jbeulich@suse.com>
80
81 * i386-opc.tbl: Fold AVX512CD templates into their respective
82 AVX512VL counterparts where possible, using Disp8ShiftVL and
83 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
84 IgnoreSize) as appropriate.
85 * i386-tbl.h: Re-generate.
86
7091c612
JB		 872018-07-19 Jan Beulich <jbeulich@suse.com>
88
89 * i386-opc.h (DISP8_SHIFT_VL): New.
90 * i386-opc.tbl (Disp8ShiftVL): Define.
91 (various): Fold AVX512VL templates into their respective
92 AVX512F counterparts where possible, using Disp8ShiftVL and
93 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
94 IgnoreSize) as appropriate.
95 * i386-tbl.h: Re-generate.
96
c30be56e
JB		 972018-07-19 Jan Beulich <jbeulich@suse.com>
98
99 * Makefile.am: Change dependencies and rule for
100 $(srcdir)/i386-init.h.
101 * Makefile.in: Re-generate.
102 * i386-gen.c (process_i386_opcodes): New local variable
103 "marker". Drop opening of input file. Recognize marker and line
104 number directives.
105 * i386-opc.tbl (OPCODE_I386_H): Define.
106 (i386-opc.h): Include it.
107 (None): Undefine.
108
11a322db
L		 1092018-07-18 H.J. Lu <hongjiu.lu@intel.com>
110
111 PR gas/23418
112 * i386-opc.h (Byte): Update comments.
113 (Word): Likewise.
114 (Dword): Likewise.
115 (Fword): Likewise.
116 (Qword): Likewise.
117 (Tbyte): Likewise.
118 (Xmmword): Likewise.
119 (Ymmword): Likewise.
120 (Zmmword): Likewise.
121 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
122 vcvttps2uqq.
123 * i386-tbl.h: Regenerated.
124
cde3679e
NC		 1252018-07-12 Sudakshina Das <sudi.das@arm.com>
126
127 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
128 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
129 * aarch64-asm-2.c: Regenerate.
130 * aarch64-dis-2.c: Regenerate.
131 * aarch64-opc-2.c: Regenerate.
132
45a28947
TC		 1332018-07-12 Tamar Christina <tamar.christina@arm.com>
134
135 PR binutils/23192
136 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
137 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
138 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
139 sqdmulh, sqrdmulh): Use Em16.
140
c597cc3d
SD		 1412018-07-11 Sudakshina Das <sudi.das@arm.com>
142
143 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
144 csdb together with them.
145 (thumb32_opcodes): Likewise.
146
a79eaed6
JB		 1472018-07-11 Jan Beulich <jbeulich@suse.com>
148
149 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
150 requiring 32-bit registers as operands 2 and 3. Improve
151 comments.
152 (mwait, mwaitx): Fold templates. Improve comments.
153 OPERAND_TYPE_INOUTPORTREG.
154 * i386-tbl.h: Re-generate.
155
2fb5be8d
JB		 1562018-07-11 Jan Beulich <jbeulich@suse.com>
157
158 * i386-gen.c (operand_type_init): Remove
159 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
160 OPERAND_TYPE_INOUTPORTREG.
161 * i386-init.h: Re-generate.
162
7f5cad30
JB		 1632018-07-11 Jan Beulich <jbeulich@suse.com>
164
165 * i386-opc.tbl (wrssd, wrussd): Add Dword.
166 (wrssq, wrussq): Add Qword.
167 * i386-tbl.h: Re-generate.
168
f0a85b07
JB		 1692018-07-11 Jan Beulich <jbeulich@suse.com>
170
171 * i386-opc.h: Rename OTMax to OTNum.
172 (OTNumOfUints): Adjust calculation.
173 (OTUnused): Directly alias to OTNum.
174
9dcb0ba4
MR		 1752018-07-09 Maciej W. Rozycki <macro@mips.com>
176
177 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
178 `reg_xys'.
179 (lea_reg_xys): Likewise.
180 (print_insn_loop_primitive): Rename `reg' local variable to
181 `reg_dxy'.
182
f311ba7e
TC		 1832018-07-06 Tamar Christina <tamar.christina@arm.com>
184
185 PR binutils/23242
186 * aarch64-tbl.h (ldarh): Fix disassembly mask.
187
cba05feb
TC		 1882018-07-06 Tamar Christina <tamar.christina@arm.com>
189
190 PR binutils/23369
191 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
192 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
193
471b9d15
MR		 1942018-07-02 Maciej W. Rozycki <macro@mips.com>
195
196 PR tdep/8282
197 * mips-dis.c (mips_option_arg_t): New enumeration.
198 (mips_options): New variable.
199 (disassembler_options_mips): New function.
200 (print_mips_disassembler_options): Reimplement in terms of
201 `disassembler_options_mips'.
202 * arm-dis.c (disassembler_options_arm): Adapt to using the
203 `disasm_options_and_args_t' structure.
204 * ppc-dis.c (disassembler_options_powerpc): Likewise.
205 * s390-dis.c (disassembler_options_s390): Likewise.
206
c0c468d5
TP		 2072018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
208
209 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
210 expected result.
211 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
212 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
213 * testsuite/ld-arm/tls-longplt.d: Likewise.
214
369c9167
TC		 2152018-06-29 Tamar Christina <tamar.christina@arm.com>
216
217 PR binutils/23192
218 * aarch64-asm-2.c: Regenerate.
219 * aarch64-dis-2.c: Likewise.
220 * aarch64-opc-2.c: Likewise.
221 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
222 * aarch64-opc.c (operand_general_constraint_met_p,
223 aarch64_print_operand): Likewise.
224 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
225 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
226 fmlal2, fmlsl2.
227 (AARCH64_OPERANDS): Add Em2.
228
30aa1306
NC		 2292018-06-26 Nick Clifton <nickc@redhat.com>
230
231 * po/uk.po: Updated Ukranian translation.
232 * po/de.po: Updated German translation.
233 * po/pt_BR.po: Updated Brazilian Portuguese translation.
234
eca4b721
NC		 2352018-06-26 Nick Clifton <nickc@redhat.com>
236
237 * nfp-dis.c: Fix spelling mistake.
238
71300e2c
NC		 2392018-06-24 Nick Clifton <nickc@redhat.com>
240
241 * configure: Regenerate.
242 * po/opcodes.pot: Regenerate.
243
719d8288
NC		 2442018-06-24 Nick Clifton <nickc@redhat.com>
245
246 2.31 branch created.
247
514cd3a0
TC		 2482018-06-19 Tamar Christina <tamar.christina@arm.com>
249
250 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
251 * aarch64-asm-2.c: Regenerate.
252 * aarch64-dis-2.c: Likewise.
253
385e4d0f
MR		 2542018-06-21 Maciej W. Rozycki <macro@mips.com>
255
256 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
257 `-M ginv' option description.
258
160d1b3d
SH		 2592018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
260
261 PR gas/23305
262 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
263 la and lla.
264
d0ac1c44
SM		 2652018-06-19 Simon Marchi <simon.marchi@ericsson.com>
266
267 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
268 * configure.ac: Remove AC_PREREQ.
269 * Makefile.in: Re-generate.
270 * aclocal.m4: Re-generate.
271 * configure: Re-generate.
272
6f20c942
FS		 2732018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
274
275 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
276 mips64r6 descriptors.
277 (parse_mips_ase_option): Handle -Mginv option.
278 (print_mips_disassembler_options): Document -Mginv.
279 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
280 (GINV): New macro.
281 (mips_opcodes): Define ginvi and ginvt.
282
730c3174
SE		 2832018-06-13 Scott Egerton <scott.egerton@imgtec.com>
284 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
285
286 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
287 * mips-opc.c (CRC, CRC64): New macros.
288 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
289 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
290 crc32cd for CRC64.
291
cb366992
EB		 2922018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
293
294 PR 20319
295 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
296 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
297
ce72cd46
AM		 2982018-06-06 Alan Modra <amodra@gmail.com>
299
300 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
301 setjmp. Move init for some other vars later too.
302
4b8e28c7
MF		 3032018-06-04 Max Filippov <jcmvbkbc@gmail.com>
304
305 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
306 (dis_private): Add new fields for property section tracking.
307 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
308 (xtensa_instruction_fits): New functions.
309 (fetch_data): Bump minimal fetch size to 4.
310 (print_insn_xtensa): Make struct dis_private static.
311 Load and prepare property table on section change.
312 Don't disassemble literals. Don't disassemble instructions that
313 cross property table boundaries.
314
55e99962
L		 3152018-06-01 H.J. Lu <hongjiu.lu@intel.com>
316
317 * configure: Regenerated.
318
733bd0ab
JB		 3192018-06-01 Jan Beulich <jbeulich@suse.com>
320
321 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
322 * i386-tbl.h: Re-generate.
323
dfd27d41
JB		 3242018-06-01 Jan Beulich <jbeulich@suse.com>
325
326 * i386-opc.tbl (sldt, str): Add NoRex64.
327 * i386-tbl.h: Re-generate.
328
64795710
JB		 3292018-06-01 Jan Beulich <jbeulich@suse.com>
330
331 * i386-opc.tbl (invpcid): Add Oword.
332 * i386-tbl.h: Re-generate.
333
030157d8
AM		 3342018-06-01 Alan Modra <amodra@gmail.com>
335
336 * sysdep.h (_bfd_error_handler): Don't declare.
337 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
338 * rl78-decode.opc: Likewise.
339 * msp430-decode.c: Regenerate.
340 * rl78-decode.c: Regenerate.
341
a9660a6f
AP		 3422018-05-30 Amit Pawar <Amit.Pawar@amd.com>
343
344 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
345 * i386-init.h : Regenerated.
346
277eb7f6
AM		 3472018-05-25 Alan Modra <amodra@gmail.com>
348
349 * Makefile.in: Regenerate.
350 * po/POTFILES.in: Regenerate.
351
98553ad3
PB		 3522018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
353
354 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
355 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
356 (insert_bab, extract_bab, insert_btab, extract_btab,
357 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
358 (BAT, BBA VBA RBS XB6S): Delete macros.
359 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
360 (BB, BD, RBX, XC6): Update for new macros.
361 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
362 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
363 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
364 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
365
7b4ae824
JD		 3662018-05-18 John Darrington <john@darrington.wattle.id.au>
367
368 * Makefile.am: Add support for s12z architecture.
369 * configure.ac: Likewise.
370 * disassemble.c: Likewise.
371 * disassemble.h: Likewise.
372 * Makefile.in: Regenerate.
373 * configure: Regenerate.
374 * s12z-dis.c: New file.
375 * s12z.h: New file.
376
29e0f0a1
AM		 3772018-05-18 Alan Modra <amodra@gmail.com>
378
379 * nfp-dis.c: Don't #include libbfd.h.
380 (init_nfp3200_priv): Use bfd_get_section_contents.
381 (nit_nfp6000_mecsr_sec): Likewise.
382
809276d2
NC		 3832018-05-17 Nick Clifton <nickc@redhat.com>
384
385 * po/zh_CN.po: Updated simplified Chinese translation.
386
ff329288
TC		 3872018-05-16 Tamar Christina <tamar.christina@arm.com>
388
389 PR binutils/23109
390 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
391 * aarch64-dis-2.c: Regenerate.
392
f9830ec1
TC		 3932018-05-15 Tamar Christina <tamar.christina@arm.com>
394
395 PR binutils/21446
396 * aarch64-asm.c (opintl.h): Include.
397 (aarch64_ins_sysreg): Enforce read/write constraints.
398 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
399 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
400 (F_REG_READ, F_REG_WRITE): New.
401 * aarch64-opc.c (aarch64_print_operand): Generate notes for
402 AARCH64_OPND_SYSREG.
403 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
404 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
405 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
406 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
407 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
408 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
409 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
410 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
411 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
412 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
413 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
414 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
415 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
416 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
417 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
418 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
419 msr (F_SYS_WRITE), mrs (F_SYS_READ).
420
7d02540a
TC		 4212018-05-15 Tamar Christina <tamar.christina@arm.com>
422
423 PR binutils/21446
424 * aarch64-dis.c (no_notes: New.
425 (parse_aarch64_dis_option): Support notes.
426 (aarch64_decode_insn, print_operands): Likewise.
427 (print_aarch64_disassembler_options): Document notes.
428 * aarch64-opc.c (aarch64_print_operand): Support notes.
429
561a72d4
TC		 4302018-05-15 Tamar Christina <tamar.christina@arm.com>
431
432 PR binutils/21446
433 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
434 and take error struct.
435 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
436 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
437 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
438 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
439 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
440 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
441 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
442 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
443 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
444 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
445 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
446 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
447 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
448 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
449 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
450 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
451 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
452 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
453 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
454 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
455 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
456 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
457 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
458 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
459 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
460 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
461 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
462 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
463 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
464 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
465 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
466 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
467 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
468 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
469 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
470 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
471 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
472 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
473 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
474 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
475 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
476 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
477 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
478 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
479 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
480 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
481 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
482 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
483 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
484 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
485 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
486 (determine_disassembling_preference, aarch64_decode_insn,
487 print_insn_aarch64_word, print_insn_data): Take errors struct.
488 (print_insn_aarch64): Use errors.
489 * aarch64-asm-2.c: Regenerate.
490 * aarch64-dis-2.c: Regenerate.
491 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
492 boolean in aarch64_insert_operan.
493 (print_operand_extractor): Likewise.
494 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
495
1678bd35
FT		 4962018-05-15 Francois H. Theron <francois.theron@netronome.com>
497
498 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
499
06cfb1c8
L		 5002018-05-09 H.J. Lu <hongjiu.lu@intel.com>
501
502 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
503
84f9f8c3
AM		 5042018-05-09 Sebastian Rasmussen <sebras@gmail.com>
505
506 * cr16-opc.c (cr16_instruction): Comment typo fix.
507 * hppa-dis.c (print_insn_hppa): Likewise.
508
e6f372ba
JW		 5092018-05-08 Jim Wilson <jimw@sifive.com>
510
511 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
512 (match_c_slli64, match_srxi_as_c_srxi): New.
513 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
514 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
515 <c.slli, c.srli, c.srai>: Use match_s_slli.
516 <c.slli64, c.srli64, c.srai64>: New.
517
f413a913
AM		 5182018-05-08 Alan Modra <amodra@gmail.com>
519
520 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
521 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
522 partition opcode space for index lookup.
523
a87a6478
PB		 5242018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
525
526 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
527 <insn_length>: ...with this. Update usage.
528 Remove duplicate call to *info->memory_error_func.
529
c0a30a9f
L		 5302018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
531 H.J. Lu <hongjiu.lu@intel.com>
532
533 * i386-dis.c (Gva): New.
534 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
535 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
536 (prefix_table): New instructions (see prefix above).
537 (mod_table): New instructions (see prefix above).
538 (OP_G): Handle va_mode.
539 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
540 CPU_MOVDIR64B_FLAGS.
541 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
542 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
543 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
544 * i386-opc.tbl: Add movidir{i,64b}.
545 * i386-init.h: Regenerated.
546 * i386-tbl.h: Likewise.
547
75c0a438
L		 5482018-05-07 H.J. Lu <hongjiu.lu@intel.com>
549
550 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
551 AddrPrefixOpReg.
552 * i386-opc.h (AddrPrefixOp0): Renamed to ...
553 (AddrPrefixOpReg): This.
554 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
555 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
556
2ceb7719
PB		 5572018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
558
559 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
560 (vle_num_opcodes): Likewise.
561 (spe2_num_opcodes): Likewise.
562 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
563 initialization loop.
564 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
565 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
566 only once.
567
b3ac5c6c
TC		 5682018-05-01 Tamar Christina <tamar.christina@arm.com>
569
570 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
571
fe944acf
FT		 5722018-04-30 Francois H. Theron <francois.theron@netronome.com>
573
574 Makefile.am: Added nfp-dis.c.
575 configure.ac: Added bfd_nfp_arch.
576 disassemble.h: Added print_insn_nfp prototype.
577 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
578 nfp-dis.c: New, for NFP support.
579 po/POTFILES.in: Added nfp-dis.c to the list.
580 Makefile.in: Regenerate.
581 configure: Regenerate.
582
e2195274
JB		 5832018-04-26 Jan Beulich <jbeulich@suse.com>
584
585 * i386-opc.tbl: Fold various non-memory operand AVX512VL
586 templates into their base ones.
587 * i386-tlb.h: Re-generate.
588
59ef5df4
JB		 5892018-04-26 Jan Beulich <jbeulich@suse.com>
590
591 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
592 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
593 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
594 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
595 * i386-init.h: Re-generate.
596
6e041cf4
JB		 5972018-04-26 Jan Beulich <jbeulich@suse.com>
598
599 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
600 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
601 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
602 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
603 comment.
604 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
605 and CpuRegMask.
606 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
607 CpuRegMask: Delete.
608 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
609 cpuregzmm, and cpuregmask.
610 * i386-init.h: Re-generate.
611 * i386-tbl.h: Re-generate.
612
0e0eea78
JB		 6132018-04-26 Jan Beulich <jbeulich@suse.com>
614
615 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
616 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
617 * i386-init.h: Re-generate.
618
2f1bada2
JB		 6192018-04-26 Jan Beulich <jbeulich@suse.com>
620
621 * i386-gen.c (VexImmExt): Delete.
622 * i386-opc.h (VexImmExt, veximmext): Delete.
623 * i386-opc.tbl: Drop all VexImmExt uses.
624 * i386-tlb.h: Re-generate.
625
bacd1457
JB		 6262018-04-25 Jan Beulich <jbeulich@suse.com>
627
628 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
629 register-only forms.
630 * i386-tlb.h: Re-generate.
631
10bba94b
TC		 6322018-04-25 Tamar Christina <tamar.christina@arm.com>
633
634 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
635
c48935d7
IT		 6362018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
637
638 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
639 PREFIX_0F1C.
640 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
641 (cpu_flags): Add CpuCLDEMOTE.
642 * i386-init.h: Regenerate.
643 * i386-opc.h (enum): Add CpuCLDEMOTE,
644 (i386_cpu_flags): Add cpucldemote.
645 * i386-opc.tbl: Add cldemote.
646 * i386-tbl.h: Regenerate.
647
211dc24b
AM		 6482018-04-16 Alan Modra <amodra@gmail.com>
649
650 * Makefile.am: Remove sh5 and sh64 support.
651 * configure.ac: Likewise.
652 * disassemble.c: Likewise.
653 * disassemble.h: Likewise.
654 * sh-dis.c: Likewise.
655 * sh64-dis.c: Delete.
656 * sh64-opc.c: Delete.
657 * sh64-opc.h: Delete.
658 * Makefile.in: Regenerate.
659 * configure: Regenerate.
660 * po/POTFILES.in: Regenerate.
661
a9a4b302
AM		 6622018-04-16 Alan Modra <amodra@gmail.com>
663
664 * Makefile.am: Remove w65 support.
665 * configure.ac: Likewise.
666 * disassemble.c: Likewise.
667 * disassemble.h: Likewise.
668 * w65-dis.c: Delete.
669 * w65-opc.h: Delete.
670 * Makefile.in: Regenerate.
671 * configure: Regenerate.
672 * po/POTFILES.in: Regenerate.
673
04cb01fd
AM		 6742018-04-16 Alan Modra <amodra@gmail.com>
675
676 * configure.ac: Remove we32k support.
677 * configure: Regenerate.
678
c2bf1eec
AM		 6792018-04-16 Alan Modra <amodra@gmail.com>
680
681 * Makefile.am: Remove m88k support.
682 * configure.ac: Likewise.
683 * disassemble.c: Likewise.
684 * disassemble.h: Likewise.
685 * m88k-dis.c: Delete.
686 * Makefile.in: Regenerate.
687 * configure: Regenerate.
688 * po/POTFILES.in: Regenerate.
689
6793974d
AM		 6902018-04-16 Alan Modra <amodra@gmail.com>
691
692 * Makefile.am: Remove i370 support.
693 * configure.ac: Likewise.
694 * disassemble.c: Likewise.
695 * disassemble.h: Likewise.
696 * i370-dis.c: Delete.
697 * i370-opc.c: Delete.
698 * Makefile.in: Regenerate.
699 * configure: Regenerate.
700 * po/POTFILES.in: Regenerate.
701
e82aa794
AM		 7022018-04-16 Alan Modra <amodra@gmail.com>
703
704 * Makefile.am: Remove h8500 support.
705 * configure.ac: Likewise.
706 * disassemble.c: Likewise.
707 * disassemble.h: Likewise.
708 * h8500-dis.c: Delete.
709 * h8500-opc.h: Delete.
710 * Makefile.in: Regenerate.
711 * configure: Regenerate.
712 * po/POTFILES.in: Regenerate.
713
fceadf09
AM		 7142018-04-16 Alan Modra <amodra@gmail.com>
715
716 * configure.ac: Remove tahoe support.
717 * configure: Regenerate.
718
ae1d3843
L		 7192018-04-15 H.J. Lu <hongjiu.lu@intel.com>
720
721 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
722 umwait.
723 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
724 64-bit mode.
725 * i386-tbl.h: Regenerated.
726
de89d0a3
IT		 7272018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
728
729 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
730 PREFIX_MOD_1_0FAE_REG_6.
731 (va_mode): New.
732 (OP_E_register): Use va_mode.
733 * i386-dis-evex.h (prefix_table):
734 New instructions (see prefixes above).
735 * i386-gen.c (cpu_flag_init): Add WAITPKG.
736 (cpu_flags): Likewise.
737 * i386-opc.h (enum): Likewise.
738 (i386_cpu_flags): Likewise.
739 * i386-opc.tbl: Add umonitor, umwait, tpause.
740 * i386-init.h: Regenerate.
741 * i386-tbl.h: Likewise.
742
a8eb42a8
AM		 7432018-04-11 Alan Modra <amodra@gmail.com>
744
745 * opcodes/i860-dis.c: Delete.
746 * opcodes/i960-dis.c: Delete.
747 * Makefile.am: Remove i860 and i960 support.
748 * configure.ac: Likewise.
749 * disassemble.c: Likewise.
750 * disassemble.h: Likewise.
751 * Makefile.in: Regenerate.
752 * configure: Regenerate.
753 * po/POTFILES.in: Regenerate.
754
caf0678c
L		 7552018-04-04 H.J. Lu <hongjiu.lu@intel.com>
756
757 PR binutils/23025
758 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
759 to 0.
760 (print_insn): Clear vex instead of vex.evex.
761
4fb0d2b9
NC		 7622018-04-04 Nick Clifton <nickc@redhat.com>
763
764 * po/es.po: Updated Spanish translation.
765
c39e5b26
JB		 7662018-03-28 Jan Beulich <jbeulich@suse.com>
767
768 * i386-gen.c (opcode_modifiers): Delete VecESize.
769 * i386-opc.h (VecESize): Delete.
770 (struct i386_opcode_modifier): Delete vecesize.
771 * i386-opc.tbl: Drop VecESize.
772 * i386-tlb.h: Re-generate.
773
8e6e0792
JB		 7742018-03-28 Jan Beulich <jbeulich@suse.com>
775
776 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
777 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
778 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
779 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
780 * i386-tlb.h: Re-generate.
781
9f123b91
JB		 7822018-03-28 Jan Beulich <jbeulich@suse.com>
783
784 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
785 Fold AVX512 forms
786 * i386-tlb.h: Re-generate.
787
9646c87b
JB		 7882018-03-28 Jan Beulich <jbeulich@suse.com>
789
790 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
791 (vex_len_table): Drop Y for vcvt*2si.
792 (putop): Replace plain 'Y' handling by abort().
793
c8d59609
NC		 7942018-03-28 Nick Clifton <nickc@redhat.com>
795
796 PR 22988
797 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
798 instructions with only a base address register.
799 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
800 handle AARHC64_OPND_SVE_ADDR_R.
801 (aarch64_print_operand): Likewise.
802 * aarch64-asm-2.c: Regenerate.
803 * aarch64_dis-2.c: Regenerate.
804 * aarch64-opc-2.c: Regenerate.
805
b8c169f3
JB		 8062018-03-22 Jan Beulich <jbeulich@suse.com>
807
808 * i386-opc.tbl: Drop VecESize from register only insn forms and
809 memory forms not allowing broadcast.
810 * i386-tlb.h: Re-generate.
811
96bc132a
JB		 8122018-03-22 Jan Beulich <jbeulich@suse.com>
813
814 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
815 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
816 sha256*): Drop Disp<N>.
817
9f79e886
JB		 8182018-03-22 Jan Beulich <jbeulich@suse.com>
819
820 * i386-dis.c (EbndS, bnd_swap_mode): New.
821 (prefix_table): Use EbndS.
822 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
823 * i386-opc.tbl (bndmov): Move misplaced Load.
824 * i386-tlb.h: Re-generate.
825
d6793fa1
JB		 8262018-03-22 Jan Beulich <jbeulich@suse.com>
827
828 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
829 templates allowing memory operands and folded ones for register
830 only flavors.
831 * i386-tlb.h: Re-generate.
832
f7768225
JB		 8332018-03-22 Jan Beulich <jbeulich@suse.com>
834
835 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
836 256-bit templates. Drop redundant leftover Disp<N>.
837 * i386-tlb.h: Re-generate.
838
0e35537d
JW		 8392018-03-14 Kito Cheng <kito.cheng@gmail.com>
840
841 * riscv-opc.c (riscv_insn_types): New.
842
b4a3689a
NC		 8432018-03-13 Nick Clifton <nickc@redhat.com>
844
845 * po/pt_BR.po: Updated Brazilian Portuguese translation.
846
d3d50934
L		 8472018-03-08 H.J. Lu <hongjiu.lu@intel.com>
848
849 * i386-opc.tbl: Add Optimize to clr.
850 * i386-tbl.h: Regenerated.
851
bd5dea88
L		 8522018-03-08 H.J. Lu <hongjiu.lu@intel.com>
853
854 * i386-gen.c (opcode_modifiers): Remove OldGcc.
855 * i386-opc.h (OldGcc): Removed.
856 (i386_opcode_modifier): Remove oldgcc.
857 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
858 instructions for old (<= 2.8.1) versions of gcc.
859 * i386-tbl.h: Regenerated.
860
e771e7c9
JB		 8612018-03-08 Jan Beulich <jbeulich@suse.com>
862
863 * i386-opc.h (EVEXDYN): New.
864 * i386-opc.tbl: Fold various AVX512VL templates.
865 * i386-tlb.h: Re-generate.
866
ed438a93
JB		 8672018-03-08 Jan Beulich <jbeulich@suse.com>
868
869 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
870 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
871 vpexpandd, vpexpandq): Fold AFX512VF templates.
872 * i386-tlb.h: Re-generate.
873
454172a9
JB		 8742018-03-08 Jan Beulich <jbeulich@suse.com>
875
876 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
877 Fold 128- and 256-bit VEX-encoded templates.
878 * i386-tlb.h: Re-generate.
879
36824150
JB		 8802018-03-08 Jan Beulich <jbeulich@suse.com>
881
882 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
883 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
884 vpexpandd, vpexpandq): Fold AVX512F templates.
885 * i386-tlb.h: Re-generate.
886
e7f5c0a9
JB		 8872018-03-08 Jan Beulich <jbeulich@suse.com>
888
889 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
890 64-bit templates. Drop Disp<N>.
891 * i386-tlb.h: Re-generate.
892
25a4277f
JB		 8932018-03-08 Jan Beulich <jbeulich@suse.com>
894
895 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
896 and 256-bit templates.
897 * i386-tlb.h: Re-generate.
898
d2224064
JB		 8992018-03-08 Jan Beulich <jbeulich@suse.com>
900
901 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
902 * i386-tlb.h: Re-generate.
903
1b193f0b
JB		 9042018-03-08 Jan Beulich <jbeulich@suse.com>
905
906 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
907 Drop NoAVX.
908 * i386-tlb.h: Re-generate.
909
f2f6a710
JB		 9102018-03-08 Jan Beulich <jbeulich@suse.com>
911
912 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
913 * i386-tlb.h: Re-generate.
914
38e314eb
JB		 9152018-03-08 Jan Beulich <jbeulich@suse.com>
916
917 * i386-gen.c (opcode_modifiers): Delete FloatD.
918 * i386-opc.h (FloatD): Delete.
919 (struct i386_opcode_modifier): Delete floatd.
920 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
921 FloatD by D.
922 * i386-tlb.h: Re-generate.
923
d53e6b98
JB		 9242018-03-08 Jan Beulich <jbeulich@suse.com>
925
926 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
927
2907c2f5
JB		 9282018-03-08 Jan Beulich <jbeulich@suse.com>
929
930 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
931 * i386-tlb.h: Re-generate.
932
73053c1f
JB		 9332018-03-08 Jan Beulich <jbeulich@suse.com>
934
935 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
936 forms.
937 * i386-tlb.h: Re-generate.
938
52fe4420
AM		 9392018-03-07 Alan Modra <amodra@gmail.com>
940
941 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
942 bfd_arch_rs6000.
943 * disassemble.h (print_insn_rs6000): Delete.
944 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
945 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
946 (print_insn_rs6000): Delete.
947
a6743a54
AM		 9482018-03-03 Alan Modra <amodra@gmail.com>
949
950 * sysdep.h (opcodes_error_handler): Define.
951 (_bfd_error_handler): Declare.
952 * Makefile.am: Remove stray #.
953 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
954 EDIT" comment.
955 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
956 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
957 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
958 opcodes_error_handler to print errors. Standardize error messages.
959 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
960 and include opintl.h.
961 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
962 * i386-gen.c: Standardize error messages.
963 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
964 * Makefile.in: Regenerate.
965 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
966 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
967 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
968 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
969 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
970 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
971 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
972 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
973 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
974 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
975 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
976 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
977 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
978
8305403a
L		 9792018-03-01 H.J. Lu <hongjiu.lu@intel.com>
980
981 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
982 vpsub[bwdq] instructions.
983 * i386-tbl.h: Regenerated.
984
e184813f
AM		 9852018-03-01 Alan Modra <amodra@gmail.com>
986
987 * configure.ac (ALL_LINGUAS): Sort.
988 * configure: Regenerate.
989
5b616bef
TP		 9902018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
991
992 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
993 macro by assignements.
994
b6f8c7c4
L		 9952018-02-27 H.J. Lu <hongjiu.lu@intel.com>
996
997 PR gas/22871
998 * i386-gen.c (opcode_modifiers): Add Optimize.
999 * i386-opc.h (Optimize): New enum.
1000 (i386_opcode_modifier): Add optimize.
1001 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1002 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1003 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1004 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1005 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1006 vpxord and vpxorq.
1007 * i386-tbl.h: Regenerated.
1008
e95b887f
AM		 10092018-02-26 Alan Modra <amodra@gmail.com>
1010
1011 * crx-dis.c (getregliststring): Allocate a large enough buffer
1012 to silence false positive gcc8 warning.
1013
0bccfb29
JW		 10142018-02-22 Shea Levy <shea@shealevy.com>
1015
1016 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1017
6b6b6807
L		 10182018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1019
1020 * i386-opc.tbl: Add {rex},
1021 * i386-tbl.h: Regenerated.
1022
75f31665
MR		 10232018-02-20 Maciej W. Rozycki <macro@mips.com>
1024
1025 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1026 (mips16_opcodes): Replace `M' with `m' for "restore".
1027
e207bc53
TP		 10282018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1029
1030 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1031
87993319
MR		 10322018-02-13 Maciej W. Rozycki <macro@mips.com>
1033
1034 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1035 variable to `function_index'.
1036
68d20676
NC		 10372018-02-13 Nick Clifton <nickc@redhat.com>
1038
1039 PR 22823
1040 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1041 about truncation of printing.
1042
d2159fdc
HW		 10432018-02-12 Henry Wong <henry@stuffedcow.net>
1044
1045 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1046
f174ef9f
NC		 10472018-02-05 Nick Clifton <nickc@redhat.com>
1048
1049 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1050
be3a8dca
IT		 10512018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1052
1053 * i386-dis.c (enum): Add pconfig.
1054 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1055 (cpu_flags): Add CpuPCONFIG.
1056 * i386-opc.h (enum): Add CpuPCONFIG.
1057 (i386_cpu_flags): Add cpupconfig.
1058 * i386-opc.tbl: Add PCONFIG instruction.
1059 * i386-init.h: Regenerate.
1060 * i386-tbl.h: Likewise.
1061
3233d7d0
IT		 10622018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1063
1064 * i386-dis.c (enum): Add PREFIX_0F09.
1065 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1066 (cpu_flags): Add CpuWBNOINVD.
1067 * i386-opc.h (enum): Add CpuWBNOINVD.
1068 (i386_cpu_flags): Add cpuwbnoinvd.
1069 * i386-opc.tbl: Add WBNOINVD instruction.
1070 * i386-init.h: Regenerate.
1071 * i386-tbl.h: Likewise.
1072
e925c834
JW		 10732018-01-17 Jim Wilson <jimw@sifive.com>
1074
1075 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1076
d777820b
IT		 10772018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1078
1079 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1080 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1081 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1082 (cpu_flags): Add CpuIBT, CpuSHSTK.
1083 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1084 (i386_cpu_flags): Add cpuibt, cpushstk.
1085 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1086 * i386-init.h: Regenerate.
1087 * i386-tbl.h: Likewise.
1088
f6efed01
NC		 10892018-01-16 Nick Clifton <nickc@redhat.com>
1090
1091 * po/pt_BR.po: Updated Brazilian Portugese translation.
1092 * po/de.po: Updated German translation.
1093
2721d702
JW		 10942018-01-15 Jim Wilson <jimw@sifive.com>
1095
1096 * riscv-opc.c (match_c_nop): New.
1097 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1098
616dcb87
NC		 10992018-01-15 Nick Clifton <nickc@redhat.com>
1100
1101 * po/uk.po: Updated Ukranian translation.
1102
3957a496
NC		 11032018-01-13 Nick Clifton <nickc@redhat.com>
1104
1105 * po/opcodes.pot: Regenerated.
1106
769c7ea5
NC		 11072018-01-13 Nick Clifton <nickc@redhat.com>
1108
1109 * configure: Regenerate.
1110
faf766e3
NC		 11112018-01-13 Nick Clifton <nickc@redhat.com>
1112
1113 2.30 branch created.
1114
888a89da
IT		 11152018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1116
1117 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1118 * i386-tbl.h: Regenerate.
1119
cbda583a
JB		 11202018-01-10 Jan Beulich <jbeulich@suse.com>
1121
1122 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1123 * i386-tbl.h: Re-generate.
1124
c9e92278
JB		 11252018-01-10 Jan Beulich <jbeulich@suse.com>
1126
1127 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1128 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1129 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1130 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1131 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1132 Disp8MemShift of AVX512VL forms.
1133 * i386-tbl.h: Re-generate.
1134
35fd2b2b
JW		 11352018-01-09 Jim Wilson <jimw@sifive.com>
1136
1137 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1138 then the hi_addr value is zero.
1139
91d8b670
JG		 11402018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1141
1142 * arm-dis.c (arm_opcodes): Add csdb.
1143 (thumb32_opcodes): Add csdb.
1144
be2e7d95
JG		 11452018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1146
1147 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1148 * aarch64-asm-2.c: Regenerate.
1149 * aarch64-dis-2.c: Regenerate.
1150 * aarch64-opc-2.c: Regenerate.
1151
704a705d
L		 11522018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1153
1154 PR gas/22681
1155 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1156 Remove AVX512 vmovd with 64-bit operands.
1157 * i386-tbl.h: Regenerated.
1158
35eeb78f
JW		 11592018-01-05 Jim Wilson <jimw@sifive.com>
1160
1161 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1162 jalr.
1163
219d1afa
AM		 11642018-01-03 Alan Modra <amodra@gmail.com>
1165
1166 Update year range in copyright notice of all files.
1167
1508bbf5
JB		 11682018-01-02 Jan Beulich <jbeulich@suse.com>
1169
1170 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1171 and OPERAND_TYPE_REGZMM entries.
1172
1e563868 1173For older changes see ChangeLog-2017
3499769a 1174\f
1e563868 1175Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1176
1177Copying and distribution of this file, with or without modification,
1178are permitted in any medium without royalty provided the copyright
1179notice and this notice are preserved.
1180
1181Local Variables:
1182mode: change-log
1183left-margin: 8
1184fill-column: 74
1185version-control: never
1186End:
GDB Binutils - Deliverables
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