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Reduce parameter list in bfd_elf32_arm_target_relocs
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1a336194
TP		 12016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
2
3 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
4 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
5 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
6
6b40c462
L		 72016-08-24 H.J. Lu <hongjiu.lu@intel.com>
8
9 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
10 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
11 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
12 PREFIX_MOD_3_0FAE_REG_4.
13 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
14 PREFIX_MOD_3_0FAE_REG_4.
15 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
16 (cpu_flags): Add CpuPTWRITE.
17 * i386-opc.h (CpuPTWRITE): New.
18 (i386_cpu_flags): Add cpuptwrite.
19 * i386-opc.tbl: Add ptwrite instruction.
20 * i386-init.h: Regenerated.
21 * i386-tbl.h: Likewise.
22
ab548d2d
AK		 232016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
24
25 * arc-dis.h: Wrap around in extern "C".
26
344bde0a
RS		 272016-08-23 Richard Sandiford <richard.sandiford@arm.com>
28
29 * aarch64-tbl.h (V8_2_INSN): New macro.
30 (aarch64_opcode_table): Use it.
31
5ce912d8
RS		 322016-08-23 Richard Sandiford <richard.sandiford@arm.com>
33
34 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
35 CORE_INSN, __FP_INSN and SIMD_INSN.
36
9d30b0bd
RS		 372016-08-23 Richard Sandiford <richard.sandiford@arm.com>
38
39 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
40 (aarch64_opcode_table): Update uses accordingly.
41
dfdaec14
AJ		 422016-07-25 Andrew Jenner <andrew@codesourcery.com>
43 Kwok Cheung Yeung <kcy@codesourcery.com>
44
45 opcodes/
46 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
47 'e_cmplwi' to 'e_cmpli' instead.
48 (OPVUPRT, OPVUPRT_MASK): Define.
49 (powerpc_opcodes): Add E200Z4 insns.
50 (vle_opcodes): Add context save/restore insns.
51
7bd374a4
MR		 522016-07-27 Maciej W. Rozycki <macro@imgtec.com>
53
54 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
55 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
56 "j".
57
db18dbab
GM		 582016-07-27 Graham Markall <graham.markall@embecosm.com>
59
60 * arc-nps400-tbl.h: Change block comments to GNU format.
61 * arc-dis.c: Add new globals addrtypenames,
62 addrtypenames_max, and addtypeunknown.
63 (get_addrtype): New function.
64 (print_insn_arc): Print colons and address types when
65 required.
66 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
67 define insert and extract functions for all address types.
68 (arc_operands): Add operands for colon and all address
69 types.
70 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
71 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
72 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
73 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
74 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
75 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
76
fecd57f9
L		 772016-07-21 H.J. Lu <hongjiu.lu@intel.com>
78
79 * configure: Regenerated.
80
37fd5ef3
CZ		 812016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
82
83 * arc-dis.c (skipclass): New structure.
84 (decodelist): New variable.
85 (is_compatible_p): New function.
86 (new_element): Likewise.
87 (skip_class_p): Likewise.
88 (find_format_from_table): Use skip_class_p function.
89 (find_format): Decode first the extension instructions.
90 (print_insn_arc): Select either ARCEM or ARCHS based on elf
91 e_flags.
92 (parse_option): New function.
93 (parse_disassembler_options): Likewise.
94 (print_arc_disassembler_options): Likewise.
95 (print_insn_arc): Use parse_disassembler_options function. Proper
96 select ARCv2 cpu variant.
97 * disassemble.c (disassembler_usage): Add ARC disassembler
98 options.
99
92281a5b
MR		 1002016-07-13 Maciej W. Rozycki <macro@imgtec.com>
101
102 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
103 annotation from the "nal" entry and reorder it beyond "bltzal".
104
6e7ced37
JM		 1052016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
106
107 * sparc-opc.c (ldtxa): New macro.
108 (sparc_opcodes): Use the macro defined above to add entries for
109 the LDTXA instructions.
110 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
111 instruction.
112
2f831b9a 1132016-07-07 James Bowman <james.bowman@ftdichip.com>
114
115 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
116 and "jmpc".
117
c07315e0
JB		 1182016-07-01 Jan Beulich <jbeulich@suse.com>
119
120 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
121 (movzb): Adjust to cover all permitted suffixes.
122 (movzw): New.
123 * i386-tbl.h: Re-generate.
124
9243100a
JB		 1252016-07-01 Jan Beulich <jbeulich@suse.com>
126
127 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
128 (lgdt): Remove Tbyte from non-64-bit variant.
129 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
130 xsaves64, xsavec64): Remove Disp16.
131 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
132 Remove Disp32S from non-64-bit variants. Remove Disp16 from
133 64-bit variants.
134 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
135 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
136 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
137 64-bit variants.
138 * i386-tbl.h: Re-generate.
139
8325cc63
JB		 1402016-07-01 Jan Beulich <jbeulich@suse.com>
141
142 * i386-opc.tbl (xlat): Remove RepPrefixOk.
143 * i386-tbl.h: Re-generate.
144
838441e4
YQ		 1452016-06-30 Yao Qi <yao.qi@linaro.org>
146
147 * arm-dis.c (print_insn): Fix typo in comment.
148
dab26bf4
RS		 1492016-06-28 Richard Sandiford <richard.sandiford@arm.com>
150
151 * aarch64-opc.c (operand_general_constraint_met_p): Check the
152 range of ldst_elemlist operands.
153 (print_register_list): Use PRIi64 to print the index.
154 (aarch64_print_operand): Likewise.
155
5703197e
TS		 1562016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
157
158 * mcore-opc.h: Remove sentinal.
159 * mcore-dis.c (print_insn_mcore): Adjust.
160
ce440d63
GM		 1612016-06-23 Graham Markall <graham.markall@embecosm.com>
162
163 * arc-opc.c: Correct description of availability of NPS400
164 features.
165
6fd3a02d
PB		 1662016-06-22 Peter Bergner <bergner@vnet.ibm.com>
167
168 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
169 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
170 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
171 xor3>: New mnemonics.
172 <setb>: Change to a VX form instruction.
173 (insert_sh6): Add support for rldixor.
174 (extract_sh6): Likewise.
175
6b477896
TS		 1762016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
177
178 * arc-ext.h: Wrap in extern C.
179
bdd582db
GM		 1802016-06-21 Graham Markall <graham.markall@embecosm.com>
181
182 * arc-dis.c (arc_insn_length): Add comment on instruction length.
183 Use same method for determining instruction length on ARC700 and
184 NPS-400.
185 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
186 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
187 with the NPS400 subclass.
188 * arc-opc.c: Likewise.
189
96074adc
JM		 1902016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
191
192 * sparc-opc.c (rdasr): New macro.
193 (wrasr): Likewise.
194 (rdpr): Likewise.
195 (wrpr): Likewise.
196 (rdhpr): Likewise.
197 (wrhpr): Likewise.
198 (sparc_opcodes): Use the macros above to fix and expand the
199 definition of read/write instructions from/to
200 asr/privileged/hyperprivileged instructions.
201 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
202 %hva_mask_nz. Prefer softint_set and softint_clear over
203 set_softint and clear_softint.
204 (print_insn_sparc): Support %ver in Rd.
205
7a10c22f
JM		 2062016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
207
208 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
209 architecture according to the hardware capabilities they require.
210
4f26fb3a
JM		 2112016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
212
213 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
214 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
215 bfd_mach_sparc_v9{c,d,e,v,m}.
216 * sparc-opc.c (MASK_V9C): Define.
217 (MASK_V9D): Likewise.
218 (MASK_V9E): Likewise.
219 (MASK_V9V): Likewise.
220 (MASK_V9M): Likewise.
221 (v6): Add MASK_V9{C,D,E,V,M}.
222 (v6notlet): Likewise.
223 (v7): Likewise.
224 (v8): Likewise.
225 (v9): Likewise.
226 (v9andleon): Likewise.
227 (v9a): Likewise.
228 (v9b): Likewise.
229 (v9c): Define.
230 (v9d): Likewise.
231 (v9e): Likewise.
232 (v9v): Likewise.
233 (v9m): Likewise.
234 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
235
3ee6e4fb
NC		 2362016-06-15 Nick Clifton <nickc@redhat.com>
237
238 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
239 constants to match expected behaviour.
240 (nds32_parse_opcode): Likewise. Also for whitespace.
241
02f3be19
AB		 2422016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
243
244 * arc-opc.c (extract_rhv1): Extract value from insn.
245
6f9f37ed 2462016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 247
248 * arc-nps400-tbl.h: Add ldbit instruction.
249 * arc-opc.c: Add flag classes required for ldbit.
250
6f9f37ed 2512016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 252
253 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
254 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
255 support the above instructions.
256
6f9f37ed 2572016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 258
259 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
260 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
261 csma, cbba, zncv, and hofs.
262 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
263 support the above instructions.
264
2652016-06-06 Graham Markall <graham.markall@embecosm.com>
266
267 * arc-nps400-tbl.h: Add andab and orab instructions.
268
2692016-06-06 Graham Markall <graham.markall@embecosm.com>
270
271 * arc-nps400-tbl.h: Add addl-like instructions.
272
2732016-06-06 Graham Markall <graham.markall@embecosm.com>
274
275 * arc-nps400-tbl.h: Add mxb and imxb instructions.
276
2772016-06-06 Graham Markall <graham.markall@embecosm.com>
278
279 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
280 instructions.
281
b2cc3f6f
AK		 2822016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
283
284 * s390-dis.c (option_use_insn_len_bits_p): New file scope
285 variable.
286 (init_disasm): Handle new command line option "insnlength".
287 (print_s390_disassembler_options): Mention new option in help
288 output.
289 (print_insn_s390): Use the encoded insn length when dumping
290 unknown instructions.
291
1857fe72
DC		 2922016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
293
294 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
295 to the address and set as symbol address for LDS/ STS immediate operands.
296
14b57c7c
AM		 2972016-06-07 Alan Modra <amodra@gmail.com>
298
299 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
300 cpu for "vle" to e500.
301 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
302 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
303 (PPCNONE): Delete, substitute throughout.
304 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
305 except for major opcode 4 and 31.
306 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
307
4d1464f2
MW		 3082016-06-07 Matthew Wahab <matthew.wahab@arm.com>
309
310 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
311 ARM_EXT_RAS in relevant entries.
312
026122a6
PB		 3132016-06-03 Peter Bergner <bergner@vnet.ibm.com>
314
315 PR binutils/20196
316 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
317 opcodes for E6500.
318
07f5af7d
L		 3192016-06-03 H.J. Lu <hongjiu.lu@intel.com>
320
321 PR binutis/18386
322 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
323 (indir_v_mode): New.
324 Add comments for '&'.
325 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
326 (putop): Handle '&'.
327 (intel_operand_size): Handle indir_v_mode.
328 (OP_E_register): Likewise.
329 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
330 64-bit indirect call/jmp for AMD64.
331 * i386-tbl.h: Regenerated
332
4eb6f892
AB		 3332016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
334
335 * arc-dis.c (struct arc_operand_iterator): New structure.
336 (find_format_from_table): All the old content from find_format,
337 with some minor adjustments, and parameter renaming.
338 (find_format_long_instructions): New function.
339 (find_format): Rewritten.
340 (arc_insn_length): Add LSB parameter.
341 (extract_operand_value): New function.
342 (operand_iterator_next): New function.
343 (print_insn_arc): Use new functions to find opcode, and iterator
344 over operands.
345 * arc-opc.c (insert_nps_3bit_dst_short): New function.
346 (extract_nps_3bit_dst_short): New function.
347 (insert_nps_3bit_src2_short): New function.
348 (extract_nps_3bit_src2_short): New function.
349 (insert_nps_bitop1_size): New function.
350 (extract_nps_bitop1_size): New function.
351 (insert_nps_bitop2_size): New function.
352 (extract_nps_bitop2_size): New function.
353 (insert_nps_bitop_mod4_msb): New function.
354 (extract_nps_bitop_mod4_msb): New function.
355 (insert_nps_bitop_mod4_lsb): New function.
356 (extract_nps_bitop_mod4_lsb): New function.
357 (insert_nps_bitop_dst_pos3_pos4): New function.
358 (extract_nps_bitop_dst_pos3_pos4): New function.
359 (insert_nps_bitop_ins_ext): New function.
360 (extract_nps_bitop_ins_ext): New function.
361 (arc_operands): Add new operands.
362 (arc_long_opcodes): New global array.
363 (arc_num_long_opcodes): New global.
364 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
365
1fe0971e
TS		 3662016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
367
368 * nds32-asm.h: Add extern "C".
369 * sh-opc.h: Likewise.
370
315f180f
GM		 3712016-06-01 Graham Markall <graham.markall@embecosm.com>
372
373 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
374 0,b,limm to the rflt instruction.
375
a2b5fccc
TS		 3762016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
377
378 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
379 constant.
380
0cbd0046
L		 3812016-05-29 H.J. Lu <hongjiu.lu@intel.com>
382
383 PR gas/20145
384 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
385 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
386 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
387 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
388 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
389 * i386-init.h: Regenerated.
390
1848e567
L		 3912016-05-27 H.J. Lu <hongjiu.lu@intel.com>
392
393 PR gas/20145
394 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
395 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
396 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
397 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
398 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
399 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
400 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
401 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
402 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
403 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
404 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
405 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
406 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
407 CpuRegMask for AVX512.
408 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
409 and CpuRegMask.
410 (set_bitfield_from_cpu_flag_init): New function.
411 (set_bitfield): Remove const on f. Call
412 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
413 * i386-opc.h (CpuRegMMX): New.
414 (CpuRegXMM): Likewise.
415 (CpuRegYMM): Likewise.
416 (CpuRegZMM): Likewise.
417 (CpuRegMask): Likewise.
418 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
419 and cpuregmask.
420 * i386-init.h: Regenerated.
421 * i386-tbl.h: Likewise.
422
e92bae62
L		 4232016-05-27 H.J. Lu <hongjiu.lu@intel.com>
424
425 PR gas/20154
426 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
427 (opcode_modifiers): Add AMD64 and Intel64.
428 (main): Properly verify CpuMax.
429 * i386-opc.h (CpuAMD64): Removed.
430 (CpuIntel64): Likewise.
431 (CpuMax): Set to CpuNo64.
432 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
433 (AMD64): New.
434 (Intel64): Likewise.
435 (i386_opcode_modifier): Add amd64 and intel64.
436 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
437 on call and jmp.
438 * i386-init.h: Regenerated.
439 * i386-tbl.h: Likewise.
440
e89c5eaa
L		 4412016-05-27 H.J. Lu <hongjiu.lu@intel.com>
442
443 PR gas/20154
444 * i386-gen.c (main): Fail if CpuMax is incorrect.
445 * i386-opc.h (CpuMax): Set to CpuIntel64.
446 * i386-tbl.h: Regenerated.
447
77d66e7b
NC		 4482016-05-27 Nick Clifton <nickc@redhat.com>
449
450 PR target/20150
451 * msp430-dis.c (msp430dis_read_two_bytes): New function.
452 (msp430dis_opcode_unsigned): New function.
453 (msp430dis_opcode_signed): New function.
454 (msp430_singleoperand): Use the new opcode reading functions.
455 Only disassenmble bytes if they were successfully read.
456 (msp430_doubleoperand): Likewise.
457 (msp430_branchinstr): Likewise.
458 (msp430x_callx_instr): Likewise.
459 (print_insn_msp430): Check that it is safe to read bytes before
460 attempting disassembly. Use the new opcode reading functions.
461
19dfcc89
PB		 4622016-05-26 Peter Bergner <bergner@vnet.ibm.com>
463
464 * ppc-opc.c (CY): New define. Document it.
465 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
466
f3ad7637
L		 4672016-05-25 H.J. Lu <hongjiu.lu@intel.com>
468
469 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
470 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
471 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
472 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
473 CPU_ANY_AVX_FLAGS.
474 * i386-init.h: Regenerated.
475
f1360d58
L		 4762016-05-25 H.J. Lu <hongjiu.lu@intel.com>
477
478 PR gas/20141
479 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
480 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
481 * i386-init.h: Regenerated.
482
293f5f65
L		 4832016-05-25 H.J. Lu <hongjiu.lu@intel.com>
484
485 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
486 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
487 * i386-init.h: Regenerated.
488
d9eca1df
CZ		 4892016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
490
491 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
492 information.
493 (print_insn_arc): Set insn_type information.
494 * arc-opc.c (C_CC): Add F_CLASS_COND.
495 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
496 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
497 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
498 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
499 (brne, brne_s, jeq_s, jne_s): Likewise.
500
87789e08
CZ		 5012016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
502
503 * arc-tbl.h (neg): New instruction variant.
504
c810e0b8
CZ		 5052016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
506
507 * arc-dis.c (find_format, find_format, get_auxreg)
508 (print_insn_arc): Changed.
509 * arc-ext.h (INSERT_XOP): Likewise.
510
3d207518
TS		 5112016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
512
513 * tic54x-dis.c (sprint_mmr): Adjust.
514 * tic54x-opc.c: Likewise.
515
514e58b7
AM		 5162016-05-19 Alan Modra <amodra@gmail.com>
517
518 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
519
e43de63c
AM		 5202016-05-19 Alan Modra <amodra@gmail.com>
521
522 * ppc-opc.c: Formatting.
523 (NSISIGNOPT): Define.
524 (powerpc_opcodes <subis>): Use NSISIGNOPT.
525
1401d2fe
MR		 5262016-05-18 Maciej W. Rozycki <macro@imgtec.com>
527
528 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
529 replacing references to `micromips_ase' throughout.
530 (_print_insn_mips): Don't use file-level microMIPS annotation to
531 determine the disassembly mode with the symbol table.
532
1178da44
PB		 5332016-05-13 Peter Bergner <bergner@vnet.ibm.com>
534
535 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
536
8f4f9071
MF		 5372016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
538
539 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
540 mips64r6.
541 * mips-opc.c (D34): New macro.
542 (mips_builtin_opcodes): Define bposge32c for DSPr3.
543
8bc52696
AF		 5442016-05-10 Alexander Fomin <alexander.fomin@intel.com>
545
546 * i386-dis.c (prefix_table): Add RDPID instruction.
547 * i386-gen.c (cpu_flag_init): Add RDPID flag.
548 (cpu_flags): Add RDPID bitfield.
549 * i386-opc.h (enum): Add RDPID element.
550 (i386_cpu_flags): Add RDPID field.
551 * i386-opc.tbl: Add RDPID instruction.
552 * i386-init.h: Regenerate.
553 * i386-tbl.h: Regenerate.
554
39d911fc
TP		 5552016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
556
557 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
558 branch type of a symbol.
559 (print_insn): Likewise.
560
16a1fa25
TP		 5612016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
562
563 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
564 Mainline Security Extensions instructions.
565 (thumb_opcodes): Add entries for narrow ARMv8-M Security
566 Extensions instructions.
567 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
568 instructions.
569 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
570 special registers.
571
d751b79e
JM		 5722016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
573
574 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
575
945e0f82
CZ		 5762016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
577
578 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
579 (arcExtMap_genOpcode): Likewise.
580 * arc-opc.c (arg_32bit_rc): Define new variable.
581 (arg_32bit_u6): Likewise.
582 (arg_32bit_limm): Likewise.
583
20f55f38
SN		 5842016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
585
586 * aarch64-gen.c (VERIFIER): Define.
587 * aarch64-opc.c (VERIFIER): Define.
588 (verify_ldpsw): Use static linkage.
589 * aarch64-opc.h (verify_ldpsw): Remove.
590 * aarch64-tbl.h: Use VERIFIER for verifiers.
591
4bd13cde
NC		 5922016-04-28 Nick Clifton <nickc@redhat.com>
593
594 PR target/19722
595 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
596 * aarch64-opc.c (verify_ldpsw): New function.
597 * aarch64-opc.h (verify_ldpsw): New prototype.
598 * aarch64-tbl.h: Add initialiser for verifier field.
599 (LDPSW): Set verifier to verify_ldpsw.
600
c0f92bf9
L		 6012016-04-23 H.J. Lu <hongjiu.lu@intel.com>
602
603 PR binutils/19983
604 PR binutils/19984
605 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
606 smaller than address size.
607
e6c7cdec
TS		 6082016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
609
610 * alpha-dis.c: Regenerate.
611 * crx-dis.c: Likewise.
612 * disassemble.c: Likewise.
613 * epiphany-opc.c: Likewise.
614 * fr30-opc.c: Likewise.
615 * frv-opc.c: Likewise.
616 * ip2k-opc.c: Likewise.
617 * iq2000-opc.c: Likewise.
618 * lm32-opc.c: Likewise.
619 * lm32-opinst.c: Likewise.
620 * m32c-opc.c: Likewise.
621 * m32r-opc.c: Likewise.
622 * m32r-opinst.c: Likewise.
623 * mep-opc.c: Likewise.
624 * mt-opc.c: Likewise.
625 * or1k-opc.c: Likewise.
626 * or1k-opinst.c: Likewise.
627 * tic80-opc.c: Likewise.
628 * xc16x-opc.c: Likewise.
629 * xstormy16-opc.c: Likewise.
630
537aefaf
AB		 6312016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
632
633 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
634 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
635 calcsd, and calcxd instructions.
636 * arc-opc.c (insert_nps_bitop_size): Delete.
637 (extract_nps_bitop_size): Delete.
638 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
639 (extract_nps_qcmp_m3): Define.
640 (extract_nps_qcmp_m2): Define.
641 (extract_nps_qcmp_m1): Define.
642 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
643 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
644 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
645 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
646 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
647 NPS_QCMP_M3.
648
c8f785f2
AB		 6492016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
650
651 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
652
6fd8e7c2
L		 6532016-04-15 H.J. Lu <hongjiu.lu@intel.com>
654
655 * Makefile.in: Regenerated with automake 1.11.6.
656 * aclocal.m4: Likewise.
657
4b0c052e
AB		 6582016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
659
660 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
661 instructions.
662 * arc-opc.c (insert_nps_cmem_uimm16): New function.
663 (extract_nps_cmem_uimm16): New function.
664 (arc_operands): Add NPS_XLDST_UIMM16 operand.
665
cb040366
AB		 6662016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
667
668 * arc-dis.c (arc_insn_length): New function.
669 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
670 (find_format): Change insnLen parameter to unsigned.
671
accc0180
NC		 6722016-04-13 Nick Clifton <nickc@redhat.com>
673
674 PR target/19937
675 * v850-opc.c (v850_opcodes): Correct masks for long versions of
676 the LD.B and LD.BU instructions.
677
f36e33da
CZ		 6782016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
679
680 * arc-dis.c (find_format): Check for extension flags.
681 (print_flags): New function.
682 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
683 .extAuxRegister.
684 * arc-ext.c (arcExtMap_coreRegName): Use
685 LAST_EXTENSION_CORE_REGISTER.
686 (arcExtMap_coreReadWrite): Likewise.
687 (dump_ARC_extmap): Update printing.
688 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
689 (arc_aux_regs): Add cpu field.
690 * arc-regs.h: Add cpu field, lower case name aux registers.
691
1c2e355e
CZ		 6922016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
693
694 * arc-tbl.h: Add rtsc, sleep with no arguments.
695
b99747ae
CZ		 6962016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
697
698 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
699 Initialize.
700 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
701 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
702 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
703 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
704 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
705 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
706 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
707 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
708 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
709 (arc_opcode arc_opcodes): Null terminate the array.
710 (arc_num_opcodes): Remove.
711 * arc-ext.h (INSERT_XOP): Define.
712 (extInstruction_t): Likewise.
713 (arcExtMap_instName): Delete.
714 (arcExtMap_insn): New function.
715 (arcExtMap_genOpcode): Likewise.
716 * arc-ext.c (ExtInstruction): Remove.
717 (create_map): Zero initialize instruction fields.
718 (arcExtMap_instName): Remove.
719 (arcExtMap_insn): New function.
720 (dump_ARC_extmap): More info while debuging.
721 (arcExtMap_genOpcode): New function.
722 * arc-dis.c (find_format): New function.
723 (print_insn_arc): Use find_format.
724 (arc_get_disassembler): Enable dump_ARC_extmap only when
725 debugging.
726
92708cec
MR		 7272016-04-11 Maciej W. Rozycki <macro@imgtec.com>
728
729 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
730 instruction bits out.
731
a42a4f84
AB		 7322016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
733
734 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
735 * arc-opc.c (arc_flag_operands): Add new flags.
736 (arc_flag_classes): Add new classes.
737
1328504b
AB		 7382016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
739
740 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
741
820f03ff
AB		 7422016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
743
744 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
745 encode1, rflt, crc16, and crc32 instructions.
746 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
747 (arc_flag_classes): Add C_NPS_R.
748 (insert_nps_bitop_size_2b): New function.
749 (extract_nps_bitop_size_2b): Likewise.
750 (insert_nps_bitop_uimm8): Likewise.
751 (extract_nps_bitop_uimm8): Likewise.
752 (arc_operands): Add new operand entries.
753
8ddf6b2a
CZ		 7542016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
755
b99747ae
CZ		 756 * arc-regs.h: Add a new subclass field. Add double assist
757 accumulator register values.
758 * arc-tbl.h: Use DPA subclass to mark the double assist
759 instructions. Use DPX/SPX subclas to mark the FPX instructions.
760 * arc-opc.c (RSP): Define instead of SP.
761 (arc_aux_regs): Add the subclass field.
8ddf6b2a 762
589a7d88
JW		 7632016-04-05 Jiong Wang <jiong.wang@arm.com>
764
765 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
766
0a191de9 7672016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 768
769 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
770 NPS_R_SRC1.
771
0a106562
AB		 7722016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
773
774 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
775 issues. No functional changes.
776
bd05ac5f
CZ		 7772016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
778
b99747ae
CZ		 779 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
780 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
781 (RTT): Remove duplicate.
782 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
783 (PCT_CONFIG*): Remove.
784 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 785
9885948f
CZ		 7862016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
787
b99747ae 788 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 789
f2dd8838
CZ		 7902016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
791
b99747ae
CZ		 792 * arc-tbl.h (invld07): Remove.
793 * arc-ext-tbl.h: New file.
794 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
795 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 796
0d2f91fe
JK		 7972016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
798
799 Fix -Wstack-usage warnings.
800 * aarch64-dis.c (print_operands): Substitute size.
801 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
802
a6b71f42
JM		 8032016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
804
805 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
806 to get a proper diagnostic when an invalid ASR register is used.
807
9780e045
NC		 8082016-03-22 Nick Clifton <nickc@redhat.com>
809
810 * configure: Regenerate.
811
e23e8ebe
AB		 8122016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
813
814 * arc-nps400-tbl.h: New file.
815 * arc-opc.c: Add top level comment.
816 (insert_nps_3bit_dst): New function.
817 (extract_nps_3bit_dst): New function.
818 (insert_nps_3bit_src2): New function.
819 (extract_nps_3bit_src2): New function.
820 (insert_nps_bitop_size): New function.
821 (extract_nps_bitop_size): New function.
822 (arc_flag_operands): Add nps400 entries.
823 (arc_flag_classes): Add nps400 entries.
824 (arc_operands): Add nps400 entries.
825 (arc_opcodes): Add nps400 include.
826
1ae8ab47
AB		 8272016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
828
829 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
830 the new class enum values.
831
8699fc3e
AB		 8322016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
833
834 * arc-dis.c (print_insn_arc): Handle nps400.
835
24740d83
AB		 8362016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
837
838 * arc-opc.c (BASE): Delete.
839
8678914f
NC		 8402016-03-18 Nick Clifton <nickc@redhat.com>
841
842 PR target/19721
843 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
844 of MOV insn that aliases an ORR insn.
845
cc933301
JW		 8462016-03-16 Jiong Wang <jiong.wang@arm.com>
847
848 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
849
f86f5863
TS		 8502016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
851
852 * mcore-opc.h: Add const qualifiers.
853 * microblaze-opc.h (struct op_code_struct): Likewise.
854 * sh-opc.h: Likewise.
855 * tic4x-dis.c (tic4x_print_indirect): Likewise.
856 (tic4x_print_op): Likewise.
857
62de1c63
AM		 8582016-03-02 Alan Modra <amodra@gmail.com>
859
d11698cd 860 * or1k-desc.h: Regenerate.
62de1c63 861 * fr30-ibld.c: Regenerate.
c697cf0b 862 * rl78-decode.c: Regenerate.
62de1c63 863
020efce5
NC		 8642016-03-01 Nick Clifton <nickc@redhat.com>
865
866 PR target/19747
867 * rl78-dis.c (print_insn_rl78_common): Fix typo.
868
b0c11777
RL		 8692016-02-24 Renlin Li <renlin.li@arm.com>
870
871 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
872 (print_insn_coprocessor): Support fp16 instructions.
873
3e309328
RL		 8742016-02-24 Renlin Li <renlin.li@arm.com>
875
876 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
877 vminnm, vrint(mpna).
878
8afc7bea
RL		 8792016-02-24 Renlin Li <renlin.li@arm.com>
880
881 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
882 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
883
4fd7268a
L		 8842016-02-15 H.J. Lu <hongjiu.lu@intel.com>
885
886 * i386-dis.c (print_insn): Parenthesize expression to prevent
887 truncated addresses.
888 (OP_J): Likewise.
889
4670103e
CZ		 8902016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
891 Janek van Oirschot <jvanoirs@synopsys.com>
892
b99747ae
CZ		 893 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
894 variable.
4670103e 895
c1d9289f
NC		 8962016-02-04 Nick Clifton <nickc@redhat.com>
897
898 PR target/19561
899 * msp430-dis.c (print_insn_msp430): Add a special case for
900 decoding an RRC instruction with the ZC bit set in the extension
901 word.
902
a143b004
AB		 9032016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
904
905 * cgen-ibld.in (insert_normal): Rework calculation of shift.
906 * epiphany-ibld.c: Regenerate.
907 * fr30-ibld.c: Regenerate.
908 * frv-ibld.c: Regenerate.
909 * ip2k-ibld.c: Regenerate.
910 * iq2000-ibld.c: Regenerate.
911 * lm32-ibld.c: Regenerate.
912 * m32c-ibld.c: Regenerate.
913 * m32r-ibld.c: Regenerate.
914 * mep-ibld.c: Regenerate.
915 * mt-ibld.c: Regenerate.
916 * or1k-ibld.c: Regenerate.
917 * xc16x-ibld.c: Regenerate.
918 * xstormy16-ibld.c: Regenerate.
919
b89807c6
AB		 9202016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
921
922 * epiphany-dis.c: Regenerated from latest cpu files.
923
d8c823c8
MM		 9242016-02-01 Michael McConville <mmcco@mykolab.com>
925
926 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
927 test bit.
928
5bc5ae88
RL		 9292016-01-25 Renlin Li <renlin.li@arm.com>
930
931 * arm-dis.c (mapping_symbol_for_insn): New function.
932 (find_ifthen_state): Call mapping_symbol_for_insn().
933
0bff6e2d
MW		 9342016-01-20 Matthew Wahab <matthew.wahab@arm.com>
935
936 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
937 of MSR UAO immediate operand.
938
100b4f2e
MR		 9392016-01-18 Maciej W. Rozycki <macro@imgtec.com>
940
941 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
942 instruction support.
943
5c14705f
AM		 9442016-01-17 Alan Modra <amodra@gmail.com>
945
946 * configure: Regenerate.
947
4d82fe66
NC		 9482016-01-14 Nick Clifton <nickc@redhat.com>
949
950 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
951 instructions that can support stack pointer operations.
952 * rl78-decode.c: Regenerate.
953 * rl78-dis.c: Fix display of stack pointer in MOVW based
954 instructions.
955
651657fa
MW		 9562016-01-14 Matthew Wahab <matthew.wahab@arm.com>
957
958 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
959 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
960 erxtatus_el1 and erxaddr_el1.
961
105bde57
MW		 9622016-01-12 Matthew Wahab <matthew.wahab@arm.com>
963
964 * arm-dis.c (arm_opcodes): Add "esb".
965 (thumb_opcodes): Likewise.
966
afa8d405
PB		 9672016-01-11 Peter Bergner <bergner@vnet.ibm.com>
968
969 * ppc-opc.c <xscmpnedp>: Delete.
970 <xvcmpnedp>: Likewise.
971 <xvcmpnedp.>: Likewise.
972 <xvcmpnesp>: Likewise.
973 <xvcmpnesp.>: Likewise.
974
83c3256e
AS		 9752016-01-08 Andreas Schwab <schwab@linux-m68k.org>
976
977 PR gas/13050
978 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
979 addition to ISA_A.
980
6f2750fe
AM		 9812016-01-01 Alan Modra <amodra@gmail.com>
982
983 Update year range in copyright notice of all files.
984
3499769a
AM		 985For older changes see ChangeLog-2015
986\f
987Copyright (C) 2016 Free Software Foundation, Inc.
988
989Copying and distribution of this file, with or without modification,
990are permitted in any medium without royalty provided the copyright
991notice and this notice are preserved.
992
993Local Variables:
994mode: change-log
995left-margin: 8
996fill-column: 74
997version-control: never
998End:
GDB Binutils - Deliverables
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