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[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6b4680fb
MW		 12015-12-14 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
7 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
8 to the scalar three same group.
9
51d543ed
MW		 102015-12-14 Matthew Wahab <matthew.wahab@arm.com>
11
12 * aarch64-asm-2.c: Regenerate.
13 * aarch64-dis-2.c: Regenerate.
14 * aarch64-opc-2.c: Regenerate.
15 * aarch64-tbl.h (QL_V3SAMEH): New.
16 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
17 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
18 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
19 fcmgt, facgt and fminp to the vector three same group.
20
40d16a76
MW		 212015-12-14 Matthew Wahab <matthew.wahab@arm.com>
22
23 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
24 (SIMD_F16): New.
25
63511907
MW		 262015-12-14 Matthew Wahab <matthew.wahab@arm.com>
27
28 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
29 removed statement.
30 (aarch64_pstatefield_supported_p): Move feature checks for AT
31 registers ..
32 (aarch64_sys_ins_reg_supported_p): .. to here.
33
b817670b
AM		 342015-12-12 Alan Modra <amodra@gmail.com>
35
36 PR 19359
37 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
38 (powerpc_opcodes): Remove single-operand mfcr.
39
9ed608f9
MW		 402015-12-11 Matthew Wahab <matthew.wahab@arm.com>
41
42 * aarch64-asm.c (aarch64_ins_hint): New.
43 * aarch64-asm.h (aarch64_ins_hint): Declare.
44 * aarch64-dis.c (aarch64_ext_hint): New.
45 * aarch64-dis.h (aarch64_ext_hint): Declare.
46 * aarch64-opc-2.c: Regenerate.
47 * aarch64-opc.c (aarch64_hint_options): New.
48 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
49
a0f7013a
MW		 502015-12-11 Matthew Wahab <matthew.wahab@arm.com>
51
52 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
53
55c144e6
MW		 542015-12-11 Matthew Wahab <matthew.wahab@arm.com>
55
56 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
57 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
58 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
59 pmscr_el2.
60 (aarch64_sys_reg_supported_p): Add architecture feature tests for
61 the new registers.
62
22a5455c
MW		 632015-12-10 Matthew Wahab <matthew.wahab@arm.com>
64
65 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
66 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
67 feature test for "s1e1rp" and "s1e1wp".
68
d6bf7ce6
MW		 692015-12-10 Matthew Wahab <matthew.wahab@arm.com>
70
71 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
72 (aarch64_sys_ins_reg_supported_p): New.
73
ea2deeec
MW		 742015-12-10 Matthew Wahab <matthew.wahab@arm.com>
75
76 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
77 with aarch64_sys_ins_reg_has_xt.
78 (aarch64_ext_sysins_op): Likewise.
79 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
80 (F_HASXT): New.
81 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
82 (aarch64_sys_regs_dc): Likewise.
83 (aarch64_sys_regs_at): Likewise.
84 (aarch64_sys_regs_tlbi): Likewise.
85 (aarch64_sys_ins_reg_has_xt): New.
86
6479e48e
MW		 872015-12-10 Matthew Wahab <matthew.wahab@arm.com>
88
89 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
90 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
91 (aarch64_pstatefields): Add "uao".
92 (aarch64_pstatefield_supported_p): Add checks for "uao".
93
47f81142
MW		 942015-12-10 Matthew Wahab <matthew.wahab@arm.com>
95
96 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
97 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
98 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
99 (aarch64_sys_reg_supported_p): Add architecture feature tests for
100 new registers.
101
c8a6db6f
MW		 1022015-12-10 Matthew Wahab <matthew.wahab@arm.com>
103
104 * aarch64-asm-2.c: Regenerate.
105 * aarch64-dis-2.c: Regenerate.
106 * aarch64-tbl.h (aarch64_feature_ras): New.
107 (RAS): New.
108 (aarch64_opcode_table): Add "esb".
109
8eab4136
L		 1102015-12-09 H.J. Lu <hongjiu.lu@intel.com>
111
112 * i386-dis.c (MOD_0F01_REG_5): New.
113 (RM_0F01_REG_5): Likewise.
114 (reg_table): Use MOD_0F01_REG_5.
115 (mod_table): Add MOD_0F01_REG_5.
116 (rm_table): Add RM_0F01_REG_5.
117 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
118 (cpu_flags): Add CpuOSPKE.
119 * i386-opc.h (CpuOSPKE): New.
120 (i386_cpu_flags): Add cpuospke.
121 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
122 * i386-init.h: Regenerated.
123 * i386-tbl.h: Likewise.
124
1eac08cc
DD		 1252015-12-07 DJ Delorie <dj@redhat.com>
126
127 * rl78-decode.opc: Enable MULU for all ISAs.
128 * rl78-decode.c: Regenerate.
129
dd2887fc
AM		 1302015-12-07 Alan Modra <amodra@gmail.com>
131
132 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
133 major opcode/xop.
134
24b368f8
CZ		 1352015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
136
137 * arc-dis.c (special_flag_p): Match full mnemonic.
138 * arc-opc.c (print_insn_arc): Check section size to read
139 appropriate number of bytes. Fix printing.
140 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
141 arguments.
142
3395762e
AV		 1432015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
144
145 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
146 <ldah>: ... to this.
147
622b9eb1
MW		 1482015-11-27 Matthew Wahab <matthew.wahab@arm.com>
149
150 * aarch64-asm-2.c: Regenerate.
151 * aarch64-dis-2.c: Regenerate.
152 * aarch64-opc-2.c: Regenerate.
153 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
154 (QL_INT2FP_H, QL_FP2INT_H): New.
155 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
156 (QL_DST_H): New.
157 (QL_FCCMP_H): New.
158 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
159 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
160 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
161 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
162 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
163 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
164 fcsel.
165
cf86120b
MW		 1662015-11-27 Matthew Wahab <matthew.wahab@arm.com>
167
168 * aarch64-opc.c (half_conv_t): New.
169 (expand_fp_imm): Replace is_dp flag with the parameter size to
170 specify the number of bytes for the required expansion. Treat
171 a 16-bit expansion like a 32-bit expansion. Add check for an
172 unsupported size request. Update comment.
173 (aarch64_print_operand): Update to support 16-bit floating point
174 values. Update for changes to expand_fp_imm.
175
3bd894a7
MW		 1762015-11-27 Matthew Wahab <matthew.wahab@arm.com>
177
178 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
179 (FP_F16): New.
180
64357d2e
MW		 1812015-11-27 Matthew Wahab <matthew.wahab@arm.com>
182
183 * aarch64-asm-2.c: Regenerate.
184 * aarch64-dis-2.c: Regenerate.
185 * aarch64-opc-2.c: Regenerate.
186 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
187 "rev64".
188
d685192a
MW		 1892015-11-27 Matthew Wahab <matthew.wahab@arm.com>
190
191 * aarch64-asm-2.c: Regenerate.
192 * aarch64-asm.c (convert_bfc_to_bfm): New.
193 (convert_to_real): Add case for OP_BFC.
194 * aarch64-dis-2.c: Regenerate.
195 * aarch64-dis.c: (convert_bfm_to_bfc): New.
196 (convert_to_alias): Add case for OP_BFC.
197 * aarch64-opc-2.c: Regenerate.
198 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
199 to allow width operand in three-operand instructions.
200 * aarch64-tbl.h (QL_BF1): New.
201 (aarch64_feature_v8_2): New.
202 (ARMV8_2): New.
203 (aarch64_opcode_table): Add "bfc".
204
35822b38
MW		 2052015-11-27 Matthew Wahab <matthew.wahab@arm.com>
206
207 * aarch64-asm-2.c: Regenerate.
208 * aarch64-dis-2.c: Regenerate.
209 * aarch64-dis.c: Weaken assert.
210 * aarch64-gen.c: Include the instruction in the list of its
211 possible aliases.
212
1a04d1a7
MW		 2132015-11-27 Matthew Wahab <matthew.wahab@arm.com>
214
215 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
216 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
217 feature test.
218
e49d43ff
TG		 2192015-11-23 Tristan Gingold <gingold@adacore.com>
220
221 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
222
250aafa4
MW		 2232015-11-20 Matthew Wahab <matthew.wahab@arm.com>
224
225 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
226 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
227 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
228 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
229 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
230 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
231 cnthv_ctl_el2, cnthv_cval_el2.
232 (aarch64_sys_reg_supported_p): Update for the new system
233 registers.
234
a915c10f
NC		 2352015-11-20 Nick Clifton <nickc@redhat.com>
236
237 PR binutils/19224
238 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
239
f8c2a965
NC		 2402015-11-20 Nick Clifton <nickc@redhat.com>
241
242 * po/zh_CN.po: Updated simplified Chinese translation.
243
c2825638
MW		 2442015-11-19 Matthew Wahab <matthew.wahab@arm.com>
245
246 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
247 of MSR PAN immediate operand.
248
e7286c56
NC		 2492015-11-16 Nick Clifton <nickc@redhat.com>
250
251 * rx-dis.c (condition_names): Replace always and never with
252 invalid, since the always/never conditions can never be legal.
253
d8bd95ef
TG		 2542015-11-13 Tristan Gingold <gingold@adacore.com>
255
256 * configure: Regenerate.
257
a680de9a
PB		 2582015-11-11 Alan Modra <amodra@gmail.com>
259 Peter Bergner <bergner@vnet.ibm.com>
260
261 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
262 Add PPC_OPCODE_VSX3 to the vsx entry.
263 (powerpc_init_dialect): Set default dialect to power9.
264 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
265 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
266 extract_l1 insert_xtq6, extract_xtq6): New static functions.
267 (insert_esync): Test for illegal L operand value.
268 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
269 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
270 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
271 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
272 PPCVSX3): New defines.
273 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
274 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
275 <mcrxr>: Use XBFRARB_MASK.
276 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
277 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
278 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
279 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
280 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
281 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
282 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
283 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
284 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
285 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
286 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
287 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
288 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
289 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
290 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
291 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
292 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
293 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
294 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
295 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
296 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
297 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
298 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
299 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
300 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
301 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
302 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
303 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
304 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
305 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
306 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
307 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
308
854eb72b
NC		 3092015-11-02 Nick Clifton <nickc@redhat.com>
310
311 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
312 instructions.
313 * rx-decode.c: Regenerate.
314
e292aa7a
NC		 3152015-11-02 Nick Clifton <nickc@redhat.com>
316
317 * rx-decode.opc (rx_disp): If the displacement is zero, set the
318 type to RX_Operand_Zero_Indirect.
319 * rx-decode.c: Regenerate.
320 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
321
43cdf5ae
YQ		 3222015-10-28 Yao Qi <yao.qi@linaro.org>
323
324 * aarch64-dis.c (aarch64_decode_insn): Add one argument
325 noaliases_p. Update comments. Pass noaliases_p rather than
326 no_aliases to aarch64_opcode_decode.
327 (print_insn_aarch64_word): Pass no_aliases to
328 aarch64_decode_insn.
329
c2f28758
VK		 3302015-10-27 Vinay <Vinay.G@kpit.com>
331
332 PR binutils/19159
333 * rl78-decode.opc (MOV): Added offset to DE register in index
334 addressing mode.
335 * rl78-decode.c: Regenerate.
336
46662804
VK		 3372015-10-27 Vinay Kumar <vinay.g@kpit.com>
338
339 PR binutils/19158
340 * rl78-decode.opc: Add 's' print operator to instructions that
341 access system registers.
342 * rl78-decode.c: Regenerate.
343 * rl78-dis.c (print_insn_rl78_common): Decode all system
344 registers.
345
02f12cd4
VK		 3462015-10-27 Vinay Kumar <vinay.g@kpit.com>
347
348 PR binutils/19157
349 * rl78-decode.opc: Add 'a' print operator to mov instructions
350 using stack pointer plus index addressing.
351 * rl78-decode.c: Regenerate.
352
485f23cf
AK		 3532015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
354
355 * s390-opc.c: Fix comment.
356 * s390-opc.txt: Change instruction type for troo, trot, trto, and
357 trtt to RRF_U0RER since the second parameter does not need to be a
358 register pair.
359
3f94e60d
NC		 3602015-10-08 Nick Clifton <nickc@redhat.com>
361
362 * arc-dis.c (print_insn_arc): Initiallise insn array.
363
875880c6
YQ		 3642015-10-07 Yao Qi <yao.qi@linaro.org>
365
366 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
367 'name' rather than 'template'.
368 * aarch64-opc.c (aarch64_print_operand): Likewise.
369
886a2506
NC		 3702015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
371
372 * arc-dis.c: Revamped file for ARC support
373 * arc-dis.h: Likewise.
374 * arc-ext.c: Likewise.
375 * arc-ext.h: Likewise.
376 * arc-opc.c: Likewise.
377 * arc-fxi.h: New file.
378 * arc-regs.h: Likewise.
379 * arc-tbl.h: Likewise.
380
36f4aab1
YQ		 3812015-10-02 Yao Qi <yao.qi@linaro.org>
382
383 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
384 argument insn type to aarch64_insn. Rename to ...
385 (aarch64_decode_insn): ... it.
386 (print_insn_aarch64_word): Caller updated.
387
7232d389
YQ		 3882015-10-02 Yao Qi <yao.qi@linaro.org>
389
390 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
391 (print_insn_aarch64_word): Caller updated.
392
7ecc513a
DV		 3932015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
394
395 * s390-mkopc.c (main): Parse htm and vx flag.
396 * s390-opc.txt: Mark instructions from the hardware transactional
397 memory and vector facilities with the "htm"/"vx" flag.
398
b08b78e7
NC		 3992015-09-28 Nick Clifton <nickc@redhat.com>
400
401 * po/de.po: Updated German translation.
402
36f7a941
TR		 4032015-09-28 Tom Rix <tom@bumblecow.com>
404
405 * ppc-opc.c (PPC500): Mark some opcodes as invalid
406
b6518b38
NC		 4072015-09-23 Nick Clifton <nickc@redhat.com>
408
409 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
410 function.
411 * tic30-dis.c (print_branch): Likewise.
412 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
413 value before left shifting.
414 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
415 * hppa-dis.c (print_insn_hppa): Likewise.
416 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
417 array.
418 * msp430-dis.c (msp430_singleoperand): Likewise.
419 (msp430_doubleoperand): Likewise.
420 (print_insn_msp430): Likewise.
421 * nds32-asm.c (parse_operand): Likewise.
422 * sh-opc.h (MASK): Likewise.
423 * v850-dis.c (get_operand_value): Likewise.
424
f04265ec
NC		 4252015-09-22 Nick Clifton <nickc@redhat.com>
426
427 * rx-decode.opc (bwl): Use RX_Bad_Size.
428 (sbwl): Likewise.
429 (ubwl): Likewise. Rename to ubw.
430 (uBWL): Rename to uBW.
431 Replace all references to uBWL with uBW.
432 * rx-decode.c: Regenerate.
433 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
434 (opsize_names): Likewise.
435 (print_insn_rx): Detect and report RX_Bad_Size.
436
6dca4fd1
AB		 4372015-09-22 Anton Blanchard <anton@samba.org>
438
439 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
440
38074311
JM		 4412015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
442
443 * sparc-dis.c (print_insn_sparc): Handle the privileged register
444 %pmcdper.
445
5f40e14d
JS		 4462015-08-24 Jan Stancek <jstancek@redhat.com>
447
448 * i386-dis.c (print_insn): Fix decoding of three byte operands.
449
ab4e4ed5
AF		 4502015-08-21 Alexander Fomin <alexander.fomin@intel.com>
451
452 PR binutils/18257
453 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
454 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
455 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
456 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
457 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
458 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
459 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
460 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
461 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
462 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
463 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
464 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
465 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
466 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
467 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
468 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
469 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
470 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
471 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
472 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
473 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
474 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
475 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
476 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
477 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
478 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
479 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
480 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
481 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
482 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
483 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
484 (vex_w_table): Replace terminals with MOD_TABLE entries for
485 most of mask instructions.
486
919b75f7
AM		 4872015-08-17 Alan Modra <amodra@gmail.com>
488
489 * cgen.sh: Trim trailing space from cgen output.
490 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
491 (print_dis_table): Likewise.
492 * opc2c.c (dump_lines): Likewise.
493 (orig_filename): Warning fix.
494 * ia64-asmtab.c: Regenerate.
495
4ab90a7a
AV		 4962015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
497
498 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
499 and higher with ARM instruction set will now mark the 26-bit
500 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
501 (arm_opcodes): Fix for unpredictable nop being recognized as a
502 teq.
503
40fc1451
SD		 5042015-08-12 Simon Dardis <simon.dardis@imgtec.com>
505
506 * micromips-opc.c (micromips_opcodes): Re-order table so that move
507 based on 'or' is first.
508 * mips-opc.c (mips_builtin_opcodes): Ditto.
509
922c5db5
NC		 5102015-08-11 Nick Clifton <nickc@redhat.com>
511
512 PR 18800
513 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
514 instruction.
515
75fb7498
RS		 5162015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
517
518 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
519
36aed29d
AP		 5202015-08-07 Amit Pawar <Amit.Pawar@amd.com>
521
522 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
523 * i386-init.h: Regenerated.
524
a8484f96
L		 5252015-07-30 H.J. Lu <hongjiu.lu@intel.com>
526
527 PR binutils/13571
528 * i386-dis.c (MOD_0FC3): New.
529 (PREFIX_0FC3): Renamed to ...
530 (PREFIX_MOD_0_0FC3): This.
531 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
532 (prefix_table): Replace Ma with Ev on movntiS.
533 (mod_table): Add MOD_0FC3.
534
37a42ee9
L		 5352015-07-27 H.J. Lu <hongjiu.lu@intel.com>
536
537 * configure: Regenerated.
538
070fe95d
AM		 5392015-07-23 Alan Modra <amodra@gmail.com>
540
541 PR 18708
542 * i386-dis.c (get64): Avoid signed integer overflow.
543
20c2a615
L		 5442015-07-22 Alexander Fomin <alexander.fomin@intel.com>
545
546 PR binutils/18631
547 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
548 "EXEvexHalfBcstXmmq" for the second operand.
549 (EVEX_W_0F79_P_2): Likewise.
550 (EVEX_W_0F7A_P_2): Likewise.
551 (EVEX_W_0F7B_P_2): Likewise.
552
6f1c2142
AM		 5532015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
554
555 * arm-dis.c (print_insn_coprocessor): Added support for quarter
556 float bitfield format.
557 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
558 quarter float bitfield format.
559
8a643cc3
L		 5602015-07-14 H.J. Lu <hongjiu.lu@intel.com>
561
562 * configure: Regenerated.
563
ef5a96d5
AM		 5642015-07-03 Alan Modra <amodra@gmail.com>
565
566 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
567 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
568 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
569
c8c8175b
SL		 5702015-07-01 Sandra Loosemore <sandra@codesourcery.com>
571 Cesar Philippidis <cesar@codesourcery.com>
572
573 * nios2-dis.c (nios2_extract_opcode): New.
574 (nios2_disassembler_state): New.
575 (nios2_find_opcode_hash): Use mach parameter to select correct
576 disassembler state.
577 (nios2_print_insn_arg): Extend to support new R2 argument letters
578 and formats.
579 (print_insn_nios2): Check for 16-bit instruction at end of memory.
580 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
581 (NIOS2_NUM_OPCODES): Rename to...
582 (NIOS2_NUM_R1_OPCODES): This.
583 (nios2_r2_opcodes): New.
584 (NIOS2_NUM_R2_OPCODES): New.
585 (nios2_num_r2_opcodes): New.
586 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
587 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
588 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
589 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
590 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
591
9916071f
AP		 5922015-06-30 Amit Pawar <Amit.Pawar@amd.com>
593
594 * i386-dis.c (OP_Mwaitx): New.
595 (rm_table): Add monitorx/mwaitx.
596 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
597 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
598 (operand_type_init): Add CpuMWAITX.
599 * i386-opc.h (CpuMWAITX): New.
600 (i386_cpu_flags): Add cpumwaitx.
601 * i386-opc.tbl: Add monitorx and mwaitx.
602 * i386-init.h: Regenerated.
603 * i386-tbl.h: Likewise.
604
7b934113
PB		 6052015-06-22 Peter Bergner <bergner@vnet.ibm.com>
606
607 * ppc-opc.c (insert_ls): Test for invalid LS operands.
608 (insert_esync): New function.
609 (LS, WC): Use insert_ls.
610 (ESYNC): Use insert_esync.
611
bdc4de1b
NC		 6122015-06-22 Nick Clifton <nickc@redhat.com>
613
614 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
615 requested region lies beyond it.
616 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
617 looking for 32-bit insns.
618 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
619 data.
620 * sh-dis.c (print_insn_sh): Likewise.
621 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
622 blocks of instructions.
623 * vax-dis.c (print_insn_vax): Check that the requested address
624 does not clash with the stop_vma.
625
11a0cf2e
PB		 6262015-06-19 Peter Bergner <bergner@vnet.ibm.com>
627
070fe95d 628 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 629 * ppc-opc.c (FXM4): Add non-zero optional value.
630 (TBR): Likewise.
631 (SXL): Likewise.
632 (insert_fxm): Handle new default operand value.
633 (extract_fxm): Likewise.
634 (insert_tbr): Likewise.
635 (extract_tbr): Likewise.
636
bdfa8b95
MW		 6372015-06-16 Matthew Wahab <matthew.wahab@arm.com>
638
639 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
640
24b4cf66
SN		 6412015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
642
643 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
644
99a2c561
PB		 6452015-06-12 Peter Bergner <bergner@vnet.ibm.com>
646
647 * ppc-opc.c: Add comment accidentally removed by old commit.
648 (MTMSRD_L): Delete.
649
40f77f82
AM		 6502015-06-04 Peter Bergner <bergner@vnet.ibm.com>
651
652 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
653
13be46a2
NC		 6542015-06-04 Nick Clifton <nickc@redhat.com>
655
656 PR 18474
657 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
658
ddfded2f
MW		 6592015-06-02 Matthew Wahab <matthew.wahab@arm.com>
660
661 * arm-dis.c (arm_opcodes): Add "setpan".
662 (thumb_opcodes): Add "setpan".
663
1af1dd51
MW		 6642015-06-02 Matthew Wahab <matthew.wahab@arm.com>
665
666 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
667 macros.
668
9e1f0fa7
MW		 6692015-06-02 Matthew Wahab <matthew.wahab@arm.com>
670
671 * aarch64-tbl.h (aarch64_feature_rdma): New.
672 (RDMA): New.
673 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
674 * aarch64-asm-2.c: Regenerate.
675 * aarch64-dis-2.c: Regenerate.
676 * aarch64-opc-2.c: Regenerate.
677
290806fd
MW		 6782015-06-02 Matthew Wahab <matthew.wahab@arm.com>
679
680 * aarch64-tbl.h (aarch64_feature_lor): New.
681 (LOR): New.
682 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
683 "stllrb", "stllrh".
684 * aarch64-asm-2.c: Regenerate.
685 * aarch64-dis-2.c: Regenerate.
686 * aarch64-opc-2.c: Regenerate.
687
f21cce2c
MW		 6882015-06-01 Matthew Wahab <matthew.wahab@arm.com>
689
690 * aarch64-opc.c (F_ARCHEXT): New.
691 (aarch64_sys_regs): Add "pan".
692 (aarch64_sys_reg_supported_p): New.
693 (aarch64_pstatefields): Add "pan".
694 (aarch64_pstatefield_supported_p): New.
695
d194d186
JB		 6962015-06-01 Jan Beulich <jbeulich@suse.com>
697
698 * i386-tbl.h: Regenerate.
699
3a8547d2
JB		 7002015-06-01 Jan Beulich <jbeulich@suse.com>
701
702 * i386-dis.c (print_insn): Swap rounding mode specifier and
703 general purpose register in Intel mode.
704
015c54d5
JB		 7052015-06-01 Jan Beulich <jbeulich@suse.com>
706
707 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
708 * i386-tbl.h: Regenerate.
709
071f0063
L		 7102015-05-18 H.J. Lu <hongjiu.lu@intel.com>
711
712 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
713 * i386-init.h: Regenerated.
714
5db04b09
L		 7152015-05-15 H.J. Lu <hongjiu.lu@intel.com>
716
717 PR binutis/18386
718 * i386-dis.c: Add comments for '@'.
719 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
720 (enum x86_64_isa): New.
721 (isa64): Likewise.
722 (print_i386_disassembler_options): Add amd64 and intel64.
723 (print_insn): Handle amd64 and intel64.
724 (putop): Handle '@'.
725 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
726 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
727 * i386-opc.h (AMD64): New.
728 (CpuIntel64): Likewise.
729 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
730 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
731 Mark direct call/jmp without Disp16|Disp32 as Intel64.
732 * i386-init.h: Regenerated.
733 * i386-tbl.h: Likewise.
734
4bc0608a
PB		 7352015-05-14 Peter Bergner <bergner@vnet.ibm.com>
736
737 * ppc-opc.c (IH) New define.
738 (powerpc_opcodes) <wait>: Do not enable for POWER7.
739 <tlbie>: Add RS operand for POWER7.
740 <slbia>: Add IH operand for POWER6.
741
70cead07
L		 7422015-05-11 H.J. Lu <hongjiu.lu@intel.com>
743
744 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
745 direct branch.
746 (jmp): Likewise.
747 * i386-tbl.h: Regenerated.
748
7b6d09fb
L		 7492015-05-11 H.J. Lu <hongjiu.lu@intel.com>
750
751 * configure.ac: Support bfd_iamcu_arch.
752 * disassemble.c (disassembler): Support bfd_iamcu_arch.
753 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
754 CPU_IAMCU_COMPAT_FLAGS.
755 (cpu_flags): Add CpuIAMCU.
756 * i386-opc.h (CpuIAMCU): New.
757 (i386_cpu_flags): Add cpuiamcu.
758 * configure: Regenerated.
759 * i386-init.h: Likewise.
760 * i386-tbl.h: Likewise.
761
31955f99
L		 7622015-05-08 H.J. Lu <hongjiu.lu@intel.com>
763
764 PR binutis/18386
765 * i386-dis.c (X86_64_E8): New.
766 (X86_64_E9): Likewise.
767 Update comments on 'T', 'U', 'V'. Add comments for '^'.
768 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
769 (x86_64_table): Add X86_64_E8 and X86_64_E9.
770 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
771 (putop): Handle '^'.
772 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
773 REX_W.
774
0952813b
DD		 7752015-04-30 DJ Delorie <dj@redhat.com>
776
777 * disassemble.c (disassembler): Choose suitable disassembler based
778 on E_ABI.
779 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
780 it to decode mul/div insns.
781 * rl78-decode.c: Regenerate.
782 * rl78-dis.c (print_insn_rl78): Rename to...
783 (print_insn_rl78_common): ...this, take ISA parameter.
784 (print_insn_rl78): New.
785 (print_insn_rl78_g10): New.
786 (print_insn_rl78_g13): New.
787 (print_insn_rl78_g14): New.
788 (rl78_get_disassembler): New.
789
f9d3ecaa
NC		 7902015-04-29 Nick Clifton <nickc@redhat.com>
791
792 * po/fr.po: Updated French translation.
793
4fff86c5
PB		 7942015-04-27 Peter Bergner <bergner@vnet.ibm.com>
795
796 * ppc-opc.c (DCBT_EO): New define.
797 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
798 <lharx>: Likewise.
799 <stbcx.>: Likewise.
800 <sthcx.>: Likewise.
801 <waitrsv>: Do not enable for POWER7 and later.
802 <waitimpl>: Likewise.
803 <dcbt>: Default to the two operand form of the instruction for all
804 "old" cpus. For "new" cpus, use the operand ordering that matches
805 whether the cpu is server or embedded.
806 <dcbtst>: Likewise.
807
3b78cfe1
AK		 8082015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
809
810 * s390-opc.c: New instruction type VV0UU2.
811 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
812 and WFC.
813
04d824a4
JB		 8142015-04-23 Jan Beulich <jbeulich@suse.com>
815
816 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
817 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
818 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
819 (vfpclasspd, vfpclassps): Add %XZ.
820
09708981
L		 8212015-04-15 H.J. Lu <hongjiu.lu@intel.com>
822
823 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
824 (PREFIX_UD_REPZ): Likewise.
825 (PREFIX_UD_REPNZ): Likewise.
826 (PREFIX_UD_DATA): Likewise.
827 (PREFIX_UD_ADDR): Likewise.
828 (PREFIX_UD_LOCK): Likewise.
829
3888916d
L		 8302015-04-15 H.J. Lu <hongjiu.lu@intel.com>
831
832 * i386-dis.c (prefix_requirement): Removed.
833 (print_insn): Don't set prefix_requirement. Check
834 dp->prefix_requirement instead of prefix_requirement.
835
f24bcbaa
L		 8362015-04-15 H.J. Lu <hongjiu.lu@intel.com>
837
838 PR binutils/17898
839 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
840 (PREFIX_MOD_0_0FC7_REG_6): This.
841 (PREFIX_MOD_3_0FC7_REG_6): New.
842 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
843 (prefix_table): Replace PREFIX_0FC7_REG_6 with
844 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
845 PREFIX_MOD_3_0FC7_REG_7.
846 (mod_table): Replace PREFIX_0FC7_REG_6 with
847 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
848 PREFIX_MOD_3_0FC7_REG_7.
849
507bd325
L		 8502015-04-15 H.J. Lu <hongjiu.lu@intel.com>
851
852 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
853 (PREFIX_MANDATORY_REPNZ): Likewise.
854 (PREFIX_MANDATORY_DATA): Likewise.
855 (PREFIX_MANDATORY_ADDR): Likewise.
856 (PREFIX_MANDATORY_LOCK): Likewise.
857 (PREFIX_MANDATORY): Likewise.
858 (PREFIX_UD_SHIFT): Set to 8
859 (PREFIX_UD_REPZ): Updated.
860 (PREFIX_UD_REPNZ): Likewise.
861 (PREFIX_UD_DATA): Likewise.
862 (PREFIX_UD_ADDR): Likewise.
863 (PREFIX_UD_LOCK): Likewise.
864 (PREFIX_IGNORED_SHIFT): New.
865 (PREFIX_IGNORED_REPZ): Likewise.
866 (PREFIX_IGNORED_REPNZ): Likewise.
867 (PREFIX_IGNORED_DATA): Likewise.
868 (PREFIX_IGNORED_ADDR): Likewise.
869 (PREFIX_IGNORED_LOCK): Likewise.
870 (PREFIX_OPCODE): Likewise.
871 (PREFIX_IGNORED): Likewise.
872 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
873 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
874 (three_byte_table): Likewise.
875 (mod_table): Likewise.
876 (mandatory_prefix): Renamed to ...
877 (prefix_requirement): This.
878 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
879 Update PREFIX_90 entry.
880 (get_valid_dis386): Check prefix_requirement to see if a prefix
881 should be ignored.
882 (print_insn): Replace mandatory_prefix with prefix_requirement.
883
f0fba320
RL		 8842015-04-15 Renlin Li <renlin.li@arm.com>
885
886 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
887 use it for ssat and ssat16.
888 (print_insn_thumb32): Add handle case for 'D' control code.
889
bf890a93
IT		 8902015-04-06 Ilya Tocar <ilya.tocar@intel.com>
891 H.J. Lu <hongjiu.lu@intel.com>
892
893 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
894 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
895 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
896 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
897 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
898 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
899 Fill prefix_requirement field.
900 (struct dis386): Add prefix_requirement field.
901 (dis386): Fill prefix_requirement field.
902 (dis386_twobyte): Ditto.
903 (twobyte_has_mandatory_prefix_: Remove.
904 (reg_table): Fill prefix_requirement field.
905 (prefix_table): Ditto.
906 (x86_64_table): Ditto.
907 (three_byte_table): Ditto.
908 (xop_table): Ditto.
909 (vex_table): Ditto.
910 (vex_len_table): Ditto.
911 (vex_w_table): Ditto.
912 (mod_table): Ditto.
913 (bad_opcode): Ditto.
914 (print_insn): Use prefix_requirement.
915 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
916 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
917 (float_reg): Ditto.
918
2f783c1f
MF		 9192015-03-30 Mike Frysinger <vapier@gentoo.org>
920
921 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
922
b9d94d62
L		 9232015-03-29 H.J. Lu <hongjiu.lu@intel.com>
924
925 * Makefile.in: Regenerated.
926
27c49e9a
AB		 9272015-03-25 Anton Blanchard <anton@samba.org>
928
929 * ppc-dis.c (disassemble_init_powerpc): Only initialise
930 powerpc_opcd_indices and vle_opcd_indices once.
931
c4e676f1
AB		 9322015-03-25 Anton Blanchard <anton@samba.org>
933
934 * ppc-opc.c (powerpc_opcodes): Add slbfee.
935
823d2571
TG		 9362015-03-24 Terry Guo <terry.guo@arm.com>
937
938 * arm-dis.c (opcode32): Updated to use new arm feature struct.
939 (opcode16): Likewise.
940 (coprocessor_opcodes): Replace bit with feature struct.
941 (neon_opcodes): Likewise.
942 (arm_opcodes): Likewise.
943 (thumb_opcodes): Likewise.
944 (thumb32_opcodes): Likewise.
945 (print_insn_coprocessor): Likewise.
946 (print_insn_arm): Likewise.
947 (select_arm_features): Follow new feature struct.
948
029f3522
GG		 9492015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
950
951 * i386-dis.c (rm_table): Add clzero.
952 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
953 Add CPU_CLZERO_FLAGS.
954 (cpu_flags): Add CpuCLZERO.
955 * i386-opc.h: Add CpuCLZERO.
956 * i386-opc.tbl: Add clzero.
957 * i386-init.h: Re-generated.
958 * i386-tbl.h: Re-generated.
959
6914869a
AB		 9602015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
961
962 * mips-opc.c (decode_mips_operand): Fix constraint issues
963 with u and y operands.
964
21e20815
AB		 9652015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
966
967 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
968
6b1d7593
AK		 9692015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
970
971 * s390-opc.c: Add new IBM z13 instructions.
972 * s390-opc.txt: Likewise.
973
c8f89a34
JW		 9742015-03-10 Renlin Li <renlin.li@arm.com>
975
976 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
977 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
978 related alias.
979 * aarch64-asm-2.c: Regenerate.
980 * aarch64-dis-2.c: Likewise.
981 * aarch64-opc-2.c: Likewise.
982
d8282f0e
JW		 9832015-03-03 Jiong Wang <jiong.wang@arm.com>
984
985 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
986
ac994365
OE		 9872015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
988
989 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
990 arch_sh_up.
991 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
992 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
993
fd63f640
V		 9942015-02-23 Vinay <Vinay.G@kpit.com>
995
996 * rl78-decode.opc (MOV): Added space between two operands for
997 'mov' instruction in index addressing mode.
998 * rl78-decode.c: Regenerate.
999
f63c1776
PA		 10002015-02-19 Pedro Alves <palves@redhat.com>
1001
1002 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1003
07774fcc
PA		 10042015-02-10 Pedro Alves <palves@redhat.com>
1005 Tom Tromey <tromey@redhat.com>
1006
1007 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1008 microblaze_and, microblaze_xor.
1009 * microblaze-opc.h (opcodes): Adjust.
1010
3f8107ab
AM		 10112015-01-28 James Bowman <james.bowman@ftdichip.com>
1012
1013 * Makefile.am: Add FT32 files.
1014 * configure.ac: Handle FT32.
1015 * disassemble.c (disassembler): Call print_insn_ft32.
1016 * ft32-dis.c: New file.
1017 * ft32-opc.c: New file.
1018 * Makefile.in: Regenerate.
1019 * configure: Regenerate.
1020 * po/POTFILES.in: Regenerate.
1021
e5fe4957
KLC		 10222015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1023
1024 * nds32-asm.c (keyword_sr): Add new system registers.
1025
1e2e8c52
AK		 10262015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1027
1028 * s390-dis.c (s390_extract_operand): Support vector register
1029 operands.
1030 (s390_print_insn_with_opcode): Support new operands types and add
1031 new handling of optional operands.
1032 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1033 and include opcode/s390.h instead.
1034 (struct op_struct): New field `flags'.
1035 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1036 (dumpTable): Dump flags.
1037 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1038 string.
1039 * s390-opc.c: Add new operands types, instruction formats, and
1040 instruction masks.
1041 (s390_opformats): Add new formats for .insn.
1042 * s390-opc.txt: Add new instructions.
1043
b90efa5b 10442015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 1045
b90efa5b 1046 Update year range in copyright notice of all files.
bffb6004 1047
b90efa5b 1048For older changes see ChangeLog-2014
252b5132 1049\f
b90efa5b 1050Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 1051
1052Copying and distribution of this file, with or without modification,
1053are permitted in any medium without royalty provided the copyright
1054notice and this notice are preserved.
1055
252b5132 1056Local Variables:
2f6d2f85
NC		 1057mode: change-log
1058left-margin: 8
1059fill-column: 74
252b5132
RH		 1060version-control: never
1061End:
GDB Binutils - Deliverables
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